summaryrefslogtreecommitdiff
AgeCommit message (Collapse)Author
2022-10-17Documentation/drivers/cbfs_smbios.md: Describe CBFS serial numberMichał Żygowski
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I6f0963417c7c580f903922ac88c95569c8782bdb Reviewed-on: https://review.coreboot.org/c/coreboot/+/65702 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
2022-10-17nb/amd/agesa/fam16kb: Remove dead codeArthur Heymans
Setting up HT resource seems to be copied from the old native family10 code. It is however not used as no device has a child device below 18.0 in any of the fam15tn board device trees. Setting up HT resources is therefore done by AGESA and resource allocation mostly happens to work. Change-Id: I7edf19f71095fb38161f19d511997cdc2fe0d76c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68412 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-17nb/amd/agesa/fam15tn: Remove dead codeArthur Heymans
Setting up HT resource seems to be copied from the old native family10 code. It is however not used as no device has a child device below 18.0 in any of the fam15tn board device trees. Setting up HT resources is therefore done by AGESA and resource allocation mostly happens to work. Change-Id: Id95e2dec4a6f3e70234fff1df67ee61e08731400 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68411 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-17arch/x86/smbios.c: Fix Upgrade processor information in SMBIOSZhixing Ma
The current SMBIOS for coreboot is missing processor info for Alder Lake and Raptor Lake SoC, specifically, voltage, max speed, and upgrade (socket type). This patch implements upgrade function. Refer to SMBIOS spec sheet for documentation on cpu socket values: https://web.archive.org/web/20221012222420/https://www.dmtf.org/sites/default/files/standards/documents/DSP0134_3.6.0.pdf BUG=NONE BRANCH=firmware-brya-14505.B TEST=Boot and verified that SMBIOS processor upgrade value is correct. Signed-off-by: Zhixing Ma <zhixing.ma@intel.com> Change-Id: I5796d31fa2d31b17afa5eddde0799b0f68d69909 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68024 Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-10-17mb/supermicro/x9sae: Add full NCT6776 supportBill XIE
X9SAE has a PS/2 controller for keyboard and mouse but its definition in ACPI used to be missing, and X9SAE used to use a generic SuperIO support initially generated by autoport, so the full NCT6776 support is added here like x9scl. Test result: Log lines like i8042: PNP: No PS/2 controller found. i8042: Probing ports directly. serio: i8042 KBD port at 0x60,0x64 irq 1 serio: i8042 AUX port at 0x60,0x64 irq 12 mousedev: PS/2 mouse device common for all mice become i8042: PNP: PS/2 Controller [PNP0303:PS2K,PNP0f13:PS2M] at 0x60,0x64 irq 1,12 serio: i8042 KBD port at 0x60,0x64 irq 1 serio: i8042 AUX port at 0x60,0x64 irq 12 mousedev: PS/2 mouse device common for all mice and more sub-devices within SuperIO is handled by the PNP driver. Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Change-Id: Ie5e73e8c3fc4e57c6683d7a7ca70e96c64dd9366 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68446 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-17soc/amd: factor out common noncar bootblockFelix Held
This code is identical for all non-CAR AMD SoCs, so factor it out to soc/amd/common/block/cpu/noncar/bootblock.c to avoid code duplication. Also integrate the bootblock.c improvement to include cpu/cpu.h which provides cpuid_eax from commit 68eb439d8091 ("soc/amd/picasso: Clean up includes"). Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I42e4aa85efd6312a3ab37f0323a35f6dd7acd8e6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68431 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-17soc/amd/*/smihandler: Make fch_apmc_smi_handler commonFred Reitberger
Rename soc/amd/common/block/cpu/smm/smi_ampc_helper.c to smi_apmc.c and add the fch_apmc_smi_handler function. Remove the duplicated function from picasso, cezanne, mendocino, and morgana SoC. The stoneyridge soc does not implement the APM_CNT_SMMINFO handler, so give the handler a unique name that does not conflict with the common handler name. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I2e6fb59a1ee15b075ee3bbb5f95debe884b66789 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68441 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-10-17mb/ocp/deltalake: Clean up includesElyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: If68ce4fef69a2466e76fc7fc504c00ee915e3e36 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68254 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2022-10-17MAINTAINERS: Add AMD Morgana SoC and birman boardFred Reitberger
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Iae811c97aba15dd6c9c740aedd7c802e14f53788 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68439 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-17mb/google/dedede/var/pirika: Add fw_config probe for ALC5682-VD & VSFrankChu
ALC5682-VD/ALC5682I-VS load different kernel driver by different hid name. Update hid name depending on the AUDIO_CODEC_SOURCE field of fw_config. Define FW_CONFIG bits 41 - 43 (SSFC bits 9 - 11) for codec selection. ALC5682-VD: _HID = "10EC5682" ALC5682I-VS: _HID = "RTL5682" BUG=b:244620955 TEST=ALC5682-VD/ALC5682I-VS audio codec can work Signed-off-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Change-Id: Ia6cb56e76bc4e245a32f29b19226fa4fae330c92 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67824 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com> Reviewed-by: Maulik Vaghela <maulikvaghela@google.com>
2022-10-17mb/*/*/gpio.h: Remove unused <soc/gpe.h>Elyes Haouas
Change-Id: I9b03ccc1100307e3c24393903600d18f6cc9abdc Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68378 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
2022-10-16Documentation/security: Update list of boards supporting vbootMartin Roth
Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Change-Id: Ie6ecb3ed97ed0581300411962c3b1bba416e0224 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68242 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-16Docs/releases: Add 4.19 relnotes template and update indexMartin Roth
The 4.19 release is planned for January 2023. Please add any updates to the coreboot code that are should go into the notes between now and then. This helps in that you get to phrase the update the way you want, and it lessens the load for the release managers. Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Change-Id: Ib5a7ddfc6cb1a8e0a485c1e1810631c86f4083c3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68459 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-10-16Docs/releases: Update coreboot-4.18 release notesMartin Roth
Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I5cf38463e44f9abaadb4dc47dbf48ef0f0514bc9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64956 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-10-15mb/starlabs/lite/{glk,glkr}: Enable PMCSean Rhodes
Enable PMC in devicetree so that resources are allocated properly for it. Tested on StarLite Mk III & IV, and both can power on correctly. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ib4384b55751a9979e470dd04f6814d4ca170ff34 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67409 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-15mb/starlabs/lite: Reset XHCI before entering S5Sean Rhodes
Reset the XHCI controller prior to S5 to avoid XHCI preventing shutdown. Linux needs to put the XHCI into D3 before shutting down but the powerstate commands do not perform a reset. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I3be70443eb85a7dff8055c9de0ca2fd89f4fc88d Reviewed-on: https://review.coreboot.org/c/coreboot/+/67678 Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-15soc/intel/apollolake: Lock down Global SMISean Rhodes
Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I9377c3b65aa342f754c303148b0b8d826d05bb94 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67662 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-15soc/intel/apollolake: Configure FSP UPDs to allow coreboot to lockdownSean Rhodes
Configure FSP S UPDs to allow coreboot to handle the lockdown. The main change here is setting `Write Protection Support` to 0, as the default is Enabled, which shouldn't allow writes (even though it seems to). The UPDs are identical on APL and GLK, but all ones configured in this patch have been there since their initial releases. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I1f6e5344cab2af7aa6001b9ec0f07b043a9caa8a Reviewed-on: https://review.coreboot.org/c/coreboot/+/67754 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-15treewide: Use 'fadt->x_pm2_cnt_blk.addrl = fadt->pm2_cnt_blk'Felix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iaecb83c3bc9c75dab427a3ca54da1e6a8f87cf9a Reviewed-on: https://review.coreboot.org/c/coreboot/+/68428 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-10-15treewide: Use 'fadt->x_pm1a_evt_blk.addrl = fadt->pm1a_evt_blk'Felix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id3002dc976b82f71b1f60a6e32b16d60a7bbbead Reviewed-on: https://review.coreboot.org/c/coreboot/+/68427 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-10-15mb/amd/padmelon: rename to pademelonFelix Held
This AMD reference board is called Pademelon and not Padmelon, so fix the name in coreboot. Also update the corresponding documentation. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id1c7331f5f3c34dc7ec4bc5a1f5fe3d12d503474 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68426 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-10-14soc/amd/picasso: Clean up includesElyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I4ed869627af11b607f910644b6f21898f7c7bba5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68237 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-14soc/amd/sata.c: Hook up directly in devicetreeArthur Heymans
Cezanne has two SATA controllers, but doesn't select SOC_AMD_COMMON_BLOCK_SATA, so it's not added to the SATA devices in the Cezanne chipset devicetree. Change-Id: If7f0a9638151cf981d891464a2c3a0ec5fc9c780 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68142 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-14soc/amd/*: Hook up IOMMU ops in devicetreeArthur Heymans
This removed the need to maintain a PCI driver. Change-Id: I43def81d615749008fcc9de8734fa2aca752aa9d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68146 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-10-14soc/amd/*: Hook up LPC ops in devicetreeArthur Heymans
This removes the need for a PCI driver. Change-Id: I6674d13f434cfa27fa6514623ba305af6681f70d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68144 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-10-14soc/amd/*: Hook up SMBus ops to devicetreeArthur Heymans
This removes the need for a PCI driver. Change-Id: Iab75f8c28a247f1370f4425e19cc215678bfa3e5 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68140 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-10-14soc/amd: factor out common eMMC codeFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If5447f9272183f83bc422520ada93d3cfd96551e Reviewed-on: https://review.coreboot.org/c/coreboot/+/68415 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-10-14ec/google/chromeec: Demote LPC EC error printk from ERR to SPEWMatt DeVillier
Several EC host commands check for support of a given feature or msg version, and a non-zero response does not necessarily indicate an actual error. Since the caller is (should be) handling the non-zero response to the host command, demote the EC printk from ERR to SPEW to clean up the console log and prevent non-errors from causing false failures in firmware tests. BUG=b:238961053 Change-Id: Ib7afc0b7e5b571acb56252f7adb518a6b2716b62 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68259 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-14util/elogtool: Add support for parsing CrOS diagnostics logHsuan Ting Chen
Remove the "_DEPRECATED_" tag from ChromeOS diagnostics event and add a subtype: "ELOG_CROS_DIAGNOSTICS_LOGS" under it. The data of "ELOG_CROS_DIAGNOSTICS_LOGS" (0x02) contains: * An uint8_t of subtype code * Any number of "ChromeOS diagnostics logs" events Each "ChromeOS diagnostics log" represents the result of one ChromeOS diagnostics test run. It is stored within an uint8_t raw[3]: * [23:19] = ELOG_CROS_DIAG_TYPE_* * [18:16] = ELOG_CROS_DIAG_RESULT_* * [15:0] = Running time in seconds Also add support for parsing this event. The parser will first calculate the number of runs it contains, and try to parse the result one by one. BUG=b:226551117 TEST=Build and boot google/tomato to OS, localhost ~ # elogtool list 0 | 2022-09-26 04:25:32 | Log area cleared | 186 1 | 2022-09-26 04:25:50 | System boot | 0 2 | 2022-09-26 04:25:50 | Firmware vboot info | boot_mode=Manual recovery | recovery_reason=0x2/0 (Recovery button pressed) | fw_tried=A | fw_try_count=0 | fw_prev_tried=A | fw_prev_result=Unknown 3 | 2022-09-26 04:25:50 | EC Event | Keyboard Recovery 4 | 2022-09-26 04:26:01 | Memory Cache Update | Normal | Success 5 | 2022-09-26 04:26:06 | System boot | 0 6 | 2022-09-26 04:26:07 | Firmware vboot info | boot_mode=Diagnostic | fw_tried=A | fw_try_count=0 | fw_prev_tried=A | fw_prev_result=Unknown 7 | 2022-09-26 04:26:07 | Diagnostics Mode | Diagnostics Logs | type=Memory check (quick), result=Aborted, time=0m0s | type=Memory check (full), result=Aborted, time=0m0s | type=Storage self-test (extended), result=Aborted, time=0m1s Change-Id: I02428cd21be2ed797eb7aab45f1ef1d782a9c047 Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67834 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-10-14soc/intel/alderlake: Create helper header file for UFSSubrata Banik
This patch creates helper header file (ufs.h) for UFS to keep required registers details and ACPI device id for UFS. BUG=none TEST=Able to build and boot Google/Kano. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: If08c54eb706876a4255542a708aa5fcd8bf43c55 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68299 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-14soc/intel/alderlake: Add UFS PCR IDSubrata Banik
Add UFS PID (`PID_UFSX2`) value 0x50. BUG=none TEST=Able to build and boot Google/Rex. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I229469475cd116bf911b6530c3c819d00c808aa9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68298 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-14soc/mediatek/mt8186: Add DEVAPC settings for ADSPTinghan Shen
Add DEVAPC permission settings for ADSP and set its domain number to 6. TEST=SOF driver is functional. BUG=b:204229221 Change-Id: I37bfea70386af953e89f3c38ac51e41af6aafa6e Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68290 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-14soc/mediatek/mt8186: Inititalize ADSPTinghan Shen
To use SOF correctly, we need to initialize ADSP in coreboot stage. TEST=SOF driver is functional. BUG=b:204229221 Change-Id: I45db587252ccdcdf75e0be2029743034a79925c5 Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68289 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-14soc/mediatek/mt8186: Add mtcmos power-on control for ADSPMandy Liu
To use SOF correctly, we need to enable power domain of ADSP. TEST=SOF driver is functional. BUG=b:204229221 Signed-off-by: Mandy Liu <mandyjh.liu@mediatek.com> Change-Id: I39d1357af5f901a91379fdf7e595f16952b962de Reviewed-on: https://review.coreboot.org/c/coreboot/+/68288 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-14soc/mediatek/mt8186: Enable ADSP clockMandy Liu
To use SOF correctly, we need to enable ADSP clock. TEST=SOF driver is functional. BUG=b:204229221 Signed-off-by: Mandy Liu <mandyjh.liu@mediatek.com> Change-Id: Ia17db889829df2668cf2af1b71c6468230de68e1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68287 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-14mb/google/rex: Add initial fw configKapil Porwal
Add initial fw config as per config.star. BUG=b:253199788, b:245158908, b:244113761, b:244012065 TEST=emerge-rex coreboot. Make sure that ACPI tables are equivalent before and after this change with CBI.FW_CONFIG set to 0x1561. Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I66f8b3e4ab414c03b8d63fdd31e0f3f424619340 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68220 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-14mb/google/rex: Add FW_CONFIG* to KconfigEran Mitrani
BUG=b:253199788 TEST=Build and boot to Google/Rex. Change-Id: Ib729c98a4d67aa46992fdccf592010b0313605a6 Signed-off-by: Eran Mitrani <mitrani@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66817 Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-14mb/google/nissa/var/yaviks: Remove fw_config probe for storage devicesReka Norman
When fw_config is unprovisioned, devicetree will disable all probed devices. However, boot-critical devices such as storage devices need to be enabled. As a temporary workaround while adding devicetree support for this, remove the fw_config probe for storage devices so that all storage devices are always enabled. On eMMC SKUs, UFS and ISH will be disabled by the PCI scan anyway. On UFS SKUs, eMMC is not disabled by the PCI scan, but keeping it enabled should have no functional impact, only a possible power impact. BUG=b:251055188 TEST=On yaviks eMMC and UFS SKUs, boot to OS and `suspend_stress_test -c 10` Change-Id: I6b3a20f3c14d5e9aa8d71f6ca436b5a682310797 Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68365 Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-14Update arm-trusted-firmware submodule to upstream masterYidi Lin
Updating from commit id 7805999e6: 2022-09-05 16:42:34 +0200 - (Merge changes from topic "st-nand-updates" into integration) to commit id c45d2febb: 2022-10-12 15:56:24 +0200 - (Merge "fix(ufs): retry commands on unit attention" into integration) This brings in 288 new commits. Signed-off-by: Yidi Lin <yidilin@chromium.org> Change-Id: I4137cab0a1a352e94e21f105717ae0b6c515b75b Reviewed-on: https://review.coreboot.org/c/coreboot/+/68386 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-10-14mb/google/nissa/var/xivu: Config I2C frequencyIan Feng
1.Change the TPM I2C freqeuncy to 1 MHz for xivu. 2.Config same settings as the baseboard for I2C buses 1-5. BUG=b:249953477 TEST=On xivu, all timing requirements in the spec are met. Frequencies: 1. I2C0 (TPM): 974.3 Khz 2. I2C1 (TouchScreen); 375.5 Khz 3. I2C3 (Audio): 389.0 Khz 4. I2C5 (Touchpad): 388.5 Khz Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: I33f712c14978b95f3a4da82d6f1f5fbae1283b17 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68071 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
2022-10-14soc/intel/alderlake: Fix unknown voltage in SMBIOSZhixing Ma
The current SMBIOS for coreboot is missing processor info for Alder Lake and Raptor Lake SoC, specifically, voltage, max speed, and upgrade (socket type). This patch implements voltage function. Refer to SMBIOS spec sheet for documentation: https://web.archive.org/web/20221012222420/https://www.dmtf.org/sites/default/files/standards/documents/DSP0134_3.6.0.pdf BUG=NONE BRANCH=firmware-brya-14505.B TEST=Boot and verified that SMBIOS processor voltage value is correct. Signed-off-by: Zhixing Ma <zhixing.ma@intel.com> Change-Id: I77712b72fa47bdcb56ffddeff15cff9f3b3bbe86 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68023 Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-14soc/intel/alderlake: Fix unknown max speed in SMBIOSZhixing Ma
The current SMBIOS for coreboot is missing processor info for Alder Lake and Raptor Lake SoC, specifically, voltage, max speed, and upgrade (socket type). This patch implements max speed function. Refer to SMBIOS spec sheet for documentation: https://web.archive.org/web/20221012222420/https://www.dmtf.org/sites/default/files/standards/documents/DSP0134_3.6.0.pdf BUG=NONE BRANCH=firmware-brya-14505.B TEST=Boot and verified that SMBIOS max speed value is correct. Signed-off-by: Zhixing Ma <zhixing.ma@intel.com> Change-Id: I09bcccc6f97238f7328224af8b852751114896fe Reviewed-on: https://review.coreboot.org/c/coreboot/+/67913 Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-14mb/amd/padmelon/bootblock/OemCustomize: add TODO for Prairie FalconFelix Held
The PCIe port descriptor list seems to be specific to Merlin Falcon and Prairie Falcon has a different PCIe root port configuration. Since I neither have the board nor the different APUs, I just add a comment about this instead of trying to come up with a PCIe port descriptor list that may or may not work properly on Prairie Falcon APUs. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8e1eb67a8f684297bbefc6e2593250d7bd45593f Reviewed-on: https://review.coreboot.org/c/coreboot/+/68407 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-10-14soc/amd/stoneyridge: move northbridge ops to northbridge deviceFelix Held
The northbridge ops should be added to the actual northbridge and not the first HT device. Neither of the devices has BARs on it, so read_resources implementation will still work correctly. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I2e5f21bfe5fff043d7d9afafa360764203dd61f6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68409 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-14soc/amd/stoneyridge: use devicetree ops over pci driverFelix Held
Stoneyridge is a SoC so it makes sense to statically use ops instead of matching them to PCI DID/VID at runtime. In contrast to the other AMD SoCs in the coreboot tree the PC driver used the PCI ID of the first HT PCI device function, so add the ops to the device 0x18 function 0 devicetree entry in this patch. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I500521701479aa271ebd61e22a1494c8bfaf87fb Reviewed-on: https://review.coreboot.org/c/coreboot/+/68408 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-14soc/amd/stoneyridge: Hook up device_operations in chipset.cbFelix Held
This removes the need for a lot of boilerplate code in the soc code to hook up device_operations to devices. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id668587e1b747c28207b213b985204b7a961a631 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68410 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-14mb/prodrive/atlas: Print HSIDMaximilian Brune
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: Ibb7aac1204bc297d16797cac5b32b119d0a9204b Reviewed-on: https://review.coreboot.org/c/coreboot/+/68224 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-14mb/google/rex: Implement WIFI SAR related changesSubrata Banik
1. Add CHROMEOS_WIFI_SAR to include the SAR configs. 2. Add get_wifi_sar_cbfs_file_name() that return the wifi SAR filename. BUG=none TEST=emerge-rex coreboot Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ia863eaa53c9456ae0e9f0e8914e0de497a32b53b Reviewed-on: https://review.coreboot.org/c/coreboot/+/68393 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-10-14mb/google/kahlee/*/devicetree: disable unused PCIe root portsFelix Held
Disable the unused PCIe root ports that are disabled in the PCIe port corresponding descriptor list passed to AGESA/binaryPI. This descriptor list is in src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c and it only has B0D2F2 (gpp_bridge_1) and B0D2F4 (gpp_bridge_3) enabled. Since the PCIe engines marked as unused in the port descriptor list won't show up as PCI devices, don't enable those PCI devices in the devicetree so that coreboot won't complain about static PCI devices not being found on the PCI bus. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If8378e343a2eb13de66171cf4f38d77ae3401016 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68382 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2022-10-14mb/google/kahlee/*/devicetree: use device aliasesFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I63b1053d36b284ed95b015c0b4b26bdf8e162e67 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68381 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-14mb/amd/padmelon/devicetree: use device aliasesFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I509daac75c80bdca808706f783b04843209cc313 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68380 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-14mb/amd/gardenia/devicetree: disable unused gpp_bridge_2Felix Held
The board's PCIe port descriptors have the PCIe engine disabled, so update the devicetree accordingly. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic97a54c3cc762a36752d6b9f21467428912a9edd Reviewed-on: https://review.coreboot.org/c/coreboot/+/68379 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-14mb/amd/gardenia/devicetree: use device aliasesFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I9a429c0fd23eb3b52a19a974b22079d675e3506a Reviewed-on: https://review.coreboot.org/c/coreboot/+/68318 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-13mb/amd,google/*/devicetree: drop CPU cluster device for StoneyridgeFelix Held
Since commit 60e9114c6210 ("include/device: ensure valid link/bus is passed to mp_cpu_bus_init"), no dummy LAPIC device is required under the CPU cluster device. Since the CPU cluster device is already present in the Stoneyridge chipset devicetree, drop the whole CPU cluster part from the mainboard's devicetrees. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8918c14be25ac9756926a9c6a2806a3dceced42a Reviewed-on: https://review.coreboot.org/c/coreboot/+/68317 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-13soc/amd/stoneyridge: add chipset devicetreesFelix Held
Add chipset devicetrees for Stoneyridge and Carrizo, which is also supported by the Stoneyridge code, but has more external PCIe ports and devices. The mainboard's devicetrees will be changed to use the aliases defined in the chipset devicetree in follow-up patches. This is a preparation to statically assign the ops for the internal devices statically in the SoC devicetree instead of dynamically adding them in ramstage. BKDG #55072 Rev 3.04 was used to check the PCI devices and functions and the MMIO addresses. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia45260b1168ed1d99993adfb98475da5b5c90d11 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68316 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-13mb/amd/padmelon: enable PCI device 3.1 for MerlinfalconFelix Held
When using a Merlin Falcon APU, explicitly enable the PCIe root port at B0D3F1. B0D3F0 is only a dummy PCI device function, but needs to also be enabled in order for the actually used function to be usable. Prairie Falcon doesn't have and PCI device 3 on bus 0, so remove D3F0 from the common mainboard devicetree. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I01f9b9ac2a9ebd5899a093d97eb5b2d76d309f66 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68315 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-13mb/amd/padmelon/devicetree: fix PCIe port device numbersFelix Held
Enable the correct PCIe root ports in the devicetree so that the configuration matches the PCIe port descriptors in src/mainboard/amd/padmelon/bootblock/OemCustomize.c. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Idb00a65adcf2059d7432a8df08654bb0ba965e24 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68314 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-13mb/amd/gardenia,padmelon/devicetree: explicitly enable IOMMU deviceFelix Held
PCI devices that aren't present in the devicetree will be treated as enabled. Since the chipset devicetree that will be added in a follow-up patch disables this device by default, explicitly enable the IOMMU device on the Stoneyridge mainboards that don't disable it to keep the same behavior. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4a2cdd00abe8309244829dc633dd8a9ca0038dfa Reviewed-on: https://review.coreboot.org/c/coreboot/+/68313 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-13mb/amd/padmelon: use override devicetrees for the different APUsFelix Held
Since the devicetree files are passed to util/sconfig without being processed by the C preprocessor, using #if in the devicetree won't give the behavior that might be expected. Instead sconfig treats the #if as a comment, but still processes all other lines. To get the intended behavior, replace the C preprocessor usage in the devicetree by moving the APU-specific parts to override devicetrees that get selected according to the selected APU type. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iddd317b27a838849fa40c0fb77d942609104cf04 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68312 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-13mb/starlabs/starbook/tgl: Remove PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4GSean Rhodes
PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is no longer needed so remove it. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I82841c2114ceb5e7a46ce228fce63d24822098d2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68084 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-13soc/amd/*: Hook up GPU ops in devicetreeArthur Heymans
This removes the need for a PCI driver. Change-Id: I4b499013a80f5c1bd6ac265a5ae8e635598d9e6c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68148 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-13soc/amd/*: Hook up GPP bridges ops to devicetreeArthur Heymans
This removes the need for a PCI driver. Change-Id: I8e235d25622d0bd3f1bb3f18ec0400a02f674a6d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68147 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-13soc/amd/acp: Hook up ops in devicetreeArthur Heymans
This removes the need for a PCI driver. Change-Id: Id25016703d1716930d9b6c6d1dab5481b10aca17 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68145 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-13soc/amd/morgana: Use devicetree ops over pci driverFelix Held
Morgana is a SoC so it makes sense to statically use ops instead of matching them to PCI DID/VID at runtime. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I67362ae4a32bc9b1dd19ee5e4caf42db8f5dd1bd Reviewed-on: https://review.coreboot.org/c/coreboot/+/68311 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-13soc/amd/mendocino: Use devicetree ops over pci driverArthur Heymans
Mendocino is a SoC so it makes sense to statically use ops instead of matching them to PCI DID/VID at runtime. Change-Id: I5619c8ad42cdeb019cb7294da884909df64a2211 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68141 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-13soc/amd/cezanne: Use devicetree ops over pci driverArthur Heymans
Cezanne is a SoC so it makes sense to statically use ops instead of matching them to PCI DID/VID at runtime. Change-Id: If535221335217cee53bca956747e7f17f0a5fd8d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68143 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-13soc/amd/picasso: Use devicetree ops over pci driverArthur Heymans
Picasso is a SoC so it makes sense to statically use ops instead of matching them to PCI DID/VID at runtime. Change-Id: Ide747c9d386731af89b27630b200676c6e439910 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67743 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-13soc/amd/*: Hook up device_operations in chipset.cbArthur Heymans
This removes the need for a lot of boilerplate code in the soc code to hook up device_operations to devices. Change-Id: I2afc1855407910f1faa9bdd4e9416dd46474658e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67738 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-13soc/amd/*: Move emmc disabling to device opsArthur Heymans
This allows for reduced use of chip_operations in the followup patch and allows the allocator to skip over the used mmio. Change-Id: I4052438185e7861792733b96a1298201c73fc3ff Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68113 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-13payloads,src: Replace ALIGN(x, a) by ALIGN_UP(x, a) for clarityElyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I80f3d2c90c58daa62651f6fd635c043b1ce38b84 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68255 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-13mb/google/skyrim: Allow variants to override romstage GPIO tableMatt DeVillier
Switch from gpio_configure_pads() to gpio_configure_pads_with_override() so variants can override romstage GPIO defaults. Rename baseboard function and add an weak empty override function to be used by variants. Will be used for touchscreen power sequencing in a follow-on commit. Change-Id: I45586237919cd07a171beac57f3510e26338f67f Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67811 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-10-13mb/google/herobrine: Create zombie variantMaulik Vaghela
Create the zombie variant of the herobrine reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:249180463 BRANCH=None TEST=util/abuild/abuild -p none -t google/herobrine -x -a make sure the build includes GOOGLE_ZOMBIE Signed-off-by: Maulik Vaghela <maulikvaghela@google.com> Change-Id: Ifecf0a6323b20012defbf14bd16ce2f1f41f4714 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68303 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bob Moragues <moragues@google.com> Reviewed-by: Shelley Chen <shchen@google.com>
2022-10-13util/cbfstool: Wrap logging macros in do - whileFred Reitberger
Wrap the console logging macros with do { ... } while (0) so they act more like functions. Add missing semicolons to calls of these macros. TEST=compile only Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I721a4a93636201fa2394ec62cbe4e743cd3ad9d0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68336 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-10-13spd/lp5: Add new memory configuration of H58G66BK7BX067 and H58G56BK7BX068EricKY Cheng
Add Hynix H58G66BK7BX067 and H58G56BK7BX068 in the memory_parts.json and re-generate the SPD. BUG=b:243337816 BRANCH=None TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5 Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com> Change-Id: I8d6aac3ecec36b126e7e41d6c9475695aa7a26b2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68212 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com>
2022-10-13soc/amd/*/psp_verstage/svc: Make svc.h macros commonFred Reitberger
The psp_verstage/svc.h SVC_CALLx macros are virtually identical between picasso/cezanne/mendocino, so move to common. TEST=timeless builds are identical Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I86a8d9b043f68c01ee487f2cdbf7f61934b4a520 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68277 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-13mb/google/brya/var/felwinter: adjust I2C5 times for TPJohn Su
This change updates scl_lcnt, scl_hcnt, sda_hold value for I2C5. BUG=b:249031186 BRANCH=brya TEST=TP function is normal from EE check. Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: I5e756b7d7e14cace24ef2dfbb323c840c867ae1a Reviewed-on: https://review.coreboot.org/c/coreboot/+/68329 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
2022-10-13soc/amd/cezanne: enable LPC decodes if platform uses LPCJeremy Soller
Change-Id: I2473fe61b299d1c6221844cd744791b8012c5c67 Signed-off-by: Jeremy Soller <jeremy@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59103 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-10-13mb/hp/z220_series: Add missing PCI Interrupt Routing TableBill XIE
HP Z220 series has PCI slot(s) but Interrupt Routing Table in ACPI used to be missing, so one is added. Note that the values within the added one are obtained from my own SFF variant. If other variants have different values, please add them in a manner similar to mb/gigabyte/ga-b75m-d3h/acpi/pci.asl. Test result: Log lines like pci 0000:00:1e.0: can't derive routing for PCI INT A ath9k 0000:04:00.0: PCI INT A: no GSI disappeared from dmesg. Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Change-Id: I8522b25ac46db2054302c8f2418927c722b157e0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68334 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-13mb/hp/z220_series: Fix the indentation of dsdt.aslBill XIE
Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Change-Id: I66f99a5afbdd2b847a916a470a5def9a6d3999bc Reviewed-on: https://review.coreboot.org/c/coreboot/+/68335 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-13Doc/releases/4.18: Improve several small thingsAngel Pons
Add a missing period, use "SoC" with lowercase 'o' to refer to a "System on a Chip", fix up the redundant "CRB board" expression (that stands for "Customer Reference Board board"), switch the position of a verb and its adverb ("never was" ---> "was never") to sound more natural, and replace "depreciate" with "deprecate" for semantic correctness. Change-Id: Ic821a9030d4ff32c76765f51f1feb0f5503d4cc0 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68330 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-13Documentation: Get rid of trailing whitespacesElyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I698a9501fd3d47e1e5793df32ae1e4118dfd95f6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68328 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-10-13mb/prodrive/hermes: Use `snprintf()` to handle stringsAngel Pons
Strings in C are highly cursed. Use `snprintf()` to minimize the potential of running into undefined behavior in the future. Change-Id: I3caef25bc7676ac84bb1c40efe6d16f50f8f4d26 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68323 Reviewed-by: Patrick Georgi <patrick@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-10-13mb/prodrive/hermes: Harden `eeprom_read_serial()`Angel Pons
The `eeprom_read_serial()` function could return a non-NULL terminated string if the serial in EEPROM has `HERMES_SN_PN_LENGTH` (32) non-NULL characters. Make this impossible by adding an additional character for a NULL byte in the static buffer, which always gets set to 0 (NULL). Change-Id: I306fe1b6dd3836156afca786e352d2a7dca0d77c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68322 Reviewed-by: Patrick Georgi <patrick@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-10-12device: Drop unused ADL-N UFS PCI Device IDSubrata Banik
This patch drops unused ADL-N UFS PCI Device ID macro `PCI_DID_INTEL_ADP_UFS`. BUG=none TEST=Able to build and boot Google/Kano. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I24e4a1a871763473df4d610b13e8a3a754470233 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68292 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.com> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-10-12soc/intel: Kconfig: Correct UART source clock value in commentWonkyu Kim
Correct UART source clock value in comment from 120 MHz to 100 MHz. BUG=b:249530903 Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: Ifc17357051ae0b3bc663da467b4fc809a46024d4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68286 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-12Revert "soc/qualcomm: Update the wait time for checking PCIe link up"Shelley Chen
This reverts commit 4b5ba9436373d1addab13cd38ee6899e49ea029f. Reason for revert: This optimization is causing the non-serial enabled tot BIOS to not boot. To get tot back into good shape, will revert for now and reevalute this fix and resubmit at a later time. BUG=b:218406702 BRANCH=None TEST=reboot from AP console (on herobrine) after flashing image-herobrine.bin. prior to fix the device would never boot to login prompt. after rever the device would boot to login prompt again. Change-Id: Iaac5f2fb2120f6aa41a0ce9a763d50fd7b9a3ec7 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68339 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Douglas Anderson <dianders@chromium.org>
2022-10-12lib/lzma: Build the source for decompression with flag -OfastZheng Bao
The decompression is critical for speed of boot. So we sacrifice some generated code size to optimize for speed. This change speeds up the LZMA decompression between 3% and 6% at a cost of just over 2k of additional code space. BUG=b:223985641 TEST=Majolica The test is done on Majolica and the result is listed below. Time saved: We tested the boot time with each flag for 10 times. The duration of each decompression process is listed as below. Load FSP-M Load ramstage Load payload Ofast Os Ofast Os Ofast Os ------------------------------------------ 62543 62959 20585 22458 9945 10626 62548 62967 20587 22461 9951 10637 62560 62980 20588 22478 9951 10641 62561 62988 20596 22478 9954 10643 62569 62993 20596 22479 9954 10643 62574 63000 20605 22492 9958 10647 62575 63026 20615 22495 9959 10647 62576 63038 20743 22614 9960 10647 62587 63044 20758 22625 9961 10647 62592 63045 20769 22637 9961 10647 ----------------------------------------- average 62568 63004 20644 22521 9955 10642 (unit: microseconds) Size sacrificed: The size of object file with -Os: ./build/ramstage/lib/lzmadecode.o: file format elf32-i386 4 .text.LzmaDecode 00000d84 00000000 00000000 00000076 2**0 CONTENTS, ALLOC, LOAD, READONLY, CODE The size of object file with -Ofast: ./build/ramstage/lib/lzmadecode.o: file format elf32-i386 4 .text.LzmaDecode 00001719 00000000 00000000 00000080 2**4 CONTENTS, ALLOC, LOAD, READONLY, CODE (Output by running "objdump -h ./build/ramstage/lib/lzmadecode.o") We can see that size is increased from 3460 bytes to 5913 bytes, a change of 2453 bytes or 171%. Change-Id: Ie003164e2e93ba8ed3ccd207f3af31c6acf1c5e2 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66392 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-10-12mb/starlabs/starbook/tgl: Configure PMC muxSean Rhodes
Configure PMC mux in devicetree. Tested on StarBook Mk V with Ubuntu 22.04. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I297d5446e43357d97357f345668cf40dcd28502d Reviewed-on: https://review.coreboot.org/c/coreboot/+/68083 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-10-12mb/starlabs/starbook/tgl: Enable P2SBSean Rhodes
Enable the P2SB so that the SPI is discoverable by the OS. Change-Id: I49802f93a97a18ecc10f48d213619855728e1290 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67029 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-12mb/starlabs/starbook/tgl: Use chipset.cb aliasesSean Rhodes
Change-Id: Ie9655406c7afe7a22f131d35633a697c5bbde4e3 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67027 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-10-12payloads/edk2: Add a recipe to build the ShimLayerSean Rhodes
The ShimLayer is required to start the Universal Payload. It will build the required HOBs and pass them accordingly. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I043271994f40813d9059a89420d4311d9d5802b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64485 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-10-12treewide: Use 'fadt->x_pm1a_cnt_blk.addrl = fadt->pm1a_cnt_blk'Elyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Ic48c5c165732c8397c06a2362191a94ae5805cf1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68276 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-12treewide: Use 'fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk'Elyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I7ddb4ea792b9a2153b7c77d2978d9e1c4544535d Reviewed-on: https://review.coreboot.org/c/coreboot/+/68275 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-12treewide: Use 'pm2_cnt_len' for 'x_pm2_cnt_blk.bit_width'Elyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I040ddab8845cc2191c6ca5af7f132ec8a504bccf Reviewed-on: https://review.coreboot.org/c/coreboot/+/68274 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-12treewide: Use 'gpe0_blk' for 'x_gpe0_blk.addrl'Elyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I05d5097097b925a7bc8058f4c23e7c13a49f03c5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68273 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-12treewide: Use 'gpe0_blk_len' for 'x_gpe0_blk.bit_width'Elyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I581cacb6086d94fe65e6f4800454f447e1ada07b Reviewed-on: https://review.coreboot.org/c/coreboot/+/68272 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-12treewide: Use 'fadt->pm_tmr_len' for 'x_pm_tmr_blk.bit_width'Elyes Haouas
Change-Id: Id4e2939b74ec93f50a4bedd0069090f0775b0556 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68271 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-12treewide: Use 'fadt->pm1_cnt_len' for 'x_pm1a_cnt_blk.bit_width'Elyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I4e468e6bb58adc44bd66149eb79dc885dbf73c67 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68270 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-12treewide: Use 'fadt->pm1_evt_len' for 'x_pm1a_evt_blk.bit_width'Elyes Haouas
Change-Id: I1e51ccad32f1c5e692c76b331eedf4d3bb260d38 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68269 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-12soc/intel/ehl: Fix incorrect access to MAC_MDIO_DATA registerMario Scheithauer
Function 'setbits16' performs an 'OR' operation with the new data and the origin register entry. This can lead to an incorrect value in the register which can then lead to issues. Change-Id: I0212420be770e2ffdabebbfaf5dfbf8d99d25915 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68214 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>