| Age | Commit message (Collapse) | Author |
|---|
|
Update embedded controller firmware version for SMBIOS type 0.
TEST=Execute "dmidecode -t 0" to check if the ec version is correct
Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Change-Id: Ibd5ee27a1b8fa4e5bc66e359d3b62e052e19e8a2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45138
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Add socket designation in type 4 smbios.
TEST=Execute "dmidecode -t 4" to check if the socket designation is correct
Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Change-Id: Icfdc201bd5b5921816bdce6c009a9db48c997e2e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45443
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Add trackpad, touchscreen, and usb port to devicetree
BUG=b:160664447
BRANCH=NONE
TEST=build bios and verify theirs function for boten
Signed-off-by: alec.wang <alec.wang@lcfc.corp-partner.google.com>
Change-Id: I057f7d15d20d1a78acd733cc5463357e9c87afb2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45732
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
Tested on out-of-tree CML-U Purism board
Change-Id: I0371e913a75e47b8e6f5a3e4da47b1e401a72b5d
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45929
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add SPD support for DDR4 memory part H5ANAG6NCJR-XNC.
Eldrid should use DRAM_ID strap ID 4 (0100) on SKUs populated
with H5ANAG6NCJR-XNC DDR4 memory parts.
BUG=b:161772961
TEST="FW_NAME=eldrid emerge-volteer coreboot" and verify it builds
successfully.
Change-Id: Ia26315479ce1a749a0f7c9e81f134f7068d7eb0b
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45963
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Add SPD support for DDR4 memory part H5ANAG6NCJR-XNC.
BUG=b:161772961
TEST=none
Change-Id: I71e4de9a28f78bbf8c7de1fcafa3596276a5f2f9
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45962
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
The kernel driver enumerates communities 0, 1, 4, and 5, and assigns
these addresses based on the BARs enumerated by coreboot. Coreboot
was defining communities 0, 1, 2, 4, and 5. This meant the kernel
was not controlling GPIOs in communities 4 and 5, since the resources
were wrong.
Remove community 2 for now. We can add it back if the kernel ends up
needing it.
BUG=b:169444894
TEST=Test controlling GPP_E5, verify actually toggles register.
Signed-off-by: Evan Green <evgreen@chromium.org>
Change-Id: I823e1aa942cfccadde01b9371d481457ab088c31
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46115
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This will reduce boot time by 7ms. Some of the initial designs
don't have a pull-up resistor on the CMD line. These designs still boot
at 400 kHz despite not having the pull-up.
BUG=b:158766134
TEST=Boot dirinboz, run integrity test, b:169940185
BRANCH=zork
Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: I6bac8284b67070ff2c5838257f4ae2ead0e69c22
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45934
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Sam McNally <sammc@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This will reduce boot time by 7ms. Some of the initial designs
don't have a pull-up resistor on the CMD line. These designs still boot
at 400 kHz despite not having the pull-up.
BUG=b:158766134
TEST=WIP
BRANCH=zork
Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: I1191d73a2a3f72f99de187a946162460acbb287a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45935
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This will reduce boot time by 7ms. Some of the initial designs
don't have a pull-up resistor on the CMD line. These designs still boot
at 400 kHz despite not having the pull-up.
BUG=b:158766134
TEST=WIP
BRANCH=zork
Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: I2fcbe35103020c3444902c077b4985f87f970671
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45936
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This will reduce boot time by 7ms. Some of the initial designs
don't have a pull-up resistor on the CMD line. These designs still boot
at 400 kHz despite not having the pull-up.
BUG=b:158766134
TEST=Boot on Vilboz with emmc
BRANCH=zork
Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: I9a1e47dbee3fcc7317857d40c5418be30d755d61
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45933
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Ethernet hardware on jecht variants doesn't support AER, so
disable it to mitigate continuous AER timeout errors in dmesg:
> pcieport 0000:00:1c.0: AER: Corrected error received: 0000:00:1c.0
> pcieport 0000:00:1c.0: AER: PCIe Bus Error: severity=Corrected, type=Data Link Layer, (Transmitter ID)
> pcieport 0000:00:1c.0: AER: device [8086:9c94] error status/mask=00001000/00002000
> pcieport 0000:00:1c.0: AER: [12] Timeout
Change-Id: Ieda82c6e13c2bbc4b3a051a3d2a7ae90728ccdc6
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46137
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Ethernet hardware on beltino variants doesn't support AER, so
disable it to mitigate continuous AER timeout errors in dmesg:
> pcieport 0000:00:1c.0: AER: Corrected error received: 0000:00:1c.0
> pcieport 0000:00:1c.0: AER: PCIe Bus Error: severity=Corrected, type=Data Link Layer, (Transmitter ID)
> pcieport 0000:00:1c.0: AER: device [8086:9c94] error status/mask=00001000/00002000
> pcieport 0000:00:1c.0: AER: [12] Timeout
Change-Id: I0f592a21d08e79cda251e80cd1f1184c4311e9df
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46136
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: I741b66e08d977f514f2512d626e3bcf22ce7d46c
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46135
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
Copied from soc/intel/broadwell.
Test: build/boot google/beltino variants, verify L1 PM substates
listed under PCIe device capabilities
Change-Id: Ib2ae3d9539de9f7e22975f00450d9d60d1fd938a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46134
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Several changes[1][2] to the Linux kernel now enable ASPM/AER for the
rt8169 network driver, for which it was previously disabled. This,
coupled with the southbridge enabling AER for all PCIe devices, has
resulted in a large amount of AER timeout errors in the kernel log for
boards which utilize the rt8169 for on-board Ethernet (e.g., google/beltino).
While performance is not impacted, the errors do accumulate.
To mitigate this, guard AER enablement via Kconfig, select it by default
(as to maintain current default behavior), and allow boards which need
to disable it to do so (implemented in subsequent commits).
This implementation is derived from that in soc/intel/broadwell.
Test: build/boot google/beltino variants with AER disabled (CB:46136),
verify dmesg log free of AER timeout errors.
[1] https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=671646c151d492c3846e6e6797e72ff757b5d65e
[2] https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=a99790bf5c7f3d68d8b01e015d3212a98ee7bd57
Change-Id: Ia03ef0d111335892c65122954c1248191ded7cb8
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46133
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
A SATA drive may be connected to SATA0.
BUG=b:162909831
BRANCH=puff
TEST=none
Change-Id: I2a4ce2f89fa6d786358e01add15f2eedfbe4b20f
Signed-off-by: Sam McNally <sammc@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46270
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
|
|
List of changes:
1. Add DDR4 and LPDDR4 memory related code
- SPD for LPDDR4
- DQ byte map
- DQS CPU-DRAM map
- Rcomp resistor
- Rcomp target
2. Fill FSP-M related UPD parameters
3. Add devicetree.cb config parameters related to FSP-M UPD
TEST=Able to build and boot ADL-P RVP till ramstage early
Change-Id: Iffc5c17ed0725f61c8c274a80a1d27161ca6cebf
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46091
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
The patch allows to configure sensors with a remote diode connected
and a on-chip local temperature sensor from the devicetree for the
board that uses this HWM. According to the documentation [1], this is
done by setting the corresponding bits in the Mode Selection Register
(22h). It is necessary for some Intel processors (Apollo Lake SoC)
that do not support PECI and the CPU temperature is taken from the
thermistor.
TEST = After loading the nct7802 module on the Kontron mAL-10 [2] with
Linux OS, we can see configuration of the HWM with one sensor in
the thermistor mode:
user@user-apl:~$ sensors
coretemp-isa-0000
Adapter: ISA adapter
Package id 0: +41.0°C (high = +110.0°C, crit = +110.0°C)
Core 0: +40.0°C (high = +110.0°C, crit = +110.0°C)
Core 1: +40.0°C (high = +110.0°C, crit = +110.0°C)
Core 2: +41.0°C (high = +110.0°C, crit = +110.0°C)
Core 3: +41.0°C (high = +110.0°C, crit = +110.0°C)
nct7802-i2c-0-2e
Adapter: SMBus CMI adapter cmi
in0: +3.35 V (min = +0.00 V, max = +4.09 V)
in1: +1.92 V
in3: +1.21 V (min = +0.00 V, max = +2.05 V)
in4: +1.68 V (min = +0.00 V, max = +2.05 V)
fan1: 0 RPM (min = 0 RPM)
fan2: 868 RPM (min = 0 RPM)
fan3: 0 RPM (min = 0 RPM)
temp1: +42.5°C (low = +0.0°C, high = +85.0°C)
(crit = +100.0°C) sensor = thermistor
temp4: +44.0°C (low = +0.0°C, high = +85.0°C)
(crit = +100.0°C)
temp6: +0.0°C
[1] page 30, section 7.2.32, Nuvoton Hardware Monitoring IC NCT7802Y
with PECI 3.0 interface, datasheet, revision 1.2, february 2012
[2] https://review.coreboot.org/c/coreboot/+/39133
Change-Id: I28cc4e5cae76cf0bcdad26a50ee6cd43a201d31e
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39766
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: Ia5ad0715b742427dffa6c0c507269d904fe19bcb
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45372
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Allows to change the I2C bus frequency by overriding i2c_frequency
option from the board devicetree. Thus, the I2C controller can use
Fast-mode (Fm), with a bit rate up to 400 kbit/s and Fast-mode Plus
(Fm+), with a bit rate up to 1 Mbit/s [1].
Tested on Kontron mAL10 COMe module with T10-TNI carrierboard [2].
[1] I2C-bus specification and user manual, doc #UM10204, Rev. 6,
4 April 2014.
[2] https://review.coreboot.org/c/coreboot/+/39133
Change-Id: If0eb477af10d00eb4f17f9c01209f170b746ad3d
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44476
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This change drops maxsleep parameter from chip config and instead
hardcodes the deepest sleep state from which the WiFi device can wake
the system up from to SLP_TYP_S3. This is similar to how other device
drivers in coreboot report _PRW property in ACPI. It relieves the
users from adding another register attribute to devicetree since all
mainboards configure the same value. If this changes in the future, it
should be easy to bring the maxsleep config parameter back.
BUG=b:169802515
BRANCH=zork
Change-Id: I42131fced008da0d51f0f777b7f2d99deaf68827
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46033
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
This change adds a call to `pci_dev_is_wake_source()` to determine and
log WiFi wake source to event log just like the Intel WiFi driver
does. This is done in preparation to merge the generic and Intel WiFi
drivers in follow-up changes.
BUG=b:169802515
BRANCH=zork
Change-Id: I20528ae1f72ca633da31e01d777c46fd5f4a337f
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46032
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
This change uses the newly added `pci_dev_is_wake_source()` helper function
to determine and log WiFi wake source instead of assuming a hard-coded
register value to check. This is done in preparation to merge the
generic WiFi and Intel WiFi drivers in coreboot in follow-up changes.
BUG=b:169802515
BRANCH=zork
Change-Id: I9bdb453092b4ce7bdab2969f13e0c0aa8166dc0a
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46031
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
This change adds a helper function `pci_dev_is_wake_source()` that
checks PME_STATUS and PME_ENABLE bits in PM control and status
register to determine if the given device is the source of wake.
BUG=b:169802515
BRANCH=zork
Change-Id: I06e9530b568543ab2f05a4f38dc5c3a527ff391e
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46030
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Move all files with register definitions into a `registers` subfolder.
Subsequent commits will move the remaining registers into this folder.
Tested with BUILD_TIMELESS=1, Packard Bell MS2290 remains identical.
Change-Id: I872269ca3c7fbbcffe83327a20bcf8d98b356beb
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45381
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
Several registers have been copy-pasted from i945 and do not exist on
Ironlake. Moreover, other register definitions were missing. Use the
newly-added definitions in existing code, in place of numerical offsets.
Tested with BUILD_TIMELESS=1, Packard Bell MS2290 remains identical.
Change-Id: I8ac99166a8029dcdbb59028b4a7ee297249de5db
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45380
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
Use the device aliases provided by tigerlake chipset.cb instead of
the raw pci device+function. Take advantage of the default states
in chipset.cb and only list the devices that are enabled for all
volteer variants.
Change-Id: I5620004afd7fa4d50389f32dd79148960a2b2662
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44039
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add aliases for devices and set most of them to off with the exception
of some essential devices.
Set a default register value as an example.
Change-Id: If50269808645ddc019e0d94fa8296df58ab7c367
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44038
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This change extends the devicetree override one more layer and allows
the chipset to provide the base devicetree. This allows the chipset to
assign alias names to devices as well as set default register values.
This works for both the baseboard devicetree.cb as well as variant
overridetree.cb.
chipset.cb:
device pci 15.0 alias i2c0 off end
devicetree.cb:
device ref i2c0 on end
BUG=b:156957424
Change-Id: Ia7500a62f6211243b519424ef3834b9e7615e2fd
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44037
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
HPD on this bridge chip is a bit useless. This is an eDP bridge so the HPD is
an internal signal that's only there to signal that the panel is done powering up.
But the bridge chip debounces this signal by between 100 ms and 400 ms (depending on process,
voltage, and temperate). One particular panel asserted HPD 84 ms after it was powered on
meaning that we saw HPD 284 ms after power on. Assume that the panel driver will have the
hardcoded delay in its prepare and always disable HPD.
Change-Id: Iea7dd75b57fa55ec182c0bee09b0f35208357892
Signed-off-by: Vinod Polimera <vpolimer@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45706
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
|
|
Don't use the silicon-specific struct type to get common config
options. Instead, use the generic config_t typedef. This allows
the function to be moved to common code in upcoming patches.
Change-Id: If80b678037b4d79387e0a0f722c540df4aae2416
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46057
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Currently, trogdor devices have a section RO_DDR_TRAINING that is used
to store memory training data. Changing so that we reuse the same
mrc_cache API as x86 platforms. This requires renaming
RW_DDR_TRAINING to RW_MRC_CACHE and removing RO_DDR_TRAINING in the
fmap table.
BUG=b:150502246
BRANCH=None
TEST=FW_NAME="lazor" emerge-trogdor coreboot chromeos-bootimage
Make sure that first boot after flashing does memory training
and next boot does not.
Boot into recovery two consecutive times and make sure memory
training occurs on both boots.
Change-Id: I16d429119563707123d538738348c7c4985b7b52
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46111
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
|
|
1. Apply the DPTF parameters received from the thermal team.
BUG=b:169183507
TEST=build and verify by thermal tool
Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com>
Change-Id: I1a1a0f9e86e519ac15904fac80cf3c2299213e52
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46087
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
According to document number 338846 and 336062 this should be set to 46 bits.
Change-Id: I0bbe6c962ffc7d5dc722f1cacf55bc0d0615db59
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45868
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
|
|
Without skipping of DRHD generation for non-PCIe stack, the OS
kernel detects incorrect DMAR table with following messages:
[ 0.561817] Your BIOS is broken; DMAR reported at address 0
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: I098605daf12a264f390613581427ec722afcddaf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45887
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Implement mt_fmeter_get_freq_khz() in MT8192 to measure frequency of
some pre-defined clocks by frequency meter.
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Change-Id: I75df0b040ed7ea73d25724a3c80040f4e731118f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45402
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
If Cr50 is running old firmware version and hence does not ensure long
interrupt pulses, override the GPIO PM configuration.
BUG=None
TEST=Build and boot waddledee to OS. Ensure that any chip override
happens before FSP silicon parameter initialization. Ensure that the
suspend/resume sequence works fine. Ensure that the reboot sequence
works fine for 50 iterations.
Change-Id: I455c51d4a63b1b5edadbf00c786ce61b0ba1ff00
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45857
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
ALS is not stuffed in octopus boards. Hence disable ALS ACPI devices.
BUG=b:169245831
BRANCH=octopus
TEST=Ensure that ALS devices are disabled in ACPI tables.
Change-Id: I5ad28f01b0515a41b314116eb2d05c520df0f86e
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45741
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
The BIOS log was looking in the spd data for the part name, but part
names are stripped from generic SPDs. For these cases, a mainboard
can override the dram part number string, so the spd logging code
needs to check for an override string when logging the dram part
number.
Change print_spd_info() to use an override string if declared.
BUG=b:168724473
TEST="emerge-volteer coreboot chromeos-bootimage", flash and boot
volteer2 and verify that the BIOS log shows a part name when
logging SPD information:
SPD: module part number is K4U6E3S4AA-MGCL
I also modified volteer to not override the part name and verified
that this change did as expected and printed a blank string.
Change-Id: I91971e07c450492dbb0588abd1c3c692ee0d3bb0
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45459
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Modify mrc_cache_load current to return the size of the mrc_cache
entry so that caller will know what the actual size of the data
returned is. This is needed for ARM devices like trogdor, which need
to know the size of the training data when populating the QcLib
interface table.
BUG=b:150502246
BRANCH=None
TEST=./util/abuild/abuild -p none -t GOOGLE_NAMI -x -a
Change-Id: Ia314717ad2a7d5232b37a19951c1aecd7f843c27
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46110
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
This will reduce boot time by 7ms. Some of the initial designs
don't have a pull-up resistor on the CMD line. These designs still boot
at 400 kHz despite not having the pull-up.
BUG=b:158766134
TEST=Boot Berknip w/ eMMC to OS.
BRANCH=zork
Change-Id: I5d55f55b8208b4dc3fbdc9d1ec6333f9e211e3fd
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45931
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Current Ram_Id: 0011 MT40A1G16KNR-075-E never be built before.
Remove it and change use micron-MT40A1G16KD-062E-E for ram_id:0011.
BRANCH=zork
BUG=b:159316110
TEST=run gen_part_id then check the generated files.
Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com>
Change-Id: I28fc39f17e06ecd39f6567613e6ff5919becb2fd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45810
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This will reduce boot time by 7ms. Some of the initial designs
don't have a pull-up resistor on the CMD line. These designs still boot
at 400 kHz despite not having the pull-up.
BUG=b:158766134
TEST=Boot Ezkinil w/ eMMC to OS.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ida0bbf9bd772ab7d384d5d097fa3b02b846a3efa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45852
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Eric Peers <epeers@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This will reduce boot time by 7ms. Some of the initial designs
don't have a pull-up resistor on the CMD line. These designs still boot
at 400 kHz despite not having the pull-up.
BUG=b:158766134
TEST=Boot on morphius with and without patch, confirm ~7ms improvement
BRANCH=zork
Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: I7f6efd3d5839f154f2487a07654be8e35634bbbc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45932
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
We don't want unnecessary die() calls to spread throughout coreboot.
Chances are high that we'd add a NON_FATAL_DIE Kconfig eventually.
Change-Id: I01c7efdf23672bad3a195b7dc1565a3cc8a087bd
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46046
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Update TSR1 passive trip temperature
BUG=b:169691800
BRANCH=None
TEST=Built and tested on dedede system
Change-Id: I172391daca981d5591fa9cc5eacad92521dd0dc5
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45859
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
|
|
BUG=b:167472333
TEST=Build and boot dedede and observe the slope and offset values
getting updated in the fsp debug log
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Change-Id: I3ea32218040263f0abef9b9dd4c52efb16289fd7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45825
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This CL fixes the CPU Throttling issue.
BUG=b:167472333
TEST=Build and boot dedede and observe the slope and offset values
getting updated in the fsp debug log
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Change-Id: I3fa32218040263f0abef8b9dd4c52efb31289fd7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45645
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
This reverts commit 69589294c205b616e80cafbbfb0b33e105a75386.
No reason was given why this should deviate from the other platforms
and the author can't explain it.
Change-Id: I2e8d6f9bd4ebba69b6f7cdd9a1c5d08aaf2e798f
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46044
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Change-Id: Ib329648f77acecccb0ced1806f61be252d03f2f4
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45869
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Print chipset as hex value in order to make it more readable.
Change-Id: Ifafbe0a1161e9fe6e790692002375f45d813b723
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45867
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Implement mainboard_silicon_init_params() to allow for disabling of
TBT root ports if the device does not have usb4 hardware.
Add code to mainboard_memory_init_params() to disable memory-related
settings associated with TBT in cases where no usb4 is available.
BUG=b:167983038
TEST=none
Change-Id: Iab23c07e15f754ca807f128b9edad7fdc9a44b9d
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45946
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
|
|
Make boot state init run before the init_chips code. This allows for
correcting tbt settings at a stage earlier than devicetree parsing.
BUG=b:167983038
TEST=none
Change-Id: I8364746ba311575e7de93fa25241ffef7faf35b4
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45961
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Override smbios_fill_dimm_locator for type 17 Locator and Bank Locator.
Also remove CONFIG(GENERATE_SMBIOS_TABLES) compile option because SMBIOS
is always enabled and it makes the code cleaner.
One sample type 17 table displayed as below:
Handle 0x0010, DMI type 17, 40 bytes
Memory Device
...
Locator: DIMM F0
Bank Locator: _Node0_Channel5_Dimm0
Tested=On OCP Delta Lake, the Locator and Bank Locator strings
are expected.
Change-Id: I84531f9ee8bc76d9529aa983bc13e64f40c93138
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45799
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
For now only implement for one socket and some of the fields
are hard-coded for DDR4 including memory device type, data width
and ECC support.
Change-Id: I3cb72d18027d972140828970206834ff55b72022
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45798
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
The fields from SystemMemoryMapHob can be used to generate SMBIOS type 17.
Tested=On OCP Delta Lake, verify the values are expected.
Change-Id: I988e7341ddd3b701c698b41451a87890f21cc928
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45797
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
With CPX-SP FSP, PCH IOAPIC handles the first 120(0x78) GSIs. Correct
the coreboot assignment of GSIs for IO APICs.
Without this patch, there are following target OS boot messages:
[ 1.098771] IOAPIC[0]: apic_id 8, version 32, address 0xfec00000, GSI 0-119
[ 1.099159] GSI range [24-31] for new IOAPIC conflicts with GSI[0-119]
After this patch, the boot messages are:
[ 0.399498] IOAPIC[0]: apic_id 8, version 32, address 0xfec00000, GSI 0-119
[ 0.399848] IOAPIC[1]: apic_id 9, version 32, address 0xfec01000, GSI 120-127
Also without this patch, there is boot stability issue. About one in
20 reboots, the target OS fails to boot with following failure:
[ 4.325795] mce: [Hardware Error]: Machine check events logged
[ 4.326597] mce: [Hardware Error]: CPU 0: Machine Check: 0 Bank 9: ee2000000003110a
[ 4.327594] mce: [Hardware Error]: TSC 0 ADDR fe9e0000 MISC 228aa040101086
[ 4.328596] mce: [Hardware Error]: PROCESSOR 0:5065b TIME 1601443875 SOCKET 0 APIC 0 microcode 700001d
The MCE error happens in bank 9. The Model specific error code
shows it is about SAD_ERR_WB_TO_MMIO error (doc 604926), which means
something goes wrong when cache write back to mmio. It is a generic
transaction type error in level 2.
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: I45e941591300dad6d583a6dcb41f45e984753c07
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45941
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Intel CPX-SP FSP ww40 release adds MeUmaEnable FSP-M parameter,
and adds some fields to HOBs.
Update FspmUpd.h and HOB header files.
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: I3d456be62a5feecdac267c1e8be52e2a25e8aac3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45940
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Rename all mt_pll_raise_ca53_freq() into mt_pll_raise_little_cpu_freq().
Implement mt_pll_raise_little_cpu_freq() in MT8192.
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Change-Id: I97d9a61f39f2eb27f0c6f911a9199bf0eaae4fbe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45401
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
|
|
There's no need to make so much noise when writing IOBP registers.
Change-Id: I1fbb6e409375240544b9b5e810523f9471435f2f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45720
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
|
|
Broadwell does this, so do it on Lynx Point too.
Change-Id: I309f0cbf93e3f75b20cdd049d9437841ef61c03a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45719
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
|
|
Change-Id: I50a783424b0d244eb824db9cd73738108f800003
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45870
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
List of changes:
1. Initial code block to select SOC_INTEL_ALDERLAKE Kconfig
2. Add minimum code to make ADL-P RVP build successfully
3. Mainly bootblock and verstage code added to reach till verstage
4. Add support for 2 mainboards as ADL-P board with default EC (Windows
SKU) and Chrome EC (Chrome SKU)
5. Add empty dsdt.asl to avoid compilation error
TEST=Able to build and boot ADL-P RVP till romstage early.
Change-Id: I2b551f48a4eb4d621d9a86c5d189c517d5610069
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46054
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
TEST=Able to build TGLRVP and JSLRVP.
Change-Id: Ie07df9f59015092a4c2a27b1451f0d556c70f0d8
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46123
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Add gfx.asl file for all IA SOCs to allow for graphics-related ACPI
devices and methods.
TEST=Able to build and boot TGL platform
Dump and disassemble DSDT, verify GFX0 device present as below
Device (GFX0)
{
Name (_ADR, 0x00020000) // _ADR: Address
}
Change-Id: I5560e900a77872552df1064dc3b7a8148e35d682
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46088
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
This patch moves gfx.asl into common block acpi directory to
avoid duplicating the same ASL code block across SoC directory.
TEST=Able to build and boot CML platform.
1) Dump and disassemble DSDT, verify GFX0 device present inside
common gfx.asl is still there.
2) Verify no ACPI error seen while running 'dmesg` from console.
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: Ie34181a6783d348265cf4299dec5c41e7f4f736f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45997
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
To remove the xhci0_force_gen1 and use usb3_port_force_gen1 instead.
The xhci0_force_gen1 is used for force all port on xhci0 to USB3 GEN1.
Now variant can use the usb3_port_force_gen1 to customize which port
it needs to limit.
BUG=b:167651308
BRANCH=zork
TEST=Build, verify the USB3 speed in gen1
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: If5f0c1f22d8c98c4461f09d074bf082c340b14d9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46041
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
In morphius, the USB3 typeA port needs to set to gen1, and for ezkinil
all the USB3 ports should force to gen1. So set the corresponding
setting to usb3_port_force_gen1 to force USB3 to Gen1.
BUG=b:167651308
BRANCH=zork
TEST=Build, verify the USB3 speed in gen1
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: I10419b91fe86fe3e06de36ddfe0d1769c1031f8e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45334
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
Add UPD usb3_port_force_gen1 for support USB3 port force to gen1.
BUG=b:167651308
BRANCH=zork
TEST=Build, verify the USB3 speed in gen1
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: I896c185988c3ea5dbdd72957b363ebdaa2747cff
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45333
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Sam McNally <sammc@google.com>
|
|
VBOOT_STARTS_VEFORE_BOOTBLOCK indicates that verstage starts before
bootblock. However "cbmem -1" will first try to match "bootblock
starting" to find out the beginning of console for current boot.
Change ENV_STRING for verstage to "verstage-before-bootblock" in the
case and add regex in cbmem utility to grab it.
BUG=b:159220781
TEST=flash and boot, check `cbmem -1`
BRANCH=zork
Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: Ica38f6bfeb05605caadac208e790fd072b352732
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46060
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
|
|
The PSP will now pass us data on the PSP boot mode and the production
silicon level. Print these values out to save in the log.
These definitions are in a vendorcode include directory that was
previously only included in verstage. Add the include directory
to all stages.
BUG=b:170237834
TEST=Build & Boot - See values printed.
BRANCH=Zork
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Iee87413d1473786cf0e148a8088d27f8d24a47a1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46113
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Sam McNally <sammc@google.com>
|
|
The transfer buffer check had gotten large enough to deserve a function
of its own, so break it out.
BUG=None
TEST=Build
Branch=Zork
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Idf46f8edb6b70c63f623522e2bcd2f22d6d4790b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46112
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
BUG=b:169199392
TEST=Corrupt vboot signature to force an error, see that the system
halts instead of rebooting forever.
BRANCH=Zork
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I949f94e78d25720f6cd7e81de8d030084e267f29
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45964
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: Id913fc4a89ad5eff6b3487354ff8be7661539fe5
Signed-off-by: Manideep Kurumella <mkurumel@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45705
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
|
|
LIMITS_CFG is not used/required by trogdor. Supporting this requires an FMAP
partition as well as code, removing this support saves space and maintenance
headaches.
Change-Id: I9f57f5b520599ba6d708c91df9851e0e86b4b6c0
Signed-off-by: Manideep Kurumella <mkurumel@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45704
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add support for trackpoint wakeup from S3 by adding device events to
mainboard and defining for morphius.
BUG=b:160345665
BRANCH=zork
TEST=tested trackpoint wake from S3 on morphius DVT
Signed-off-by: Josie Nordrum <josienordrum@google.com>
Change-Id: I982f0f4b60fbaeb389774531e1dee83da77cb8a1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45965
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
psp_verstage uses separate printk implementation, which does not include
code to add console output to cbmem.
Add cbmemc_init and cbmemc_tx_byte to add console output to cbmem.
BUG=b:159220781
TEST=build
BRANCH=zork
Change-Id: I63ba5814903565c372dbeb50004565a371dad730
Signed-off-by: Kangheui Won <khwon@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46059
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Updating from commit id 4bb06cc1:
COIL: Change denylist to blocklist
to commit id 4c523ed1:
vboot2: Add support for modexp acceleration
This brings in 10 new commmits.
Change-Id: Iff6eb99c8ed3046b6fdb6c1e2892aab956f3b562
Signed-off-by: Kangheui Won <khwon@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45986
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Eric Peers <epeers@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
|
|
The PSP bootloader version 0.08.0B.7B added support for the Mod Exp
svc call.
BUG=b:169157796
BRANCH=zork
TEST=build verstage for zork
Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: Ifdbf20544b21b7fa90a49c5497ff4a5da61bebb1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45985
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Eric Peers <epeers@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
|
|
The PSP bootloader version 0.08.0B.7B added support for the Mod Exp
svc call.
BUG=b:169157796
TEST=Build
BRANCH=Zork
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I1ce69c80cec77e1692cf9713a739cc4da4677da6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45942
Reviewed-by: Eric Peers <epeers@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
`pci_dev_init()` is used to load and run option ROM on VGA class
devices (PCI_CLASS_DISPLAY_VGA). WiFi device is not a VGA class device
and hence the call to `pci_dev_init()` is not required. This change
drops the call to `pci_dev_init()` from `wifi_pci_dev_init()` in Intel
WiFi driver.
BUG=b:169802515
BRANCH=zork
Change-Id: I6588ea0a5c848904088d05fd1cbdf677b2dc8ea9
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46029
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
WiFi devices supported by the generic WiFi driver are PCIe devices
which need to be managed using the standard pci_dev_* operations to
read, set and enable resources. This change updates the
device_operations structure `wifi_generic_ops` to use the standard
pci_dev_* operations for these devices.
BUG=b:169802515
BRANCH=zork
Change-Id: I8b306259e205ecb963c0563000bd96ec6b978b8b
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46028
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
Add an empty SPD in SPD_SOURCES when creating a new variant of
hatch, volteer, waddledee, or waddledoo, so that coreboot can build
successfully.
For variants that use spd_tools, add an empty mem_parts_used.txt so
that the developer can add the supported memory parts and regenerate
the Makefile.inc with the correct SPD references.
Add an empty SPD for LPDDR4x for waddledee and waddledoo to use.
BUG=b:169422833
TEST=create a new variant of hatch, volteer, waddledee, and waddledoo.
Observe that each one succeeds.
Signed-off-by: Paul Fagerburg <pfagerburg@google.com>
Change-Id: I06dfb6103701bf8949180595f1e98fac48bcc585
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45746
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
|
|
Remove #include "chip.h", which is not needed and causes a build
problem in a later change. Alphabetise the #includes. Add <types.h>.
Change-Id: If19ccd144bd352a196adccd75f9f6f139eae4e4a
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45968
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Prepare for common ACPI code.
Move get_srat_memory_entries() from soc_util.c to soc_acpi.c where
the other srat ACPI functions are located.
Change-Id: If26641497e1c16d5cf493490711aa08d6e1cb640
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45846
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Continue preparations for common ACPI code.
Add code from skx and common/acpi to check the SCI register
instead of using a define.
Change-Id: I6b638d28775320894a6ab24ef486e67c181591eb
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45844
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Prepare for common ACPI code. Move skx soc ACPI functions to a
separate file.
Change-Id: I12526c17a0dcbc45494ae19c8abaf8bf9a1eab47
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45843
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Prepare for common ACPI code. Move cpx soc ACPI functions to a
separate file, soc_acpi.c
Change-Id: I4aaca660e2f94d856676681417ae6c5d8c28a1f1
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45842
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Reorder the functions to make it easier to compare with
soc/intel/common/block/acpi/acpi.c and cpx/acpi.c.
Move the xeon_sp specific functions to the top.
Change-Id: I7bc147781261c2fc39374f5bfe3ba79047b4993a
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45841
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Reorder the functions to make it easier to compare with
soc/intel/common/block/acpi/acpi.c.
Move the xeon_sp specific functions to the top.
Change-Id: I9034eb774a14ee1e2f9b16c7bd7673ebad69c113
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45840
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Continue separating the CPU from the PCH.
Move the PCH IRQ ASL from the uncore_irq.asl to a new file,
pch_irq.asl.
Change-Id: Iaf8ae87ecc9f8365cc093516f15d9c5a31c7d1d5
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45839
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Move ACPI macros to a header file to be used in multiple
ASL files.
This could be moved to intel/common in the future to reduce
the amount of duplicate ASL code.
Tested by checking build/dsdt.asl doesn't change.
Change-Id: Id2441763fe335154048c9a584a227a18e8c5391c
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45838
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Remove the NumElements and allow the ASL compiler to fill them in.
This is safer than hard coding the NumElements.
For Package (NumElements) {PackageList}, "If NumElements is absent,
it is automatically set by the ASL compiler to match the number of
elements in the PackageList" ACPI v6.2 sec 19.6.101.
Change-Id: I73df9e31011ad0861d4755fdbcbbd93e4e0b5a51
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45837
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Refer to
commit 0359d9d (soc/intel: Make use of PMC low power program
from common block)
commit 1366e44 (soc/intel: Move pch_enable_ioapic() to common
code)
commit 78463a7 (soc/intel: Move soc_pch_pirq_init() to common code)
commit 8971ccd (soc/intel: Move pch_misc_init() to common code)
for details
Change-Id: Ic83d332cf2bfe8eded1667dd1503e718d854f10b
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46053
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
List of changes:
1. Select common ACPI Kconfig to include common ACPI code block
from IA-common code
2. Select ACPI Kconfig support for wake up from sleep states.
3. Add SoC ASL code in ASL 2.0 syntax for SoC IPs like IPU, ISH,
LAN, HDA etc.
Change-Id: I7509e8c46038b1edfc501db74e763f198efb56ab
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45972
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Adjust Touchscreen delay off values to let suspend off timing match
power down specificatiion.
BRANCH=zork
BUG=b:163434386
TEST=Measuring scope timing
Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com>
Change-Id: I58866122f441cc3c427e659b8a5fdb6643987882
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45785
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
|
|
There is requirement to change PM flow for S0ix along with TBT firmware
update under device attached and no device attached scenarios. This
change invokes D3CE and D3CX in DMA _PS3 and _PS0 respectively.
BUG=b:158777291
TEST=Validated s0ix cycles for USB4 device attached and no device
attached test cases along with updated TBT firmware rev35.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: Iebc8065fe4c8600960d089577608890ab12a95fc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45014
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
This patch makes Fleex EC wake up AP from s0ix when the state of
charge drops to 5%.
Demonstrated as follows:
1. Boot Fleex.
2. Run powerd_dbus_suspend.
3. On EC, run battfake 5.
4. System resumes.
BUG=b:163721887
BRANCH=Octopus
TEST=Verified on Fleex:
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Change-Id: I4a998ad0aef5a7cfc6fd18995bde5571e6127e77
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45967
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
|
|
Add case for LPDDR4x to spd_get_name().
BUG=b:169800932, b:168724473
TEST=none
Change-Id: I6bae373468b8ad5ae0a6b8dd6bbe14143afb85af
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45886
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
