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2024-09-21soc/intel/ptl: Remove usb2_port_reset_msg_en config structure fieldJeremy Compostella
Similarly to what is done in Meteor Lake, the PortResetMessageEnable UPD can be set based on usb2_port[].type_c setting and therefore usb2_port_reset_msg_en is not necessary. BUG=b/348678529 TEST=Build for fatcat Change-Id: I914f73ff06bfb801fc319b45b23d7ce4cb7a6d57 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84429 Reviewed-by: Pranava Y N <pranavayn@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-09-21soc/intel/ptl: Provide the TCSS port policy setting optionsJeremy Compostella
Each TCSS port can be associated a setting via the tcss_cap_policy device tree field. The setting can be picked within five values listed by this commit. BUG=b/348678529 TEST=fatcat board build tcss_cap_policy[0]=TCSS_TYPE_C_PORT_FULL_FUN Change-Id: I914f73ff06bfb801fc319b45b23d7ce4cb7a6d56 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84419 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Pranava Y N <pranavayn@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-09-20efi: Set EFIAPI to 32-bit ABI for FSP1_1Jeremy Compostella
Because PLATFORM_USES_FSP2_X86_32 default to false when PLATFORM_USES_FSP1_1, efi_datatype.h wrongly defines EFI as __attribute__((__ms_abi__)). TEST=When some code involved in the build of a platform using FSP 1.1 such as Google/CYAN includes efi_datatype.h, it does not hit the following error: '__ms_abi__' calling convention is not supported for this target Change-Id: I914f73ff06bfb801fc319b45b23d7ce4cb7a6d5d Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84402 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-20mb/intel: Correct number of jacks in hda_verb.cNicholas Sudsgaard
This was found due to the `_Static_assert()` from CB:84360 failing. Change-Id: I08881e3fb25abca8c34a04b3bea6534c0dbf391a Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84424 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-20Makefile.mk: Skip unnecessary recompiles when static.{c,h} are updatedNicholas Chin
The generated static.c file output by sconfig is currently added as a prerequisite for all objects to ensure that static.h exists before compiling anything that might need it. However, this forces every single object out of date when the compiled devicetree is updated, even though not every file actually needs static.h. Only static.h actually needs to exist before compilation of other objects, since static.c is an independent compilation unit that doesn't need to exist before other objects can be built. Thus, change the prerequisite from static.c to static.h, and add a rule for static.h that depends on static.c. The recipe is a simple `true` since sconfig generates static.c and static.h at the same time. To prevent unnecessary recompiles, make static.h an order-only prerequisite [1] using the new generated files argument for create_cc_template to ensure that the header exists before any object might need it, but without forcing a recompile of all objects by default whenever it is updated. On a clean build, all objects will be compiled since they do not exist, and these will occur after static.h is generated due to the default order-only prerequisite. On subsequent incremental compiles, sources that do need static.h will be appropriately marked out of date due to the generated .d dependency files from the compiler, which list static.h as a normal prerequisite for each objects that do include it, which overrides the default order-only prerequisite. The dependency files generated for all other objects will not include static.h, and thus the objects will not be updated since the default order-only dependency does not force them out of date. After updating the devicetree of qemu-i440fx after a clean build, comparing the build log with `make --debug=why` with the generated dependency files indicates that only objects that actually depend on static.h were rebuilt, instead of every object. Running a timeless incremental build after making a change in the devicetree yielded identical roms when performed with this patch and main, with the only difference being the number of objects that needed to be rebuilt. Also tested with the E6430. [1] https://www.gnu.org/software/make/manual/html_node/Prerequisite-Types.html Change-Id: I34efc162760ae703285f3982fa16cc23a86b37f6 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84387 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-20Makefile: Allow defining order-only prerequisites in create_cc_templateNicholas Chin
Generated files such as static.h are currently added as prerequisites for all compilation units to ensure that they exist and are up to date before anything that might need them is compiled. However, this has the side effect of forcing every compilation unit out of date when such files are regenerated, even if the object has no dependency on the generated file. GNU Make has order-only prerequisites [1] which are used to define prerequisites that must be updated before a given target, but which don't force the target out of date. Add a new argument to create_cc_template, similar to the "additional dependencies" argument, which allows dependencies on such generated files for a specified object class and source suffix to be defined. This new functionality will be utilized in subsequent commits to fix up the dependencies on generated files. Objects that do depend on generated headers will still be handled correctly due to the .d dependency files that are generated by the compiler during the build, which declare normal prerequisites to any headers an object directly or indirectly includes. As per the GNU Make documentation, normal prerequisites take precedence over order-only prerequisites, so the header dependencies declared in the .d files will override the order-only one declared through create_cc_template. This does mean that a necessary rebuild of an object due to a generated file may be missed if the dependency file from the compiler is missing, but this is an unusual situation that is unlikely to occur during normal incremental builds. [1] https://www.gnu.org/software/make/manual/html_node/Prerequisite-Types.html Change-Id: I50d87b3d9012967eefb197be12b2e0f096b0b67c Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84386 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-09-20soc/mediatek/common: Correct eMMC src clk frequency to 400 MHzkiwi liu
Mediatek SoCs start operating at eMMC clock around 3MHz right after power-on due to wrong src_hz value. In JEDEC spec, eMMC clock needs under 400kHz. When we need to set a clock output frequency, we actually set a frequency division value. Originally, we set the source clock frequency to 50MHz, the target frequency to 400KHz, and get the division value 128. However, the actual source clock frequency is 400MHz, so the final actual output is 400MHz/128=3.125MHz. So we correct source clock frequency to 400MHz for eMMC output clock of 400KHz. BUG=b:356578805 TEST=test boot ok; measure eMMC clock ok; no boot time impact Change-Id: I9c8836b23fb21e9b0bdc80fbe85142ea0fa5e381 Signed-off-by: Mengqi Zhang <mengqi.zhang@mediatek.corp-partner.google.com> Signed-off-by: Kiwi Liu <kiwi.liu@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84298 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com>
2024-09-20soc/intel/common/block/acpi: Fix GPE1 blocks to ACPI FADT tableCliff Huang
Use CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1 to add GPE1 block rather than checking if GPE1_STS(0) is '0'. BUG:362310295 TEST=with the flag, boot google/fatcat or intel/ptlrvp to OS and check that FADT table includes GPE1. FADT should have: GPE1 Block Address : 00001810 GPE1 Block Length : 18 GPE1 Base Offset : 80 Without the flag, boot to OS and check that FADT table does not include GPE1. FADT should have: GPE1 Block Address : 0 GPE1 Block Length : 0 GPE1 Base Offset : 0 Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: Idd8115044faff3161ea6bd1cae6c0fe8aa0ff8d7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/84392 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-09-20mb/google/dedede/var/beadrix: Add LTE only daughterboard supportKevin Yang
Due to beadrix DB has C1 port before, and add FW_CONFIG without C1 port for LTE sku. BUG=b:364431483 BRANCH=firmware-dedede-13606.B TEST=emerge-dedede coreboot chromeos-bootimage Set fw config to DB_PORTS_LTE and check 1.fw_config match found: DB_PORTS=DB_PORTS_LTE <= show LTE present message 2.USB3 port 3: enabled 1 <= LTE port enable Change-Id: Ica5a2d6e19421b132a0bdbad77806a17e2c1ce69 Signed-off-by: Kevin Yang <kevin.yang@ecs.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84232 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-09-19mb/google/brox: Remove psys related implementationSowmya Aralguppe
psys is not an optimal solution for no/low battery boot. Hence remove function and macros related to psys implementation. BUG=b:335046538 BRANCH=None TEST=Build and boot on brox board Change-Id: I6c0e9561367b5846b00be27012f002dd7c299414 Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84397 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-19mb/gigabyte/ga-945gcm-s2l: Correct number of jacks in hda_verb.cNicholas Sudsgaard
This was found due to the `_Static_assert()` from CB:84360 failing. Change-Id: I01db9dad872cd4c9238b6c6aac73f3e6367710a4 Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84416 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-09-19mb/system76/oryp9: Correct number of jacks in hda_verb.cNicholas Sudsgaard
This was found due to the `_Static_assert()` from CB:84360 failing. Change-Id: I3870bcd2482e55a5abcbd27cd0be18f25a35afbc Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84415 Reviewed-by: Tim Crawford <tcrawford@system76.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-19mb/system76/mtl: Enable gfx register for GMA ACPITim Crawford
Add gfx register so GMA ACPI data is generated. Fixes brightness controls on Windows. Change-Id: I10948fb2ba670ba5232f1b116acdd1820ad0c07d Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84224 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-09-19soc/intel/mtl: Hook up GMA ACPI brightness controlsJeremy Soller
Add function needed to generate ACPI backlight control SSDT, along with Kconfig values for accessing the registers. Change-Id: Ied08e5e9fe4913bd60474ed7dcf88b945172558d Signed-off-by: Jeremy Soller <jeremy@sysetm76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82729 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-09-19soc/intel/common/block/acpi: exclude DMI fixed memory range if no DMICliff Huang
In newer SOC, such as PTL, there is no DMI. Exclude DMI memory range in northbridge.asl if DMI_BASE_SIZE is '0' BUG=b:348678529 TEST=Build CB with DMI_BASE_SIZE set to '0' in the SOC directory. Boot to OS and check ACPI PDRC device from the ACPI DSDT table. There should not have an entry for DMI in its _CRS method. Verified on Intel® Simics® Pre Silicon Simulation platform for PTL using google/fatcat mainboard. Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: I971af2eb214b5940fa09d9dc0f9717bb5f0dfb4d Reviewed-on: https://review.coreboot.org/c/coreboot/+/84349 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-19mb/google/nissa/var/riven: enable WIFI SARDavid Wu
According to the CL:chrome-internal:7651905, Riven will use the fw_config to separate SAR setting. CNVI + ID_0 --> wifi_sar_0.hex for WIFI6 PCIE + ID_1 --> wifi_sar_9.hex for WIFI7 BUG=b:366060274 TEST=build, enabled iwlwifi debug, and check dmesg as below. iwl_sar_fill_table Chain[0]: iwl_sar_fill_table Band[0] = 132 * .125dBm iwl_sar_fill_table Band[1] = 136 * .125dBm iwl_sar_fill_table Band[2] = 136 * .125dBm iwl_sar_fill_table Band[3] = 136 * .125dBm iwl_sar_fill_table Band[4] = 136 * .125dBm iwl_sar_fill_table Band[5] = 144 * .125dBm iwl_sar_fill_table Band[6] = 144 * .125dBm iwl_sar_fill_table Band[7] = 144 * .125dBm iwl_sar_fill_table Band[8] = 144 * .125dBm iwl_sar_fill_table Band[9] = 144 * .125dBm iwl_sar_fill_table Band[10] = 144 * .125dBm iwl_sar_fill_table Chain[1]: iwl_sar_fill_table Band[0] = 132 * .125dBm iwl_sar_fill_table Band[1] = 136 * .125dBm iwl_sar_fill_table Band[2] = 136 * .125dBm iwl_sar_fill_table Band[3] = 136 * .125dBm iwl_sar_fill_table Band[4] = 136 * .125dBm iwl_sar_fill_table Band[5] = 144 * .125dBm iwl_sar_fill_table Band[6] = 144 * .125dBm iwl_sar_fill_table Band[7] = 144 * .125dBm iwl_sar_fill_table Band[8] = 144 * .125dBm iwl_sar_fill_table Band[9] = 144 * .125dBm iwl_sar_fill_table Band[10] = 144 * .125dBm Cq-Depend: chrome-internal:7651905 Change-Id: I647d64a008991a7a20791b2c87ea6308af6bb82e Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84339 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-09-19soc/intel/ehl/fsp_params: Do not re-enable 'PchPwrOptEnable' for real-time ↵Mario Scheithauer
tuning If real-time tuning was enabled, 'PchPwrOptEnable' was set two times with different values. This patch fixes the issue. BUG=none TEST=Enabled FSP UPD debug output and checked 'PchPwrOptEnable' offset Change-Id: I2f31015c1da51a4ae1b8d5226f5d7b60a6023f3d Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84399 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-18mb/siemens/{mc_ehl2,mc_ehl3,mc_ehl5}: Enable real-time tuning in FSPMario Scheithauer
The real-time feature should also be activated for all mc_ehl mainboards, as it has already been done for mainboard mc_ehl1. It improves performance in the real-time environment for these mainboards. Change-Id: I04859b2f32bc11344b0620925f2414e7a6df625e Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84391 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-18mb/google/brox: Switch USB-C port locationsJameson Thies
The ordering of the USB-C port locations is swapped. When facing the left panel, the correct ordering is port 1 (left) then port 0 (right). Swap the positions of the two USB-C ports to their correct values. BUG=b:349822718 TEST=Booted to OS, confirmed correct physical_location at /sys/class/typec. Change-Id: I98e3042c64aba885b602c99916734c2dbb9d66bd Signed-off-by: Jameson Thies <jthies@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84403 Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-18lib/jpeg: return string (not int) error messagesNigel Tao
Change-Id: I465a6eebc2a41ca9a618b1e86dee015cea40800b Signed-off-by: Nigel Tao <nigeltao@golang.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84341 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-09-18soc/intel: Move CSE update ELOG to cse_lite.cSubrata Banik
The ELOG for CSE updates was being added in fsp_params.c, but the actual update happens in cse_lite.c. This commit moves the ELOG to cse_lite.c to more accurately reflect where the event is happening. This also removes the need for a sol_type variable in meteorlake/romstage/fsp_params.c. It also helps to avoid redundant ELOG event entry while performing CSE update (due to CSE RO to RW switch dependency). BUG=b:361253028 (Multiple CSE sync elog prints for Nissa/Trulo) TEST=Able to see only one instance of ELOG while performimg CSE sync. w/o this patch: elogtool list 0 | Log area cleared | 4088 1 | Kernel Event | Clean Shutdown 2 | Early Sign of Life | MRC Early SOL Screen Shown 3 | Early Sign of Life | CSE Sync Early SOL Screen Shown 4 | System boot | 29 5 | Memory Cache Update | Normal | Success 6 | Early Sign of Life | CSE Sync Early SOL Screen Shown w/ this patch: elogtool list 0 | Log area cleared | 4088 1 | Early Sign of Life | MRC Early SOL Screen Shown 2 | Memory Cache Update | Normal | Success 3 | System boot | 30 4 | Memory Cache Update | Normal | Success 5 | Early Sign of Life | CSE Sync Early SOL Screen Shown Change-Id: I37fe3f097e581f79bf67db1ceb923f10ce651d62 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84398 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Jakub Czapiga <czapiga@google.com> Reviewed-by: Jayvik Desai <jayvik@google.com>
2024-09-18mb/facebook/fbg1701: Correct number of jacks in hda_verb.cNicholas Sudsgaard
This was found due to the `_Static_assert()` from CB:84360 failing. Change-Id: I60bb9e7df368b786e17bb49a6f35d27372fd21de Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84394 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-18mb/msi/ms7e06: Correct number of jacks in hda_verb.cNicholas Sudsgaard
This was found due to the `_Static_assert()` from CB:84360 failing. Change-Id: I5cf34d8c4e27835d126eb66f2015d2e9d93b700f Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84396 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2024-09-18soc/intel/ptl: Add SoC ACPI directory for Panther LakeRavi Sarawadi
List of changes: 1. Select common ACPI Kconfig to include common ACPI code block from IA-common code 2. Select ACPI Kconfig support for wake-up from sleep states. 3. Add SoC ASL code for SoC IPs like IPU, HDA etc. 4. PTL replaces DMI3 with SAF to ensure common/block/acpi/acpi/northbridge.asl binding with PTL change, #if DMI_BASE_SIZE guard check is added in northbridge.asl 5. include GPIO ASL that supports new pinctrl schema. BUG=b:348678529 TEST=Verified on Intel® Simics® Pre Silicon Simulation platform for PTL using google/fatcat mainboard. Change-Id: Ia5cf899b049cb8eb27b4ea30c7f3ce7a14884f15 Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83772 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-09-17mainboard/google/{brox,brya}: Drop redundant CRASHLOG configSubrata Banik
This commit drops redundant CRASHLOG option for the brox and brya mainboards as SOC_INTEL_CRASHLOG config is now selected by the Alder Lake SoC directly. TEST=Able to build and boot google/brox w/o any functional impact of the crashlog feature. Change-Id: I83859d6e61a151d6930785df3466c185c69e8e66 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84366 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-17soc/intel/alderlake: Enable CRASHLOG for Chrome OSSubrata Banik
Enable the CRASHLOG config option for Chrome OS boards. This allows the Chrome OS crash reporter to collect and analyze crash dumps, aiding in debugging and improving system stability. TEST=Able to build and boot google/brox Change-Id: Ia23ef1cbebdba9a3b724204eb25ee788afa3e8fd Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84365 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-09-17mb/ocp/tiogapass: Update dead links in the documentationAlicja Michalska
Change-Id: I685d1aaabab0cb14f88025cdc80d86342e354a63 Signed-off-by: Alicja Michalska <alicja.michalska@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84388 Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-17mb/google/brya/var/trulo: Update ISH GPIO config for tablet mode switchVarun Upadhyay
This patch configures the GPIO pins for ISH to notify EC about the tablet mode change in accordance with schematic_20240607. BUG=b:347811875 TEST=Build and boot google/trulo. Placed the device in tabletmode & on EC console,"tabletmode" command shows "tablet mode". Change-Id: Id22e397e46b522428ffdabe34a445ed7e4fb6fc5 Signed-off-by: Varun Upadhyay <varun.upadhyay@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84351 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-09-17Revert "soc/intel/meteorlake: Skip the TCSS D3 cold entry sequence"Subrata Banik
This reverts commit 88a496a9c81ba6447a4c1453a45d09ee79f30309. This workaround is not valid with the latest Intel PRQ silicon, so I'm dropping it now. Additionally, able to boot to ChromeOS without any hang, and I also ran an S0ix cycle without any failures. BUG=b:244082753 TEST=Able to boot google/rex0 to CrOS. Change-Id: Idf0da5841705888d2787f61dd6e6fada2fbe3e3e Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84368 Reviewed-by: Jakub Czapiga <czapiga@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-17mb/google/brya: Drop redundant entries of crashlog configSubrata Banik
This patch removes the redundant crashlog config (SOC_INTEL_CRASHLOG) entry from BOARD_GOOGLE_BRYA0 and BOARD_GOOGLE_BRASK. BOARD_GOOGLE_BRYA_COMMON already selects a crashlog config, and brya0/brask board eventually selects the BOARD_GOOGLE_BRYA_COMMON config, making SOC_INTEL_CRASHLOG redundant. TEST=Successfully built and booted google/brya0. Change-Id: Iaff7954d4dafb4c6ca72a1521dfb434fb36b495a Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84364 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-17mb/google/brox: Drop redundant entries of crashlog configSubrata Banik
This patch removes the redundant crashlog config (SOC_INTEL_CRASHLOG) entry from BOARD_GOOGLE_BASEBOARD_BROX. BOARD_GOOGLE_BROX_COMMON already selects a crashlog config, and brox baseboard eventually selects the BOARD_GOOGLE_BROX_COMMON config, making SOC_INTEL_CRASHLOG redundant. TEST=Successfully built and booted google/brox. Change-Id: Idcb03d13ee3943f188246663d47f47cb8afccbd9 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84363 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-09-16soc/amd/common/psp/psb: add missing newline in debug messageFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I794899fa55b510e6f39dadc1a831b86389ab31ca Reviewed-on: https://review.coreboot.org/c/coreboot/+/84355 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-09-16mb/google/volteer: Fix USB port definitionsMatt DeVillier
Commit bc8f5405b542 ("tgl mainboards: Move usb{2,3}_ports settings into XHCI device scope") not only moved the USB port definitions under the XHCI device reference, but also combined multiple register definitions. In doing so, it broke the inheritance from the baseboard, since the variant overridetree registers now replaced the entire usb2_ports/ usb3_ports structs, rather than replacing individual array elements therein. This resulted in any USB ports inherited from the baseboard and not overridden by the variant being non-functional as they were not included in the resulting combined devicetree. To fix this, return to overriding individual array elements in the usb2/3_ports structs. TEST=build/boot google/drobit. Verify all USB ports present and functional. Verify mainboard/static.c in built shows all ports. Change-Id: I54921fa4ecf594a1ecbcfa7c45e5d745d4a95652 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84348 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2024-09-16mb/google/brox/jubilant: Update cpu power limit settingsRen Kuo
1)Modify jubilant cpu power limit setting depend on the brox baseboad settgins,refer to CL: https://review.coreboot.org/c/coreboot/+/83752 2)Update PL1,PL2, and PL4 value from jubilant thermal design PL1 = 15W PL2 = 41W PL4 = 87W BUG=b:364441688 BRANCH=None TEST=Able to successfully boot on jubilant photo SKU1 and SKU2 boards with AC w/o battery. Test on AC 65W and 45W w/o battery,and check the PL values. Change-Id: I9a143d9faaa6c57b0d314c0ff6c0e55f556d7216 Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84219 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
2024-09-14ec/google/chromeec: Optimize battery string readout with cachingSubrata Banik
This commit refactors the long battery string implementation to include caching of the EC response for battery information (model, serial, and manufacturer). This optimization reduces resume time by approximately 63ms by minimizing communication overhead between the AP and EC. BUG=b:366338622 TEST=Verified on google/tivviks_ufs: * Long battery string is displayed when EC_GOOGLE_CHROMEEC_READ_BATTERY_LONG_STRING is enabled. * Short battery string is displayed when EC_GOOGLE_CHROMEEC_READ_BATTERY_LONG_STRING=n. Change-Id: I32ae5b5e618f20335f3d344811a97f1416df529e Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84354 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2024-09-14ec/google/chromeec: Add option to control reading long battery stringsSubrata Banik
Older ChromeOS devices (pre-CR50) do not support reading long battery strings. This commit adds a Kconfig option, EC_GOOGLE_CHROMEEC_READ_BATTERY_LONG_STRING, to enable or disable this feature. This allows devices with TPM_GOOGLE (CR50/TI50) to read and display long battery strings, while older devices like google/link, wolf, samus, and chell will continue to display only the first 8 characters. This change ensures compatibility with older devices while enabling the display of complete battery information on newer platforms. BUG=b:366338622 TEST=Verified on google/tivviks_ufs: * Long battery string is displayed when EC_GOOGLE_CHROMEEC_READ_BATTERY_LONG_STRING is enabled. * Short battery string is displayed when EC_GOOGLE_CHROMEEC_READ_BATTERY_LONG_STRING=n. Change-Id: I7859809278b7e926bbe8beb1a0a9e12c7e6c220d Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84352 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2024-09-14mainboard/intel/avenuecity_crb: Update full IIO configurationShuo Liu
Change-Id: I88baa159475ac57ec6a2a638ab84f76a6af4fe82 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84318 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-13mb/google/brox: Fix booting to kernel without batterySowmya Aralguppe
When battery is disconnected and only adaptor is connected higher PL2 power draw causes cpu brown out and system does not boot to kernel. To avoid this set Boot frequency UPD to 1. Reduce PL4 value to overcome power spikes from SoC during boot. Remove Psys implementation as it impacts active state platform performance. BUG=b:335046538,b:329722827 BRANCH=None TEST=Able to successfully boot on 3 different Brox proto2 SKU1 and SKU2 boards with 65W, 45W and 30W adaptors for 3 iterations of cold boot. Change-Id: I58e136c607ea9290ecac0cee453d6632760a6433 Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83752 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-09-13Documentation/mb/starlabs/byte_adl: Correct titleSean Rhodes
Change-Id: Ia35c656a66c623e88579cf4b9e894c77a404c375 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84280 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
2024-09-13mb/google/brask/var/bujia: Fix PSYS voltage settingShon
It return 0 when google_chromeec_command() on success, so get_input_power_voltage() should return adaptor voltage instead of psys_config default value. BUG=b:329037849 BRANCH=firmware-brya-14505.B TEST= cbmem -c | grep -i PsysPmax Change-Id: I848c92752b7a7b53f47c6296aad0bdda20e9b0bd Signed-off-by: Shon <shon.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84333 Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-13util/autoport: Make printing of SPDX headers genericNicholas Chin
Previously, Add_gpl() was only used with C and ASL source code files, and was hard coded to use the C /* */ style comment, preventing it from being used with files with other comment styles. Convert this into a generic function for adding arbitrary SPDX license identifiers for arbitrary filetypes. This replaces the hard coded GPL-2.0-or-later string used in gma-mainboard.ads with a call to the new function. This is also used to add SPDX headers to Kconfig and Makefile sources; as previous commits added them to all such files in the tree. Tested against logs from a Latitude E6430 (Ivy Bridge) and Precision M6800 (Haswell) to check that license headers that were already being generated did not change. Change-Id: I24a1ccd0afb7045e878bf6eaae7a23f828a9240d Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83184 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-09-13amdfwtool: Add PSP backup directory for A/B recoveryZheng Bao
Change-Id: Ia5a745c86595554c83cd13a35c312c17987b716b Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75682 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-13soc/intel/xeon_sp/gnr: Support full IIO UPD configurationsShuo Liu
Change-Id: Iebfadffd2da83992af983b8c0dfe2706f81eb728 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84317 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-13configs: Disable graphics on intel/archercity CRBShuo Liu
Change-Id: Ic78190a6bff233388bf52fdbb94fa3d7812010f2 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84320 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-09-13soc/intel/xeon_sp/gnr: Move CPU ID definition to common headerJincheng Li
Change-Id: I816c6f68840c122fbc37085e31a1b0368a819f4a Signed-off-by: Jincheng Li <jincheng.li@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84313 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-13soc/intel/xeon_sp/gnr: Enlarge MAX_CPUS to 512Jincheng Li
GNR-AP supports up-to 128 cores/256 threads per socket. Enlarge MAX_CPUS to 512 = 128*2*2 with 2 socket configuration considered. Change-Id: I8dc46dcdd3ca1c3ddfa47fbb28912a2c6e4c46fa Signed-off-by: Jincheng Li <jincheng.li@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84312 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-13vc/intel/fsp/fsp2_0/graniterapids: Update FSP headersJincheng Li
FSP n-1 headers in vc/intel/fsp/fsp2_0/graniterapid are updated to pass compilation with full platform codes. Change-Id: I1d13ddd4db8409a4928bd1bf152a9c284d138e48 Signed-off-by: Jincheng Li <jincheng.li@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84303 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-09-13soc/intel/xeon_sp/gnr: Use default DCACHE_BSP_STACK_SIZEGang Chen
For Xeon-SP, DCACHE_BSP_STACK_SIZE is by default 0x10000. For GNR, this default size is enough. Use the default size so that more CAR spaces could be saved for other purpose. Change-Id: I68a79df150c4954ef8d703987d7c0bb446ba4cda Signed-off-by: Gang Chen <gang.c.chen@intel.com> Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84302 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-13soc/intel/ptl: Do initial Panther Lake SoC commit till ramstageSaurabh Mishra
List of changes: 1. Add required SoC programming till ramstage. 2. Include only required headers into include/soc. 3. Skeleton code used to call FSP-S API. BUG=b:348678529 TEST=Verified on Intel® Simics® Pre Silicon Simulation platform for PTL using google/fatcat mainboard. Change-Id: I61930726ad0c765bfa1d72c5df893262be884834 Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84332 Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-09-13soc/intel/cmn/block/cpu: Simplify calculation of non-eviction waysSubrata Banik
The calculation of non-eviction ways (used for cache-as-ram configuration) has been simplified by removing conditional move instructions and directly adding the remainder to the quotient. This achieves the same ceiling operation but with potentially improved efficiency (less instructions). No functional changes are expected. TEST=Able to build and boot google/rex. Change-Id: I7cf5ff19ec440d049edc3bf52c660dea96b1f08a Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84236 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
2024-09-12mb/google/brox: Set PCIE WLAN bluetooth companion deviceKarthikeyan Ramasubramanian
To publish the Bluetooth Regulator Domain Settings under the right ACPI device scope, the wifi generic driver requires the bluetooth companion to be set accordingly. BUG=b:362672785 TEST=Build Brox firmware and boot to OS. Ensure that the BRDS table is populated under the right ACPI device scope. Scope (\_SB.PCI0.XHCI.RHUB.HS10) { Name (BRDS, Package (0x02) { 0x00000001, Package (0x0A) { 0x00000012, 0x00000001, 0x00000001, 0x7C, 0x70, 0x70, 0x70, 0x70, 0x70, 0x70 } }) } Change-Id: I9a74a995bca8d412b85c243c7f2f98c9917b5e76 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84296 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bob Moragues <moragues@google.com>
2024-09-12mb/google/brox/var/brox: Enable ASPM for PCIe4 SSD of CPUKarthikeyan Ramasubramanian
Check that lnkCap supports ASPM L1, so set it to ASPM_L1 to avoid excessive power consumption. BUG=b:363854853 TEST=emerge-brox sys-boot/coreboot sys-boot/chromeos-bootimage Change-Id: I386f8e88a5af661b1f4c04d2e2a34cd181608bd8 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84278 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: <srinivas.kulkarni@intel.com>
2024-09-12amdfwtool: Set the fields when the header is createdZheng Bao
The fields spi_block_size and base_addr of regular PSP header, lookup and reserved of combo header, are constants. So we move the setting statements to the creation functions. Only update the count, size and fletcher in later function file_dir_header. TEST=Binary identical test on all AMD SOC platforms Change-Id: I55c400e45536a57841b01d7c90d3fef9afa53e78 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84130 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-09-12soc/mediatek: Remove redundant struct pad_func and PAD_* definitionsYidi Lin
Clean up redundant `struct pad_func` and `PAD_*` definitions. This patch also refactors the PAD_* macros by, - Repurposing PAD_FUNC and dropping PAD_FUNC_SEL. - Adding PAD_FUNC_DOWN and PAD_FUNC_UP to avoid the implicit initialization. BUG=none TEST=emerge-{elm, kukui, asurada, cherry, corsola, geralt, rauru} coreboot Change-Id: I12b8f6749015bff52988208a7c3aa01e952612c6 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84222 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-12payloads/edk2/Makefile: detect invalid commit hash on checkoutSergii Dmytruk
There is already a check for invalid reference, however `git rev-parse reference` doesn't fail on unknown commit hash unless `^{object}` peeling operator is used (`^{commit}` can be used as well). Change-Id: I7ef39aeee2e902ac2fad6ac41b546c47418e1dec Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84292 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-09-12payloads/edk2: Update default branch for MrChromebox repo to 2024-08Matt DeVillier
Update the default branch used for MrChromebox's edk2 fork from 2023-09 to 2024-08. This updated branch has been rebased on the latest upstream stable tag (edk2-stable202408), and updates the EFI filesystem drivers which had been causing some issues with bootable USBs created using Rufus as it tried to unload the filesystem drivers and load its own. TEST=build/boot google boards link, panther, lulu, reef, ampton, akemi, banshee, zork, dewatt, frostflow with edk2 payload selected. Change-Id: I459b668345ed2a34e198e6a3d3a2da94b2940e69 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84293 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-12amdfwtool: Add a unified function to add combo entriesZheng Bao
TEST=Binary identical test on all AMD SOC platform with use_combo Change-Id: I41c5c6fb5acf92604dd06becf1eda680a1fab545 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84131 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-12amdfwtool: Add combo new layout for new familyZheng Bao
The new layout definition has a new way to support combo. It packs multiple ISH entries into PSP L1 directory. TEST=Identical test on all AMD platform Change-Id: If573cdeaeb56e95d2fed235c9337fab82d622757 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84233 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-09-12mb/google/brox/variants/brox: remove PL4 value modificationSumeet Pawnikar
Remove PL4 value modification based on PsysPL3 value. BUG=None BRANCH=None TEST=Built and boot on brox system Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Change-Id: Ic7fbc6386769aa9f76a8665a742c97dfd790fd1d Reviewed-on: https://review.coreboot.org/c/coreboot/+/83662 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-09-11soc/intel/raptorlake: Fall back to Intel microcode repoFelix Singer
With the release 20240910 of the Intel microcode repository, it also includes the updated microcode file with version 0x129, which makes the one from the coreboot blobs repo superfluous. Thus, use the one from the Intel repository again. Change-Id: I7fb58874719a8373072419e34b3f8923f7db927d Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84295 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-113rdparty/intel-microcode: Update submodule to upstream mainFelix Singer
Updating from commit id 2f56505: 2024-08-14 19:59:27 -0600 - (microcode-20240813 Release) to commit id fbfe741: 2024-09-10 12:02:03 -0600 - (microcode-20240910 Release) This brings in 1 new commits: fbfe741 microcode-20240910 Release Change-Id: If66975c71ade0f08b81fb90d0a91e61ca3405804 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84294 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-11mb/google/brox/var/lotso: Update verb tableJian Tong
Correct the number of NID entries. BUG=b:349996984 TEST=emerge-brox sys-boot/coreboot sys-boot/chromeos-bootimage Change-Id: I5f5553a5d8014f957d6b89ac4c1039594817bf32 Signed-off-by: Jian Tong <tongjian@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84184 Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-09-11mb/google/brox/var/jubilant: Enable ASPM for PCIe4 SSD of CPURen Kuo
Enable ASPM of CPU PCIe4 for SSD to improve power consumption. BUG=b:364441213 BRANCH=None TEST="sh -c 'lspci -vvnn || lspci -nn'" 01:00.0 Non-Volatile memory controller LnkCtl: ASPM L1 Enabled Change-Id: I4380bb8748f2847b1824e20edb19578c7aedfe4f Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84279 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-09-11soc/intel/cml, pci_ids: Remove IDs of non-existent graphics devicesMaxim Polyakov
These identifiers are not included in the GPU list from Intel [1]. At the same time, 0x9B44 is not PCI DID of graphics device at all: 8086:9B44 - 10th Gen Core Processor Host Bridge/DRAM Registers [2]. [1] https://web.archive.org/web/20240731152818/https:// dgpu-docs.intel.com/devices/hardware-table.html [2] https://web.archive.org/web/20231004011832/https://devicehunt.com/ view/type/pci/vendor/8086/device/9B44 Change-Id: I8ff7b062f930cb63ffd9caf240874742bd53fc23 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83862 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2024-09-11soc/intel/cml, pci_ids: Fix IDs for Intel Comet Lake-S/H GT1Maxim Polyakov
According to the Intel GPU list [1], these devices have the following IDs: 8086:9BA8 - Comet Lake-S GT1 [UHD Graphics 610] [2] 8086:9BA5 - Comet Lake-S GT1 [UHD Graphics 610] 8086:9BA4 - Comet Lake-H GT1 [UHD Graphics 610] [3] 8086:9BA2 - Comet Lake-H GT1 [UHD Graphics 610] Allows coreboot to correctly initialize IGD (8086:9ba8) in Intel Celeron G5905 CPU (ID a0653, Cometlake-H/S G1 (6+2), ucode: 000000f9). This can also be verified using devicehunt.com [2,3]. [1] https://web.archive.org/web/20240731152818/https:// dgpu-docs.intel.com/devices/hardware-table.html [2] https://web.archive.org/web/20240731150632/https://devicehunt.com/ view/type/pci/vendor/8086/device/9BA8 [3] https://web.archive.org/web/20230928015210/https://devicehunt.com/ view/type/pci/vendor/8086/device/9BA4 Change-Id: I776f434f3627d6fbd046a92eb736b1ffcac8274a Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83861 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2024-09-11soc/intel/cml, pci_ids: Fix ID for Comet Lake-H GT2Maxim Polyakov
According to the Intel GPU list[1], 0x3E9B is DID of "Intel UHD Graphics 630" for the Coffee Lake processor family and has already been added to the pci_ids.h as PCI_IDE_INTEL_CFL_H_GT2. At the same time, the real PCI DID for Comet Lake-H GT2 is 0x9BC2 [1], which is missing in the file. [1] https://web.archive.org/web/20240731152818/https:// dgpu-docs.intel.com/devices/hardware-table.html Change-Id: Iacab0a03388af3f6fd5d78a597580037889e8ef2 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83708 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2024-09-11util/lint/lint-final-newlines: Supply dirs in rowMaximilian Brune
This just orders the EXCLUDED_DIRS directories in a row based manner, since there are quite a few them now and it is arguably easier to read and to add new directories if they are written in a row based fashion. Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I802aece355bba4900e71824d802c4b2438726e84 Reviewed-on: https://review.coreboot.org/c/coreboot/+/83872 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2024-09-11tree: Use boolean for dmi_power_optimize_disableElyes Haouas
Change-Id: Ifbe76bd69d847603345a4a1fa4f41e529634fa92 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84158 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-11tree: use boolean for hybrid_storage_modeElyes Haouas
Change-Id: I84aad5497d17065f9d42776452f2d2d24cd50a91 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84157 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-09-10tree: Use boolean for lpss_s0ix_enableElyes Haouas
lpss_s0ix_enable is already defined as boolean: `git grep lpss_s0ix_enable $(find -type f -name "*.h") src/soc/intel/apollolake/chip.h: bool lpss_s0ix_enable;` Change-Id: I34bd568defe202daaad6136b9c184bc292a226b3 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84160 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2024-09-10intel/alderlake: Order Kconfig selectors for FSP pathsNico Huber
Should make the sorting order of the paths more obvious. Change-Id: Ie73e717f37f80a11a903e99cc094ea4d76e1ca1f Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83827 Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-10intel/alderlake: Drop redundant Client/AlderLake* FSP pathsNico Huber
The Alder Lake "Client" FSP paths have been replaced by symlinks to Raptor Lake in the FSP repo. Hence we get the same files anyway and can spare us to maintain the individual paths. Change-Id: Ia9b256ce1940894e2cf31acaa4a83ea39f6723b6 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83826 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2024-09-10mb/google/brox/var/lotso: Enable ASPM for PCIe4 SSD of CPUWentao Qin
Check that lnkCap supports ASPM L1, so set it to ASPM_L1 to avoid excessive power consumption. BUG=b:364484621, b:361828368 TEST=emerge-brox sys-boot/coreboot sys-boot/chromeos-bootimage w/o this CL - ``` lspci -vv | grep -A30 "KIOXIA" | grep -E "LnkCap|LnkCtl" LnkCap: Port #0, Speed 16GT/s, Width x4, ASPM L1, Exit Latency L1 <64us LnkCtl: ASPM Disabled; RCB 64 bytes, LnkDisable- CommClk+ ``` w/ this CL - ``` lspci -vv | grep -A30 "KIOXIA" | grep -E "LnkCap|LnkCtl" LnkCap: Port #0, Speed 16GT/s, Width x4, ASPM L1, Exit Latency L1 <64us LnkCtl: ASPM L1 Enabled; RCB 64 bytes, LnkDisable- CommClk+ ``` Change-Id: I8a7f69bb82ad24b29566541d7694f87f9c6458d6 Signed-off-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84241 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: wen zhang <zhangwen6@huaqin.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-10mb/starlabs/starbook/adl: Add USB ACPI to devicetreeSean Rhodes
Change-Id: I7050a4d12efd65c7026abf3e45961e2061b7170a Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84263 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-09-10mb/starlabs/starbook/adl: Remove PMC GPIO routingSean Rhodes
These aren't used so remove them Change-Id: I340b3474fba1bc7fbde520138ae99c3e355882bf Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84262 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-09-10mb/starlabs/starbook/adl: Alphabetize and group FSP UPDsSean Rhodes
Change-Id: I63612af7320dfdbe57029b898b4cf07e9d6f13b0 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84261 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-09-10ec/starlabs/merlin: Don't report the battery serial number to ACPISean Rhodes
Reporting the battery serial number to ACPI causes Windows to say there isn't a battery present. As the serial number is as useful as waterproof towel, don't do it. Change-Id: I97a28b1d8d7bb45ea4790c8125cd3c1bc52ee5f9 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83633 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-09-10ec/starlabs/merlin: Move the chip id checkSean Rhodes
As the merlin EC supports both the IT8987 and IT5570, move the check into the code so the same variant directory can be used for both chips. Change-Id: I8c43a367e42f7e56ddd26b1c8fe7bf4b275d4ac3 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83632 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-10mb/dell/snb_ivb_latitude: Move early_init.c out of variantsNicholas Chin
Now that the USB configs are in the devicetree, only the bootblock_mainboard_early_init function remains in early_init.c. It is identical between every variant except the E6230, which enabled fewer decode ranges in the LPC_EN register. Enabling the additional decode ranges probably shouldn't cause issues, so go with the majority. TEST=Timeless builds do not change with the exception of the E6230. Change-Id: Ic43915888f5893652991b7402ebab3bd3a2cf278 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84097 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-09-10util/ifdtool: Exit with failure on unrecognized flagsHsuan Ting Chen
ifdtool will exit with success while encountering an unrecognized flag. For example, -g is a newly introduced flag, when we want to call it with an older version of ifdtool, we will get the return value 0 and cause confusion. This patch change the exit status for unrecognized flags and doesn't change the exit status for -h and -?. BUG=b:362983041 BRANCH=none TEST=futility update --servo --image /var/tmp/image.bin --quirks unlock_csme on the servo host with old ifdtool Signed-off-by: Hsuan Ting Chen <roccochen@google.com> Change-Id: I046ad7ec790cda41a98a1de5cd730d32f65a9067 Reviewed-on: https://review.coreboot.org/c/coreboot/+/84260 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-09-10mb/google/nissa/var/teliks: Update eMMC DLL tuning valueszengqinghong
Update eMMC DLL tuning values for improved initialization reliability. BUG=b:361013271 TEST=Cold reboot stress test over 2500 cycles Change-Id: Icd1f9c7bdec2bc99152a13ac4ce0724a26718a52 Signed-off-by: Qinghong Zeng <zengqinghong@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84248 Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-by: Jayvik Desai <jayvik@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-10mb/google/nissa/var/joxer: Use `DB_USB` to probe conn1 deviceSubrata Banik
Joxer experienced error messages during developer mode entry due to failed USB-C1 probing. This patch adds the `DB_USB DB_1C` probe directive to the `conn1` device in the overridetree, ensuring USB-C1 is only probed when `FW_CONFIG` supports the applicable hardware SKU. This should resolve the error flood seen during dev mode entry on Joxer. BUG=b:364240631 TEST=Able to build and boot google/joxer to OS without any error. w/o this patch: send_packet: CrosEC result code 9 send_packet: CrosEC result code 3 Failed to get PD_MUX_INFO port1 ret:-3 update_all_tcss_ports_states: port C1: get_usb_pd_mux_info failed send_packet: CrosEC result code 9 send_packet: CrosEC result code 3 Failed to get PD_MUX_INFO port1 ret:-3 w/ this patch: No error reported during dev mode entry Change-Id: I8cdefa01409d5a8a75032f30dacde40057e064dd Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84255 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-09-10include/console/system76_ec.h: Remove unused <stddef.h>Elyes Haouas
Change-Id: I3ac96786b4bbf7c8b3a8b57f58df396b1b754bd3 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83953 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-10nb/amd/agesa/agesa_helper.h: Remove unused <stddef.h>Elyes Haouas
Change-Id: I991ce1e264c3ca01bc34904b5efe758a3eb58806 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83952 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-10cpu/x86/smm/smm_module_handler: Remove <commonlib/bsd/compiler.h>Elyes Haouas
<commonlib/bsd/compiler.h> is automatically included. Change-Id: I653f6c6099512c6e5ab64207f99e7813e4403f05 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83045 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2024-09-09Docs: Revert false MyST Parser toctree conversionsNicholas Chin
Commit 35599f9a6671 (Docs: Replace Recommonmark with MyST Parser) converted recommonmark style toctrees in bulk using a script. This was done by searching for lists of references, which is how recommonmark denoted toctree entries. However, this also converted lists of external URLs, which would not normally be included in the toctree. Revert these cases back to lists of URLs as they were before the migration. Change-Id: Ie4da3d908d4b84c2c7e3572fb4baaeed1f8edb45 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84244 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-09-09Doc/rmodules.md: Move to libNicholas Chin
The content of this page fits lib the best, which also reflects the location of the rmodule runtime code in the src tree. This also fixes a "document isn't included in any toctree" warning from Sphinx since it is now added to the lib/index.md toctree. Change-Id: I86545f4c1a7e1b3ccefa4f6085e764536f33f29c Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84240 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-09-09Doc/rmodules.md: Change header levelsNicholas Chin
Increase the header levels of headers following the initial "Relocatable Modules (rmodules)" so that there is only one title for the page with the other headings as subheadings. Also fix header capitalization while we're here. Change-Id: I72ae99ba10bf5b2386da2cc702efaf25328d6811 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84239 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-09intel/alderlake: Sort FSP paths, most specific selectors firstNico Huber
The `!FSP_USE_REPO` is most specific, if we're not using the FSP repo, we can ignore all the FSP-repo paths. Hence put these first. Having `FSP_TYPE_IOT` selected is also more specific, we can ignore all the "Client" paths then. This makes sure that we don't catch a "Client" by accident (otherwise we'd have to add a `!FSP_TYPE_IOT` for those). Change-Id: Ibe9931d8f964a337c46fde31a3bc22c69d40eded Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83825 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
2024-09-09util/cbfstool: Print max empty entry size in error messageYu-Ping Wu
Currently, cbfstool prints the following error message when the added file doesn't fit in the region: E: Could not add [file, 1024 bytes (1 KB)@0x0]; too big? It requires manual inspection to know the space left in the region. To make that easier, also print the maximum empty CBFS entry size in the error message: E: Could not add file [header 76 + content 1024 bytes (1 KB)] @0x0; Largest empty slot: 512 bytes Change-Id: I00bcc83abe8b0a33dcd7b75521e6cfccd8953661 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84204 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com>
2024-09-09soc/mediatek/common: Move common GPIO definitions to gpio_defs.hYidi Lin
BUG=none TEST=emerge-{asurada, cherry, corsola, geralt, rauru} coreboot Change-Id: If35dcc4d88732f92c7c43a5eed0478ec52cf1802 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84221 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-09soc/amd/cezanne: Add an option to enable A/B recovery schemeZheng Bao
Extracted from NDA spec #56995: "The A/B recovery scheme formally separates the SPI flash space into different partitions; a primary, “A” and secondary, “B”, which hold the same set of system firmware. Under this scheme, the partitions A and B can hold identical contents initially, but each partition can be updated individually. Normally the system boots from partition A, but if the A partition is found to be corrupted, the system will switch to partition B and boot. The OEM BIOS can then choose to continue the boot from partition B, or repair partition A using contents from partition B." The Cezanne platform supports both A/B recovery and no recovery method. It needs this flag passed to amdfwtool to enable the A/B recovery layout. Change-Id: Id1c8028faee9c544628d65fd77be2a378ed7eab6 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84195 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-09-09mb/google/zork: Add Kconfig to set IGD UMA allocation via APCBMatt DeVillier
Add a Kconfig choice to select the IGD UMA allocation, which selects a precompiled ACPB binary with the corresponding UMA value set. Default to the previous value (128MB) for non-ChromeOS builds, and 64MB for ChromeOS as that is the value used there. TEST=build/boot google/morphius, verify UMA size changes with selection via dxdiag tool under Windows. Change-Id: I6debd10527c33ce37ef3ada20955c8f7b7500039 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84237 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-09Docs/mb/starlabs/byte_adl.md: Fix embedded rST syntaxNicholas Chin
MyST Parser uses {eval-rst} to denote embedded reStructuredText blocks, not eval_rst as was previously used by recommonmark. Change-Id: I3476d205605675690eb0d434f4ae9b7b2f091748 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84238 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-09soc/intel/xeon_sp: Reserve MMIO high rangeShuo Liu
Xeon-SP supports MMIO high range, a.k.a. MMIO range above 4G. FSP will assign domain MMIO high windows from this range. However, there will be unassigned parts among these high windows for non-domain device usage (e.g. misc devices belonging to an IIO stack but not belonged to any PCIe domains under that stack). This will cause segmentation in MTRR UC coverage. For example, in SPR-XCC where only CPM0/HQM0 are supported and instantiated to PCIe domains, MMIO ranges are still reserved for CPM1/HQM1. See more at src/soc/intel/xeon_sp/spr/ioat.c. Reserve MMIO high range as a whole under domain0/00:0.0. During MTRR calculation, this reservation will connect the discontinued domain MMIO high windows together to form one continuous range, and save MTRR register usage from inadequacy. This change is initially raised for SPR but could be effective for GNR as well. TESTED = Build and boot in intel/archercity CRB, MTRR register usage decreases from 7 to 3 in 2S system. TESTED = Only setting MTRR for below 4GB ranges test fails with LinuxBoot on SPR (through x86_setup_mtrrs_with_detect_no_above_4gb) tsc: Detected 2000.000 MHz processor last_pfn = 0x2080000 max_arch_pfn = 0x10000000000 x86/PAT: Configuration [0-7]: WB WC UC- UC WB WP UC- WT WARNING: BIOS bug: CPU MTRRs don't cover all of memory, losing 129024MB of RAM. ------------[ cut here ]------------ WARNING: CPU: 0 PID: 0 at arch/x86/kernel/cpu/mtrr/cleanup.c:978 mtrr_trim_uncached_memory+0x2b9/0x2f9 ... Call Trace: ? 0xffffffff8f600000 ? setup_arch+0x4bb/0xaed ? printk+0x53/0x6a ? start_kernel+0x55/0x507 ? load_ucode_intel_bsp+0x1c/0x4d ? secondary_startup_64_no_verify+0xc2/0xcb random: get_random_bytes called from init_oops_id+0x1d/0x2c with crng_init=0 ---[ end trace 0e56686fd458f0c5 ]--- update e820 for mtrr modified physical RAM map: modified: [mem 0x0000000000000000-0x0000000000000fff] reserved ... modified: [mem 0x00000000ff000000-0x000000207fffffff] reserved last_pfn = 0x6354e max_arch_pfn = 0x10000000000 Memory KASLR using RDRAND RDTSC... x2apic: enabled by BIOS, switching to x2apic ops Using GB pages for direct mapping ... Initmem setup node 0 [mem 0x0000000000001000-0x000000006354dfff] DMA zone: 28769 pages in unavailable ranges DMA32 zone: 19122 pages in unavailable ranges BUG: unable to handle page fault for address: ff24b56eba60cff8 BAD Oops: 0000 [#1] SMP NOPTI CPU: 0 PID: 0 Comm: swapper Tainted: G W 5.10.50 #2 ... Call Trace: ? set_pte_vaddr_p4d+0x24/0x35 ? __native_set_fixmap+0x21/0x28 ? map_vsyscall+0x35/0x56 ? setup_arch+0xa00/0xaed ? printk+0x53/0x6a ? start_kernel+0x55/0x507 ? load_ucode_intel_bsp+0x1c/0x4d ? secondary_startup_64_no_verify+0xc2/0xcb CR2: ff24b56eba60cff8 ---[ end trace 0e56686fd458f0c6 ]--- RIP: 0010:fill_pud+0xa/0x62 ... Kernel panic - not syncing: Attempted to kill the idle task! ---[ end Kernel panic - not syncing: Attempted to kill the idle task! ]--- Change-Id: Ib2a0e1f1f13e797c1fab6aca589d060c4d3fa15b Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83538 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-09-08mb/dell/snb_ivb_latitude/*/hda_verb.c: Use AZALIA_PIN_DESC macroNicholas Chin
Use the AZALIA_PIN_DESC macro from include/device/azalia_device.h instead of magic numbers, as well as the enums for each of the register field values. The macros were generated by running util/hda-decoder against the original azalia logs used for the original board ports. TEST=Timeless builds for all variants did not change between main and this patch Change-Id: If5ecee39efbddbba101f820dead82efcb848b6bc Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84099 Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2024-09-08mb/google/kahlee: Add Kconfig to set IGD UMA allocationMatt DeVillier
Add a Kconfig choice to select the IGD UMA allocation. Default to the previous value (32MB). TEST=build/boot google/liara, verify UMA size changes with selection. Change-Id: Ia53d6d39d4f06c896ec13808234144b89da101f8 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84235 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-07soc/intel/ptl: Add GPIOs for Panther Lake SOCCliff Huang
Add definitions for the GPIO pins on Panther Lake SoC, as well as GPIO IRQ routing information and defines for ACPI ASL. For now, add the following GPIO communities and GPIO groups: Comm. 0: GPP_V, GPP_C Comm. 1: GPP_F, GPP_E Comm. 3: CPUJTAG, GPP_H, GPP_A, VGPIO3 Comm. 4: GPP_S Comm. 5: GPP_B, GPP_D, VGPIO ref doc: - PT EDS vol2 - Panther Lake H GPIO Implementation Summary (#817954) BUG=b:348678529 TEST=Verify on Intel Silicon platform for PTL using google/fatcat mainboard. Note that these GPIO changes cannot be verified along as they are merely data structure and defines for the SOC. With the GPIO ASL, we should see the following GPIO instances under /sys/bus/acpi/devices when booting to OS: INTC10BC:00/ INTC10BC:01/ INTC10BC:02/ INTC10BC:03/ INTC10BC:04/ Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: Iae1bc072841214efaec7a10719dbc742f2da795b Reviewed-on: https://review.coreboot.org/c/coreboot/+/83789 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-09-07soc/intel/{common,alderlake}: Add missing ADL-N SKUsMichał Żygowski
Based on DOC #767454 (public) version 1.2. Allows to boot the HARDKERNEL ODROID H4+ with N97 SoC. Without this patch the MCH ID was not recognized and the SA driver did not pick up the stolen ranges, causing the PCI MMIO allocation to be placed in the stolen areas. TEST=Boot HARDKERNEL ODROID H4+ with N97 SoC to Ubuntu 23.04. Change-Id: I0fbdb12c6411e4109e68a13960b4570701629bc9 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84212 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-09-07nb/intel/sandybridge: Add Kconfig to set default IGD allocationMatt DeVillier
Add a Kconfig choice to select the default IGD memory allocation, for users/boards which do not use an option table to set it. TEST=build/boot google/link, verify IGD size changes with selection. Change-Id: I83d57cf4657cfccbb21416c5da05eeff9e95a44f Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84225 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-28 10:38:15 +0000