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2009-01-20This patch makes the recently added assembler debug optional, as it mayStefan Reinauer
cause problems with certain toolchains. This patch will also safe some hard disk space for those of us working on laptops or netbooks with always too small disks. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3876 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-20fix inconsistent user interface naming. don't show compile paths to usersStefan Reinauer
during bootup (trivial) Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3875 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-20fix coding style (trivial)Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3874 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-20Trivial stuff:Stefan Reinauer
* fix a warning that should not be one. * fix capitalization typo Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3873 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-20Check the printk format string against the matching arguments. We haveCarl-Daniel Hailfinger
this type of checking in the v3 code since ages, but v2 will happily compile any code with bogus printk format strings and/or parameters. This can cause real bugs and at least needs to emit a warning, if not an error. Go with a warning for now since most of the flagged format strings are wrong but harmless in a 32-bit x86 environment. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3872 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-19ouch. never do last minute changes. :-(Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3871 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-19First shot at factoring SMM code into generic parts and southbridge specificStefan Reinauer
parts. This should help to reduce the code duplication for Rudolf's K8/VIA SMM implementation... Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Joseph Smith <joe@settoplinux.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3870 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-18flashrom: Fix ICH9 locking register address and add important debug output.FENG yu ning
Signed-off-by: FENG yu ning <fengyuning1984@gmail.com> Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: FENG yu ning <fengyuning1984@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3869 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-16The DBM90T code sets bit 10 in _PSS as part of the control value, butCarl-Daniel Hailfinger
bit 10 is part of NewVID. That means the resulting VID is wrong and causes the processor to crash. The Pistachio code has the same bug. This patch fixes the wrong setting and changes control from a magic and incorrect unexplained value (0xE8202C00) to a combination of explained values and shifts which has the right value (0xE8202800). It is tested on my machine and it survived 200 changes from minimum to maximum frequency every 100 ms under heavy load and under no load. In the long term we want to consolidate all AMD FIDVID code into one generic library file. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Maggie Li has tested it on her DBM690T board. It is ok. Acked-by: Maggie li <Maggie.li@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3868 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-16First part of heterogenous dualchannel support.Carl-Daniel Hailfinger
Do not allow non-identical DIMMs yet, but prepare the code. Calculate tCL related settings per DIMM in a dual channel setup. The check for compatibility will come in a later patch, but since DIMMs still have to be identical, this does not hurt. Factor out tRC calculation to prepare for per-DIMM calculation. Add diagnostic messages to tRC code. Test booted to FILO, behaviour is identical if you ignore the added debug messages (which are switched off by default). Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3867 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-16Refactor K8 rev F DDR2 CL timing retrieval.Carl-Daniel Hailfinger
This will allow usage of compatible DIMMS in a dual channel setup instead of requiring the DIMMS to be identical. Code impact is minimal because a large chunk of code has been moved into a separate function with almost no changes. Tested, yields identical results and identical logs. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3866 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-16Since all K8 targets now have CONFIG_USE_PRINTK_IN_CAR enabled, usingCarl-Daniel Hailfinger
print_* in K8 RAM init does not make sense anymore. Convert almost all print_* to printk_*. This improves readability a lot and makes the code shorter. Reorder the SPD equality checks in the dual channel DIMM compatibility checking code. This is to make sure that we know if any other mismatches are present in the DIMM. The new order eases debugging with the old code. Add a comment about false negatives in that code. This needs to be implemented correctly, but that is hard to do in an efficient way. Check if the DIMMS in a dual channel setup have any compatible CAS latencies. Add better comments to explain why wrong-at-first-glance SPD CL walking code is actually correct. Fix a few typos. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3865 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-15Adds a retry/faildown to SB600 SATA detection logic.Dan Lykowski
SATA port status kept returning 0x1: BAR5+po+28h 1h = Device presence detected but Phy communication not established This patch adds logic to force 1.5g if the drive fails to communicate at 3.0g. Signed-off-by: Dan Lykowski <lykowdk@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3864 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-15amdk8: This patch fixes ram init problems when using the 9W Sempron part.Dan Lykowski
Trying to read the FIDVID register when the processor does not support FIDVID control causes a GP Fault. This patch reads the startup FID from a different MSR. I have verified this patch to work on the dbm690t platform. Signed-off-by: Dan Lykowski <lykowdk@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3863 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-15flashrom: Add ICH opcode debugging.Peter Stuge
Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3862 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-15Similarly to flashchips array, this patch intends to make the tableStephan Guilloux
board_pciid_enables more readable. Signed-off-by: Stephan Guilloux <stephan.guilloux@free.fr> > What real problem does this solve? 1. Next time someone adds a new struct member, we avoid mistakes of ordering of initializers 2. we avoid mistakes in the first place. The .x = y stuff was added for a (good) reason, I think this is an improvement. Acked-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3861 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-13flashrom: Always print address when verification fails, not only with -V.Peter Stuge
Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3860 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-12flashrom: Board enable for GIGABYTE GA-MA78G-DS3HPeter Stuge
This board has 2x MX25L8005 flash chips behind an IT8718F LPC->SPI bridge. The board uses GIGABYTE's patented BIOS failover technology, and at this point we do not know how to control which of the two chips flashrom actually hits. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Yul Rottmann <yulrottmann@bitel.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3859 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-12flashrom: IT8718F works just like IT8716F.Peter Stuge
Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Yul Rottmann <yulrottmann@bitel.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3858 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-12flashrom: Check return value of fscanf()/fwrite()/fread()Peter Stuge
Fix build error on distros with warn_unused_result attributes in glibc. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Yul Rottmann <yulrottmann@bitel.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3857 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-12Check to see if K8 processor is capable of changing FIDVID otherwise it will ↵Dan Lykowski
throw a GP# when reading FIDVID_STATUS Signed-off-by: Dan Lykowski <lykowdk@gmail.com> Acked-by: Zheng Bao <zheng.bao@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3856 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-11flashrom: Update usage in READMEIdwer Vollering
Mimicked from flashrom.c Signed-off-by: Idwer Vollering <vidwer@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3855 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-11Ignore some more sections, created by newer toolchainsPatrick Georgi
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3854 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-08Add erase and write functions to the following chip definitions:Carl-Daniel Hailfinger
AT25DF021 AT25DF041A AT25DF081 AT25DF161 AT25DF321 AT25DF321A AT25DF641 AT25F512B AT25FS010 AT25FS040 AT26DF081A AT26DF161 AT26DF161A AT26DF321 AT26F004 Straight from the data sheets, untested because I lack the hardware. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3853 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-08The flashrom man page has incomplete author/copyright sections and anCarl-Daniel Hailfinger
incorrect license section. - Remove the copyright listings and refer the reader to the source files. - Update the author list to those which have copyright messages in the source files. - Correct the license from GPL v2+ to (GPL v2, with some files under later versions as well) Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3852 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-08This patch improves machine parseability and human readability ofStephan Guilloux
flashchips.c over what's currently in flashrom HEAD. The explicit initialization makes sure any future struct flashchip reordering is not needed. (Except for the case where we need arrays of some of the struct members.) Signed-off-by: Stephan Guilloux <mailto:stephan.guilloux@free.fr> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3851 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-07Add SST49LF020 support.Sven Schnelle
Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3850 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-07Add AMD-768 chipset support.Sven Schnelle
Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3849 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-07Add i631x LPC support.Sven Schnelle
Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3848 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-06The ACPI PSS CPU Pstate table was calculating the frequency incorrectly forMarc Jones
revF CPUs. The 100MHz/200MHz stepping is already handled in the FID setting and doesn't need to be checked to set the fid_multiplier. The multiplier is always 100. Signed-off-by: Marc Jones <marcj303@gmail.com> Acked-by: zheng bao <zheng.bao@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3847 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-06Add support for the Winbond W83627UHG Super I/O.Dan Lykowski
Signed-off-by: Dan Lykowski <lykowdk@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3846 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-29The SB600 RPR documentation does not mention what to do if SATA_BAR0+6Carl-Daniel Hailfinger
is no longer 0xA0 or 0xB0. It simply assumes that will never happen. My 500 GB Seagate Barracuda ST3500820AS triggers that corner case on the first init after poweron. The current code hangs forever with my drive. Fix this by rerunning the init sequence after SATA_BAR0+6 is no longer 0xA0 or 0xB0. Add support for SATA port 2-4 (Primary Slave, Secondary Master, Secondary Slave). If only the 2nd SATA port is connected and the hardware acts strangely (contrary to documentation), it will print the error message below and continue anyway. The official AMD asm code behaves the same way. SATA port 0 status = 0 No Primary Master SATA drive on Slot0 SATA port 1 status = 23 0x6=7f, 0x7=7f drive no longer selected after 0 ms, retrying init [8 repetitions] 0x6=7f, 0x7=7f drive no longer selected after 0 ms, retrying init Primary Slave device is not ready after 10 tries Activate and improve debug messages for SPEW log level. Fix some comments. New log messages look like this: PCI: 00:12.0 init sata_bar0=3020 sata_bar1=3060 sata_bar2=3030 sata_bar3=3070 sata_bar4=3000 sata_bar5=fc309000 SATA port 0 status = 23 0x6=a0, 0x7=80 drive detection not yet completed, waiting... 0x6=a0, 0x7=80 drive detection not yet completed, waiting... [... 281 repetitions ...] 0x6=0, 0x7=50 drive no longer selected after 2820 ms, retrying init drive detection done after 0 ms Primary Master device is ready after 2 tries SATA port 1 status = 23 drive detection done after 0 ms Primary Slave device is ready after 1 tries SATA port 2 status = 0 No Secondary Master SATA drive on Slot2 SATA port 3 status = 0 No Secondary Slave SATA drive on Slot3 With this patch, my Asus M2A-VM boots into Linux without problems. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Zheng Bao <zheng.bao@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3845 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-24Fix AMD Pistachio implicit declarations in the same way as with AMDZheng Bao
DBM690T. Remove trailing whitespace. Signed-off-by: Zheng Bao <Zheng.bao@amd.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3844 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-24Fix implicit declarations in the AMD DBM690T target by using the rightCarl-Daniel Hailfinger
header files. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Zheng Bao <Zheng.bao@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3843 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-23This belongs to changeset: 3840Rudolf Marek
The attached patch adds missing bits to ACPI to make Windows XP and Windows Vista happy. The FADT bootarch flags Blacklists MSI for this chipset (maybe not needed) Adds modified amdk8_util.asl Adds the SSDT table to chain of tables Aligns the FACS correctly (this should be done for other boards) Adds the _CRS method to Asus M2V-MX SE acpi DSDT. Fixes the FACS table length. Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3842 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-23Following patch fixes error code 12 in Windows XP and Vista. The function ↵Rudolf Marek
field of _PRT entry must be always 0xffff (any function). Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-By: Patrick Georgi <patrick@georgi-clan.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3841 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-23The attached patch adds missing bits to ACPI to make Windows XP and Windows ↵Rudolf Marek
Vista happy. The FADT bootarch flags Blacklists MSI for this chipset (maybe not needed) Adds modified amdk8_util.asl Adds the SSDT table to chain of tables Aligns the FACS correctly (this should be done for other boards) Adds the _CRS method to Asus M2V-MX SE acpi DSDT. Fixes the FACS table length. Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3840 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-23Handle RS690 quirks for 1 GHz noncoherent HyperTransport.Carl-Daniel Hailfinger
The RS690 chipset has a problem where it will not work with 1 GHz HT speed unless NB_CFG_Q_F1000_800 bit 0 is set. Tested, works on my Asus M2A-VM with an 1 GHz HT capable processor. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Bao, Zheng says: As a matter of fact, both 600Mhz and 1Ghz have their own specific setting. This patch has been tested on dbm690t which HT link works on 800Mhz. Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3839 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-23Remove a unneccessary typedef from acpi_tables.c in the AMD PistachioCarl-Daniel Hailfinger
and DBM690T targets. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Zheng Bao <Zheng.bao@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3838 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-23Fix implicit declarations of pci_read_config32 and pci_write_config32 inMaggie Li
the SB600 code. Signed-off-by: Maggie Li <Maggie.li@amd.com> Reviewed-by: Zheng bao <Zheng.bao@amd.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3837 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-23Add verbose debugging output at SPEW level to noncoherent HyperTransportCarl-Daniel Hailfinger
initialization. This patch has helped immensely to track down a bug in 690G ncHT init. It depends on my earlier patch which enables CONFIG_USE_PRINTK_IN_CAR for all boards using HT. Of course that means ROMCC is not an option anymore for those boards, but I don't think that's a big problem. Another way to solve this would be #defining printk_spew to nothing. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Marc says: ROMCC doesn't make sense for k8 boards. Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3836 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-22Fix implicit declarations of get_bus_conf.Carl-Daniel Hailfinger
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3835 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-22If you pass a bogus layout file to the -l option flashrom will segfault.Uwe Hermann
Fix that by throwing an error instead. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3834 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-22Add another board-enable line for the Kontron 986LCD-M/mITX.Uwe Hermann
There seem to be at least two versions of the board out there, and the subsystem IDs changed between the versions. Patch successfully tested on hardware. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3833 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-22Fix implicit declarations of pci_read_config8 and pci_write_config8 inCarl-Daniel Hailfinger
the following files: src/mainboard/intel/jarrell/reset.c src/mainboard/supermicro/x6dai_g/reset.c src/mainboard/supermicro/x6dhe_g2/reset.c src/mainboard/supermicro/x6dhe_g/reset.c src/mainboard/supermicro/x6dhr_ig2/reset.c src/mainboard/supermicro/x6dhr_ig/reset.c Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3832 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-22Fix implicit udelay src/southbridge/nvidia/mcp55/mcp55_aza.cCarl-Daniel Hailfinger
Fix imlicit mdelay in src/southbridge/nvidia/mcp55/mcp55_nic.c Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3831 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-22flashrom: Initialize ICH SPI opcodes also for ICH9 and later.Peter Stuge
Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3830 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-22In the process of trying to debug some HT sync problems I added lots ofCarl-Daniel Hailfinger
debug code to src/northbridge/amd/amdk8/incoherent_ht.c. However, printk is not available for all boards at that stage. I have changed the following boards: agami/aruma arima/hdama asus/a8n_e broadcom/blast ibm/e325 ibm/e326 iwill/dk8s2 iwill/dk8x msi/ms7135 newisys/khepri sunw/ultra40 tyan/s2850 tyan/s2875 tyan/s2880 tyan/s2881 tyan/s2882 tyan/s2885 tyan/s2891 tyan/s2892 tyan/s2895 tyan/s4880 tyan/s4882 abuild works fine for all of them. agami/aruma needs a Config-abuild.lb which doesn't have fallback and normal due to size problems. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3829 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-20Fix dell/s1850 broken in r3822, and prepare it for implicit declaration Corey Osgood
error patch. Signed-off-by: Corey Osgood <corey.osgood@gmail.com> Acked-by: Corey Osgood <corey.osgood@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3828 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-20This adds register map based on NSC PC87392 datasheet. LDN#2 can beMichał Mirosław
used for a SIR/FIR device. Signed-off-by: Michał Mirosław <mirq-linux@rere.qmqm.pl> Acked-by: Ulf Jordan <jordan@chalmers.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3827 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-20This adds a mptable for the VIA pc2500e. I've tested with the devicesJonathan A. Kollasch
in the VT8237R, and a card interrupting at Pin-A on either PCI slot. Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3826 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-19Add some comments to make it easier to enable onboard VGA forUwe Hermann
different ROM chip sizes (trivial, tested with 256 KB chip). Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3825 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-19Fix breakage caused by r3822. I should have known not to touch the k8 stuff...Corey Osgood
Signed-off-by: Corey Osgood <corey.osgood@gmail.com> Acked-by: Corey Osgood <corey.osgood@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3824 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-19This patch fixes the build for asus/m2v-mx_se. Its hard_reset function is notMyles Watson
implemented (It just prints "hard_reset not implemented. FIX ME!" This patch defines HAVE_HARD_RESET 1 and adds a #warning hard_reset not implemented. The net effect is that hard_reset prints something instead of just entering an infinite loop. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3823 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-19Fix a LOT of implicit function declarations before they become errors.Corey Osgood
Signed-off-by: Corey Osgood <corey.osgood@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3822 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-19I honestly have no idea if the previous use of the vt8235's serial functionsCorey Osgood
worked or not, but my board doesn't have COM1, and those function don't support using COM2, so I've changed auto.c to use the fintek f71805f functions, the fintek is the onboard super io. I also cleaned up a whitespace issue and unused variable. Signed-off-by: Corey Osgood <corey.osgood@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3821 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-18Fix the only implicit declaration before it becomes an error.Corey Osgood
Signed-off-by: Corey Osgood <corey.osgood@gmail.com> Acked-by: Corey Osgood <corey.osgood@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3820 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-18Fix implicit declaration in cn700/vt8237 codeCorey Osgood
Signed-off-by: Corey Osgood <corey.osgood@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3819 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-18This patch gets rid of all the implicit definition warnings for serengeti ↵Myles Watson
except get_nodes. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3818 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-18Add another CPUID to the Via C7's table, the one on my Jetway J7F2.Corey Osgood
Signed-off-by: Corey Osgood <corey.osgood@gmail.com> Acked-by: Corey Osgood <corey.osgood@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3817 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-17Add 690G and 690(MT) internal graphics support.Zheng Bao
The device ID of 690G is 0x791E, while the ID of 690M and 690T is 0x791F This fixes booting on 690G. Signed-off-by: Zheng Bao <zheng.bao@amd.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3816 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-15Add initial support for the ASUS P2B-DS (dual-CPU) mainboard.Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3815 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-15* add a generic preop-opcode-pair table.FENG yu ning
* rename ich_check_opcodes to ich_init_opcodes. * let ich_init_opcodes do not need to access flashchip structure: . move the definition of struct preop_opcode_pair to a better place . remove preop_opcode_pairs from 'struct flashchip' . modify ich_init_opcodes and generate_opcodes so that they do not access the flashchip structure * call ich_init_opcodes during chipset enable. Now OPCODES generation mechanism works. * fix a coding style mistake. Signed-off-by: FENG yu ning <fengyuning1984@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3814 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-14oops. there went a new mainboard into the tree and i missed it. Add mainboardStefan Reinauer
specific changes based on the DBM690T code. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3813 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-13Move mainboard specific changes to the coreboot memory table into theStefan Reinauer
mainboard specific code. (And add a hook to allow other mainboards do a similar thing if required) Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Ronald G Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3812 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-12Improve comments in early SB600 setup, handle non-LPC strapping andCarl-Daniel Hailfinger
document verification against the data sheets. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Maggie Li <maggie.li@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3811 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-10Use -O2 and -mcpu=p2 as romcc options for all Intel 440BX boards.Uwe Hermann
This should hopefully make the "too few registers" error pop up less often. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Peter Stuge <peter@stuge.se> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3810 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-10Add 28 flash chips of the MX29 series to the flashrom ID table andCarl-Daniel Hailfinger
support the MX29LV040C. MX29LV040C probe and read support tested by khetzal on IRC. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3809 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-09AMD PISTACHIO mainboard support.Maggie Li
The following ACPI features are supported: 1. S1, S4, S5 sleep and wake up (by power button). 2. Thermal configuration based on ADT7475. 3. HPET timer. 4. Interrupt routing based on ACPI table. Signed-off-by: Maggie Li <maggie.li@amd.com> Reviewed-by: Michael Xie <michael.xie@amd.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3808 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-09Add (parts of the) support for multiple DIMMs on the Intel 440BX chipset.Uwe Hermann
This is tested on hardware with four 128MB DIMMs and works ok, _iff_ you also fix additional registers (e.g. DRB, RPS, ...) for your setup. This requirement will be eliminated in another upcoming patch (i.e. all of the required settings will be auto-detected). Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Joseph Smith <joe@settoplinux.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3807 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-08Kill obsolete and misplaced comment.Carl-Daniel Hailfinger
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3806 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-08Generates OPCODES struct from the ICH7/ICH9/VIA chipset if its SPIFENG yu ning
configuration is locked down. Signed-off-by: FENG yu ning <fengyuning1984@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3805 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-08Breaks chip info into multiple lines.FENG yu ning
Signed-off-by: FENG yu ning <fengyuning1984@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3804 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-06flashrom: Display test status in -L chip listingPeter Stuge
Looks like this: Supported flash chips: Tested OK operations: Known BAD operations: AMD Am29F002(N)BB AMD Am29F002(N)BT PROBE READ ERASE WRITE AMD Am29F016D AMD Am29F040B PROBE READ ERASE WRITE AMD Am29LV040B Atmel AT45CS1282 READ Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3803 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-05Fixes to AMD MCT code, found by Marco Schmidt <mschmidt@dspace.de>Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3802 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-05The TALERT of ADT7461 should be pull back high if the temperature is within ↵Maggie Li
the limit. It is done by reading the register whose device address is 0xC. It is not trivial as it looks. Signed-off-by: Maggie Li <maggie.li@amd.com> Reviewed-by: Joe Bao <zheng.bao@amd.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3801 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-05Add initial support for the NEC PowerMate 2000 board.Uwe Hermann
See details at: http://support.necam.com/mobilesolutions/hardware/Desktops/pm2000/celeron/ Thanks to Quentin RAMEAU <quentin.rameau@gmail.com> for providing the required information and for testing the patch. This boots into a Linux console just fine. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Corey Osgood <corey.osgood@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3800 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-05flashrom: Add AMD SB700 flash enableNiels Ole Salscheider
This patch adds SB700 support to flashrom. The code for enabling the flash rom is the same as for SB600. It was tested (read, write, verify) with an ASUS M3A-H/HDMI which contains a Macronix MX25L8005. Signed-off-by: Niels Ole Salscheider <niels_ole@salscheider-online.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3799 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-05flashrom: Fix compilation of r3797 with gcc-4.3.2Peter Stuge
Thanks to Niels Ole Salscheider for the problem report. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3798 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-05flashrom: Check if erase succeeds and exit with error on failure.Peter Stuge
flashrom used to exit 0 even if erase failed. Not anymore. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3797 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-04This belongs to changeset 3795.Rudolf Marek
The patch changes the LDTSTOP length as well mostly default content of 0xec, 0xe4 and 0xe5 registers. I'm suspecting that the documentation may be wrong. Furthermore this fix for powernow may not work on CPUs hit by errata #181. Workaround should be implemented. The powernow may not work on pre-A2 revisions of VT8237S silicon, revision reg is unknown. Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3796 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-04The patch changes the LDTSTOP length as well mostly default content of 0xec,Rudolf Marek
0xe4 and 0xe5 registers. I'm suspecting that the documentation may be wrong. Furthermore this fix for powernow may not work on CPUs hit by errata #181. Workaround should be implemented. The powernow may not work on pre-A2 revisions of VT8237S silicon, revision reg is unknown. Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3795 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-04Patch to util/inteltool:Stefan Reinauer
* PMBASE dumping now knows the registers. * Add support for i965, i975, ICH8M * Add support for Darwin OS using DirectIO Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3794 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-04Add RDID/REMS IDs for the following flash chips:Carl-Daniel Hailfinger
SST_25VF512A_REMS SST_25VF010_REMS SST_25VF020_REMS SST_25VF040_REMS SST_25VF040B_REMS SST_25VF080_REMS SST_25VF080B_REMS SST_25VF032B_REMS SST_26VF016 SST_26VF032 W_25X16 W_25X32 W_25X64 Straight from the data sheets. The REMS IDs help in case the RDID opcode is unavailable (due to opcode lockdown) or unsupported by the chip. Some day, we need to pair probe functions together with IDs. Multiple pairs can exist per chip and duplicating chip definitions does not really make sense. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3793 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-03flashrom: gcc thinks base could be used uninitialized, so shut it up.Peter Stuge
Bug from r3791. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3792 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-03flashrom: Fix bug in r3790Peter Stuge
If flashbase was set before probe_flash() it would only ever be used once, for the very first flash chip probe. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3791 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-03Replace #ifdefs for sc520 systems by run time probing.Stefan Reinauer
fixes #109 Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3790 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-02build_opt_tbl:Stefan Reinauer
make sure the temporary files are created in the same directory as the target files so they can be rename()d. This fixes a compilation issue on machines with the build directory living on another partition than /tmp. Pretty trivial. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3789 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-02I missed the svn add on r3787. These are the additional files. Joe Bao
Add AMD dbm690t ACPI support. The following ACPI features are supported. 1. S1, S5 sleep and wake up (by power button or PS/2 keyboard/mouse). 2. AMD powernow-k8 driver. 3. Thermal configuration based on ADT7461. 4. IDE timing settings. 5. HPET timer. 6. Interrupt routing based on ACPI table. Signed-off-by: Joe Bao <zheng.bao@amd.com> Reviewed-by: Maggie Li <maggie.li@amd.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3788 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-01Add AMD dbm690t ACPI support.Joe Bao
The following ACPI features are supported. 1. S1, S5 sleep and wake up (by power button or PS/2 keyboard/mouse). 2. AMD powernow-k8 driver. 3. Thermal configuration based on ADT7461. 4. IDE timing settings. 5. HPET timer. 6. Interrupt routing based on ACPI table. Signed-off-by: Joe Bao <zheng.bao@amd.com> Reviewed-by: Maggie Li <maggie.li@amd.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3787 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-01Add AMD rs690 VID DID reporting and some minor cleanups.Joe Bao
Signed-off-by: Joe Bao <zheng.bao@amd.com> Reviewed-by: Maggie Li <maggie.li@amd.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3786 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-01Add AMD sb600 HPET setup and some minor cleanups.Joe Bao
Signed-off-by: Joe Bao <zheng.bao@amd.com> Reviewed-by: Maggie Li <maggie.li@amd.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3785 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-01The Winbond Super I/O chips have another indirection of registers. TheStefan Reinauer
hwmon has generic registers and banked registers, mostly temperature handling, and SMI/GPIO stuff. Not all LDNs are switched via register offset 0x07, make it a parameter. Add support for dumping the hardware monitor of Winbond W83627THF/THG parts with the -e option. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3784 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-30ok, another attempt to the build_opt_tbl problem:Stefan Reinauer
- create temp files and move them afterwards - remove dummy option -b - fix usage - drop implicit creation of .c file if no --option is specified. Now let's see if this fixes the issue. :-) We don't want to take 24s instead of 6s to build an image reliably (Yes, yes, I know Tiano takes over 20 minutes) Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3783 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-29Copyright update by Jason Wang for freshly written sb600 code.Jason WangQingpei.wang
Signed-off-by: Jason Wang<Qingpei.wang@amd.com> Reviewed-by: Joe, Bao <Zheng.Bao@amd.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3782 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-28Declare special commands to support the Atmel AT25F512A.Carl-Daniel Hailfinger
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3781 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-28If a chip has any TEST_BAD_* flag set, we don't even list theCarl-Daniel Hailfinger
unsupported functions, giving the user the impression that the unsupported functions are tested. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3780 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-28Add support for the AMD/ATI SB600 southbridge SPI functionality.Jason Wang
This has been tested by Uwe Hermann on an RS690/SB600 board. Signed-off-by: Jason Wang <Qingpei.Wang@amd.com> Reviewed-by: Joe Bao <zheng.bao@amd.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3779 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-28This patch from Ralf Grosse Boerger makes debugging more comfortable. Stefan Reinauer
With this patch it's possible to - determine the according source code line for each asm statement (objdump -dS) - determine the source code file for each asm statement (objdump -ddl) This isn't exactly trivial because cache_as_ram_auto.c gets compiled to assembly and converted by a perl script afterwards. This patch solves the problem - by extending cache_as_ram_auto.inc with debug information and line numbers - by correcting the perl calls (".text" --> "\.text") - by creating a disassembly with source code and line numbers. (ctr0.disasm and coreboot.disasm) There's one minor downside to the patch: A complete abuild run takes up around 1.6G instead of about 700MB now. But I'm sure this is quite reasonable for the benefits. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Please commit while this is being worked out. Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3778 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-28This patch fixes the ugly race condition created through build_opt_tblStefan Reinauer
running twice at the same time, overwriting its output files. This caused a depending rule to produce an object file with no symbols in it. This should silence up the regularly happening build failure messages on the mailing list since we moved to the newer, much faster server. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3777 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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