| Age | Commit message (Collapse) | Author |
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Configure eMMC DLL tuning values for Craask board.
BUG=b:238985924
TEST="Use the value to boot on Nivviks and Craask successfully."
Change-Id: I14f3e2329404cca94e14034d1fb52fcb99a2ddc9
Signed-off-by: Simon Yang <simon1.yang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66218
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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The first CSE Lite SKU is available, therefore enable the Kconfig
option to have the CSE reboot the system into its RW FW during a cold
boot.
BUG=b:240228892
TEST=TBD
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I00ef4176cf08cbeed06e446cfe68f06cb1ea27b4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66287
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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List of changes:
1. Add support for new elog event type to log vboot info (type 0xB7).
2. Add support string for fw_slot name, boot status and boot mode.
3. Print fw slot information like FW try count, FW current slot,
previous FW slot, previous FW boot result and boot mode.
BUG=b:215615970
TEST=Able to build and boot google/kano to OS.
localhost # elogtool list
0 | 2022-07-01 11:10:27 | Log area cleared | 4088
1 | 2022-07-01 11:10:27 | Memory Cache Update | Normal | Success
2 | 2022-07-01 11:10:42 | System boot | 360
3 | 2022-07-01 11:10:42 | Power Fail
4 | 2022-07-01 11:10:42 | SUS Power Fail
5 | 2022-07-01 11:10:42 | ACPI Wake | S5
6 | 2022-07-01 11:10:42 | Wake Source | Power Button | 0
7 | 2022-07-01 11:10:42 | Chrome OS Developer Mode
8 | 2022-07-01 11:10:42 | Firmware vboot info |
boot_mode=Developer |
fw_tried=B | fw_try_count=0 |
fw_prev_tried=B | fw_prev_result=Unknown
9 | 2022-07-01 11:11:42 | System boot | 361
10 | 2022-07-01 11:11:42 | System Reset
11 | 2022-07-01 11:11:42 | Firmware vboot info |
boot_mode=Developer |
fw_tried=B | fw_try_count=0 |
fw_prev_tried=B | fw_prev_result=Success
localhost # crossystem recovery_request=1
localhost # elogtool list
41 | 2022-07-13 12:13:48 | Firmware vboot info |
boot_mode=Manual recovery boot |
recovery_reason: 0x1/0 (Recovery requested
from legacy utility) | fw_tried=A |
fw_try_count=0 | fw_prev_tried=A |
fw_prev_result=Unknown
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I48b5d54723683cef51e416fc6f58da000507fbcc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65562
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch calls into vboot API (vb2api_get_fw_boot_info) to retrieve
FW slot boot information like (tries count, current boot slot, previous
boot slot, previous boot status and boot mode).
Upon retrieval of the vboot information, elog callback from ramstage
records the info into the eventlog.
Additionally, this patch refactors the existing event logging mechanism
to add newer APIs to record vboot firmware boot related information.
BUG=b:215615970
TEST=Build and boot google/kano to ChromeOS and run below command to
check the cbmem log:
Scenario 1:
localhost ~ # cbmem -c | grep VB2
[INFO ] VB2:vb2_check_recovery() Recovery reason from previous boot:
0x0 / 0x0
[INFO ] VB2:vb2api_fill_boot_config() boot_mode=`Developer boot`
VB2:vb2api_get_fw_boot_info() fw_tried=`A` fw_try_count=0
fw_prev_tried=`A` fw_prev_result=`Success`.
....
Scenario 2:
localhost ~ # crossystem recovery_request=1
localhost ~ # cbmem -c | grep VB2
[INFO ] VB2:vb2api_fill_boot_config() boot_mode=`Manual recovery boot`
VB2:vb2api_fill_boot_config() recovery_reason=0x13 / 0x00
VB2:vb2api_get_fw_boot_info() fw_tried=`A` fw_try_count=0
fw_prev_tried=`A` fw_prev_result=`Unknown`.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I6882cd1c4dbe5e24f6460388cd1af4e4a05fc4da
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65561
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Updating from commit id a975eed306:
2kernel.c: check display request in vb2api_kernel_phase2
to commit id 18cb85b52d:
2load_kernel.c: Expose load kernel as vb2_api
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I58c5d54723683cef51e416fc6f58da000507fbcc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66269
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add static check to ensure the reserved APOB DRAM space is the same size
as the MRC_CACHE region specified in the fmap.
Update sabrina APOB DRAM size to match the fmap.
TEST: Timeless builds identical. Test build with a larger MRC_CACHE than
APOB DRAM failed the assert as expected.
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: Ia14f6ef94b9062df0612fe96098b1012085ccf9c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65878
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Firmware component that does memory training already limits the memory
controller to train at 5500 Mbps for all memory parts in Sabrina. Hence
removing this interim SPD change to limit the speed.
BUG=b:238074863
TEST=Build and boot to OS in Skyrim.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I2bc82c7407a97aac282708c3e0bd56ae99a8fc31
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66290
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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In order to pass PCIe base address to payloads, implement pcie_fill_lb()
to fill coreboot table with PCIe info.
BUG=b:182963902,b:216686574,b:181098581
TEST=Verified on Qualcomm sc7280 development board with NVMe endpoint
(Koixa NVMe, Model-KBG40ZPZ256G with FW AEGA0102). Confirmed NVMe is
getting detected in response to 'storage init' command in depthcharge
CLI prompt.
Output logs:
->dpch: storage init
Initializing NVMe controller 1e0f:0001
Identified NVMe model KBG40ZPZ256G TOSHIBA MEMORY
Added NVMe drive "NVMe Namespace 1" lbasize:512, count:0x1dcf32b0
* 0: NVMe Namespace 1
1 devices total
Also verified NVMe boot path that is depthcharge is able to load the
kernel image from NVMe storage.
Change-Id: I1ca2be55b98c8d1b86576072078cdda02ac55940
Signed-off-by: Veerabhadrarao Badiganti <quic_vbadigan@quicinc.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57614
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Enable PCIe driver for herobrine board.
BUG=b:182963902,b:216686574,b:181098581
TEST=Verified on Qualcomm sc7280 development board with NVMe card
(Koixa NVMe, Model-KBG40ZPZ256G with FW AEGA0102). Confirmed NVMe is
getting detected in response to 'storage init' command in depthcharge
CLI prompt.
Output logs:
->dpch: storage init
Initializing NVMe controller 1e0f:0001
Identified NVMe model KBG40ZPZ256G TOSHIBA MEMORY
Added NVMe drive "NVMe Namespace 1" lbasize:512, count:0x1dcf32b0
* 0: NVMe Namespace 1
1 devices total
Also verified NVMe boot path, that is depthcharge is able to load the
kernel image from NVMe storage.
Change-Id: Idb693ca219ba1e5dfc8aec34027085b53af49a2c
Signed-off-by: Veerabhadrarao Badiganti <quic_vbadigan@quicinc.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65661
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add 'pci_map_bus' function and PCIE_QCOM config for Qualcomm platform.
BUG=b:182963902,b:216686574,b:181098581
TEST=Verified on Qualcomm sc7280 development board with NVMe endpoint
(Koixa NVMe, Model-KBG40ZPZ256G with FW AEGA0102). Confirmed NVMe is
getting detected in response to 'storage init' command in depthcharge
CLI prompt.
Output logs:
->dpch: storage init
Initializing NVMe controller 1e0f:0001
Identified NVMe model KBG40ZPZ256G TOSHIBA MEMORY
Added NVMe drive "NVMe Namespace 1" lbasize:512, count:0x1dcf32b0
* 0: NVMe Namespace 1
1 devices total
Also verified NVMe boot path that is depthcharge is able to load the
kernel image from NVMe storage.
Change-Id: I7d1217502cbd7d4d0cdd298919ae82435630d61c
Signed-off-by: Prasad Malisetty <quic_pmaliset@quicinc.com>
Signed-off-by: Veerabhadrarao Badiganti <quic_vbadigan@quicinc.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57615
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add PCIe domain support for herobrine by enabling it in the devicetree.
BUG=b:182963902,b:216686574,b:181098581
TEST=Verified on Qualcomm sc7280 development board with NVMe card
(Koixa NVMe, Model-KBG40ZPZ256G with FW AEGA0102). Confirmed NVMe is
getting detected in response to 'storage init' command in depthcharge
CLI prompt.
Output logs:
->dpch: storage init
Initializing NVMe controller 1e0f:0001
Identified NVMe model KBG40ZPZ256G TOSHIBA MEMORY
Added NVMe drive "NVMe Namespace 1" lbasize:512, count:0x1dcf32b0
* 0: NVMe Namespace 1
1 devices total
Also verified NVMe boot path, that is depthcharge is able to load the
kernel image from NVMe storage.
Change-Id: Ied8fbbc8d20698ee081d93ba184b7d0291bb6a76
Signed-off-by: Veerabhadrarao Badiganti <quic_vbadigan@quicinc.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65137
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Enable PCIe functionality on sc7280 and supply all the needed data
for PCIe generic platform driver.
BUG=b:182963902,b:216686574,b:181098581
TEST=Verified on Qualcomm sc7280 development board with NVMe card
(Koixa NVMe, Model-KBG40ZPZ256G with FW AEGA0102). Confirmed NVMe is
getting detected in response to 'storage init' command in depthcharge
CLI prompt.
Output logs:
->dpch: storage init
Initializing NVMe controller 1e0f:0001
Identified NVMe model KBG40ZPZ256G TOSHIBA MEMORY
Added NVMe drive "NVMe Namespace 1" lbasize:512, count:0x1dcf32b0
* 0: NVMe Namespace 1
1 devices total
Also verified NVMe boot path, that is depthcharge is able to load the
kernel image from NVMe storage.
Change-Id: I1f79a0ae2dea594d6026d55a15978eeb92a8ff18
Signed-off-by: Prasad Malisetty <quic_pmaliset@quicinc.com>
Signed-off-by: Veerabhadrarao Badiganti <quic_vbadigan@quicinc.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66148
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Disabling the Package C-state demotion feature for brya baseboard
as a work around to the S0ix issue and also this doesn't have any
impact on the power and performance measured and verified by the
PNP team.
This feature will be enabled after its functionality is verified with no
issues and also based on its impact on PNP.
BUG=none
BRANCH=firmware-brya-14505.B
TEST=Boot and verified that S0ix issue is resolved.
Signed-off-by: Zhixing Ma <zhixing.ma@intel.com>
Change-Id: Id3941c8870d41b25488c8ac5d38534fa94664d4a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65805
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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This adds SPDX-License-Identifiers to all of the files in src/include
that are missing them or have unrecognized identifiers.
Files that were written specifically for coreboot and don't have license
information are licensed GPL-2.0-only, which is the license for the
overall coreboot project.
Files that were sourced from Linux are similarly GPL-2.0-only.
The cpu/power files were committed with source that was licensed as
GPL-2.0-or-later, so presumably that's the license for that entire
commit.
The final file, vbe.h gives a pointer to the BSD-2-Clause license
at opensource.org.
Change-Id: I3f8fd7848ce11c1a0060e05903fb17a7583b4725
Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66284
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
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Sabrina"
This reverts commit 78261e308de5361b2ff045091e8fb18cad2a5035.
Reason for revert: Now that PSP supports a soft fuse flag to toggle the
verstage serial logs, prevent PSP verstage from writing to the UART.
BUG=None
TEST=Build and boot to OS in Skyrim with PSP verstage. Ensure that PSP
verstage logs are not seen twice in the console.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I7ef2d585c320ea5903197939136dd2049a71af95
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66248
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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HW Modexp engine is verified to be working fine. Any verification
failures during PSP verstage are because the firmware body is not read
correctly. This might be because of the incorrect SPI ROM mapping. Hence
enable the HW modexp engine for keyblock, preamble and firmware body
verification.
BUG=b:240175446
TEST=Build and boot to OS in Skyrim with PSP verstage using one of the
FW slots.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I8f6742630a7049354a24053fce28c477e53259e6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66247
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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This is required to enable PSP verstage on SoCs with recovery A/B
layout.
BUG=b:217414563
TEST=Ensure that the concerned type 0x3a PSP entry is present in PSP L2
directory. Build and boot to OS in Skyrim with both PSP and x86
verstage.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I5fae2b5dbcc95a99af3df9f59bb8516280ec1281
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66246
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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clang shows the warning below:
src/drivers/elog/elog.c:171:13: error:
format string is not a string literal
(potentially insecure) [-Werror,-Wformat-security]
elog_debug(msg);
^~~
Found-by: clang (13.0.1)
Change-Id: I3f8949f9ce0c4ef4823530c61c503b0883bb5efc
Signed-off-by: Matei Dibu <matdibu@protonmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66262
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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Add PCIe platform driver for Qualcomm platforms.
Reference:
- linux/drivers/pci/controller/dwc/pcie-qcom.c
- Linux driver base commit: 82a823833f4e3769e82cdb4df1bc2234bc65b16c
BUG=b:182963902,b:216686574,b:181098581
TEST=Verified on Qualcomm sc7280 development board with NVMe card
(Koixa NVMe, Model-KBG40ZPZ256G with FW AEGA0102). Confirmed NVMe is
getting detected in response to 'storage init' command in depthcharge
CLI prompt.
Output logs:
->dpch: storage init
Initializing NVMe controller 1e0f:0001
Identified NVMe model KBG40ZPZ256G TOSHIBA MEMORY
Added NVMe drive "NVMe Namespace 1" lbasize:512, count:0x1dcf32b0
* 0: NVMe Namespace 1
1 devices total
Also verified NVMe boot path, that is depthcharge is able to load the
kernel image from NVMe storage.
Change-Id: Iccf60aa56541f5230fa9c3f821d7709615c36631
Signed-off-by: Prasad Malisetty <quic_pmaliset@quicinc.com>
Signed-off-by: Veerabhadrarao Badiganti <quic_vbadigan@quicinc.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/53902
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Update MrChromebox’ default branch from uefipayload_202107 to
uefipayload_202207.
This is based on upstream edk2, commit f26b70c (UefiPayloadPkg:
Add support for logging to CBMEM console).
Tested on:
* StarBook Mk V
* StarLite Mk III
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I16a012485e4b4957439e776914ffd016b4506a47
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66083
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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SMMSTORE support in edk2 was not allowed in upstream edk2
as it was bootloader specific.
Shortly, it will be built from edk2-platforms and then,
it will be retired.
For now, the patches exist in the MrChromeBox fork (TIANOCORE_UEFIPAYLOAD), so enable
these by default when SMMSTORE_v2 is enabled.
Change-Id: I1861bf739c2e25f661b4f06a303348f0537dc8b3
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65867
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Allow passing custom build parameters to any version of edk2, not
just forks.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I4eed535415ba15ae73e22cada9153820538f5f6d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66210
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
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Fix the license in header file.
BUG=none
BRANCH=firmware-brya-14505.B
TEST=none
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I025f7c571d09e4cc63a659279e63d17c098c01cf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66253
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
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- Move configs for PCIe ports not present on z220_sff_workstation
from the devicetree.cb of base board to the overridetree.cb of
z220_cmt_workstation.
- Add a note for ME/AMT Flash Override jumper, for it is hard to
flash from OEM firmware either internally or externally without
closing this jumper.
- Add a side note for similar HP Compaq Elite 8300 SFF.
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Change-Id: I35d8b97f52a83910a61c12b1f7367ee7a19a9ad7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65703
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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DPTF Policy and temperature sensor values from thermal team.
BUG=b:236294162
TEST=emerge-brask coreboot
Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: Iebcfb74c4bc719e6d8d8d9317435becd912eaf85
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65657
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
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futility now supports image truncation and signing of whole images with
a single command invocation. Use it for vboot-enabled coreboot images.
TEST=Build and run coreboot on google/volteer
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I49eb7e977b635ccb9f6c1b76e53c36e82be1d795
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66127
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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Test build for QEMU x86 i440fx/piix4.
Change-Id: I97d059947f7049b2491a98985795a4655891c3b3
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64991
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
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Change-Id: I30bbd0288475fbefec55ce294e7963df1de6aa6a
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60720
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
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Change-Id: I21b954ce62259bb77d88775c3086cfac17dd90c7
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60719
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
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Replace `LNotEqual(a, b)` with `a != b`.
Change-Id: If0e9fcea680d487c28a965e944b3333bb5a07026
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60696
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Replace `LLess(a, b)` with `a < b`.
Change-Id: Ief1d069ae0fb19a2179f08c2e9cf416367661e69
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60674
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Replace `Add (a, b, c)` with `c = a + b`.
Change-Id: If848d391e5ec33ebfb08515414739dbdd5011e08
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66249
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
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This patch enables display port configuration as per the Rex
schematics.
TEST=Able to dump FSP UPD to ensure the override is successful.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I9e81d037416e46e52cb72344425d6d8725dae192
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66209
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
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Pujjoflex support OZ711LV2LN SD card controller,
Select the Bayhub LV2 driver for OZ711LV2LN SD card.
BUG=b:215487382
TEST=Build FW and checking SD card work as expected in OS.
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Change-Id: I6759fde1eaf24599a1fdb364d6e78f4e4e12f311
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66178
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
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Create RAM IDs for:
DRAM Part Name ID to assign
MT62F512M32D2DR-031 WT:B 0 (0000)
MT62F1G32D2DS-026 WT:B 1 (0001)
MT62F2G32D4DS-026 WT:B 2 (0010)
BUG=b:240289148
TEST=emerge-rex coreboot
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Change-Id: Ib24e07bca363984db3484aa500f7d6ea4817e517
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66164
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
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The gpios and the tick delay register are different between MT8188
and previous MediaTek SoCs, so we need to add this patch to support
SPI.
TEST=build pass
BUG=b:236331724
Signed-off-by: Liya Li <ot_liya.li@mediatek.corp-partner.google.com>
Change-Id: I6065b9d285dfd36c191f274f500fdb694920276e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66185
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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MT8188 SPI tick delay setting is moved to `spi_cmd_reg` register which
is different from previous SoCs, so we define a macro to get the
designated register.
TEST=build pass.
BUG=b:233720142
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: Ia30e94a8688c0e1c1d4b3d15206f28e5bd8c9bd4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66184
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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TEST=build pass.
BUG=b:233720142
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I869c0879d09e00cf66882adb728c9ccb6ac57e03
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66183
Reviewed-by: Yidi Lin <yidilin@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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TEST=build pass.
BUG=b:233720142
Signed-off-by: Song Fan <ot_song.fan@mediatek.corp-partner.google.com>
Change-Id: Ic300b70a38ac204b098ca9ab15cf7045b66fd76d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66182
Reviewed-by: Yidi Lin <yidilin@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add RTC header file for SoC-specific settings. Add RTC support in
romstage.
TEST=build pass.
BUG=b:233720142
Signed-off-by: Song Fan <ot_song.fan@mediatek.corp-partner.google.com>
Change-Id: I38115ce0c9a4e1c1b2b7c8e6d40f47e99f7f86b3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66181
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Move the common definitions to rtc_reg_common.h, so we can reuse those
definitions on MT8188.
TEST=build pass
BUG=b:233720142
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: Ia1d916a88b7cb875b35ee5813b7b52d9e98f5009
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66180
Reviewed-by: Yidi Lin <yidilin@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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TEST=get voltage as 340mV for channel 0 in MTK EVB.
BUG=b:233720142
Signed-off-by: Hui Liu <hui.liu@mediatek.corp-partner.google.com>
Change-Id: Idd1edcce6cb62fcf6991bb9342c409150989c5ca
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66121
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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The AUXADC register definitions are the same for all MediaTek SoCs, so
we move struct mtk_auxadc_regs to auxadc_common.h.
TEST=build pass.
BUG=b:233720142
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I48978a93137a7de42f8ea2873be3130cb8f534f3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66123
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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This patch override `CnviBtCore` FSP UPD.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I90c9b360969aada0b0e031d62b48476fac5cee0e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66208
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Add CS42L42 support in device tree.
BUG=b:240006200
BRANCH=firmware-brya-14505.B
TEST=Check cs42l42 driver can probe successfully in kernel.
cs42l42 i2c-10134242:00: Cirrus Logic CS42L42, Revision: B1
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I861f47c12f4cebb016a4cfbe225f97d34d55e233
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66223
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
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Remove the parameter and set I2C bus speed to fast. Will fill the
tuning value after real tuning.
BUG=b:240006200
BRANCH=firmware-brya-14505.B
TEST=build passed.
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: Iba7fe4551959617ecfa49719c1124bf85d624c31
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66220
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
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Create the gaelin variant of the brask reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:239514438
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_GAELIN
Signed-off-by: Raymond Chung <raymondchung@ami.corp-partner.google.com>
Change-Id: I7f1ff8690c7c57f8960e004d0490d5cede8667f3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66177
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
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Add TDP and Power Limit settings for ADL-S 8+8 150W, 4+0 and 2+0.
The System Agent PCI IDs were not present in older 2.1 revision of
DOC #619501. Now that the mapping of these IDs to SKUs is known, fill
the missing TDPs and Power Limit settings based on DOC #626343.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I23dd8478e60bcc81a1048f2f6e6717dd281d1a69
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66053
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
|
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Add missing System Agent PCI IDs for ADL-S 4+0 and 2+0 to configure
VccIn Aux Imon IccMax. They were not present in older 2.1 revision of
DOC #619501. Based on DOC #619501 rev 2.6.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Idfd57ce9b63db5d5fcc9d4efb8aa27ed7cc6222d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66052
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
|
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Based on DOC #619501, #634885, #626343.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ib50db521e4d127a773f903b45d4bec5c5cc180d4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63840
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
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The patch updates platform_is_resuming() API such that platform resume
state is determined from the saved state (CBMEM) instead of checking PMC
registers (PM1_STS & PM1_CNT) as they are getting cleared (before/early)
ramstage.
coreboot sends DISCONNECT IPC command which times out during resume (S3)
if system has servoV4 connected on port0. The issue occurs only during
the first cycle of resume (S3) test cycle after cold boot due to side
effect of platform_is_resuming() API that is not determining the resume
(S3) state correctly in ramstage.
PM1_STS and PM1_CNT register gets cleared at the start of ramstage.
platform_is_resuming() function was checks the cleared register value
and fails the condition of resume (S3) resulting in sending DISCONNECT
IPC command. Checking the platform resume state from the CBMEM saved
state using acpe_get_sleep_type() function helps cross verify the
system previous state at the later part of ramstage.
localhost ~ # cbmem -c | grep ERROR
[ERROR] EC returned error result code 3
[ERROR] PMC IPC timeout after 1000 ms
[ERROR] PMC IPC command 0x200a7 failed
[ERROR] pmc_send_ipc_cmd failed
[ERROR] Failed to setup port:0 to initial state
[ERROR] PMC IPC timeout after 1000 ms
[ERROR] PMC IPC command 0x200a7 failed
[ERROR] pmc_send_ipc_cmd failed
[ERROR] Failed to setup port:1 to initial state
[ERROR] GENERIC: 0.0 missing read_resources
[ERROR] PMC IPC timeout after 1000 ms
[ERROR] PMC IPC command 0xd0 failed
[ERROR] PMC: Failed sending PCI Enumeration Done Command
BUG=b:227289581
TEST=Verified system boots to OS and verified below tests on
Redrix (ADL-P) and Nivviks (ADL-N)
1. coreboot doesn't send the DISCONNECT during S3 resume
2. suspend S3 passes with both suzyq and servoV4 connected
3. After S3 resume, system detects the pen drive with Superspeed
4. After system resumes from S3, hot-plug the pen drive, system detects
the pen drive
Signed-off-by: Harsha B R <harsha.b.r@intel.com>
Change-Id: I353ab49073bc4b5288943e19a75efa04bd809227
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66126
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This adds support for Micron MT62F2G32D4DS-026 chips.
BUG=b:240289148
TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Change-Id: I1212506d742178803a7e7bf7e0236d1095f7af9d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66163
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
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Add weida touchscreen support for drawcia.
BRANCH=dedede
TEST=Build and verify that touchscreen works on drawcia.
Change-Id: Ic76f3529771c6eeeafef7ca50fc400065aac2211
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65471
Reviewed-by: Ivan Chen <yulunchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
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Replace `LEqual(a, b)` with `a == b`.
Change-Id: I4e219bea8df64db1d49beb8534f0f37fee0df5b6
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60668
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
|
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Replace `LEqual(a, b)` with `a == b`.
Change-Id: Ifffd21a663739f72a5584e26b79b0627dd532d9e
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60667
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
|
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Replace `LEqual(a, b)` with `a == b`.
Change-Id: I3aebd29bba285229979b79867c881018f61e2060
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60666
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
|
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Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I0ae8c6624b79ce6c269244bd1435900d4d7f997a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65953
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
|
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set i2c address to 0x14 for Goodix touchscreen
BUG=b:239180430
TEST=USE="project_joxer emerge-nissa coreboot"
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: I11a2d9c684bc511b3942f88f74a2495e796bc3c2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66192
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
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When the dGPU is entering GCOFF, the link should first be placed into
L2/L3 as appropriate for the design, then when exiting, the link should
be placed back into L0. This patch fixes that oversight.
BUG=b:239719056
TEST=build
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ia3bdfe5641216675e06ebe82ffe58bf8c049b26b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66200
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
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The EEs noticed this pin was misbehaving; it was accidentally set to a
low output, but should be open-drain (NC). This patch fixes that.
BUG=b:237837108
TEST=verified by EEs
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ie76a951320c49b9fbc1f23b96f04c9f86ad44d42
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66204
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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For some yet unknown reason, when this GPIO is locked, there is an
interrupt storm for IRQ #9 apparently caused by GPE 0x66. GPP_F14 is set
to GPE 0x64 on the ADL platform, so this doesn't quite make sense. This
patch removes the lock and fixes this IRQ storm, but the root cause is
not identified yet.
BUG=b:236997604
TEST=`grep ' 9:' /proc/interrupts` shows a reasonable value now
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I3d1c66fac80a173798ae33e48b1776d9f4fb5eaa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66201
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
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After staring at lots of scope shots, the EE has determined that a few
modifications to the GCOFF sequence can be made:
- Remove delay between PERST# assertion and GPU_ALLRAILS_PG deassertion
- Remove delay after ramping down FBVDD
This patch implements these minor changes.
BUG=b:240199017
TEST=verified by EE
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I7d492b3e65a231bc5f64fe9c3add60b5e72eb072
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66199
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
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After some debugging, it has been determined that the ASPM L0s substate
is functional, but there is still some problem with ASPM L1 substates,
so this patch updates ASPM status for the dGPU from disabled to L0s
only.
BUG=b:240390998
TEST=tested with nvidia tools
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I584bdbf26eda20246034263446492bf4daf5f3b6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66198
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
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There are 3 more CPU PCIe RP UPDs that are the current code is not setting,
and some boards may want to set these, so this patch adds support to set
these UPDs. The default values for any existing boards using these UPDs
should not change with this patch.
The UPDs are:
- CpuPcieRpDetectTimeoutMs
- CpuPcieRpAspm
- CpuPcieRpSlotImplemented
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Id48019f984e8e53ff3ce0c3c23e02dab65112c99
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66197
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Generate SPD id for hynix H54G68CYRBX248
BUG=b:239899929
BRANCH=firmware-brya-14505.B
TEST=run part_id_gen to generate SPD id
Change-Id: I96babe340678ca9b82b06d3193b93a7676f23fef
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66072
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Generate SPD id for Hynix H54G68CYRBX248
BUG=b:239888704
BRANCH=firmware-brya-14505.B
TEST=run part_id_gen to generate SPD id
Change-Id: I9412b988bcdb0c744e016f3add6dacda8185d6db
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66071
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Generate initial SPD for H54G68CYRBX248
BUG=b:239888704
BRANCH=firmware-brya-14505.B
TEST=util/spd_tools/bin/spd_gen spd/lp4x/memory_parts.json lp4x
Change-Id: Iae75391938446e9ee387b779ddcaa378a23ee52e
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66070
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
GPP_F0 to GPP_F4 is for CNVi and should be NF1.
GPP_F5 is for CNVi CLK_REQ, and should be NF3 CRF_XTAL_CLKREQ.
BUG=b:240006200
BRANCH=firmware-brya-14505.B
TEST=CNVi wifi can get probed in kernel.
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: Ice3fde3a457f6f5c058c0a7d3ca2e63775bda96c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66175
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
|
|
Add SLP_S0 residency register and enable LPIT support.
Change-Id: I45e1fc9df3e782cdaac810af3189c5797b1fe413
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66091
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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|
devmem2 and pcimem are useful tools which allow working (reading and
writing) with memory mapped IO.
Change-Id: Ifda547b44af3c8e11cd4171a1dfbce3713455303
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66171
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The current "normal" EPB (six) setting resulted in the desired out of
box power and performance for several CPU generations.
However, a power and performance analysis on Alder Lake and Raptor
Lake CPUs demonstrates that this value results in undesirable higher
uncore power and that seven is a more appropriate value.
Note: the Linux kernel "4ecc933b x86: intel_epb: Allow model specific
normal EPB value" patch sets the EPB to 7 for Alder Lake.
BRANCH=firmware-brya-14505.B
BUG=b:239853069
TEST=verify that EPB is set by coreboot
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Change-Id: I5784656903d4c58bedc5063ee3ef310a99711050
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66059
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Cliff Huang <cliff.huang@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
According to document 619503 ADL EDS Vol2, bit 18 of MSR_POWER_CTL
must be set to be able to set the Energy/Performance Bias using MSR
IA32_ENERGY_PERF_BIAS.
Note that since this bit was not set until this patch, the
`set_energy_perf_bias(ENERGY_POLICY_NORMAL);' call in
`soc_core_init()` was systematically failing.
BRANCH=firmware-brya-14505.B
BUG=b:239853069
TEST=verify that EPB is set by coreboot
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Change-Id: Ic24abdd7f63f4707b8996da4755a26be148efe4a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66058
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
This patch adds a new variant called Pazquel360 \
that is identical to Pazquel for now.
BUG=b:239987191
TEST=make
Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com>
Change-Id: I0a9ca4a59fb44256d0d8fcdbdf2a7db533c84412
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66150
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Bob Moragues <moragues@google.com>
|
|
The concise multi-line comment style is for inside function bodies to
save space. Outside of it, use non-concise style.
Change-Id: I34d9ec6984b598a37c438fa3c395b5478207e31d
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65885
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
This adds the initial gpio configuration for the rex initial variant.
BUG=b:238165977
TEST=Boots and no errors on simics
Change-Id: I55ab31c7943e22df9cec8db4a9f0c3ab6f065ae1
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65952
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
This patch fixes the documentation discrepancy of GPIO reset type
between PCH EDS and GPIO BWG.
As per GPIO BWG, there are four GPIO reset types in Meteor Lake as
below:
- Power Good - (Value 00)
- Deep - (Value 01)
- Host Reset/PLTRST - (Value 10)
- Global Reset for GPP - (Value 11)
Also, dropped the need for having dedicated reset type for GPIO
community 3. As per the MTL EDS, all GPIO communities have the same
reset type.
BUG=b:213293047
TEST=Able to build and boot Google/Rex without below error msg.
[ERROR] gpio_pad_reset_config_override: Logical to Chipset mapping
not found
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Id7ea16d89b6f01b00a7b7c52945f6e01e8db6cbd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66155
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-by: Will Kim <norwayforest92@gmail.com>
|
|
This patch introduces a new macro for GPP PAD reset type as
`Global Reset` as documented in Alder Lake EDS doc 630603.
BUG=b:213293047
TEST=Able to build Google/Kano with this change.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I39428911babc393dd10750801522a00d0b26d3e5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66154
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Id7fe11269276f0752545a51d92395cfc03445471
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66124
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
|
|
Bind the PCDs that allow edk2 to use the whole display to a
Kconfig option called TIANOCORE_FULL_SCREEN_SETUP.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ic977a199f3b308c566391e37f126c4fe518b2eb6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66162
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
|
|
The `call int-multiply` couldn't handle the Kconfig option being a
string so do the calculation in bash.
Tested on:
* Qemu
* StarLite Mk III
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I1879d7efd504e2c42dadb12d2d8add4f69ca7b9c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66161
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
|
|
This caused edk2 serial output to be disabled 100% of the time.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: If272369b405e7745fe82f49026cbed0abc50f355
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66160
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
|
|
converting the SVG logo to BMP at compile time using 'convert'
introduces terrible aliasing artifacts, so use a properly converted
BMP file as the default instead.
Test: boot qemu w/Tianocore, observe lack of aliasing in coreboot logo
Change-Id: I62d643c24abca57fa35b79732d8cedc83b94815f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66144
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Using 'convert' to convert the SVG logo to BMP for Tianocore
introduces terrible aliasing, so add a logo in BMP format
(converted using GIMP).
The default logo file used by Tianocore will be changed in a
subsequent commit.
Change-Id: I2490707a330713709dd4ba8ae99b22b123ba64da
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66143
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
|
|
Enabling them causes firmware keyblock/preamble and/or body verification
failure. Hence disabling them to use software based verification.
Re-enable them once the issue is root-caused.
BUG=b:217414563
TEST=Build and boot to OS in Skyrim with PSP and x86 verstage.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I7e259ae5d790977d08afcb0a77f8d4f38c85f39e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66134
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Currently only SHA_GENERIC is used and does not need to be passed.
BUG=b:217414563
TEST=Build and boot to OS in Skyrim with PSP and x86 verstage.
Change-Id: Id705b1361fffaf940c51515e7f77d7fb0677fc4a
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66133
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
|
|
ChromeOS connection manager (shill) already
has support for dock MAC address passthrough, therefore remove the
code to pass a dock's MAC address in ACPI.
BUG=b:235045188
TEST=build coreboot
Signed-off-by: Franklin Lin <franklin_lin@wistron.corp-partner.google.com>
Change-Id: I78320a7c6b0fd5392e24b63bff234229a3f4b9bc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66040
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Follow latest schematic 6/27 to update the DQ map.
BUG=b:240006200
BRANCH=firmware-brya-14505.B
TEST=build passed.
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I8d0de04a001cab53a245185707ebc9da7a501ec4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66122
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
|
|
wifi
This reverts commit 5e6fd360de7fe92f1e8b1b3eb20241809e2a6aff.
On nereid, the SSDT entry for the PCIe wifi device is missing, causing
wake-on-WLAN not to work since the _PRW is missing.
It seems like when commit 5e6fd360de changed the SSDT generation logic
for CNVi and PCIe wifi, it broke the PCIe case. `wifi_pcie_ops` are
never assigned to any device, so
`parent && parent->ops == &wifi_pcie_ops` always returns false, and the
`wifi_cnvi_ops` are used even for PCIe devices.
Undo the changes in that CL. This allows both the CNVi and PCIe cases to
work. That CL was meant to fix an issue with the CNVi _PRW containing
garbage, but I can't reproduce this when the change is undone.
It was also meant to fix the following error on CNVi devices, but I
don't see any errors with this change:
[ERROR] NONE missing set_resources
BUB=b:233325709
TEST=On both nivviks (CNVi) and nereid (PCIe), check that the SSDT
contains the correct wifi device entries (below), including a _PRW
containing the correct GPE, and check that wake-on-WLAN works.
nivviks:
```
Scope (\_SB.PCI0.CNVW)
{
Name (_PRW, Package (0x02) // _PRW: Power Resources for Wake
{
0x6D,
0x03
})
Method (_DSM, 4, Serialized) // _DSM: Device-Specific Method
{
<snip>
}
}
```
nereid:
```
Device (\_SB.PCI0.RP01.WF00)
{
Name (_UID, 0x923ACF1C) // _UID: Unique ID
Name (_DDN, "WIFI Device") // _DDN: DOS Device Name
Name (_ADR, 0x0000000000000000) // _ADR: Address
}
Scope (\_SB.PCI0.RP01.WF00)
{
Name (_PRW, Package (0x02) // _PRW: Power Resources for Wake
{
0x23,
0x03
})
Method (_DSM, 4, Serialized) // _DSM: Device-Specific Method
{
<snip>
}
}
```
Fixes: 5e6fd360de ("drivers/wifi/generic: Fix properties in generic-under-PCI device case")
Change-Id: I100c5ee3842997c50444e5ce68d583834ed3a8ad
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66063
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add critical, passive policy, and pl values from thermal team.
BUG=b:239495499
TEST=Build and test on MB, system can boot to OS.
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: I8beb3b57ff56c6fe413bb0e3dd43d693aee08e36
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66125
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
|
|
Beginning FSP 2.2 specifications Fsps Config Upd "FspEventHandler"
was moved to Fsps Arch Upd. Hence we were not seeing Fsps Debug
log was not using coreboot debug library.
This change assigns Fspd Arch Upd FspEventHandler with coreboot
ramstage debug handler when FSP_USES_CB_DEBUG_EVENT_HANDLER
Kconfig is enabled.
Before:
Dumping FSPS_UPD - Size: 0x00001510
0x00000000: 0x41 0x44 0x4C 0x55 0x50 0x44 0x5F 0x53 0x02 0x00 0x00
0x00000010: 0x00
With the fix:
[SPEW ] Dumping FSPS_UPD - Size: 0x00001528
[SPEW ] 0x00000000: 0x41 0x44 0x4C 0x55 0x50 0x44 0x5F 0x53 0x02
[SPEW ] 0x00000010: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
[SPEW ] 0x00000020: 0x01 0x00 0x00 0x00 0x20 0x00 0x00 0x00 0xAA
[SPEW ] 0x00000030: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
[SPEW ] 0x00000040: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
BUG=b:237263080
TEST=Able to build and boot MTL RVP, verified the FSP-S debug
log is using coreboot debug library.
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: Ie63258f6427b3da7927a866bc3767f548b16e3e2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66146
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
commit 108e53792804
("payloads/tianocore: Add a proper target for the Boot Splash")
introduced 2 bugs in bootsplash handling:
- the "logo" make target added a spurious "/edk2" to the project dir
- the "logo" make target failed to account for the case where no user-
defined logo file is used (the upstream Tianocore one will be used
in this case)
Fix both these issues.
Test: build/boot qemu w/Tianocore w/o user-defined bootsplash file.
Change-Id: Ieebc547670213459823f58956ae87c6bf94b74ef
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66142
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
|
|
Pujjo support WLAN device, enable PCIe port 4 for WLAN device
BUG=b:239899932
TEST=Build and boot on pujjo
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Change-Id: Ic8b7240941cf87a4f27963d50fffe28875114a81
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66073
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
revalant ---> relevant
Change-Id: Id31a57644947bf8c0f461dbfc9ca8b1984e9acb8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66151
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
|
|
To avoid unnecessary PCIe early initialization for non-NVMe devices
(which would take about 150ms on dojo), skip setting PCIe ops when
initializing mt8195 SoC.
BUG=b:238850212
TEST=emerge-cherry coreboot
TEST=Dojo SKU1 (eMMC) boot time <= 1s
BRANCH=cherry
Change-Id: I8945890ba422c0c4eb42683935220b7afbb80dfd
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65993
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
|
|
Implement mainboard_needs_pcie_init() for cherry as a callback for
mt8195 SoC to determine whether to initialize PCIe. When the SKU id is
unknown or unprovisioned (for example at the beginning of the factory
flow), we should still initialize PCIe. Otherwise the devices with NVMe
will fail to boot.
BUG=b:238850212
TEST=emerge-cherry coreboot
BRANCH=cherry
Change-Id: I2ed0ceeb37d2924ca16485fb2d130959a7eff102
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65992
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
|
|
1. Set Type-A USB3 port0/1 tx_de_emp to 0x2B to fix the USB3 Gen2 RX
signal integrity issue.
2. Disable unused USB port.
BUG=b:238230292
TEST=build FW and check Type-A USB3 port0/port1 RX pass
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I8356ca30a965e5774a1556c5cb81e1586c55496c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66118
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
On SoCs which use A/B recovery layout, PSP verstage and signing keys are
expected to be present only in PSP L2 directory. Update amdfwtool to
include the PSP verstage and signing key only in PSP L2 directory.
BUG=b:239519603, b:238938623
TEST=Build and boot to OS in Skyrim with PSP verstage.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: Ieeb415be800b7ccf10d6983eb0b567e0a5eaa955
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66128
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
|
|
Joxer will have both eMMC and UFS SKUs, which require different
settings in the descriptor. So update the descriptor at run-time based
on fw_config.
By default, the descriptor is configured for UFS. This configuration
still boots fine on eMMC SKUs, it just might cause problems with S0ix.
This is a temporary workaround. It will be removed once we've
implemented a proper solution for configuring the descriptor differently
for different SKUs.
BUG=b:238234376
TEST=Make an identical change for nivviks. On both nivviks (eMMC) and
nirwen (UFS), check that it boots and that the logs show the descriptor
being configured as expected.
Change-Id: I14232eb773936f2ecd183687208d332136935601
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65870
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
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SSPM is "Secure System Power Manager" that provides power control in
secure domain. The initialization flow is to load SSPM firmware to
its SRAM space and then enable.
It takes 21 ms to load sspm.bin.
coreboot logs:
CBFS: Found 'sspm.bin' @0x21680 size 0xa815 in mcache @0xffffeac4
mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137348 bytes)
TEST=we can see the sspm logs.
BUG=b:233720142
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: Ib6443b64734048c1d71eeac650f36d7c4ac709cf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66067
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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Load MCUPM firmware and boot up MCUPM in ramstage.
It takes 41 ms to load mcupm.bin.
coreboot logs:
CBFS: Found 'mcupm.bin' @0x12580 size 0xf0c6 in mcache @0xffffead0
mtk_init_mcu: Loaded (and reset) mcupm.bin in 41 msecs (122184 bytes)
TEST=we can see the mcupm logs after reset releases.
BUG=b:233720142
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: Id1e62d9d6ede1c453e03eeda0d9b16fafa9e2372
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66066
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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