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2017-07-28src/cpu: Fix checkpatch warning: no spaces at the start of a lineMartin Roth
Change-Id: Iabdaaaee49e8c5cead304cda66412aa36a2ffd19 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20729 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2017-07-28util/inteltool: Clean up checkpatch.pl warningsPratik Prajapati
Remove braces around single statements. "WARNING: braces {} are not necessary for single statement blocks" Change-Id: Id5a7dc3a9672266b66d7f46db2ff087b98fd174d Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/20771 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-28util/inteltool: Add support for SGX statusPratik Prajapati
Add support for dumping Intel Software Guard Extension (SGX) status. --sgx or -x is the command line switch to get SGX status. The code iterates through all cores and reads MSRs to check if SGX is supported, enabled and the feature is locked. Change-Id: I1f5046c1f6703f5429c8717053ffe9c981cedf6f Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/20758 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-07-28soc/intel/skylake: Remove incorrect ME PG-status printBarnali Sarkar
As per discussion with CSME team, ME is NOT using PCI Config Space register HFSTS2 Bit 10 to update ME power-gated status. ME goes to CM0-PG state after ME device becomes idle after Bit 2 of MMIO register offset 0x800 (D0i3 Control - HECI1_D0I3C) is being set. And to retrieve the PG status of ME, one should read from the PWRMBASE+offset 0x590 (which should give the value 0xF9) and PWRMBASE+offset 0x594 (which should give the value 0xFF). But, also it needs some time for the ME FW to go to idle state and reflect these values in PWRMBASE registers after D0i3 bit is being set. This does not happen instantly. So, in coreboot, if we read the ME PG state in finalize.c, which happens just after FSP Notify phase, where actually ME D0i3 bit is set, we do not read the correct PG state values (i.e, 0xF9 and 0xFF). But, once it boots to Kernel, if we read those same registers through iotool mmio_read32 command, we get correct values. So, removing the ME PG state prints from coreboot, since it is actually showing wrong information, although ME Power Gating is successful. Change-Id: Idd31a9803b4c9db7d4bb8bbec5374583a8df0c41 Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/20172 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-28libpayload: Double HEAP_SIZE in default configRicardo Ribalda Delgado
Bettong board with the standard configuration is not capable of running nvramui with the default size. malloc error happens on PDC_makelines(). Resulting in: Booting from CBFS... Run img/nvramcui Calling addr 0x00100000 initscr(): Unable to create stdscr. exited with status 1 Change-Id: I56a0fb3319fe77599bf3dd6c328a0b70be60a348 Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com> Reviewed-on: https://review.coreboot.org/20681 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2017-07-28siemens/nc_fpga: Add support for lowest FAN speed to FAN controllerWerner Zeh
The functionality of the FAN controller is extended to provide a lowest startup speed of the FAN. Add the parameter "fanmin" to the fan_ctrl_t structure and initialize the value. Change-Id: Ib2e093ed6f5fc29bbea879779eb4777eb371b937 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/20789 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-07-28vendorcode/siemens: Fix typo in hwilibWerner Zeh
The parameter shall be FANStartSpeed instead of FANStartpeed. Change-Id: I977da687ba8d9d0bad4c184cd0945ecaa52286ad Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/20788 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2017-07-28google/kahlee: Add ASL for Elan touchpadIvy Jian
Add ASL for the Elan touchpad driver connection in ChromeOS. This is based on the Auron and Rambi ASL. The AMD ACPI code doesn't have the auto table generation the newer Intel Chrome SOC use. Device visible to OS: /sys/bus/acpi/devices/ELAN0000 Change-Id: Id3fc8c8855b0296f43a502e81143498d663468ec Signed-off-by: Ivy Jian <ivy_jian@compal.com> Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19844 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-28google/kahlee: Fix ASL whitespace and formattingMarc Jones
Clean up the ASL whitespace and formatting to match the iasl -d style as other parts of coreboot. Change-Id: I61689cb55dc26cbad160d45aa0a36c00b386fe0c Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19843 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-28google/kahlee: Remove conflicting AAHB IRQ ASLIvy Jian
The AMD internal A-link (AAHB device) doesn't support an IRQ, so remove it. This solves a conflict with the GPIO IRQ required for touchpad operation. Change-Id: Iefaf33cfb2babc29d35b5372fc3a338a72c78a4a Signed-off-by: Ivy Jian <ivy_jian@compal.com> Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19842 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-28mb/google/soraka: configure GPP_B8 to control WLAN_PE_RSTRizwan Qureshi
WLAN_PE_RST control was moved from EC to SoC, it connected to GPP_B8. Configure GPP_B8 to drive low. TEST=Wifi card is detected and connect to an AP. Change-Id: I6a6ea0ddefe8402284fe37665864c7a1961cbc15 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/20804 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-07-27google/kahlee: Set SERIRQ to continuous modeMarc Jones
The Kahlee Nuvoton EC firmware doesn't support SERIRQ quiet mode, yet. Set continuous mode until the quiet mode feature is available. This allows keyboard and other EC based interrupts through. Change-Id: If77c91fde2bd0f4da85413879fefb753ae6297de Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19840 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-27google/kahlee: Pass GPIO setting in amdinitenvMarshall Dawson
GPIOs for I2C3 were being unset in amdinitmid if the GPIO enable table wasn't passed. It had been initialy set in amdinitreset. Pull the GPIO settings into their own file that can be used in bootblock and later stages. Change-Id: I41cd7873f8c8543c95ad8653e0a3887f7d0487a2 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19839 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-27google/kahlee: Update PCIe link/lane configurationMarshall Dawson
Enable: GPP0 x1 - WLan GPP1 x1 - Card Reader Change-Id: Idbfc2a3260b85949810bdd8dc904e59f8a779e48 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19838 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-27google/kahlee: Set FADT legacy and 8042 supportedMarc Jones
The EC is a legacy 8042 device. Don't set LEGACY_FREE and correctly report in the FADT. Change-Id: I041ea4b44372178f3d6073b6ebc8003abc097703 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19836 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-07-27google/kahlee: Add ChromeOS and ChromeECMarshall Dawson
Add the basics for building as a ChromeOS device. ChromeOS and ChromeEC are dependent on each other, so bring them in together. The EC is a Nuvoton and you can find additional details in the Chromium EC repo. Add the Google HWID "Kahlee TEST 6421". The chromeos.fmd for Kahlee takes advantage of the AGESA located outside cbfs and includes typical RW, VPD, and MRC areas. There are some updates required to depthcharge, vboot, GPIOs, and the ChromeEC before we have a complete-ish system. Change-Id: Ifb0a6afc01dd80ef9e7bb81039d9152936043999 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19835 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-27google/kahlee: Update GPIO tableMarshall Dawson
Update GPIO settings based on the schematic. Change-Id: Ic8a876198a3ba9029d1aabb273418923e40bfcc6 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19834 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-07-27google/kahlee: Update for single DIMMMarshall Dawson
Update for a single DIMM with an SPD at address A0. Change-Id: I646f079c99cbaffd7094773243600c3030308325 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19833 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-07-27google/kahlee: Remove AMD IMCMarshall Dawson
Kahlee does not use the AMD IMC. Remove the files and calls. Change-Id: Ia837551b592b4f473eb38c06c516586fb6c95c88 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19832 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-07-27google/kahlee: Update KconfigMarc Jones
Update for the Stoney Ridge FT4 package and the on chip UART. Change-Id: I11468834a9ef03da084c156c74d55a19416d98c4 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19831 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-07-27google/kahlee: Start Kahlee mainboardMarc Jones
Copied from amd/gardenia. Update the appropriate board name strings. Uses the soc/ structure. Change-Id: Ia68b16969518f4d63d5d2dea7658a472b2daca05 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19830 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-27soc/amd/stoneyridge: Remove unused SD controllerMarshall Dawson
Remove the unused support code from the old multi-device hudson SD controller. The binaryPI blob contains the correct steps for setting up SD and the public BKDG doesn't completely document the controller. The sd.c file was using device IDs not associated with the Stoney Ridge APU. The hudson_enable() code removed was also looking for incorrect device IDs and the PM_MANUAL_RESET register doesn't behave as the source indicates. The SD default settings may be overridden. Future improvements may include a few Kconfig options and a weak call to the mainboard for overriding additional defaults. BUG=chrome-os-partner:62580062 Change-Id: I7dbd70320740e8a05e6bf16af125d67012f20674 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/20401 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-27soc/amd/stoneyridge: Enable verstage supportMarshall Dawson
Add Kconfig selects for vboot and update the makefile to pick up files to be used in verstage. Change-Id: If5c439a330d687156006aec2ebaea18ff2c96b3e Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/19756 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-07-27soc/amd/common: Convert to C_ENVIRONMENT_BOOTBLOCKMarshall Dawson
Add dedicated CAR setup and teardown functions and Kconfig options to force their inclusion into the build. The .S files are mostly duplicated code from the old cache_as_ram.inc file. The .S files use global proc names in anticipation for use with the Kconfig symbols C_ENVIRONMENT_BOOTBLOCK and POSTCAR_STAGE. Move the mainboard romstage functionality into the soc directory and change the function name to be compatible with the call from assembly_entry.S. Drop the BIST check like other devices. Move InitReset and InitEarly to bootblock. These AGESA entry points set some default settings, and release/recapture the AP cores. There are currently some early dependencies on InitReset. Future work should include: * Pull the necessary functionality from InitReset into bootblock * Move InitReset and InitEarly to car_stage_entry() and out of bootblock - Add a mechanism for the BSP to give the APs an address to call and skip most of bootblock and verstage (when available) (1) - Reunify BiosCallOuts.c and OemCustomize.c (1) During the InitReset call, the BSP enables the APs by setting core enable bits in F18F0x1DC and APs begin fetching/executing from the reset vector. The BSP waits for all APs to also reach InitReset, where they enter an endless loop. The BSP sends a command to them to execute a HLT instruction and the BSP eventually returns from InitReset. The goal would be to preserve this process but prevent APs from rerunning early code. Change-Id: I811c7ef875b980874f3c4b1f234f969ae5618c44 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/19755 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-07-27soc/amd/stoneyridge: Convert 48Mhz enable to read/write32Marshall Dawson
Use the appropriate read32() and write32() calls. Remove unnecessary cast. Change-Id: Ib5430bdb30844d3508a09ddb77a969c0628f6c7d Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/20791 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-07-27soc/amd/stoneyridge: Clarify BAR mask in SPI baseMarshall Dawson
The format of the D14F3xA0 SPI Base_Addr register is different than a traditional BAR. Change the function to preserve any enables already in place. Change the AND mask to remove the reserved field and the enables. Change-Id: I9a43c029a2e1576703ce9cdc787d18658e9190a5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/20790 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-07-27soc/intel/cannonlake: Correct gpio definitionLijian Zhao
The following changes have been applied for GPIO: 1. Correct port id using by GPIO community 3 for CNL-LP. 2. Correct number of doubleword for each pad from 2 to 4. Change-Id: I717d1ffba8e6722543f4cf8083fe6145fa85e184 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/20775 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-07-27libpayload/storage: Replace 1s AHCI reset delay with a timeoutNico Huber
AHCI spec explicitly states that we may poll. TEST=Ran FILO on kontron/bsl6 and observed that the controller always becomes ready during the first delay. Change-Id: If34694abff14d719d10d89bc6771dbfa12065071 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20764 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-07-27libpayload/storage: Enable bus mastering for AHCINico Huber
This is (thankfully) not done by coreboot any more for recent chipsets. Change-Id: If56e38037f7b1e53871ee63e6ff297028c59d493 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20763 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-07-27siemens/mc_apl1: Select skip RAPL configurationMario Scheithauer
The mc_apl1 mainboard needs to disable the RAPL algorithm for a constant power management of the processor package. An active RAPL algorithm leads to negative effects with our real time software. Change-Id: I09ca56a034fd3896a000e64cac35f12fb507a682 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/20760 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-27soc/intel/apollolake: Make usage of RAPL selectableMario Scheithauer
Apollo Lake SoC supports configuration of Running Average Power Limits (RAPL) for package domain. This feature is not required for all APL mainboards. According to the APL SoC EDS Vol 4 chapter 18.4 Power Limiting Control it is not necessary to enable the RAPL algorithm per default. For that reason make the RAPL configuration selectable. Change-Id: Ib737b162f72b76c15e5768859f9099e2e7ef6426 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/20759 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-27timestamp: Apply factor to recorded stampsKyösti Mälkki
If we dont have a constant TSC rate, timestamp table has odd leaps and may appear to run backwards. Add functionality to apply a factor such that all stamps are in the same timebase. Change-Id: Idab9c2c00e117c4d247db8cc9a2897640fa01edd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/19330 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-27mainboard/google/poppy: Configure GPIO.1 and GPIO.2 for daisy chain modeV Sowmya
Configure GPIO.1 and GPIO.2 as sensor SDA and SCL respectively for TPS68470 PMIC in daisy chain mode. * GPIO.1: Sensor SDA in daisy chain mode. * GPIO.2: Sensor SCL in daisy chain mode. BUG=b:38326541 BRANCH=none TEST=Build and boot soraka. Dump and verify that the generated DSDT table has the required entries. Verified that sensor probe is successful. Change-Id: I7f9686427772a33c06e4cdaafee9b0349d700639 Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/20665 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rajmohan Mani <rajmohan.mani@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-07-27mb/google/kblrvp: Add camera devices power sequencing through ACPI power ↵V Sowmya
resources This patch controls the camera devices power through ACPI power resource. * Add Opregions for PMIC1 and PMIC2, * TI_PMIC_POWER_OPREGION * TI_PMIC_VR_VAL_OPREGION * TI_PMIC_CLK_OPREGION * TI_PMIC_CLK_FREQ_OPREGION * Add power resources for sensors and VCM, * OVTH for CAM0 * OVFI for CAM1 * VCMP for VCM * Implement _ON and _OFF methods for sensor and VCM module's power on and power off sequences. BUG=none BRANCH=none TEST=Build and boot kblrvp. Dump and verify that the generated DSDT table has the required entries. Verified that sensor probe is successful. Change-Id: I02c4784ab3f4d6e1f0e657ad50b727ff11da8b9c Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/20663 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-07-27mb/google/kblrvp: Configure ports and endpoints for sensor and CIO2 devicesV Sowmya
Bind the camera sensor and CIO2 devices through the ports and endpoints configuration available in _DSD ACPI object. * Port represents an interface in a device. * Endpoint represents a connection to that interface. BUG=none BRANCH=none TEST=Build and boot kblrvp. Dump and verify that the generated DSDT table has the required entries. Change-Id: If328864dbb61586a4887c7fcae740a12eda7cc92 Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/20662 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-07-27mainboard/intel/kblrvp: Add MIPI camera supportV Sowmya
This patch adds mipi_camera.asl and enables I2C2, I2C3, CIO2 and IMGU devices, * Add TPS68470 PMIC1 and PMIC2 related ACPI objects. * Add OV cameras related ACPI objects. * Add Dongwoon AF DAC related ACPI objects. * SSDB: Sensor specific database for camera sensor. * CAMD: ACPI object to specify the camera device type. KBLRVP has two PMIC's sitting on I2C2 and I2C3. CAM0 and CAM1 power requirements are handled by PMIC1 and PMIC2 respectively. BUG=none BRANCH=none TEST=Build and boot kblrvp. Dump and verify that the generated DSDT table has the required entries. Change-Id: Ibaf26dad74ca1e7c9f415ae75c4ed8558ad99e2f Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/20661 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-07-27soc/intel/skylake/igd.c: check return value of init_igd_opregionMartin Kepplinger
init_igd_opregion itself is supposed to return cb_err so this adds error handling, just like other implentations of write_acpi_tables do it. this had been found by coverity: *** CID 1378270: Error handling issues (CHECKED_RETURN) /src/soc/intel/skylake/igd.c: 147 in write_acpi_igd_opregion() 141 /* If IGD is disabled, exit here */ 142 if (pci_read_config16(device, PCI_VENDOR_ID) == 0xFFFF) 143 return current; 144 145 printk(BIOS_DEBUG, "ACPI: * IGD OpRegion\n"); 146 opregion = (igd_opregion_t *)current; CID 1378270: Error handling issues (CHECKED_RETURN) Calling "init_igd_opregion" without checking return value (as is done elsewhere 5 out of 6 times). 147 init_igd_opregion(opregion); 148 update_igd_opregion(opregion); 149 current += sizeof(igd_opregion_t); 150 current = acpi_align_current(current); TEST=Built Change-Id: If6f5d53037f093607d89cfe8faf193d55de7f6c4 Found-by: Coverity (CID 1378270: Error handling issues (CHECKED_RETURN)) Signed-off-by: Martin Kepplinger <martink@posteo.de> Reviewed-on: https://review.coreboot.org/20766 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2017-07-26intel/cannonlake_rvp: Split RVP boards and SPDLijian Zhao
Add both Cannonlake U DDR4 RVP and Cannonlake Y LPDDR4 RVP support. Implement SPD entry to FSPM for both platforms, seperated platform specific DQ/DQS/Rcomp input to FSPM as well. Change-Id: If71662353ddba89a9e831503a2d80dd5ebd65de3 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/20503 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-26mainboard/intel/glkrvp: configure RAPL PL1 for GLKCole Nelson
Sets RAPL PL1 power to ~6W. Note: 7.5W setting gives a run-time 6W actual measured power. Tested on GLK w/kernel 4.11.0 by reading MSR 0x610 at runtime and comparing to measured power on an instrumented board. Change-Id: I07caeb2895a579387025d3b0fb7f1d2c3d5e2665 Signed-off-by: Cole Nelson <colex.nelson@intel.com> Reviewed-on: https://review.coreboot.org/19746 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-07-26mainboard/intel/glkrvp: Add support for GLKRVPHannah Williams
GLKRVP is a reference board for GLK SOC RVP1 has DDR4 and RVP2 has LPDDR4 RVP2 is enabled by default and CONFIG_IS_GLK_RVP_1 should be selected if building for RVP1 GLKRVP can work with internal Intel EC or external Chrome EC AIC. For internal EC, CONFIG_EC_GOOGLE_CHROMEEC will not be selected ( CONFIG_GLK_INTEL_EC should be selected for internal EC config) By default, CONFIG_GLK_CHROME_EC is selected for external ChromeEC AIC config. Signed-off-by: Hannah Williams <hannah.williams@intel.com> Change-Id: Iab688aca6a4f5c5e32801215ba3a1a440e50fbef Reviewed-on: https://review.coreboot.org/19604 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-26libpayload: Clean up unaligned memset() supportNico Huber
Use a `for` instead of a `while` loop and use meaningful identifiers. Also, don't use more than one variable for one and the same purpose, don't use more (non-const) variables than necessary, don't alter more than one variable per statement, don't compare pointers of different types and don't do pointer arithmetic on `void *`. This was meant as a fix up to a regression but that has already been fixed. Change-Id: I0c8fd118d127a26cfcf68bfb0bf681495821e80a Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20750 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-07-26payloads/depthcharge: Fix clean targetNico Huber
This line has a weird history. It got a `|| exit 0` removed lately which obviously was there to fix the presence of the superfluous `test` at the beginning. Now, remove the `test` too to make the clean target always succeed again ;) Change-Id: I9e069cf5d9ac8416cf350161439aa60798ef7b6b Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20769 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-07-26Port cmos.default handling to C environment bootblockNico Huber
Gather related code in the new file drivers/pc80/rtc/mc146818rtc_boot.c, call sanitize_cmos() from C environment bootblock. Change-Id: Ia5c64de208a5986299c0508d0e11eeb8473deef1 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20768 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-26drivers/pc80/rtc: Build for bootblock and postcar stages tooNico Huber
Fixes builds with BOOTBLOCK_CONSOLE && USE_OPTION_TABLE. Change-Id: I1c7e9baa60f33c2c3651e2def0335454f7e20451 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20767 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-26soc/intel/skylake/chip.h: Provide enum values for SataModeNico Huber
The values were verified to be correct with the KabylakeFsp0001 from github. Skylake FSP documentation disagrees so YMMV. Change-Id: I1ee04dbbed48d5376dbc24ae70753b059f2646eb Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20765 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-26vendorcode/intel/fsp/fsp2_0/glk: Update header files as per v52_27Ravi Sarawadi
Update glk header files as per v52_27 FSP code. Change-Id: I8e313a2b854e60b1ad8a5c6e080641e323de56a8 Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-on: https://review.coreboot.org/20673 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-26soc/intel/apollolake: Update memory HOB info save functionRavi Sarawadi
SMBIOS memory HOB produced by glk FSP v52_27 has new structure members, which are not available in current apl FSP. New FSP-m header file in https://review.coreboot.org/#/c/20673/ lists new SMBIOS structure members. Break memory HOB save routine into different functions for glk and apl to accomodate new changes. Change-Id: I33c6e4f2842cebbb326b6a05436fa69e3836ffc6 Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-on: https://review.coreboot.org/20674 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-07-26intel/common/block/itss: Extend itss_irq_init() to handle IOSF 1.0Werner Zeh
Current implementation of itss_irq_init() uses 8 bit write access to IRQ routing registers which is not supported on Apollo Lake. This commit moves the register access from 8 bit to 32 bit so that this function can be used with every platform. Change-Id: I15c3c33a16329fd57f0ad7f99d720adbf300d094 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/20680 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-25amd/gardenia: Correct PCIe port settingsMarshall Dawson
Fix the OEM settings for two ports. Fix and clarify comments to reflect Rev. B of the board design. Change-Id: I2812ea5945f67229872e78041c771606047bbbec Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/20744 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-07-25sb/intel/i82801jx: Add Interrupt pin and routing RCBA offsets macrosArthur Heymans
Change-Id: If8e82a291f666d5f310422b100f02d5df17ab74e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19255 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-07-25sb/intel/i82801jx: Route all PIRQ to INT11Arthur Heymans
Interrupt 11 is not used by legacy devices and so can always be used for PCI interrupts. Full legacy IRQ routing is complicated and hard to get right. Change-Id: I6c718f4b9fb91ffcc4a136120581a4fcd7ec7231 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19254 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-07-25vendorcode/amd/agesa: f15tn & f16kb: fix assertMartin Roth
Fixes warning by GCC 7.1: note: did you mean to use logical not? Change-Id: If8167c6fe88135ae89eb795eeda09e6937b1684f Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20698 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-07-25amd/gardenia: Fix IS_ENABLED for fan controlMarshall Dawson
Convert from #if to if(). Change-Id: I50b3ed9ecd5947ff625536b196d90ebd4e8f1c56 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/20746 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-07-25sb/intel/common/gpio: Only set one bit at timePatrick Rudolph
Make sure to set only one bit instead of arbitrary bits set in argument. Change-Id: I39426193d15d8581f79bc2a45c0edb53b19a2cd3 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/20707 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-25amd/gardenia: Fix IS_ENABLED for xHCIMarshall Dawson
Convert from #if to if(). Change-Id: I7c149856da22b72d2a83bd7f06d031df328dbb35 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/20745 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-07-25abuild: Update file locationsMartin Roth
The full path to the passed/failed build lists needs to be specified. On the builders, the absolute path is passed in, which conflicted with the ${TOP} value, causing this to fail on the builders. When TOP was removed from the path, the builders worked correctly, but it failed when run locally. This fixes the path in either case. Change-Id: Ia4370f4a2b84991edccfc723a3136b88ca27db7d Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20660 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-07-25src/vendorcode/amd/agesa/f15tn: Fix bitmaskMartin Roth
Fixes GCC 7.1 error: error: '<<' in boolean context, did you mean '<' ? Change-Id: I1a28522279982b30d25f1a4a4433a1db767f8a02 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20699 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-07-25soc/intel/skylake: Add IGD id for mobile Xeon with GT2Nico Huber
Change-Id: I2cd210dd0443b854294ce7ee8e267594e3ea1780 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20651 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2017-07-25drivers/intel/fsp2_0: Add NULL check while locating hob list ptrSubrata Banik
Assert incase unable to locate hob list pointer due to cbmem is not available. Change-Id: I17f54b07ab149ae06d09226ed9063189d829efe2 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/20749 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-25soc/intel/skylake: soc/intel/skylake: Initialize struct member to 0Subrata Banik
As per GCC 7.1 compiler struct reset_reply is considered as uninitialized inside send_heci_reset_message function. Change-Id: Ide53a9267dfba1a00263ada1d7016a48ecb9aad8 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/20739 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-07-25soc/intel/skylake: Skip Spi Flash Lockdown from FSPBarnali Sarkar
coreboot was setting SPI FPR register to protect the mrc_cache data range stored in flash. This programming was being done after FSP Notify 1. But, FSP was locking the SPI by setting FLOCKDN Bit during Notify phase 1, due to which coreboot was unable to protect that range. As solution, FSP introduced a new UPD SpiFlashCfgLockDown to skip the lockdown of flash on interest of bootloader. Set that UPD to 0 to skip the lockdown of FAST_SPI flash from FSP. The same is being done from coreboot after end of Post at finalize.c file. BUG=b:63049493 BRANCH=none TEST=FPR can be set properly to protect the mrc_cache range. The issue reported in the bug doesn't come when both software and hardware WP is enabled with this patch. Change-Id: I3ffca2f1b05ab2e4ef631275ef7c3a6e23e393aa Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/20645 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-25vendercode/intel/fsp/skykabylake: Add new UPD SpiFlashCfgLockDownBarnali Sarkar
A new UPD named SpiFlashCfgLockDown is added in the FSP-S header file. This change is going to come in FSP in the next FSP release. This patch is pushed to urgently fix the SPI FPR locking issue. CQ-DEPEND=CL:*414049 BUG=b:63049493 BRANCH=none TEST=Built and boot poppy Change-Id: I4725506103781a358b18ee70f4fdd56bf4ab3d96 Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/20644 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-25soc/intel/common/block: Modify fast_spi_lock_bar functionBarnali Sarkar
Use 16bit write to avoid touching the upper two bytes that may cause write cycle to fail in case a prior transaction has not completed. This function sets the WRSDIS(Bit 11) and FLOCKDN (Bit 15) of the SPIBAR + BIOS_HSFSTS_CTL. While WRSDIS is lockable with FLOCKDN, writing both in the same cycle is guaranteed to work by design. Avoid read->modify->write operation not to clear the RW1C bits unintentionally. Change-Id: Ia7880aaca0ed64150c994d49786a0a008bbaa98b Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/20643 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-07-25src/arch: Fix checkpatch warning: no spaces at the start of a lineMartin Roth
Change-Id: Id9846ceb714dceaea12ea33ce2aa2b8e5bb6f4df Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20728 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-07-25src/device: Fix checkpatch warning: no spaces at the start of a lineMartin Roth
This excludes some files in the device/oprom/x86emu folder which are mostly spaces, and which I felt should be handled separately. debug.c, decode.c, fpu.c, ops.c, ops2.c, & prim_ops.c Change-Id: I5c12d3fc942c9ad99bbe6e6e54db93e5a8402392 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20730 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-07-25src/lib: Fix checkpatch warning: no spaces at the start of a lineMartin Roth
Change-Id: I332c44c6db0a5ea05db076474caf77d6c50d4673 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20732 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-07-24soc/intel/common/block: Add max SPI transaction time-out as 5 secBarnali Sarkar
Earlier 15ms time-out was kept for SPI transactions which was not enough for SPI Erase transactions. Increase the max time-out time to 5 secs which was present in SKL before common code. This increase in time-out won't disturb other SPI transactions like Read, Write or Read Status, since, for those it will come out of the loop once FDONE bit or FCERR bit is set. BUG=b:63959637 BRANCH=none TEST=Built and booted poppy and all SPI transactions succeeded. Change-Id: I1c015d80b33677de11755fb2097373631d1fa8c4 Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/20738 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-24google/reef: Configure EN_PP3300_DX_LTE on coralPatrick Georgi
BUG=b:63876329 BRANCH=none TEST=none Change-Id: I98c700d5b928c031129cf0138d22652a28d1ad1d Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/20752 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-07-24google/reef: copy gpio.c for coralPatrick Georgi
It requires changes to match the hardware. Except for the weak attributes that are now removed in coral's copy, the file is identical to the baseboard version. BUG=b:63876329 BRANCH=none TEST=none Change-Id: Ib0c5f0ecae9919f20631dacef0253416989fb011 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/20751 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-07-24nb/intel/i440bx: Add final newline to raminit.cMartin Roth
The newline lint check just went in, and immediately broke the build due to a commit that went in earlier today. This fixes the build. Change-Id: Ic4ba8ce0c8085861bc6c654afdee3fea9f4621fc Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20754 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-07-24mb/lenovo/t430: Disable `usb_always_on` by default in CMOSPatrick Rudolph
Fix regression introduced by commit 7ffb329f. The default value for usb_always_on is no longer sane and is replaced by the same default that is used on all other boards (disabled). Change-Id: Ia8854a8491bc56507d01e08e1ca1e195a1d62bfc Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/20575 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2017-07-24soc/intel/skylake: Use common opregion implementationPatrick Rudolph
Enable SOC_INTEL_COMMON_GFX_OPREGION for all FSP versions. Allows to get rid of opregion.c, as it's no longer needed. Change-Id: I39190488e12917a09dbf7ee3947a33940ebc290b Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/20222 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2017-07-24util/lint: Update final newline checkMartin Roth
- Exclude .png and .patch files. - Turn into a lint-stable test. Change-Id: I4a5c77d7856bc5017ba441d458378b4837c1c7d5 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20706 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-07-24sb/intel/i82801jx: Generate default fadt and madtArthur Heymans
Function copied from i82801gx with offsets fixed for i82801lx. Change-Id: Ib420c69470c3190cc1eac234ce68a18382fbc04a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19253 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-07-24Update files with no newline at the endMartin Roth
Change-Id: I8febb8d74e2463622cab0313c543ceebec71fdf4 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20705 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-07-24Fix files with multiple newlines at the end.Martin Roth
Change-Id: Iaab26033e947cb9cf299faf1ce6d40a90a9facbe Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20704 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-07-24mainboard/google/soraka: pull high TOUCHSCREEN_STOP_L pinWisley Chen
After updating to Wacom Firmware version 501, touchscreen can't work. Wacom FW (ver. 501) enables STOP function. STOP Pin: High: Normal Operation Low: Stop Scanning So pull TOUCHSCREEN_STOP_L high BUG=b:37007801, b:37265219 BRANCH=none TEST=manual testing on Soraka board and touchscreen works at boot and after suspend/resume. Change-Id: I8a2bdce1554fd99dea30cf91fa48d0529f40b7b0 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/20664 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-07-23sb/intel/i82801jx: Add function to detect s3 resumeArthur Heymans
File copied from i82801gx. Change-Id: I107087b6448f18b6a5ae21c2ae0392c057dd23b2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19252 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2017-07-23sb/intel/i82801jx: Add addition IO resourcesArthur Heymans
Adapted from i82801gx. Change-Id: I9108a45135908b7c4e74e9df3bb8f89f55893299 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19251 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2017-07-23asus/p2b-d: Use romstage from asus/p2b-ds.Keith Hui
The romstage for both is line-for-line identical. Merge both into P2B-DS so it benefits from my modernization efforts. Change-Id: Idd964f4c5c4dfd9e2e0ac4a4f41e4ee9a84a729c Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/20691 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-07-23asus/p2b-f: Use romstage from asus/p2b-ls.Keith Hui
The romstage for both is line-for-line identical. Merge both into P2B-LS so it benefits from my modernization efforts. Change-Id: I2d1a46236f83a4955ceb5e98b576cce0560f28df Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/20690 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-07-23440BX boards: Drop unused #includes from romstageKeith Hui
Romstage of many 440BX boards included headers that are not used. Remove them as part of a bigger cleanup effort. Change-Id: I89ddeda3c90e1a4907c05851185b69f3b29e54ba Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/20693 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-07-23asus/p2b-ls: Drop onboard LAN from devicetree.cbKeith Hui
I am able to complete a board-status run over onboard ethernet (ie. it works) without this entry, so it's not necessary. Change-Id: Iabdf1a1ff3c904bea1b7b5eaefb1d23831dd2cb9 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/20683 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-07-23northbridge/intel/i440bx: Merge RAM init routinesKeith Hui
There are 4 routines used in RAM init that most if not all i440bx mainboards call in the same order. Implements a single RAM init routine for them to allow for future consolidation. Boards to be changed to use this one routine in a future change. Change-Id: Ib553b07b117de12b7982586bce0f9355f55013a0 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/20676 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-07-23depthcharge: Update buildMartin Roth
- Add prompt so the defconfig can be selected for the build. - Remove target rename code from makefile. The old versions don't build with the latest vboot, so this isn't useful anymore. - Change $(info ...) to an echo. info prints immediately when evaluated, which made it print when it shouldn't have, on make clean for example. - Split up single line shell scripts into multiple lines - Change checkout target to only update the commit id when actually changing versions instead of on every build. Change-Id: I46fc2822cf93c821b402e8961ceecedc088f486c Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20667 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-07-23depthcharge: Update stable commit idMartin Roth
Update from commit eb583fa8 - Wed Mar 29, 2017 (rk3399_sdhci: Reintroduce PHY power-cycling at 52MHz) to commit 5a086f5c - Tue Jul 11, 2017 (ps8751: enable software sync) This brings the stable version of depthcharge forward by 74 commits. Change-Id: I3a3719fa3a91824042d452de7774be85b884d96d Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20666 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-07-23mainboard/google/{poppy,soraka}: Enable S0ixRajat Jain
Enable S0ix for poppy and soraka in their device trees respectively. BUG=b:36630881 BRANCH=none TEST=Verified S0ix and S3 operation on Poppy and Soraka (250+ iterations). Change-Id: I9ba91499e54f729970448af6f71804ad5b3cb836 Signed-off-by: Rajat Jain <rajatja@google.com> Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/20689 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-22northbridge/intel/i440bx: Move NB macro to i440bx.hKeith Hui
This move makes the NB macro more widely available, in preparation for implementing get_top_of_ram(). Change-Id: Icd8e82cfdfdccb662b2139d0e5d1d5af72cbae7f Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/20675 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2017-07-22soc/intel/cannonlake: Keep variable from going out of scopeMartin Roth
The variable p was going out of scope while still being pointed to by *cpu_name. Fix coverity ID 1378215 (Pointer to local outside scope) Change-Id: I6ad7b1919104b4d97869efe5065e39c2a43de638 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20682 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2017-07-22mainboard/google/poppy/variants/soraka: Update GPP_{D1,D2,B7} configFurquan Shaikh
GPP_B7, GPP_D1 and GPP_D2 are not used going forward. Mark them as NC in gpio table. BUG=b:62322846,b:62240755 Change-Id: I7aee08314e6ce96d5913ae315bf75f5c04ab7370 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/20672 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-07-22mainboard/google/poppy/variants/soraka: Define separate gpio tablesFurquan Shaikh
Now that soraka is starting to deviate from the baseboard w.r.t. gpio settings, make a new copy of gpio table before we make any variant-specific changes in it. BUG=b:62240755,b:62322846 BRANCH=None TEST=Verified with gpio_debug=1 in skylake/gpio.c that the gpio configuration before and after this change remains same. Change-Id: I448d18f18b63e9bfb739c518d599de3b9b602dc2 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/20671 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-21arch/arm/armv7: Correct checkpatch errorsLogan Carlson
- Correct whitespace issues with files under arch/arm/armv7. - Fix comments and remove unnecessary line continuations in mmu.c Change-Id: I69d50030b07b1919555feca44967472922176a81 Signed-off-by: Logan Carlson <logancarlson@google.com> Reviewed-on: https://review.coreboot.org/19996 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-07-21Revert "soc/intel/cannonlake: Add postcar stage support"Martin Roth
This reverts commit 399c022a8c6cba7ad6d75fdf377a690395877611. This was merged too early. I'll repost it. Change-Id: Iabac0aaa0a16404c885875137cf34bf64bf956f7 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20686 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-07-21Revert "soc/intel/cannonlake: Call into FSP siliconinit"Martin Roth
This reverts commit dbe7f893c0e3fffc4e9862d872d65df752feaf9d. This was merged too early. I'll repost it. Change-Id: Ife56f45e91c0b961d0fad0e1872c6df3f9e18973 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20685 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-07-21I82801JX: Add IS_ENABLED around config optionsMartin Roth
This chipset was just added and had a few places that needed to be fixed. Change-Id: Ief048c4876c5a2cb538c9cb4b295aba46a4fff62 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20684 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-07-21soc/intel/apollolake: Add pci device id for GLK IGDHannah Williams
Change-Id: Id2c94afed8976687524a0913ea1c13aeddd98333 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/20654 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-07-21soc/intel/cannonlake: Call into FSP siliconinitLijian Zhao
The following changes can make system call into FSP siliconinit and exit from that until payloads. 1. Add frame to call fspsinit. 2. Temporarily set all the USB OC pin to 0 to pass FSP siliconinit. Change-Id: I1c9c35ececf3c28d7a024f10a5d326700cc8ac49 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/20581 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-21soc/intel/cannonlake: Add postcar stage supportLijian Zhao
Initialize postcar frame once finish FSP memoryinit Change-Id: I888d471fa620b7fc9f8975524a31f662e1fc5079 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/20534 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-21util/lint: exclude patch files from asm syntax checkMartin Roth
This allows the paches to add cross-compile support for true x86 16-bit GCC (ia16) to go in. Change-Id: If9246b5fb2f3578afea601fd63b7d716ddf8597e Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/19714 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-07-21util/vgabios: Don't call redefined printk in printkStefan Reinauer
A few pieces of coreboot code (like the video bios emulator) are imported from other code bases, and hence might call printf. In order to see the output, we redefine printf to printk. However, when we are re-importing this code in a userspace utility, we might call printk instead of printf if we're not careful. A good fix for this would be to not call printf in coreboot ever. As a short term fix to keep testbios from segfaulting, we just don't call printf from printk, so we don't cause our own stack to overflow. Change-Id: I789075422dd8c5f8069d576fa7baf4176f6caf55 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/20658 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>