Age | Commit message (Collapse) | Author |
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device arrangement that can be statically configured during boot.
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_RESET to specify reset vector address (ppc4xx reset vector is at end of
memory, rather than at beginning of ROM)
CONFIG_SYS_CLK_FREQ to specify frequency of system clock (needed for ppc4xx
clock speed calculation)
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remove unused make.base.lb
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Bump up debugging messages and reduce the size of memory test until that is
running correctly.
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The object rules now have four members, this is getting KLUDGY!
[object, source, type (i.e. suffix), base]
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which boots linux as a payload.
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- SMP cleanups (remove SMP only use CONFIG_SMP)
- Minor tweaks to romcc to keep it from taking forever compiling
- failover fixes
- Get a good implementation of k8_cpufixup and sizeram for the opteron
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* remove dead code from coherent_ht.c
* add ldtstop code for link speed changes
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- Changes to allow more code to be compiled both ways
- Working SMP support
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Moved payload into romimage
More flexible romimage declaration
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due to different routing defaults of different boards.
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- Remove some debugging code from auto.c
- Update coeherent_ht.c so we get the proper broadcast routes.
- Fix the dram probing code.
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- Add initial support for the amd8131
- Update the mptable to something possible
- hdama/Config add the amd8131 southbridge
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bridge resources
- coherent_ht.c remove dead idle loop.
- raminit.c Enable a 64MB mmio window just below 4GB
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masking right when setting cpucnt/nodecnt
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- romcc_io.h Add include guards.
- hdama/Config nothing really but I have been moving the setting back and forth between 1 and 2 cpus
- auto.c Changed the enabled debugging comments. This almost works with 2 cpus
- coherent_ht.c First pass at getting this right. It can now find 2 cpus and place them
in some semblance of a working state.
- raminit.c Fix problems with 4GB of ram. Disable some of the debugging code.
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assigned value
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