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2023-01-02soc/intel/common: Move SGX supported API to cpulibPratikkumar Prajapati
Move is_sgx_supported() API to common cpulib code, so that this function can be used by other code without enabling SOC_INTEL_COMMON_BLOCK_SGX_ENABLE config option. Change-Id: Ib630ac451152ae2471c862fced992dde3b49d05d Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71116 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2023-01-01apollolake/include/soc/meminit.h: Add missing stdboolElyes Haouas
stdbool is added through types.h file. Change-Id: I317faf322a7e73b706724802d99815ab50e655e2 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71245 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-31security/intel/stm/StmPlatformResource.c: Fix typo on "threads"Elyes HAOUAS
Change-Id: Id57a9c689d5fa35cf1b4df9c37b12dd95cb9ef23 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-12-31mb/google/brya/var/gladios: Update audio codec i2c timingKevin Chiu
Adjust audio codec i2c timing to 399 kHz. BUG=b:262959586 TEST=FW_NAME=gladios emerge-brask coreboot Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Change-Id: I2f621e3af39fb40ab270c9de35d51dd43147b8f7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70897 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ricky Chang <rickytlchang@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-31Enable VBOOT_VBNV_FLASH for SOC_INTEL_BRASWELLYu-Ping Wu
To deprecate VBOOT_VBNV_CMOS [1], replace VBOOT_VBNV_CMOS with VBOOT_VBNV_FLASH for boards using SOC_INTEL_BRASWELL. Currently BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES is selected for CPU_INTEL_HASWELL, SOC_INTEL_BRASWELL and others (see [2]). However, there seems to be no particular reason on those platforms. We've dropped the config for haswell. Now do the same for SOC_INTEL_BRASWELL, so that VBOOT_VBNV_FLASH can be enabled. VBOOT_VBNV_FLASH is enabled for the following boards: - facebook/fbg1701: A 0x2000 RW_NVRAM region is allocated, with the FW_MAIN_A(CBFS) size reduced by 0x2000. - google/cyan, intel/strago: Repurpose RW_UNUSED as RW_NVRAM. [1] https://issuetracker.google.com/issues/235293589 [2] commit 6c2568f4f58b9a1b209c9af36d7f980fde784f08 ("drivers/spi: Add BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES config") BUG=b:235293589 TEST=./util/abuild/abuild -t FACEBOOK_FBG1701 -a (with VBOOT selected) TEST=./util/abuild/abuild -x -t GOOGLE_CYAN -a TEST=./util/abuild/abuild -x -t INTEL_STRAGO -a Change-Id: I46542c2887b254f59245f20b8642b023a7871708 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71544 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
2022-12-31mb/facebook/fbg1701: Enlarge COREBOOT region for VBOOT by 64kBYu-Ping Wu
When VBOOT is enabled, the COREBOOT region (of size 0x09B000) is not large enough. Therefore, adjust vboot-rw.fmd (which is used only with VBOOT) layout by moving 0x10000 space from FW_MAIN_A(CBFS) region to COREBOOT(CBFS) region. TEST=./util/abuild/abuild -t FACEBOOK_FBG1701 -a (with VBOOT selected) Change-Id: I1bc0d6981b873ca631cc4cc0720ab212700a65aa Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71543 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
2022-12-31mb/google/rambi: Drop ChromeOS supportYu-Ping Wu
There is an ongoing effort to deprecate VBOOT_VBNV_CMOS [1] and replace with VBOOT_VBNV_FLASH. However, the rambi's CAR is too small for early flash access in romstage: /usr/local/google/home/yupingso/projects/coreboot/util/crossgcc/xgcc/bin/i386-elf-ld.bfd: Cache as RAM area is too full /usr/local/google/home/yupingso/projects/coreboot/util/crossgcc/xgcc/bin/i386-elf-ld.bfd: section .car.mrc_var VMA [00000000fe008000,00000000fe00ffff] overlaps section .car.data VMA [00000000fe000000,00000000fe008787] make: *** [src/arch/x86/Makefile.inc:194: coreboot-builds/GOOGLE_RAMBI/cbfs/fallback/romstage.debug] Error 1 More precisely, DCACHE_RAM_SIZE is 0x8000, and the current .car.data size is 0x76c0. If BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES is unselected, then the _bss region will increase by 0x10c8 bytes (for global variables such as `elog_mirror_buf` and `sfg`), so that .car.data will exceed 0x8000. Since rambi has reached its AUE (2021-09-01), disable MAINBOARD_HAS_CHROMEOS and VBOOT configs. [1] https://issuetracker.google.com/issues/235293589 BUG=b:235293589 TEST=./util/abuild/abuild -t GOOGLE_RAMBI -a TEST=./util/abuild/abuild -x -t GOOGLE_RAMBI -a Change-Id: Id56795dd0653784b4d7141142ebef0b19a46ddc3 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71545 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-12-30fw_config: Fix typo in documentBora Guvendik
There is no fw_config_probe_one api, change it to fw_config_probe. BUG=none TEST=none Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: I916713c038f72a1718be8c9d4e8e21420effbf76 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71276 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-12-30mb/google/skyrim/var/frostflow: Update I2C setting for touchpadJohn Su
Update setting for touchpad I2C frequency. And meet touchpad i2c SPEC (380 ~ 400 kHz). BUG=b:261159229 TEST=On frostflow, touchpad i2c spec from EE measure Frequencies: I2C0 (Touchpad): 390.1 kHz Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: Ied00e43e87404489af2b570206a70b685e554b78 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71564 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-29{ec,mb}/system76/acpi: Use Printf() for debug printsFelix Singer
Change-Id: Ia5ae30a1ee976b8059936027b28ac56f37279217 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71516 Reviewed-by: Tim Crawford <tcrawford@system76.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-29mb/intel/mtlrvp: Add configuration for UART devicesHarsha B R
This patch adds below configuration for MTL-RVP UART devices, Interface -> UART0 PCI -> 0:0x1e:0 Device -> AP UART BUG=b:224325352 TEST=Able to build with the patch and boot the mtlrvp ito chromeOS using subsequent patches in the train. UART logs appear on AP console. Signed-off-by: Harsha B R <harsha.b.r@intel.com> Change-Id: I4702d603aa49357f4db0d18d646e536d9d81787e Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70873 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-12-29mb/intel/mtlrvp: Configure GPIO Tier-1 GPEs for MTL-RVPHarsha B R
Configure GPIO Tier-1 GPE's that defines the route for GPE events for MTL-RVP. Configure GPE route as below, PMC_GPE0_DW0 -> GPP_B PMC_GPE0_DW1 -> GPP_D PMC_GPE0_DW2 -> GPP_E BUG=b:224325352 TEST=Able to build with the patch and boot the mtlrvp to ChromeOS using subsequent patches in the train Signed-off-by: Harsha B R <harsha.b.r@intel.com> Change-Id: Ieab95b72ade75734b0788a32566649d90acbc48a Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70872 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-12-28coding_style: Add more guidelines on error handling, die() and assert()Julius Werner
This patch adds a new section to the coding style which codifies existing practices about how to handle errors and how to use the die() and assert() macros. Also clean up some references to Linux-specific facilities that do not exist in coreboot in the adjacent function return type guidelines, and add a small blurb of documentation to the definition of the assert() macro itself. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Ice37ed9f995a56d69476e95a352209041b337284 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70775 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-12-28src/security/vboot: Fix wrong CONFIG nameMaximilian Brune
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I2af3bc9bf9eaf258b9180da5fc5494b21764f379 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71518 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-28mb/google/brya/var/kuldax: Add wifi sar tableDavid Wu
Add wifi sar table for kuldax BUG=b:248367859 BRANCH=firmware-brya-14505.B TEST=emerge-brask coreboot-private-files-baseboard-brya coreboot chromeos-bootimage Change-Id: I5ade590c739aae391e47e8bb66ee03c086e8d56e Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71270 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-27soc/intel/alderlake: Use common gpio.h includeDinesh Gehlot
Replace the intelblocks/gpio.h and soc/gpio.h includes with the common gpio.h which will include soc/gpio.h which will include intelblocks/gpio.h BUG=b:261778357 TEST=Able to build and boot Google/brya. Change-Id: Ia90a8ea7b4ee125657c7277e3e14018cfe5423a9 Signed-off-by: Dinesh Gehlot <digehlot@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71266 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-12-27mb/google/brya/var/kano: Enable Fast VMode for kanoDavid Wu
Fast VMode nmakes the SoC throttle when the current exceeds the I_TRIP threshold. BUG=b:252966799 BRANCH=firmware-brya-14505.B TEST=Verify that the feature is enabled by reading from fsp log Change-Id: I15c3eea6ebb7f104bce0ba8cb544ecde7f488343 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71267 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-27mb/intel/mtlrvp: Configure devicetree and GPIOs for MTL-RVPHarsha B R
Add devicetree and GPIO configuration for MTL-RVP Changes include, 1. Add initial devicetree to support MTL-RVP board & variant 2. Add initial setup for ramstage gpio config BRANCH=none BUG=b:224325352 TEST=Able to build with the patch and boot the mtlrvp to chromeOS using subsequent patches in the train. Signed-off-by: Harsha B R <harsha.b.r@intel.com> Change-Id: I3173c3f32b36d24467431df3652badd70efeab93 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69396 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Usha P <usha.p@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-12-27mb/intel/mtlrvp: Add bootblock and early gpio for MTL-RVPHarsha B R
This patch adds initial bootblock code. This also configures required GPIOs for early board initialization. 1. Add bootblock file for MTL-RVP 2. Add early gpio config for MTL-P variant in gpio.c BRANCH=none BUG=b:224325352 TEST=Able to build with the patch and boot the mtlrvp platform to ChromeOS with the subsequent patches in the train Signed-off-by: Harsha B R <harsha.b.r@intel.com> Change-Id: I9c0893e52036147c5f6bbfafc6d818e9d3460bed Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69886 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Usha P <usha.p@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-12-27mb/google/rex: Enable PMC IPC configSubrata Banik
TEST=Able to build and boot Google/Rex. Device (PMC) { Name (_HID, "INTC1026") // _HID: Hardware ID Name (_DDN, "Intel(R) Meteor Lake IPC Controller") // _DDN: DOS Dev ice Name Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0B) } ... } Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I28c0153a770b36cde0653ac92d2e5ad1b8dd3449 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71268 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-27tree/acpi: Replace constant "Zero" with actual numberFelix Singer
Change-Id: I5a3e3506415f424bf0fdd48fc449520a76622af5 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71525 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-27{superio,ec}/acpi: Replace constant "Zero" with actual numberFelix Singer
Change-Id: I449ec5b0bbf3f24d51688efef151d3018d2848b2 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71524 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-27mainboard/acpi: Replace constant "Zero" with actual numberFelix Singer
Change-Id: I4f2f02623b060ef0ebefc5aceb713c77a8b1e9a6 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71523 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-27{acpi,arch,soc}/acpi: Replace constant "One" with actual numberFelix Singer
Change-Id: I3dfd7dd1de3bd27c35c195bd43c4a5b8c5a2dc53 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71522 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-27mainboard/acpi: Replace constant "One" with actual numberFelix Singer
Change-Id: Id1078b14a805eea53d2a7c5a8183a5413f26e115 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71521 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-27{superio,ec}/acpi: Replace constant "One" with actual numberFelix Singer
Change-Id: I5c77b6d1e1dc1134f62dcb3e93df01dc9c2f386c Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71520 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-27mb/google/brya/var/marasov: Add DmaProperty for ISHSubrata Banik
On Marasov, the ISH is running closed source firmware, so the ChromeOS security requirements specify it must be behind an IOMMU. Add DmaProperty to the ISH _DSD on Marasov. TEST=Kernel marks ISH (PCI device 12.0) as untrusted, and changes the IOMMU group type to "DMA". Also, device still goes to S0i3. Before: $ cat /sys/devices/pci0000\:00/0000\:00\:12.0/untrusted 0 After: $ cat /sys/devices/pci0000\:00/0000\:00\:12.0/untrusted 1 Change-Id: I4b65b8909c41b06852fe7771375029bd2e76e111 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71263 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-27drivers/intel/ish: Add ADL-P ISH DIDSubrata Banik
This patch adds ISH ID for ADL-P to ensure dynamic ASL code is added into SSDT. With this patch: Scope (\_SB.PCI0.ISHB) { Name (_DSD, Package (0x02) // _DSD: Device-Specific Data { ToUUID ("70d24161-6dd5-4c9e-8070-705531292865"), Package (0x01) { Package (0x02) { "DmaProperty", One } } }) } Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I48dc6056155824239bb88eda2b0ff5bcd36ced15 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71262 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyle Lin <kylelinck@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-27mb/google/brya/var/marasov: Remove ISH firmware-nameSubrata Banik
For marasov, the ISH main firmware will be included in the CSE region in flash instead of loading it from rootfs. So remove the ISH firmware-name. TEST=Boot to OS on Marasov UFS SKUs. Check ISH firmware is not loaded by kernel, and device still goes to S0i3. Change-Id: I278e5d403ef9515e538a527f43949e505d750bb1 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71261 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyle Lin <kylelinck@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Jamie Chen <jamie.chen@intel.com>
2022-12-26sio/winbond/w83627hf/acpi: Replace Divide(a,b,c,d) with ASL 2.0 syntaxElyes Haouas
Replace Divide (a,b,c,d) with: c = a % b d = a / b Change-Id: I0e9fdabbb4b5bd9698968cd8acb497dcde14e433 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71508 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-26tree/acpi: Replace Divide(a,b,c,d) with ASL 2.0 syntaxFelix Singer
Replace `Divide (a, b, c, d)` with these instructions: c = a % b d = a / b Change-Id: I44366be5b5145a5d19f85df7a2f338866cb9c8b0 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71515 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-12-26mb/lenovo/s230u/acpi: Replace Not(a, b) with ASL 2.0 syntaxFelix Singer
Replace `Not (a, b)` with `b = ~a`. Change-Id: I0f18119c8e91222e59a56b8509f12c6ece6d04ce Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71514 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-26tree/acpi: Replace Not(a) with ASL 2.0 syntaxFelix Singer
Replace `Not (a)` with `~a`. Change-Id: I53993fb7b46b3614d18ee001323f17efacbf04c1 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71513 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-26drivers/pc80/vga: Add NULL check for `vga_line_write()`Subrata Banik
This patch ensures vga_line_write() returns if the argument 1 (aka output string) is NULL. TEST=Able to build and boot Google/Taeko. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I716ce82c0afe21f7fe2f6d7bdc5229f8087242fa Reviewed-on: https://review.coreboot.org/c/coreboot/+/71264 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-12-26sio/acpi/pnp.asl: Replace Not(a) with ASL 2.0 syntaxElyes Haouas
Change-Id: Icbd2ab736b9fc3300ee82896c31b373fe92e1d54 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71509 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-26nb/intel/ironlake/acpi: Replace Index(a, b) with ASL 2.0 syntaxElyes Haouas
Change-Id: I6af7131e151700569d50e8bc42bfaeb7a58fa7d3 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71507 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-26nb/intel/sandybridge/acpi: Replace Index(a, b) with ASL 2.0 syntaxElyes Haouas
Change-Id: I75bc048d9e04be8d0cab25f6aad1c71d3e7a4008 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71506 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-26nb/intel/haswell/acpi: Replace Index(a, b) with ASL 2.0 syntaxElyes Haouas
Change-Id: I1ff0132e17b08f492828eb13d66e167eae45250d Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71505 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-26soc/intel/baytrail/acpi: Replace Index(a, b) with ASL 2.0 syntaxElyes Haouas
Change-Id: Iab611cda1083da4378a6e509d11ea26bdbb45edd Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71503 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-26soc/intel/braswell/acpi: Replace Index(a, b) with ASL 2.0 syntaxElyes Haouas
Change-Id: I7da6ee3c5bce6b32874e59ad46290b86db8f97c6 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71502 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-25soc/intel/meteorlake: Make use of is_devfn_enabled() functionDinesh Gehlot
1. Replace all pcidev_path_on_root() and is_dev_enabled() functions combination with is_devfn_enabled(). 2. Remove unused local variable of device structure type (struct device *). 3. Replace pcidev_path_on_root() and dev->enabled check with is_devfn_enabled() call. TEST=Able to build and boot without any regression seen on MTL. Port of 'commit 50134eccbdf4 ("soc/intel/alderlake: Make use of is_devfn_enabled() function")' Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: I54bbd2bdba69a19e0559738035916fa7ac60faaa Reviewed-on: https://review.coreboot.org/c/coreboot/+/71161 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-12-25soc/intel: Move max speed API to commonDinesh Gehlot
This patch moves API "smbios_cpu_get_max_speed_mhz()" to common code from board specific. This API was made generic in 'commit d34364bdea12 ("soc/intel/alderlake: Utilize `CPU_BCLK_MHZ` over dedicated macro")' BUG=NONE TEST=Boot and verified that SMBIOS max speed value is correct on brya and rex. (brya) dmidecode -t : "Max Speed: 4400 MHz" (rex) dmidecode -t : "Max Speed: 3400 MHz" Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: I87040ab23319097287e191d7fc9579f16d716e62 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70879 Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-25arch/riscv: Use 'enum cb_err'Elyes Haouas
Change-Id: I5a589a43b1e92cca6b531ca161174eefb5592569 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68371 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-12-25arch/x86: Use 'enum cb_err'Elyes Haouas
Change-Id: I38e4b8c6adfaaa45377b2fbe0644285d21841cd1 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68369 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-12-25util/docker: Update setuptools to get dtc buildingMartin Roth
python3-setuptools installed via apt-get is not currently working to build dtc from git.kernel.org. Falling back to setuptools version 58.2.0 allows it to build again. The failure message was: /usr/lib/python3/dist-packages/setuptools/installer.py:27: SetuptoolsDeprecationWarning: setuptools.installer is deprecated. Requirements should be satisfied by a PEP 517 installer. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I04cb6d776c3748f9a4b0cfc4ffd4f46458560d3d Reviewed-on: https://review.coreboot.org/c/coreboot/+/71500 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-24util/mb/google: Add support for rexSubrata Banik
Add the file templates for creating a new variant of Rex. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I4abca1f999accc008eb2549fcc13199b8d9bdc7a Reviewed-on: https://review.coreboot.org/c/coreboot/+/71086 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-12-24mb/google/rex: Enable DPTF functionality for Rexzhaojohn
Enable DPTF functionality for Meteor Lake Rex board. BUG=b:262498724 TEST=Booted to OS and verified DPTF entries in ACPI SSDT on Rex board. Change-Id: I87b2d71650be9ce940d9452bf4a76d4cd1ddba52 Signed-off-by: zhaojohn <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70884 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-24soc/intel/alderlake: Select SOC_INTEL_CSE_SEND_EOP_LATETracy Wu
With enabling FSP Notify Phase APIs, it has chance to issue a global reset in FSP after CSE EOP (with selecting SOC_INTEL_CSE_SEND_EOP_EARLY ), which CSE already in idle mode and cause failure. For this reason we should drop SOC_INTEL_CSE_SEND_EOP_EARLY in all ADL sku and select SOC_INTEL_CSE_SEND_EOP_LATE instead. BUG=b:261544011 BRANCH=firmware-brya-14505.B TEST=tested and verified on Marasov, make sure this kind of global reset can be executed successfully. Signed-off-by: Tracy Wu <tracy.wu@intel.corp-partner.google.com> Change-Id: I29736ca8efee64dd03feb48404241ee6295b7c72 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71224 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-12-24mb/google/volteer/eldrid: Correct DDR4 SPDs for EldridJohnny Li
Correct DDR4 SPDs from H5AG36EXNDX019 to H5AG36EXNDX017. DRAM Part Name ID to assign H5AG36EXNDX017 0 (0000) BUG=b:236739240 BRANCH=Volteer TEST="FW_NAME=eldrid emerge-volteer coreboot" and verify it builds successfully. Signed-off-by: Johnny Li <johnny_li@wistron.corp-partner.google.com> Change-Id: If248714088835eb5dd48fa12223c273199297228 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71160 Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-24spd/ddr4: Correct Hynix ddr4 part number from H5AG36EXNDX019 to H5AG36EXNDX017Johnny Li
Correct Hynix ddr4 part number H5AG36EXNDX019 to H5AG36EXNDX017 by Hynix Memory spec. BUG=b:236739240 BRANCH=Volteer TEST="util/spd_tools/bin/spd_gen memory_parts.json ddr4" and verify it builds successfully. Signed-off-by: Johnny Li <johnny_li@wistron.corp-partner.google.com> Change-Id: I6195fa1402691afc303f5223de48f552660cd97f Reviewed-on: https://review.coreboot.org/c/coreboot/+/71159 Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-24mb/google/brya/var/zydron: Use SSFC for mipi instead of fw_configDavid Wu
Kano didn't use SSFC in mass production, however Zydron needs SSFC for 2rd source mipi instead of fw_config. BUG=b:262939431 TEST=Boot to OS and check functional with ov2740/hi556 camera. Change-Id: Idb2a35d67af0b5a7dedc66b0f7eccd8a3b4612d1 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70881 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
2022-12-24soc/amd/mendocino: Split the EFS from the AMDFW bodyKarthikeyan Ramasubramanian
Contents of unsigned AMDFW in RW sections are verified twice in PSP verstage - first time by vboot verifying the firmware body, second time by CBFS verification while the file is loaded to update PSP about the boot region. This redundant verification adds to boot time. Minimize the redundancy by splitting the EFS header from the AMDFW body and keep them as 2 separate CBFS files. This helps to improve the boot time by another 25 ms. BUG=None TEST=Build Skyrim BIOS image and boot to OS. Observe boot time improvement of ~25ms. Before: 6:end of verified boot 363,676 (16) 11:start of bootblock 641,392 (277,716) After: 6:end of verified boot 361,655 (16) 11:start of bootblock 616,967 (255,312) Change-Id: Ib18a4f5c6781e5a7868e9395c0f1212da0823100 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70839 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-24util/amdfwtool: Write EFS and AMDFW body in separate filesKarthikeyan Ramasubramanian
Add support to write EFS and AMDFW body to separate files. This is done through passing an optional --body-location parameter to the amdfwtool. If that option is not passed, then EFS will be written in the same file as the AMDFW body. This will help to keep the minimum data to be loaded/mapped from CBFS in PSP verstage. BUG=None TEST=Build and boot to OS in Skyrim. Change-Id: I79325c81394cf8a0c663752d094adf6660896127 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70778 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-24mb/google/rex: Use GPP_C15 as WWAN_DPR_SAR_ODLSubrata Banik
BUG=b:263413949 TEST=Able to build and boot Google/Rex. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I453fe8e1f4b4b8d4730ade259899d76aec949a44 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71231 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-12-24mb/google/rex: Rename GPP_D07 to FPMCU_UWB_MUX_SELSubrata Banik
BUG=b:263412235 TEST=Able to build and boot Google/Rex. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ia444cc8e3666fe15479ece81d068f9e8f1d339ea Reviewed-on: https://review.coreboot.org/c/coreboot/+/71228 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-12-24mb/google/nissa/var/craask: Use get_wifi_sar_fw_config_filenameEric Lai
Use get_wifi_sar_fw_config_filename to remove the duplicate code. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I04176fee373e534d42c72506df73a092ad55e65b Reviewed-on: https://review.coreboot.org/c/coreboot/+/71218 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-12-24mb/google/volteer/var/lindar: Use get_wifi_sar_fw_config_filenameEric Lai
Use get_wifi_sar_fw_config_filename to remove the duplicate code. WIFI_SAR_CBFS_DEFAULT_FILENAME is not exist, so return the non-exist id has the same outcome. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: Ib34e6b4f435880d62936ae54f19ba2ec752eced2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-12-24mb/google/brya/var/taeko: Use get_wifi_sar_fw_config_filenameEric Lai
Use get_wifi_sar_fw_config_filename to remove the duplicate code. WIFI_SAR_CBFS_DEFAULT_FILENAME is not exist, so return the non-exist id has the same outcome. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: Ib7a764d8cc3160c26abad9c1757812b955bef066 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71122 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-12-24mb/google/nissa/var/pujjo: Use get_wifi_sar_fw_config_filenameEric Lai
Use get_wifi_sar_fw_config_filename to remove the duplicate code. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: Ifde714c19f7ab9fe08f870060037db190a80dbd0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71084 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-12-24vc/google/chromeos: use fw_config field to return sar filenameEric Lai
Use fw_config field to return sar filename instead of fw_config probe. Return filename unconditionly because the sar_id must be valid in CBI. If invalid sar_id, the file won't exist in CBFS by design. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I7b75c5d4fd3c459ad7232bb16c6218a6218f1f77 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70896 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-12-24lib: add stub for fw_config_get_fieldEric Lai
Return UNDEFINED_FW_CONFIG with disabled fw_config. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I0d31ff3ba7706039c622bd1ec825d216a0f21fe4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71176 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-12-23Revert "security/tpm/: turn tis_{init,open} into tis_probe"Sergii Dmytruk
This reverts commit d43154486d27323f64334203e9bc8baf08af6845. From CB:68991: This causes CraterLake boot up process to die. Investigation in progress. Change-Id: I4a6c11b0e638a891108fe230bdaea92d5fbca020 Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71205 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: siemens-bot Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-12-23Revert "drivers/pc80/tpm: probe for TPM family of a device"Sergii Dmytruk
This reverts commit 907a81e2a79f394c316644429165ae66679bafd6. This reportedly breaks TPM and measured boot flow completely. Change-Id: Id0d98ecc7807faa1617ad16dc9a24343c5a66b06 Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71204 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-12-23mb/google/poppy: Use runtime detection for touchscreens/digitizersMatt DeVillier
Now that power sequencing has been implemented, switch from using ACPI "probed" flag to "detect" flag for all i2c touchscreens/digitizers. This removes non-present devices from the SSDT and relieves the OS of the burden of probing. BUG=b:121309055 TEST=build/boot Windows/linux on all poppy variants, verify all touchscreens functional in OS, dump ACPI and verify only i2c devices actually present on the board have entries in the SSDT. Change-Id: I4c1d8ae8c41c1f4283718a86fccbf5ae4fc399b6 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70921 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-23mb/google/poppy: Set touchpad/touchscreen IRQs to LEVEL vs EDGEMatt DeVillier
The GPIOs themselves are configured as level triggered, and the drivers (both Linux and Windows) work better with LEVEL vs EDGE triggering. TEST=tested with rest of patch train Change-Id: Iee01dac943b6c2955f7af42ce0e9395fc609682f Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70920 Reviewed-by: CoolStar <coolstarorganization@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-23mb/google/poppy: Implement touchscreen,digitizer power sequencingMatt DeVillier
For touchscreens/digitizers on poppy variants, drive the enable GPIO high and hold in reset in romstage, then release from reset in ramstage. This will allow coreboot to detect the presence of i2c touchscreens/digitizers during ACPI SSDT generation (enabled in a subsequent commit). TEST=tested with the rest of patch train Change-Id: I90ac4f09c343a28328f7d30254f0448cbe0c78b3 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70919 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-12-23mb/siemens/mc_apl{4,7}: Limit I2C bus speed to 100 kHz on bus 7Werner Zeh
Due to a high I2C bus load on the mainboard I2C frequency of 400 kHz leads to poor signaling. Therefore limit the I2C speed to 100 kHz for this bus. In addition, add a generic I2C device with 100 kHz bus speed to the devicetree so that the OS will not switch to higher clock rates, too. Test= Measure the I2C signals at coreboot and OS runtime and ensure the clock is always at 100 kHz. Change-Id: I6b0a642cd3f5b77331663ac8c76ed0a116ae77ca Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71227 Reviewed-by: Jan Samek <jan.samek@siemens.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-23mb/siemens/mc_apl7: Init I2C controller before PTN3460 is initializedWerner Zeh
When PTN3460_EARLY_INIT is selected, the PTN3460 (DP-2-LVDS-bridge) will be initialized before all devices are initialized. This is necessary to get a valid EDID data set into the PTN3460 before the graphic controller is initialized in order to be able to show a splash screen. For ptn3460_init() to work properly the I2C bus this bridge is connected to needs to be initialized. As this I2C bus initialization would be done too late in the normal flow, it needs to be called here explicitly before ptn3460_init() to initialize the I2C bus with the needed conditions. Otherwise the default I2C settings of the controller will be used which results in a clock rate too high for this mainboard. Test=Measure I2C bus signals and make sure that the clock is <= 400 kHz. Change-Id: I1775fb7c2d29f765224d0e7c7ff9fcd4dbf847c5 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71226 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-23cpu/x86: Set up a separate stack for APsArthur Heymans
APs use a lot less stack, so set up a separate stack for those in .bss. Now that CPU_INFO_V2 is the only code path that is used, there is no need to align stacks in c_start.S. Change-Id: I7a681a2e3003da0400843daa5d6d6180d952abf5 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-12-23soc/intel/cmn/block/pmc: Add pmc_or_mmio32 utility functionTim Chu
Change-Id: I5f9845dd3ea098d990710eaaa2d5db495f876cdd Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71099 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-23soc/intel/broadwell: Add Kconfig option to hide Intel MEMatt DeVillier
On broadwell devices, coreboot currently disables and hides the ME PCI interface by default, without any way to opt out of this behavior. Add a Kconfig option to allow for leaving the ME PCI interface enabled, but set the default to disabled as to leave the current behavior unchanged. Change-Id: If670d548c46834740f4e21bb2361b537807c32bf Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71196 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-12-23sb/intel/lynxpoint: Add Kconfig option to hide Intel MEMatt DeVillier
On lynxpoint devices, coreboot currently disables and hides the ME PCI interface by default, without any way to opt out of this behavior. Add a Kconfig option to allow for leaving the ME PCI interface enabled, but set the default to disabled as to leave the current behavior unchanged. Change-Id: I994cb5b05829eddad2e423a7440a9458f9952370 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71195 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-12-23soc/intel/meteorlake: Add DPTF ACPI Device IDs into header fileSubrata Banik
This patch adds DPTF ACPI Device IDs into the header file (soc/dptf.h). Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ib78258ac1b9a5252bb5e6fae4d7cc30a3f103e78 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71126 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-23soc/intel: Drop SoC specific DPTF implementationSubrata Banik
This patch drops the SoC specific implementation as DPTF driver can now fillin those platform specific data using SoC specific macros. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: If65976f15374ba2410b537b1646ce466ba02969b Reviewed-on: https://review.coreboot.org/c/coreboot/+/71112 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-12-23drivers/intel/dptf: Implement API to fill DPTF platform infoSubrata Banik
This patch fills in a generic platform info structure based on the inputs from the SoC dptf header file (soc/dptf.h). It will help to make things common and drop unnecessary back and forth call between common code and SoC code. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I3521882495485cef686655abd65337515bae5faa Reviewed-on: https://review.coreboot.org/c/coreboot/+/71111 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-23soc/mediatek: Add DEVAPC_DEBUG optionYidi Lin
Add DEVAPC_DEBUG option and set this option to disabled by default. This option prevents DEVAPC log flooding during the boot process. Enable this option when we need to debug DEVAPC issues. TEST=DEVAPC log is disabled by default. Change-Id: I26bc0378b8a766c6a8cc4903d64a921c3e96b93f Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71158 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-23mb/google/geralt: Pass SD card detect GPIO to payloadsLiju-Clr Chen
1. Add an option for SD card initialization. 2. If CONFIG SDCARD_INIT is configured, pass SD card detect GPIO to payloads for SD card detection and initialize MSDC for SD card configuration. BUG=b:244250437 TEST=build pass Signed-off-by: Liju-Clr Chen <liju-clr.chen@mediatek.com> Change-Id: I2d3683eb673f438c9190c11d4679a3ca97c76a98 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71136 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-12-23tree: Replace And(a,b) with ASL 2.0 syntaxFelix Singer
Replace `And (a, b)` with `a & b`. Change-Id: Id8bbd1a477e6286bbcb5fa31afd1c7a860b1c7dc Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70851 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-23tree: Replace And(a,b,c) with ASL 2.0 syntaxFelix Singer
Replace `And (a, b, c)` with `c = a & b`, respectively `c &= b` where possible. Change-Id: Ie558f9d0b597c56ca3b31498edb68de8877d3a2f Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70850 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-23tree: Replace Or(a,b,c) with ASL 2.0 syntaxFelix Singer
Replace `Or (a, b, c)` with `c = a | b`, respectively `c |= b` where possible. Change-Id: Icf194b248075f290de90fb4bc4e9a0cd9d76ec61 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70846 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-23tree: Replace ShiftLeft(a,b) with ASL 2.0 syntaxFelix Singer
Replace `ShiftLeft (a, b)` with `a << b`. Change-Id: I812b1ed9dcf3a5749b39a9beb9f870258ad6a0de Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70842 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-23tree: Replace ShiftLeft(a,b,c) with ASL 2.0 syntaxFelix Singer
Replace `ShiftLeft (a, b, c)` with `c = a << b`. Change-Id: Ibd25a05f49f79e80592482a1b0532334f727af58 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70841 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-23tree: Replace ShiftRight(a,b,c) with ASL 2.0 syntaxFelix Singer
Replace `ShiftRight (a, b, c)` with `c = a >> b`. One case was simplified to just `a >> b`. Change-Id: I889012b0a3067138e6f02d3fe8e97151effb5c2a Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70840 Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-23mb,x86/smm: Disable unused IO trapsKyösti Mälkki
Only IO trap #3 for lenovo/x60,t60 and getac/p470 have implemented the IO trap handler. Change-Id: Ibadce174f673e88380f4b6745fd9ed8b73177a13 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70367 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-23Docs: Add page for external resourcesMartin Roth
This is a page to add links to other sites that have firmware related material, or other things that are of interest to the community. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Icf411e67bf865426b1a3b99ecbabed2302a7b738 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70239 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-12-23mb/google/poppy/nocturne: Fix touchscreen reset GPIO configMatt DeVillier
The touchscreen reset GPIO is configured as PAD_CFG_TERM_GPO with an internal pull-down, which puts it in a state of contention when the reset pin is released / set to high. Fix this by changing the reset GPIO to PAD_CFG_GPO like all other poppy variants use for the touchscreen reset. TEST=build/boot nocturne, touchscreen still works. Change-Id: I1ad4bb9d4194485990f54ffa7bae05f5c9a39deb Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71185 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-23mb/google/sarien: Add default fmap for non-ChromeOS buildsMatt DeVillier
Test: build/boot google/sarien with non-ChromeOS build, edk2 payload. Linux 5.15, Windows 11 tested. Change-Id: Ibc1857e6b120b0bb827ed610981c4d2bf8f78d1f Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58184 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-23mb/google/hatch: Use runtime detection for touchscreens/digitizersMatt DeVillier
Now that power sequencing has been implemented, switch from using ACPI "probed" flag to "detect" flag for all i2c touchscreens. This removes non-present devices from the SSDT and relieves the OS of the burden of probing. BUG=b:121309055 TEST=build/boot Windows/linux on multiple hatch variants, verify all touchscreens functional in OS, dump ACPI and verify only i2c devices actually present on the board have entries in the SSDT. Change-Id: I2eae486eaa5e42cfe42ecc066a58b09fe2bd9138 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71062 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-23mb/google/hatch: Set touchpad/screen IRQs to LEVEL vs EDGEMatt DeVillier
The GPIOs themselves are configured as level triggered, and the drivers (both Linux and Windows) work better with LEVEL vs EDGE triggering. TEST=tested with rest of patch train Change-Id: I580348d0aabb24f0241d6e9992c5a17942bd57ab Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71061 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-23mb/google/hatch/*: Add missing enable GPIO for ELAN touchscreensMatt DeVillier
Some ELAN touchscreens were missing the entries for the enable GPIO and associated delays. Add them to variants with ELAN0001 touchscreens missing the entries. TEST=tested with rest of patch train Change-Id: I9ce81ad6ee8183c522d05fbe3f57af87e5895df3 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71060 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-12-23mb/google/hatch: Implement touchscreen power sequencingMatt DeVillier
For touchscreens on hatch variants, drive the enable GPIO high starting in romstage, then disable the reset GPIO in ramstage. This will allow coreboot to detect the presence of i2c touchscreens during ACPI SSDT generation (implemented in a subsequent commit). BUG=b:121309055 TEST=tested with rest of patch train Change-Id: I86c5f41b7820eaf5252c276ae854a4206e09385f Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71059 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-23mb/google/hatch: Add method to set GPIOs in romstageMatt DeVillier
Add method variant_romstage_gpio_table() with empty weak implementation to allow variants to override as needed for touchscreen power sequencing (to be implemented in a subsequent commit). Call method in romstage to program any GPIOs the variant may need to set. TEST=tested with rest of patch train Change-Id: I1939387b5bb98d6d282fd044e9ce8780dbe0d2c5 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71058 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-23mb/google/poppy/rammus: disable USB xDCIMatt DeVillier
With xDCI enabled, the right USB-C port does not work for USB data. Additionally, it was disabled in stock ChromeOS firmware. TEST=build/boot rammus, confirm right USB-C port works for booting, under OS in Windows/Linux. Change-Id: Ie343577d772563fa7d432b62aa8faa41d760102a Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71016 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: CoolStar <coolstarorganization@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-23mb/google/zork: update ACPI HID/CID for Synaptics touchpadsMatt DeVillier
The currently assigned ACPI HID 'PNP0C50' is not a valid per Windows WHQL validation tests. To ensure compatibility with both Windows and Linux, set the HID to 'SYNA0000' and CID to 'ACPI0C50' as previously done for other boards (eg, google/lulu). TEST=boot Linux 5.1x, Windows 10 on berknip/morphius, verify all touchpad functions work correctly. Change-Id: I9d8362719ddbfe523dd83964556b05bb8f1bb1ba Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71138 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-23mb/google/volteer: update ACPI HID/CID for Synaptics touchpadsMatt DeVillier
The currently assigned ACPI HID 'PNP0C50' is not a valid per Windows WHQL validation tests. To ensure compatibility with both Windows and Linux, set the HID to 'SYNA0000' and CID to 'ACPI0C50' as previously done for other boards (eg, google/lulu). TEST=boot Linux 5.1x, Windows 10 on lindar, verify all touchpad functions work correctly. Change-Id: If2deedbd572b771c1e7793a3b3c37a3114aa2a48 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71077 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-22soc/intel/apollolake/acpi: Remove STOM from ACPISean Rhodes
This should only contain resources that the PCI domain uses. Stolen memory prevents the PCI domain from allocating anything where it is. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I1562396f0b747a81bbc584314956809bd3865ff9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66267 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-22soc/intel/apollolake/acpi: Improve comments and unify code word spellingSean Rhodes
ACPI: Improve comments and unify code word spelling Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I1efbe930d0b8daec7c7bd2c1d84a4a3a5cad2ffb Reviewed-on: https://review.coreboot.org/c/coreboot/+/66245 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-22soc/intel/apollolake/acpi: Tidy the Legacy video RAMSean Rhodes
Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ie6572638c6bbe910745de55afa44458fb6b8db9c Reviewed-on: https://review.coreboot.org/c/coreboot/+/66240 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-22soc/intel/apollolake/acpi: Tidy the PCI Memory RegionSean Rhodes
Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I8997f9c111142a908b60675023d1a7dd86d3632a Reviewed-on: https://review.coreboot.org/c/coreboot/+/66238 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-22soc/intel/apollolake/acpi: Add bits of TOLUD registerSean Rhodes
The values in this patch were found in the following datasheets: * 334819 (APL) * 336561 (GLK) Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I9a4a05f9c764eecaac3d473ba612dca6cc81518f Reviewed-on: https://review.coreboot.org/c/coreboot/+/66234 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-21 16:14:06 +0000