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This reverts commit 6ab188ee6c99b1d9924b607d7e939d91e35014ec.
This breaks the build using a slightly older toolchain that doesn't know
this option yet.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0bdc909c0e53b5353743dca521c963bbec792f7e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83311
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
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Change-Id: I3cb1f11beba61afdf2be6188bde9ff135f8ace50
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83288
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
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This double-colon target doesn't do anything unless it's implemented by
another makefile. It's intended to be used only by the site-local
makefile to allow it to run any necessary steps before the actual
coreboot build begins.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I01f98c9cf8375bca21ab87f9becf66a25402c758
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83198
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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This port was done via autoport and subsequent manual tweaking.
Special thanks to Nicholas Chin! This port would have never succeeded
without his help.
The board features two socketed DIP-8 SPI flash chips, as well as a
BIOS selection switch and onboard Power and Reset switches.
Working:
- Haswell MRC.bin
- All four DDR3/DDR3L DIMM slots
- S3 suspend and resume
- Libgfxinit
- HDMI-Out Port
- USB 2.0 Ports
- Vertical Type A USB 2.0
- USB 3.1 Gen1 Ports
- HD Audio Jack (audio output)
- Front panel audio connector (audio output)
- RJ-45 Gigabit LAN Port
- SATA3 6.0 Gb/s connectors
- mSATA/mini-PCI Express slot
- half mini-PCI Express slot
- PCI Express 3.0 x16 slots (both)
- PCI Express 2.0 x4 slot
- PCI Express 2.0 x1 slot
Working (board-specific)
- Power Switch with LED (functional, yet no LED)
- Reset Switch with LED (functional, yet no LED)
- BIOS Selection Switch
- Slow Mode Switch (locks the CPU at 800MHz)
not (yet) tested:
- IR header
- COM Port header
- Power LED header
- eSATA connector
- USB 2.0 headers
- PS/2 Mouse/Keyboard Port
- HDMI-In Port
- Optical SPDIF Out Port
not (yet) working:
- Software fan control: While the Nuvoton chip is correctly discovered,
the numbering of the fan connectors is faulty, resulting in the wrong
fan being controlled.
- Dr. Debug: on vendor firmware, the LEDs turn off after successful
boot. On coreboot, the LED shows two bright zeros after boot.
- Post Status Checker (PSC)
Change-Id: Iaa156b34ed65e66dd5de5a26010409999a5f8746
Signed-off-by: Jan Philipp Groß <jeangrande@mailbox.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82906
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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Updating from commit id 09fcd218:
2024-02-23 06:42:12 +0000 - (Makefile: Test compiler for -Wincompatible-function-pointer-types)
to commit id b6f44e62:
2024-07-01 04:30:14 +0000 - (futility: updater: Increase try count from 8 to 10)
This brings in 58 new commits:
b6f44e62 futility: updater: Increase try count from 8 to 10
cfc87db2 OWNERS: Add czapiga
eabf5784 OWNERS: Remove twawrzynczak and quasisec
f8af818e host: Add stub implementation for pkcs11 key
aaf4ecbb crossystem: Add support for Panther Lake gpiochip
de89c5cd make_dev_ssd: allow ptracers to write proc/mem
ffc9cc15 utility: Add vbnv_util.py for debugging
b6174bdb futility: show: Print keyblock signature size and data size
6e39c99f Android: Add support for doing zipalign before doing apksigner
ead73381 futility: flash: Enhance WP status reporting by adding more instructions
c3368084 futility: modify private key validation to work for both local and cloud
c22d72f8 futility: flash: Correct the output syntax of 32bit hex
f423ae13 crossystem: Drop support for tried_fwb and fwb_tries
fc5488c7 futility: flash: Correct the allowlist of options
16dede85 Revert "futility: Split load_firmware_image() into two functions for AP and EC"
ded07831 futility: Try to load ecrw versions regardless of image type
7a685705 futility: Refactor code for --manifest
f5ad0856 futility: Add more checks for incompatible arguments
05659d33 futility/updater_manifest: Warn about inconsistent RW versions
6720827b futility: Support ecrw version for --manifest
daae7e56 futility: Split load_firmware_image() into two functions for AP and EC
40c77bba futility: Warn about inconsistent RW_FWID_A and RW_FWID_B versions
c168ac8e tests/futility/data: Update bios_geralt_cbfs.bin with swapped ecrw
512648ae host/lib: Add cbfstool_file_exists() and cbfstool_extract()
e37e6511 sign_official_build: add missing info keyword
2c0758b4 sign_official_build: loem support for firmware
016f6149 scripts/image_signing/swap_ec_rw: Always add ecrw.* as raw CBFS file
b26c700a scripts/image_signing/swap_ecrw: Support ecrw.version
2e8d1003 tlcl: Add const qualifier to TlclTakeOwnership arguments
96b8674c host: stop installing unused image signing scripts
8da83c43 Android: Handle update certs using for hardcoded certs
4ca60534 scripts/image_signing: Add swap_ec_rw
d30d6b54 make_dev_ssd: Remove logic choosing editor value
4cc5d090 futility/dump_fmap: Fix error message prefix for '-x'
e7062a58 futility/dump_fmap: Exit with error if specified section is not found
4489dd09 scripts: Remove newbitmaps directory
8dcc82b0 host/lib/cbfstool: Redesign cbfstool_get_config_value() API
856fd693 Android: Hack for now to let things silently fail instead of erroring
28845c97 sign_uefi: Handle case where the crdyshim key does not exist
201244c3 sign_uefi_unittest: Refactor in preparation for more tests
702f8b53 tests: Add tests for cbfstool_get_config_value()
52a21327 Android: Add support for gcloud KMS in android signing
3310c49f tests/futility/test_update.sh: Use unique test names for IFD tests
493f7afc sign_gsc_firmware: add support for Nightly target
5c307cad keycfg: more consistent typo fix
11e4f60b image_signing: Add missing arg in sign_uefi_kernel
37c730d8 keycfg: handle arrays appropriately in key_config
59c37697 sign_uefi: Add detached crdyboot signature
b66926e2 sign_uefi: Refactor the is-pkcs11 function for reuse
94aa8b80 image_signing: Pass crdyshim private key to sign_uefi.py
0ac99bcb sign_uefi: Stop signing crdyboot files with sbsign
6f6a6432 vboot_reference-sys: replace denylist with allowlist
73ebd8f8 vboot_reference-sys: add vboot_host pkg-config fallback
476282ef make_dev_ssd: Skip firmware validity checks on nonchrome
9330a65a vboot_reference: Add support for allowing overlayfs
48c8833f sign_official_build: remove cloud-signing
aa70bb19 create_new_keys.sh: add --arv-root-uri
38d1af69 sign_official_build: Dedup calls to sign_uefi.py
Change-Id: I14aaf1e1e230107e7bae60195c7e4684bf5a0533
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83295
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
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The filename of the Elkhart Lake FSP binary changed in the FSP
repository. It's unlikely that it will be renamed to the original name
soon. Thus, update the filename in the coreboot repository.
Updating from commit id cc6399e:
2024-03-04 15:40:41 +0800 - (IoT MTL-UH & MTL-PS PV (3471_49) FSP)
to commit id 800c857:
2024-06-25 15:47:28 +0800 - (Update Fsp.fd)
This brings in 23 new commits:
800c857 Update Fsp.fd
41e4590 NEX AZB IPU24.4 (5254_00) FSP
0efd8a3 IoT RPL-PS PV (5045_47) FSP
196e3fe Update README.md
380afd8 Update README.md
5dc88ca NEX ADL-PS IPU24.3/MR6 (5045_02) FSP
22762e9 Merge branch 'master' of https://github.com/intel/FSP
8134dbd Elkhart Lake IPU2024.3 FSP
3819544 add required SECURITY.md file for OSSF Scorecard compliance
a6ee963 Delete AlderLakeFspBinPkg.dec
9d819ea Deprecate Client/AlderLakeFspBinPkg
f963690 Raptor Lake FSP C.1.C8.50
f67f9ef Raptor Lake FSP C.0.C8.50
68c3cfa NEX ADL-PS IPU 2024.3 (5045_02) FSP
f0d04d9 NEX ADL-P IPU 2024.3 (5045_02) FSP
6fa139c NEX ADL-S IPU 2024.3 (5045_02) FSP
c4af5ac NEX TGL IPU 2024.3 (7092_01) FSP
8cf0372 IoT ADL-N MR4 (5061_00)
e5ceb0b Merge branch 'master' of https://github.com/intel/FSP
aada6a5 Elkhart Lake IPU2024.2 FSP
90d1d3b Update README.md
1a5a3ee Testing
61c069a NEX RPL-S MR3 (4445_03) FSP
Change-Id: I47013bce65054f2c496c9aa7c16e55b51d65e5fe
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83294
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Ensure consistent spacing around colons in bit fields, operators,
statements and function calls.
Found by the linter (check-style).
Change-Id: I817b1dcf106cc360a7db56e5b4b0716d5419e2cd
Signed-off-by: Alexander Goncharov <chat@joursoir.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83281
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Also capitalize the first letter of each help line while I'm here.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I595265d53a5ecfeb5989075dd4ce23dbdf366c00
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83125
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
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This almost completely replaces the original clean-symlink target to
remove links from site-local into the coreboot tree. Changes include:
- Symbolic links removed are based on the EXTERNAL_SYMLINKS value of
symlink.txt files under site-local.
- Verify that there are site-local symlink.txt files to work on before
doing anything.
- Verify that the symlink.txt files reference links inside the coreboot
directory.
- Print out whether or not there are remaining symbolic links in the
tree.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ife0e7cf1b856b7394cd5e1de9b35856bd984663c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83124
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
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Define a devicetree alias for `cpu_cluster` so that it can be referenced
in C code as `DEV_PTR(cpu_bus)`.
Change-Id: Id6ead3d98d8fc17cab44ecf0b2af60a23187e036
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83275
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Currently the HiFive Unleashed produces the following exception:
[DEBUG] Exception: Load address misaligned
[DEBUG] Hart ID: 0
[DEBUG] Previous mode: machine
[DEBUG] Bad instruction pc: 0x080010d0
[DEBUG] Bad address: 0x08026ab3
[DEBUG] Stored ra: 0x080010c8
[DEBUG] Stored sp: 0x08010cc8
The coreboot LZ4 decompression code does some misaligned access during
decompression which the FU540 apparently does not support in SRAM.
Make the compiler generate code that adheres to natural alignment by
fixing the LZ4_readLE16() function and creating LZ4_readLE32().
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Id165829bfd35be2bce2bbb019c208a304f627add
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81910
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The touchscreen vendor (Goodix) needs to use this value
(hid-report-addr) in the touch driver, and this value
needs to be changed later.So add generic property list to allow populating vendor specific device properties to ACPI SSDT table.
BUG=b:342932183
BRANCH=None
TEST=emerge-brox coreboot
Change-Id: I8b18e0a2925e6fd36e3a470bde9910661b7558b8
Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83139
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ifd19cdcfbdf0b01984e0db0aa880fdcb256663b4
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83255
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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Add LCE_LMFBX101117480 MIPI panel for Wugtrio.
Datasheet: LMFBX101117480-10.1-TLCM-24.05.20-2.pdf
BUG=b:331870701
TEST=emerge-staryu coreboot chromeos-bootimage
BRANCH=corsola
Change-Id: I863e172400ffb26b5c9c240a21d15c6a2240b4ad
Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83221
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
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Add STA panel LCE_LMFBX101117480 serializable data to CBFS.
Datasheet: LMFBX101117480-10.1-TLCM-24.05.20-2.pdf
About the init code, we communicated with the vendor through the
datasheet to confirm the writing method of each register value.
BUG=b:331870701
TEST=build and check the CBFS includes the panel
BRANCH=None
Change-Id: I60858109e4b07f720461e320212d7b197ec1130c
Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83220
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Xuxin Xiong <xuxinxiong@huaqin.corp-partner.google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
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Change-Id: I25415d7fd82879889ffaa1bb534ad5d0b174854e
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82736
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ia26dcf097db125a5a734660d08d875459179241b
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82734
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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Configuring USB2_PORT_EMPTY is equal to just not setting it. So remove
it to clean up a bit.
Change-Id: I6854f4a0d3e7b51b242549556a5838d4183d3473
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83246
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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Change-Id: I1992c20dcdc5e974143690d44ee199d7c3394cfd
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83251
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
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Change-Id: I6d7bcd298408e15677f27d1a9797a490c57c9fc9
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83247
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
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Change-Id: Ide5126c6e642ca16249efeaf46321724f2ddce9a
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83245
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
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Use one line per *_common flag like it's done elsewhere in the tree.
It makes the list of options more readable.
Change-Id: I33c500e6eb74daf1e66c2b5e07b50f81c0f4587d
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83226
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
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Configuring them to 0 is equal to not configuring them at all. So remove
them to clean up a bit.
Change-Id: I9a9eb370e8e9e8874ad8b4b8ac0f43d61c1a4b9b
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83250
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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Change-Id: I03508c50fe56fd85f8bf89f724863e546d4140e9
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83249
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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Configuring them to 0 is equal to not configuring them at all. So remove
them to clean up a bit.
Change-Id: I18134ac784fffb703e1fe513e5914f05faa749c9
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83248
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Also, remove superfluous comments from devices which repeat their name.
Change-Id: I009330042b59c9e6e78aa6f3819546b771b26ff0
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83244
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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Rename fdt_node_name to the actual function name and also rename the
references.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I527146df26264a0c3af1ad01c21644d751b80236
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83084
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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In the HD Audio Specification Rev. 1.0a, every bitfield in the GCAP
register is RO (Read Only). However, it is known that in some Intel
PCHs (e.g 6-series and 7-series, documents 324645 and 326776), some
of the bitfields in the GCAP register are R/WO (Read / Write Once).
GCAP is RO on 5-series PCHs; 8-series and 9-series PCHs have a lock
bit for GCAP elsewhere.
Lock GCAP by reading GCAP and writing back the same value. This has
no effect on platforms that implement GCAP as a RO register or lock
GCAP through a different mechanism.
Change-Id: Id61e6976a455273e8c681dbeb4bad35d57b1a8a2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83218
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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For Gen1 SoCs, the range starting from the end of VTd BAR to the end
of 32-bit domain MMIO resource window is reserved for unknown devices.
Get them reserved.
TEST=Build and boot on intel/archercity CRB
Change-Id: Ie133fe3173ce9696769c7247bd2524c7b21b1cf8
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83136
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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vtd_probe_bar_size is used to decide the BAR size.
TEST=Build and boot on intel/archercity CRB
Change-Id: Ie45dd29e386cbfcb136ce2152aba2ec67757ee3c
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82431
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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VT-d spec 4.0 supports size definition for DRHD BAR to support DRHD
sizes larger than 4KB. If the value in the field is N, the size of
the register set is 2^N 4 KB pages.
Some latest OS (e.g. Linux kernel 6.5) will have VTd driver trying
to use the beyond 4KB part of the DRHD BAR if they exist. They need
the DRHD size field to set up page mapping before access those
registers.
Re-add acpi_create_dmar_drhd with a size parameter to support the
needs.
TEST=Build and boot on intel/archercity CRB
Change-Id: I49dd5de2eca257a5f6240e36d05755cabca96d1c
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Signed-off-by: Gang Chen <gang.c.chen@intel.com>
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82429
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I8ce94c8bc7ed137eaace12d6cb0befa6c0d39a37
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82925
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
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When CNVi based Wifi6 is disabled, CNVi based Bluetooth must be turned
off, based on fw_config. Otherwise, when device boots without the cbi
settings for wifi6, boot may fail with assertion error for line 817 &
819 of file 'src/soc/intel/alderlake/fsp_params.c'.
BUG=b:345596420
BRANCH=NONE
TEST=Dut boots fine with both Wifi6 & Wifi7 based cbi settings, along
with enumeration of corresponding BT device.
Change-Id: I03fde02fa4b36f4e47d6f0e95675feddb3bee7cd
Signed-off-by: Poornima Tom <poornima.tom@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83148
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
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PCIe based GPIOs of Wifi7 module are enabled based on firmware config.
BUG=b:345596420
BRANCH=NONE
TEST= Based on fw config configured, wifi6 or wifi7 along with
bluetooth ports are detected.
Change-Id: If0584e91b5143c6df742961657d242c046409b3a
Signed-off-by: Poornima Tom <poornima.tom@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83077
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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PCIe based Bluetooth is on port8. This cl enables bluetooth for PCIe
based Wifi7 module.
BUG=b:345596420
BRANCH=NONE
TEST=With proper FW config enabled, BT gets detected on port8
Change-Id: I989cf6122f2555cc89f622e4ce5d21b574d0458e
Signed-off-by: Poornima Tom <poornima.tom@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83076
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Enable pcie based, discreete wifi7 on root port4.
BUG=b:345596420
BRANCH=NONE
TEST=Verified Wifi7 module detection based on cbi settings
Change-Id: I8c2f4a750a1cb00c587bce21bc83ee583d0f4341
Signed-off-by: Poornima Tom <poornima.tom@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83075
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add a new fw config field for wifi category as WIFI_6, which is CNVi
based and WIFI_7, which is PCIe based. Also, enable WIFI_6 for existing
CNVi based wifi port as well as bluetooth port.
BUG=b:345596420
BRANCH=NONE
TEST=Verified Wifi6 module detection
Change-Id: I4b218f772405bdb1b741b4d5e640d7b4f145cd76
Signed-off-by: Poornima Tom <poornima.tom@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83074
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Add wake configuration and set 'add_acpi_dma_property'=true for CNVi.
Also, add "set 'add_acpi_dma_property' to true to tell the OS to enforce DMA protection for this device.
BUG=b:345596420
BRANCH=NONE
TEST=SSDT dump showed below:
Scope (\_SB.PCI0.RP01.WF00)
{
Name (_PRW, Package (0x02) // _PRW: Power Resources for Wake
{
0x23,
0x03
})
Name (_DSD, Package (0x02) // _DSD: Device-Specific Data
{
ToUUID ("70d24161-6dd5-4c9e-8070-705531292865"),
Package (0x01)
{
Package (0x02)
{
"DmaProperty",
One
}
}
Change-Id: If04539fe8dceb5c2edfc06a324ede11147b78b6d
Signed-off-by: Poornima Tom <poornima.tom@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83138
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I6cc2b3947a2c79e8962985e035e7cc74c2deb307
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83215
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
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Updating from commit id 17bef2248:
2024-02-05 23:33:50 +0100 - (Merge "feat(fvp): delegate FFH RAS handling to SP" into integration)
to commit id fe4df8bda:
2024-06-07 12:55:56 +0200 - (Merge "feat(rockchip): add RK3566/RK3568 Socs support" into integration)
This brings in 713 new commits.
Change-Id: Icce3595fef3a844034e7cc76fc8480ed5b21618c
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83000
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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This patch configures Serial IO UARTs mode as below.
UART0 and UART1 in PCI mode and keep UART2 disable as per hardware design.
BUG=b:338917836
BRANCH=firmware-brya-14505.B
TEST= USE="-project_all project_bujia" emerge-brask coreboot
Change-Id: I5617331aaf505b97e25a717b145fb70dc53f5a38
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83205
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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This target looks for symbolic links in the coreboot directory,
excluding the 3rdparty and crossgcc directories, which both typically
have numerous symbolic links, and deletes anything that is found.
All possible links are verified as symbolic links before being removed.
Any removed links show where they were linked from in case they need to
be restored.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I8a56e7c628701e4a0471833443b08ab2bcceb27e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83123
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This almost completely replaces the original symlink target for creating
symbolic links from site-local into the coreboot tree. Changes include:
- A comment about the format of the symlink.txt file
- Verify that there are symlink.txt files before doing anything.
- Note that symbolic links that already exist are being skipped.
- Only use the first line of the symlink.txt file
- Make sure the symbolic link to be created is inside the coreboot dir.
- Output errors to STDERR
- echo -e isn't supported by posix shells, so replace /t with two spaces
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I9b0d1b5bc19556bc41ca98519390e69ea104bd1b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83122
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Eric Lai <ericllai@google.com>
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ALC257 does not supoort built-in digtal buzzer, So use external pwm
to PCBEEP for beep sound.
BUG=b:346956771
BRANCH=None
TEST=emerge-brox coreboot sys-boot/chromeos-bootimage
firmware-shell: devbeep -> can output beep normally.
Change-Id: If924f9f27f229420e78015f418a97b2d5daf62e5
Signed-off-by: Jing Tong <tongjian@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83147
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Add 802.11be (aka. Wi-Fi 7) enable/disable support based on document
559910 Intel Connectivity Platforms BIOS_Guidelines revision 8.3.
There are countries where Wi-Fi 7 should be disabled by default. This
adds capability for OEM to enable or disable by updating the board
specific Specific Absorption Rate (SAR) binary.
BUG=b:348345300
BRANCH=firmware-rex-15709.B
TEST=SSDT dump shows that the _DSM method returns the value supplied
by the SAR binary for function 12
Change-Id: Ifa1482d7511f48f5138d4c68566f07ce79f37a7a
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82207
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
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Since the 'maxlen' parameter's type is changed to size_t, the type of
the local variable 'i' which this is compared against should also be
changed to size_t.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ibe35d3741bc6d8a16a3bad3ec27aafc30745d931
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83224
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
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The return type of strspn and strcspn is supposed to be a size_t and not
a signed integer.
TEST=Now the openSIL code can be built with the coreboot headers without
needing to add '-Wno-builtin-declaration-mismatch' or
'-Wno-incompatible-library-redeclaration' to the cflags. Before the
build would error out with various 'mismatch in return type of built-in
function' errors.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0ff612e2eee4f556f5c572b02cbc600ca411ae20
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83223
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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The third parameter of strncpy and strncmp is supposed to be a size_t
and not a signed int.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I485e45e18232a0d1625d4d626f923ec66cfbe4a2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83222
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
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Use the existing `azalia_enter_reset()` function instead of explicitly
clearing the bit (and having to explain in a comment what this means).
Change-Id: I04924e68420a93a1ad46f5a7ab359e38c0f7e210
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83217
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Now that the device tree code has been made available in libpayload, we
should reintroduce the node and property allocation optimization for
libpayload's memory allocator that was originally dropped when porting
this code from depthcharge to coreboot.
On a Qualcomm SC7180 unflattening a normal ChromeOS kernel device tree,
this saves roughly ~145ms. The total scratch space used is about ~1350
nodes and ~5200 properties, so we leave a little room to grow with the
constants hardcoded here.
Change-Id: I0f4d80a8b750febfb069b32ef47304ccecdc35af
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83208
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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This patch adds initial code block required to build google/fatcat
board with Intel Meteor Lake Silicon. Later after the initial board
power-on is successful, we shall switch to Panther Lake silicon to
build the google/fatcat reference design.
BUG=b:347669091
TEST=Able to build the google/fatcat and able to hit power-on reset
using Intel Meteor Lake SoC platform.
Change-Id: Iad78aec51b2f0f240991c9c35842764a60be988e
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83197
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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For most of SoCs, DRHD is by default with the size of 4KB. However,
larger sizes are allowed as well. Rename acpi_create_dmar_drhd to
acpi_create_dmar_drhd_4k to support the default case while a later
patch will re-add acpi_create_dmar_drhd with a size parameter.
TEST=intel/archercity CRB
Change-Id: Ic0a0618aa8e46d3fec2ceac7a91742122993df91
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83202
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Follow nissa baseboard setting for storage field.
option STORAGE_EMMC 0
option STORAGE_NVME 1
option STORAGE_UFS 2
BUG=b:333486830
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot chromeos-bootimage
Change-Id: I75b4b3037c245f7d517cb33d487f71da98f6c4e8
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83207
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
|
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The Fn key on Lotso emits a scancode of 94 (0x5e).
BUG=b:322721490
TEST=Flash Lotso, boot to Linux kernel, and verify that KEY_FN is
generated when pressed using `evtest`.
Change-Id: I999627f0ea9db1d79376150a04920ac877a48447
Signed-off-by: Wen Zhang <zhangwen6@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83204
Reviewed-by: Dengwu Yu <yudengwu@huaqin.corp-partner.google.com>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
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On board version 1 and later, touchscreen is not stuffed. Hence
configure the relevant GPIOs as not connected, disable the concerned I2C
bus in the devicetree as well as SoC chip config for board version 1.
BUG=b:347333500
TEST=Build Brox BIOS image and boot to OS. Ensure that there are no
peripherals detected in I2C 1 bus through i2cdetect tool. Ensure that no
touchscreen devices are exported through ACPI SSDT table. Ensure that
other I2C peripherals - eg. Trackpad and Ti50 are functional. Ensure
that the device is able to suspend and resume for 25 cycles.
Change-Id: Ia0578b90b0e8158ae28bcc51add637844ba6acf6
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83199
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Kernel need the default brightness steps. Otherwise following error
messages are observed in the kernel:
[Firmware Bug]: ACPI(GFX0) defines _DOD but not _DOS
ACPI BIOS Error (bug): Could not resolve symbol [^^XBCL], AE_NOT_FOUND
ACPI Error: Aborting method \_SB.PCI0.GFX0.LCD0._BCL due to previous
error (AE_NOT_FOUND)
BUG=b:346807006
TEST=Build Brox BIOS image and boot to OS. Ensure that the concerned
error messages are resolved. Ensure that the backlight controls are
functional.
Change-Id: Icd569b0efef31908edb1b7dc384e60a16fc5bd0c
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83152
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
|
|
Change-Id: I64ffba35303c1291f56ae6a038325a7482158ad3
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83189
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Change-Id: I84da5365907664ce223dec4adb22a8f1a6e2a144
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83188
Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
|
|
Change-Id: I50706d7a077767d2295d6d5f209c30109d607277
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83179
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com>
Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Change-Id: Iecb4851bedb7c9ed7793763d80acbcbb068e8832
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83172
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: I22ba991a9d559b0ecc7b3ceddcfd099890dd6c3a
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83171
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
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Some dongles require more time to be ready,
this CL extedns the DP mode entry timeout from 0.5s to 1.5s and make
sure the tested dongle display works.
Before:
[WARN ] DP not ready after 500ms. Abort.
After:
[INFO ] DP ready after 1211 ms
BUG=b:348309582
TEST=emerge coreboot
verify tested dongles and monitors display works
Change-Id: I22d7800b50f6f7de9f147ae6998a5015d0dc0be9
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83206
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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This also changes how debug messages will be printed. I focused on
reducing clutter on the screen and made the style of the messages
consistent.
Before:
azalia_audio: Initializing codec #5
codec not ready.
azalia_audio: Initializing codec #4
codec not valid.
azalia_audio: Initializing codec #3
azalia_audio: viddid: ffffffff
azalia_audio: verb_size: 4
azalia_audio: verb loaded.
After:
azalia_audio: codec #5 not ready
azalia_audio: codec #4 not valid
azalia_audio: initializing codec #3...
azalia_audio: - vendor/device id: 0xffffffff
azalia_audio: - verb size: 4
azalia_audio: - verb loaded
Change-Id: I92b6d184abccdbe0e1bfce98a2c959a97a618a29
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80332
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Update board type to BOARD_TYPE_ULT_ULX
BUG=b:348147663
BRANCH=none
TEST=Built and compare the results of
command 'dmidecode --type 17 | grep Speed'
[Before]
Speed: 8400 MT/s
Configured Memory Speed: 6400 MT/s
[After]
Speed: 8400 MT/s
Configured Memory Speed: 5200 MT/s
Change-Id: I049d7c19424f41e83480f4b80bafd6ef8b9e30f6
Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83191
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Jian Tong <tongjian@huaqin.corp-partner.google.com>
|
|
Macros were being printed before the SPDX header in dsdt.asl, so fix
this. Previous output:
#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
/* SPDX-License-Identifier: GPL-2.0-only */
Change-Id: Idebdcf816911af9d262a114c86461e6fa5bfd1f8
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83187
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Add FW_CONFIG for no port LTE skus, and probe LTE port in devicetree.
BUG=b:339534479
BRANCH=firmware-dedede-13606.B
TEST=emerge-dedede coreboot chromeos-bootimage
flash and check boot log on DUT.
Change-Id: I5235df33a36f3b9472ee8b615e4622f6ee3fb1a4
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83054
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
|
|
If a board supports FW_CONFIG or ChromeEC CBI, the options should be
selected by the mainboard. These are not something that need to be a
choice to enable or disable in Kconfig.
The defaults are pointless, so remove them. The symbols default to no.
Correct the descriptions of FW_CONFIG_SOURCE_CBFS and
FW_CONFIG_SOURCE_VPD. They come after CBI and do not override any other
options.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Icf170dc2ef790d6f5a897a9c7c2ea64033bf1dc9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83118
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
Fill in ec.h according to schematic_20240614.
BUG=b:333486830
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot chromeos-bootimage
Change-Id: Ie1edf655fd20c0c1baee01fa90ed03501e3fe161
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83154
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Fill ec pins in gpio.h and configure GPE0 DW2 in overridetree according to schematic_20240614.
BUG=b:333486830
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot chromeos-bootimage
Change-Id: I9de842a8a66632314d5fdf6444005d34338a1100
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83155
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
|
|
The generated dsdt.asl and early_init.c files contained 2 consecutive
blank lines, so remove one of them.
Change-Id: Iad74098518320c5389cb86badb8737e81dd656ae
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83186
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Since Qemu doesn't provide an XSDT, coreboot adds one as separate ACPI
table. Qemu only provides the smaller ACPI 1.0 RSDP, but the XSDT can
only fit into the bigger ACPI 2.0 RSDP. Currently the exsting RSDP is
being reused, without a size check, which works fine on the first boot.
However after reboot the XSDT pointer seems to be valid, even though the
checksum isn't. Since the XSDT then isn't reserved again on reboot, the
memory it's pointing to is reused by other tables, causing the
payload/OS to see an invalid XSDT.
Instead of corrupting the smaller existing RSDP, allocate a new RSDP
structure and properly fill it with both, existing RSDT and XSDT.
In addition return the correct length of allocated ACPI tables to the
calling code. It was ommiting the size of the allocated XSDT and SSDT.
TEST: Run "qemu-system-x86_64 -M q35" and reboot the virtual machine.
With this patch applied XSDT is always valid from the OS
point of view.
Change-Id: Ie4972230c3654714f3dcbaab46a3f70152e75163
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83116
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Set PsysPL2 and PsysPL3 in addition to making adjustments
to PL2 and PL4 in order to prevent brownouts when we don't
have a battery or have an empty battery at boot time.
BUG=b:335046538,b:329722827
BRANCH=None
TEST=flash
Able to successfully boot on a SKU1 with 45W, 60W+ adapters
and SKU2 with a 60W or higher type C adapter.
30W is still being worked on.
Change-Id: Ie36f16b2c938dce29cd2130a86fc8c08f5ba0902
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83087
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
This commit simply adds support for a Do Not Disturb key. HUTRR94 added
support for a new usage titled "System Do Not Disturb" which toggles a
system-wide Do Not Disturb setting.
BUG=b:342467600
TEST=Build and flash a board that generates a scancode for a Do Not
Disturb key. Verify that KEY_DO_NOT_DISTURB is generated in the Linux
kernel with patches[0] that add this new event code using `evtest`.
[0] - https://git.kernel.org/pub/scm/linux/kernel/git/hid/hid.git/commit/?id=22d6d060ac77955291deb43efc2f3f4f9632c6cb
Change-Id: I26e719bbde5106305282fe43dd15833a3e48e41e
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82997
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Forest Mittelberg <bmbm@google.com>
|
|
Add support for an Accessibility key. HUTRR116 added support for a new
usage titled "System Accessibility Binding" which toggles a
system-wide bound accessibility UI or command.
BUG=b:333095388
TEST=Build and flash a board that contains an accessibility key. Verify
that KEY_ACCESSIBILITY is generated in the Linux kernel with patches[0]
that add this new event code using `evtest`.
```
Testing ... (interrupt to exit)
Event: time 1718924048.882841, -------------- SYN_REPORT ------------
Event: time 1718924054.062428, type 4 (EV_MSC), code 4 (MSC_SCAN), value a9
Event: time 1718924054.062428, type 1 (EV_KEY), code 590 (?), value 1
Event: time 1718924054.062428, -------------- SYN_REPORT ------------
Event: time 1718924054.195904, type 4 (EV_MSC), code 4 (MSC_SCAN), value a9
Event: time 1718924054.195904, type 1 (EV_KEY), code 590 (?), value 0
Event: time 1718924054.195904, -------------- SYN_REPORT ------------
```
[0] - https://git.kernel.org/pub/scm/linux/kernel/git/hid/hid.git/commit/?id=0c7dd00de018ff70b3452c424901816e26366a8a
Change-Id: Ifc639b37e89ec251f55859331ab5c2f4b2b45a7d
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82996
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Forest Mittelberg <bmbm@google.com>
|
|
This patch creates a new tereid variant, which is a Twin Lake platform.
This variant uses Nereid board mounted with the Twin Lake SOC and
hence the plan is to reuse the existing nereid variant code.
BUG=b:346442939
TEST=Generate the Tereid firmware builds and verify with boot check.
Change-Id: I052c3ba93d00e2df7e205c3127210bacaa956ca0
Signed-off-by: Sowmya V <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83145
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The SATA controller is configured to AHCI mode by default. Drop the
setting from the devicetree.
Change-Id: I027b393300e2cbad827e176afddc197007314f10
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83178
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com>
|
|
The attributes are initialized with 0 and thus setting them to 0 makes
them superfluous. Remove them.
Change-Id: I572a9092633c61907794ecbbbe431066d889c5fb
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83177
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
The attributes are initialized with 0 and thus setting them to 0 makes
them superfluous. Remove them.
Change-Id: Icdf58a85bbde0dcb4e555df68cd20eade241dde3
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83176
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com>
|
|
The attributes are initialized with 0 and thus setting them to 0 makes
them superfluous. Remove them.
Change-Id: Icb41f0a9baded01267410bd4c9458ab4bfb82b70
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83175
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com>
|
|
The attributes are initialized with 0 and thus setting them to 0 makes
them superfluous. Remove them.
Change-Id: I1239132d5f25345ebb051d216e9187f3d2250339
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83174
Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
The attributes are initialized with 0 and thus setting them to 0 makes
them superfluous. Remove them.
Change-Id: Ic16d568c38d708da27efa7229e23019e71c0019b
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83173
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
In commit 854dd9a5d1153fbb7ace2a7619bb98d024e284ce
(Makefile.mk: Put site-local path first) the inclusion of
site-local/Makefile.inc was moved to the first place. Unfortunately,
the very next line where subdirs-y is modified resets the variable
instead of extending it which overwrites the inclusion of
site-local/Makefile.inc. This breaks setups where
site-local/Makefile.inc is required.
This patch fixes it.
Change-Id: I36ad1aca5742869c84e2fb556f898f896c6f037a
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83190
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
|
|
Configure GPP_R2 as input, no pull according to schematic_20240614.
BUG=b:333486830
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot
Change-Id: Ic678b77e5489f56d8ff92b265a6ca5852c0f7e8d
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83142
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
|
|
Change-Id: I7114612e686a0bf3cfc241f45fa62077fad16f5a
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83161
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
The southbridge/intel/bd82x6x/pch.h header was previously used to
configure a few registers in SPIBAR, but these have since been moved to
PCH code and the devicetree, making it unnecessary in mainboard.c
Change-Id: I904c95394b4fea73b4990342e647595b5f10335f
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82601
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: I0b49ff8b6275fdde326c79ec21c34faa03094f9e
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83160
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
|
|
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I990d74d9fff06b17ec8a6ee962955e4b0df8b907
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77970
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add 64 bit encode/decode functions to libpayload, since it is required
in the patch that moves device_tree to commonlib.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I5dba9a7f41147a511ba1250786e7c51ce623e70a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83082
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
"site-local" Makfile(s) may need to override some of the macros/paths
used elsewhere in src/* Makefiles. If we include it last src/*
Makefile.mk will have already been processed. MAINBOARD_BLOBS_DIR is
an example where the path needs to be overwritten in site-local
requiring it to be included first before src/mainboard/* Makefile.mk
is processed.
Change-Id: I8ea865cd73aba5092a628b0422e5c4121b32fb4d
Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68799
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
Set a pointer in lib_sysinfo for CSE_BP_INFO and CSE_INFO.
BUG=b:343022317
TEST=Verified CBMEM data in depthcharge on Screebo
Signed-off-by: Eran Mitrani <mitrani@google.com>
Change-Id: I3aa64d1e439a0596e732a3c0608d60913cefd19f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82790
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
Remove m4 as an explicity installed package as it will be
installed automatically by flex and bison.
Change-Id: Ic4f1c5e6f3324429914bf593047d802dfcc0cb30
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82512
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add supported memory part in mem_parts_used.txt, then generate.
H54G56CYRBX247
BUG=b:199645942
TEST=run part_id_gen to generate SPD id
Change-Id: I2169d71695d8d133d26cafe5c7be33b976dd8603
Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83127
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Generated using update_ec_headers.sh [EC-DIR].
The original include/ec_commands.h version in the EC repo is:
d0771e49e7 MKBP: Increase key matrix size
The original include/ec_cmd_api.h version in the EC repo is:
d0771e49e7 MKBP: Increase key matrix size
Change-Id: I4f3dfc3f145e50e6114894352cdc118ad5a9565b
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82995
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Forest Mittelberg <bmbm@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This commit simply updates the input-event-codes.h to the HID
maintainers' tree at SHA c412e40267dd4ac020c5f8dc8c1cccc04e796ff4.
Change-Id: Ic1fb9b18ced37866b84230929cd5c785d0dde9ba
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82993
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
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The generator inserts into the gpio.h an unnecessary blank line in
front of the list of macros in the table. Let's remove this from the
template to make the code cleaner. These changes have no effect on the
configuration of macros.
Change-Id: I1141ca630cb6d9a46be5bce2b434762ef8e6fdd0
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83003
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This error does not affect the generated files as the tests are
running [1, 2, 3]. However, this once again confirms the need to
work on updating the utility.
[1] CB:67132
[2] CB:67133
[3] CB:67134
Change-Id: I91e74d65977bd5e10589530258d1709ea33f1af5
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83002
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Configure TSEG size by reading CONFIG_SMM_TSEG_SIZE in romstage.
The remaining Qemu code can already handle the bigger TSEG region.
TEST: Increased TSEG to 8MiB.
Change-Id: I1ae5ac93ecca83ae9c319c666aac844bbd5b259f
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83114
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
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Add support for PE32+ binaries which can be found on X64 UEFI
builds.
TEST: Able to relocate and boot a X64 FSP.
Change-Id: I22586834d7c9f3ab3a5e31bba957584587ec14e0
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82680
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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With commit 101098c41a ("sdm845: Combine BB with QC-Sec for ROM boot"),
most files from ipqheader were moved to the qualcomm directory.
Change-Id: I4e5136bd5ec4fd47bbd93cea2e4614fa63a3bd4e
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83028
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
|
|
Currently, the payload cannot create new CBMEM entries as there is
no such infrastructure available. The Intel CSE driver in the payload
needs below CBMEM entries -
1. CBMEM_ID_CSE_INFO to -
a. Avoid reading ISH firmware version on consecutive boots.
b. Track state of PSR data during CSE downgrade operation.
2. CBMEM_ID_CSE_BP_INFO to avoid reading CSE boot partition
information on consecutive boots.
The idea here is to create required CBMEM entries in coreboot so
that later they can be consumed by the payload.
BUG=b:305898363
TEST=Store CSE version info in CBMEM area in depthcharge on Screebo
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I9561884f7b9f24d9533d2c433b4f6d062c9b1585
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83103
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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