| Age | Commit message (Collapse) | Author |
|---|
|
Change a86d1b8 (soc/intel/common: Add SMM common code for Intel
Platforms) moved APL to use common SMM code. However, smi.c and smm.h
files under soc/intel/apollolake/ were not removed. This change
removes the dead files since they are not used anymore.
BUG=b:110836465
Change-Id: I1ff213372521fd47e2335de6a4b438d16c74ecd3
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27252
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Call to pmc_disable_all_gpe is required before enabling SMIs to ensure
that we do not end up in a recursive SMI handler loop as mentioned in
change 74145f7 (intel/common/pmc: Disable all GPEs during
pmc_init). Thus, this call was added at the end of
pmc_fill_power_state as we want to ensure that all the GPE registers
are backed up before being cleared for identifying the wake source in
ramstage.
This resulted in a side-effect on APL where pmc_fixup_power_state was
called much later in the boot process. Even though we have got rid of
pmc_fixup_power_state, this change moves the call to
pmc_disable_all_gpe to happen just before enabling SMIs. This helps to
keep the disabling of GPEs logically before the enabling of SMIs and
any clean ups that happen in pmc or soc-specific code should not
affect the state of GPEs.
BUG=b:110836465
TEST=Verified that wake sources are correctly identified on KBL and
APL. Also, no SMI handler issues observed when resuming.
Change-Id: I122a8118edcec117f25beee71a23c0a44ae862ed
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27251
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Now that APL does not need pmc_fixup_power_state, this function can be
removed from the PMC common code as well.
BUG=b:110836465
Change-Id: I94de41f3e52228bca4b7a5579afe5a23719429be
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27250
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
On APL, call to pmc_fixup_power_state was added because GPE0_EN
registers did not have the right bits set on resume from S3 -- this
was a result of GPE_CFG registers getting reset to their default state
on resume. GPE_CFG registers are programmed as part of pmc_gpe_init
which was previously done only in ramstage.
However, with change a673d1c (soc/intel/apollolake: Initialize GPEs in
bootblock), call to pmc_gpe_init was added to bootblock which means
that GPE_CFG registers will have the right state by the time control
reaches romstage where pmc_fill_power_state is called. Thus, call to
pmc_fixup_power_state is totally redundant and in fact leads to
side-effects because of the call to pmc_disable_all_gpe at the end of
pmc_fill_power_state.
BUG=b:110836465
TEST=Verified on yorp that wake source is correctly identified on
resume from S3.
Change-Id: Ia63ddbe381ce8a59736c231d745fd71d008d5d92
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27249
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
%edx gets clobbered before the c handler is invoked. This is just a
cleanup cl to make the next cl look clean.
BUG=b:80539294
TEST=verified SMI still works on grunt.
Change-Id: I21bf41ed4fdeaaa8737c883f202a39cb57c2b517
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/27228
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
When generating a backtrace we need an indicator when we have hit the
beginning of the stack. The i386 ABI states that %ebp points to the next
stack frame. NULL can be used to indicate the end of the stack.
We could add a NULL return pointer at %ebp+4, but I decided to omit it
since a NULL stack pointer can be used as an indicator that there is no
return pointer.
BUG=b:80539294
TEST=built and tested on grunt
Change-Id: I8a48114d31a5c716335d264fa4fe4da41dc5bf11
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/27226
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This reduces the cognitive overhead of referencing locals via esp since
it changes with every push.
BUG=b:80539294
TEST=built and booted on grunt.
Change-Id: Ib7eb98ce3483d4fc803696c1b2496d8384317536
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/27225
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
This makes it easier to spot unused RAM.
BUG=b:80539294
TEST=built and tested on grunt. Verified unused memory was set to 0xcdcdcdcd
Change-Id: I335eaf642bd8526f31819eaac95ce80c2df3c300
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/27227
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
These files are directly extracted from the vendor firmware
Change-Id: I1f05c913872c5d2d8c8279d89eac52fd4bf4e35e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27222
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
Type of vbt_len should be size_t, change to fix compiler error
Change-Id: I22798fa0edb98fcb9acc1b2dd52f34a61bc511e9
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27224
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
An unidentified combination of speculative reads and branch
predictions inside WRPROT-cacheable memory can cause invalidation of
cachelines and loss of stack on models based on NetBurst
microarchitecture.
Therefore disable WRPROT region entirely for all family F models.
As an extreme example, just changing the location of a constant string
passed to printk() has been witnessed to make a the boot fail early on
in romstage.
Change-Id: I1df84ad55e2d8d6d4e8dca10125131b5f525f0d7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/27133
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
|
|
For cases with POSTCAR_STAGE=y this reference pulled
in the implementation of run_ramstage() which we would
not call.
Using _program results with the same region being marked
as WRPROT-cacheble.
Change-Id: Ie1eaf6f5bb8baa13e946112c4fc3d854dbf750a3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/27232
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Keith Hui <buurin@gmail.com>
|
|
Change-Id: Ieb809a078356f696afd813c39c65da1d7c7482c8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/27231
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Don't consume CBMEM for stage cache when we would
never use it.
Change-Id: I606e0457ff3085822554c4041fc56f0d28cc9c2d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/27230
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Disabling the MMU with proper cache behavior is a bit tricky on ARM64:
you can flush the cache first and then disable the MMU (like we have
been doing), but then you run the risk of having new cache lines
allocated in the tiny window between the two, which may or may not
become a problem when those get flushed at a later point (on some
platforms certain memory regions "go away" at certain points in a way
that makes the CPU very unhappy if it ever issues a write cycle to
them again afterwards).
The obvious alternative is to first disable the MMU and then flush the
cache, ensuring that every memory access after the flush already has the
non-cacheable attribute. But we can't just flip the order around in the
C code that we have because then those accesses in the tiny window
in-between will go straight to memory, so loads may yield the wrong
result or stores may get overwritten again by the later cache flush.
In the end, this all shouldn't really be a problem because we can do
both operations purely from registers without doing any explicit memory
accesses in-between. We just have to reimplement the function in
assembly to make sure the compiler doesn't insert any stack accesses at
the wrong points.
Change-Id: Ic552960c91400dadae6f130b2521a696eeb4c0b1
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/27238
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Some arm64 files that were imported from other projects use the
__ASSEMBLY__ macro to test whether a header is included from a C or an
assembly file. This patch switches them to the coreboot standard
__ASSEMBLER__, which has the advantage of being a GCC builtin so that
the including file doesn't have to supply it explicitly.
Change-Id: I1023f72dd13857b14ce060388e97c658e748928f
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/27237
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
This file has been dead since commit 7dcf9d51 (arm64: tegra132:
tegra210: Remove old arm64/stage_entry.S), I just forgot to remove it.
Change-Id: I0dd6666371036ecd42c1b256dbbe22a01ae959b8
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/27236
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
TPM config items added upstream before ready
SPI/TPM is not functional on Cheza yet
Change-Id: I302e00014dc31279fe2574765763ecdbf326b449
Signed-off-by: T Michael Turney <mturney@codeaurora.org>
Reviewed-on: https://review.coreboot.org/27213
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
With -D, the newly built toolchain isn't installed into $prefix/...
but into $DESTDIR/$prefix/... while being built for $prefix alone.
This is useful for distributions, but it breaks down when the build
host already has the toolchain installed in $prefix without proper
build isolation (cf. gentoo):
In such cases libgcc etc are built using the new compiler (as gcc's
build system is smart enough to state the path explicitly), but that
compiler then uses its regular algorithm to determine the path to as,
ld, ...
That makes it use the tools from $prefix, which might differ in formats
(assembly, certain object file flags, ...): nds32le-elf in particular
has rather unstable formats still, and so new compilers can't work
with old binutils.
The approach to deal with this is to take an unused path that's
specified by gcc's build system ($out/gcc/$arch/$version) and symlink
it to the new toolchain - these explicitly given directories take
precedence over the default search path, and so the new binutils
are used.
Change-Id: Ia9a262e73f56cd486a2ae07422b598c205a03aed
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/27241
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This change adds GSMI callback elog_gsmi_cb_mainboard_log_wake_source
to enable logging of EC wake events in S0ix.
BUG=b:79449585
TEST=Verified that S0ix entry/exit events are added to eventlog:
=========== Lid open ================
62 | 2018-06-25 14:02:36 | S0ix Enter
63 | 2018-06-25 14:02:56 | S0ix Exit
64 | 2018-06-25 14:03:26 | Wake Source | GPE # | 15
65 | 2018-06-25 14:03:32 | Wake Source | GPE # | 65
66 | 2018-06-25 14:03:37 | EC Event | Lid Open
Change-Id: Icc8cd3624966ff66d2cf189871e452cf650cec40
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27235
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This change adds GSMI callback elog_gsmi_cb_platform_log_wake_source
to enable wake source logging from S0ix on APL/GLK. Additionally,
elog.c is added to smm stage.
BUG=b:79449585
TEST=Verified that S0ix entry/exit events are added to eventlog:
=========== Power button ============
59 | 2018-06-25 14:01:11 | S0ix Enter
60 | 2018-06-25 14:01:30 | S0ix Exit
61 | 2018-06-25 14:02:00 | Wake Source | Power Button | 0
=========== Lid open ================
62 | 2018-06-25 14:02:36 | S0ix Enter
63 | 2018-06-25 14:02:56 | S0ix Exit
64 | 2018-06-25 14:03:26 | Wake Source | GPE # | 15
65 | 2018-06-25 14:03:32 | Wake Source | GPE # | 65
66 | 2018-06-25 14:03:37 | EC Event | Lid Open
=========== Trackpad ================
67 | 2018-06-25 14:04:20 | S0ix Enter
68 | 2018-06-25 14:04:33 | S0ix Exit
69 | 2018-06-25 14:05:03 | Wake Source | GPE # | 15
70 | 2018-06-25 14:05:08 | Wake Source | GPE # | 66
Change-Id: I005de58c73d00dc9d7e64f1459f6d786792b94db
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27234
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Limit is the maximum number of bits to be tested, however it's being checked
against the number of bytes of uint32_t. when it should be number of bits.
Create a macro to provide the number of bits, and use it instead of sizeof.
BUG=b:75996437
TEST=Add debug messages to see code passing beyond the check, build and
boot grunt, check that it passed the limit check, remove debug code.
Change-Id: Id1dfda26d789183b346b20c37fec923d996b80db
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/27162
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Adds Open Cellular rotundu mainboard supports.
Working:
- 2x Ethernet support
- MSATA support
- CPU init
- Memory init
- USB support
- EMMC but disabled
Not working:
- TPM support
Create directory structure and Kconfig files for OpenCellular
Rotundu and copy sources from intel/minnowmax.
Change-Id: I391d4bdd485f4bf5396c764fe3f11d98369593e4
Signed-off-by: Hong Gan <hgan@fb.com>
Signed-off-by: David Hendricks <dhendricks@fb.com>
Reviewed-on: https://review.coreboot.org/22894
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
|
|
This adds another camelbackmountain_fsp derivative, along with a .fmd
file for the board. For now it's been tested to build and boot.
Change-Id: I9e8804264967c19f6b51fc44575b0db36f600f88
Signed-off-by: David Hendricks <dhendricks@fb.com>
Reviewed-on: https://review.coreboot.org/25884
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
|
|
Once a second bootblock has been added using topswap (-j)
option, Update the entries in second FIT using -j option with
update-fit command.
Additionally add a -q option which allows to insert the address of
a FMAP region (which should hold a microcode) as the first entry in
the second FIT.
BUG=None
BRANCH=None
TEST= Create ROM images with -j options and update FIT using -q option.
example:
./build/util/cbfstool/cbfstool coreboot.tmp create \
-M build/fmap.fmap -r COREBOOT,FW_MAIN_A,FW_MAIN_B,RW_LEGACY
build/util/cbfstool/cbfstool coreboot.tmp add \
-f build/cbfs/fallback/bootblock.bin -n bootblock -t \
bootblock -b -49152 -j 0x10000
build/util/cbfstool/cbfstool coreboot.tmp add-master-header -j 0x10000
build/util/cbfstool/cbfstool coreboot.tmp add -f build/cpu_microcode_blob.bin \
-n cpu_microcode_blob.bin -t microcode -r COREBOOT -a 16
build/util/cbfstool/cbfstool coreboot.tmp. update-fit \
-n cpu_microcode_blob.bin -x 4 -j 0x10000 -q FW_MAIN_A
Also try the failure scenarion by providing invalid topswap size.
Change-Id: I9a417031c279038903cdf1761a791f2da0fe8644
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/26836
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add an option '-j' which takes the size of topswap boundary.
This option serves both as a bool and a size for creating
a second bootblock to be used with topswap feature in Intel CPUs.
'-j' is also used in conjunction with add-master-header to
update the location of cbfs master header in the second bootblock.
BUG=None
BRANHC=None
TEST=add bootblock entry to the image with -j option specifying different
topswap sizes and also use the -j option for add-master-header.
Change-Id: I3e455dc8b7f54e55f2229491695cf4218d9cfef8
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/22537
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Put the PCIe clock pins in power-saving mode for the BayHub eMMC bridge to
save power. This requires use of an additional register (Misc control
register 2) and another bit in the existing 'protect' register. The naming
of bit 0 of that register is incorrect, based on the latest datasheet
(14 June 2018) so fix that too.
BUG=b:73726008
BRANCH=none
TEST=boot without this patch:
iotools mem_read32 0xfed80e00
0x0046ffff
With this patch:
$ iotools mem_read32 0xfed80e00
0x00463fff
Also see that the PCIe clock stops when eMMC is idle and can be started by
starting disk activity.
Change-Id: I5ad1467b2e2e151215d2dfd2ce48cd4a451fe480
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://review.coreboot.org/26515
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
There are many boards in coreboot which support multiple
variants. When abuild is used to compile a single target, it builds
all its variants. If a target has 5 variants, then abuild takes nearly
10x the time to compile all variants of the target. This change adds
an option -b/--board-variant to enable abuild to compile only a single
variant of the target.
TEST=Verified:
1. abuild builds all variants of the target if -b option is not
provided.
2. abuild builds a single variant if -b option is provided.
3. abuild prints appropriate error message if invalid variant name is
provided.
Change-Id: I3781568c6409c5ec2610a8386a21d86037428e7f
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27215
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Now that sconfig is able to support variant-specific override trees,
this change updates octopus boards to use this feature. Following
devices are moved from baseboard devicetree to variant specific
devicetree:
1. Touchscreen
2. Trackpad
3. Digitizer
4. Audio codec
BUG=b:80081934
TEST=Verified that the right devices show up in static.c for each
variant.
Change-Id: I8df0cdf4dbcd7613aa4ef4042c272eca2915da9e
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27219
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
"ops" field was used in device structure only to add
default_dev_ops_root for root device. It was always set to NULL for
all other devices. This change gets rid of ops field from struct
device and instead hardcodes default_dev_ops_root in pass1 for root
device.
BUG=b:80081934
TEST=Verified that static.c generated with and without this change is
exactly the same.
Change-Id: I0848788610c2ed27274daf4920de3068a9784d4c
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27209
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This change adds support to allow variants to override the devices and
properties in base device tree by providing an override device
tree. It works as follows:
1. Both base and override device trees are parsed from provided input
files.
2. Walk through the trees in lockstep fashion using depth-first
traversal checking if a node in override tree has a matching node in
base tree.
- If matching node is found, then update the properties of base node
using the override node. Continue walking the children of the nodes.
- If matching node is not found, then copy the entire override
subtree of the node under the current base parent. In addition to
that, chip instance pointers of the nodes in override tree need to be
updated if they were pointing to the override parents chip instance.
Since chip always expects a device to be present, it leads to a
side-effect that overriding chip registers requires that a device is
always provided for the chip in the override tree as well.
BUG=b:80081934
Change-Id: I6604e4f8abe3fc48240e942fea32da96031e1e46
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27206
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This change adds a new config option OVERRIDE_DEVICETREE that allows
variants to provide an override devicetree file to override the
registers and/or add new devices on top of the ones provided by
baseboard devicetree using CONFIG_DEVICETREE.
BUG=b:80081934
Change-Id: Ica046b7e0d70d0f1e8d94da714d1e62032277916
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/26691
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
We found GPP_C3 keeps high when system in S0ix mode. It caused 1.8V
leakage. To fix this problem, add GPP_C3 into config for Pantheon
Synaptics touchscreen.
BUG=b:78436458
BRANCH=None
TEST=Let DUT in S0ix mode and check GPP_C3 is normal.
Change-Id: Idb2dab93178af1dae54265e49522b473b69a35af
Signed-off-by: Crystal Lin <crystal_lin@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/27177
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This change allows sconfig utility to accept an extra optional
parameter to specify override device tree that can be used to override
the properties or add new devices in addition to that provided by base
device tree. This is helpful for variants that share most of the
devicetree but have to override certain registers or add some devices
which might not be applicable to base devicetree.
In order to support the override devicetree, following changes are
made in this CL:
1. override_root_dev and override_root_bus are provided.
2. main() function is updated to accept an optional argument.
3. If override device file is provided, then parse_devicetree is
called for override_devtree as well.
This change in itself does not provide the override feature. It is
only a small step towards the final goal. The override devicetree
parsed by sconfig is currently unused.
BUG=b:80081934
Change-Id: I477e038c8922ae1a9ed5d8bf22a5f927a19a69c7
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/26689
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
This patch updates DPTF parameters for Octopus baseboard.
BUG=b:79779737
BRANCH=None
TEST=Build coreboot for Octopus board.
Change-Id: I1456b7b9ee9e02491c66b0709c710e1a7ec08cc5
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/27027
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Change-Id: I243c22c83a5575c2e1500cc869c41691c4fba415
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/27014
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
|
|
This change enables xDCI controller on nami.
BUG=b:110443736
BRANCH=None
TEST=None
Change-Id: Ieb63e0d65ac1a142c151a3f93afe306b80a5d99a
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/27181
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
From checkpatch output, look for keywords starting with 'ERROR:' &
'WARNING:' .
Also check for keywork ': FILE:' instead of the same without the
colon (:).
BUG=None
BRANCH=None
TEST=Check if patch https://review.coreboot.org/#/c/coreboot/+/22537/21
is processed & json output is generated properly.
Change-Id: Ib690ab34a1ffabc4f83642634fd34beea16a64dc
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/27170
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Recent patches in coreboot have fixed the freeze issues related to the
use of me_cleaner on Nehalem.
However, at least on the Lenovo X201, with me_cleaner some PCIe devices
(like the SATA and USB controllers) disappear. In particular, setting
the AltMeDisable bit ("-S" or "-s" flag) makes them disappear
completely, while unsetting it makes them disappear only during cold
boots.
This kind of behaviour was already observed by Youness Alaoui on the
Purism Librem laptops ([1]), and it seems related to some required
board-specific PCIe configuration in the ME's MFS partition.
For this reason, on the Lenovo X201, "-w EFFS" has been added to the
me_cleaner arguments, which whitelists the MFS-equivalent partition for
ME generation 2. This fixes all the issues, and the PCIe devices work as
expected.
[1] https://puri.sm/posts/deep-dive-into-intel-me-disablement/
Change-Id: Ie77a80d2cb4945cf1c984bdb0fb1cc2f18e82ebc
Signed-off-by: Nicola Corna <nicola@corna.info>
Reviewed-on: https://review.coreboot.org/27178
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
During Speaker playback, quad Channel I/V feedback data is
captured from SSP0 Rx. Out of these 4-channels, Stereo V-Sense data
needs to be given as echo ref stream.
So, adding stereo capture config to max98373_capture_formats.
BUG=b:110074225
TEST='Audio playback and Capture Stereo echo ref data'
Change-Id: I6fe619ece94d5011caffe37ef10b48f956938db9
Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Reviewed-on: https://review.coreboot.org/27182
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
i2c/alps driver implementation is an exact copy of the i2c/hid driver
with only the addition of ALPS0001_HID. This can be supported by the
i2c/hid driver using the hid field in devicetree which is what glkrvp
mainboard does. So, this change removes the i2c/alps driver which is
anyways unused.
Change-Id: I60761c384f3d800532b2b346272da7be28b77acd
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27208
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
This change fixes the issue reported by Coverity CID 1393576 to ensure
that config is checked for NULL before it is actually used.
Change-Id: I5f0cd2bf2437fc640f4cf8d8203a971daf1f8d17
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27207
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Enrico Granata <egranata@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
Tested with GRUB 2.02 as a payload, booting Arch Linux as
well as Debian. This code is based on the output of autoport
as well as other mainboards supported in coreboot already.
Working:
- Serial port I/O
- S3 suspend/resume. Untested with SeaBIOS since it failed
to resume on a similar board. It is likely to be due to
low memory corruption, but I have not worked on it.
- USB ports and headers
- USB3 ports attached to the ASM1042 controller. SeaBIOS can
boot from them, and it is likely GRUB can detect devices on
those ports as well. The chip has a small SPI flash nearby,
which seems to hold an Option ROM.
- Gigabit Ethernet
- Integrated graphics (libgfxinit)
- VGA BIOS for integrated graphics init
- PCIe x16 graphics
- PCIe x1
- SATA controller
- Hardware Monitor
- Fan Control (fancontrol on linux works well)
- Native raminit
- flashrom, using the internal programmer. Tested with coreboot,
as well as with the vendor firmware.
- NVRAM settings. Only debug_level has been tested.
Untested:
- DVI port. It can detect a "fake" display, that is, an
EEPROM connected to the DVI port. Thus, gma-mainboard.ads
has been setup accordingly.
- PS/2 port.
- Audio: Only rear output (green) has been tested.
- EHCI debug.
- Parallel port header.
- Non-Linux OSes
- ACPI thermal zone and fan control (probably not working)
Not working:
- Booting from devices attached to the ASM1061 controller.
Devices on ports work fine once Linux has loaded.
- Any SATA devices with Tianocore (payload issue)
Change-Id: I7e89ebe43a2e1ff0308f4876e98bbf2f5a0d85f2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/26419
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Regarding "Intel 945G/945GZ/945GC/945P/945PL Express Chipset Family",
Document Number: 307502-005, page 91, if Channel B is empty,
all of the C1DRBs are programmed with the same value as C0DRB3.
Mobile 945 express chipset datasheet doesn't mention this specific case.
Change-Id: Ic26103aac7f920e5696b445e125d33405df4f43b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/27204
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
- add K4E6E304EC-EGCF and K4EBE304EC-EGCF to memory strapping table
BUG=b:110498646
BRANCH=none
TEST=none
Change-Id: Iddacdf1e1d0e2bae0c6168c86e54f5f602cd9d19
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/27184
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This configures a GPIO pin for enabling/disabling bluetooth on the
next version of the atlas board. The default is for bluetooth to be
enabled at this point.
BUG=b:110614620,b:110613353
BRANCH=none
TEST=none
Change-Id: I4ba940e89b1dc03548b7ab44b8f84dc9a3097acb
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/27185
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This patch ensures serial debug is not enabled by default on Cannonlake
platform.
Change-Id: Id925c8c73971a027e45ea3c61e878f134bc9feff
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/27205
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Modify DPTF TRT parameters to solve thermal sensor QT2 PSV problem.
BUG=b:109941652
TEST=The thermal team verify OK
Change-Id: Id9d39d8282712a0341fea10f74c0e40bb1ac9d7c
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/27088
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Move GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC under each variant config and
select it for bip and fleex only.
Functional change in this CL is that EC SW sync will be enabled for
phaser.
BUG=b:110523400
Change-Id: If6f37c6b2ee71130b9ed5b10ce92fb23fa1c39fc
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27179
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
Bootblock has grown beyond 32K, grow to 40K
Change-Id: Iedc52151e223ebf4ff5b35a419b5378a6f1c661b
Signed-off-by: T Michael Turney <mturney@codeaurora.org>
Reviewed-on: https://review.coreboot.org/26760
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
|
|
Add CONFIG_LP_CHROMEOS to configuration file
Change-Id: I528dee96cf5052b99b8f7573010d98fd80680688
Signed-off-by: T Michael Turney <mturney@codeaurora.org>
Reviewed-on: https://review.coreboot.org/26711
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
Commit 77034fa [intel/common: compress VBT] compressed vbt.bin in
CBFS, but only changed the loader in soc/intel/common, forgetting
the separate one used by FSP 1.1.
As the soc/intel/common loader has now been rolled into the one in
drivers/intel/gma, replace the VBT loader used by FSP 1.1 with the GMA one.
Also, remove 2 now-unused header files.
Test: build/boot google/chell, observe display initialized prior
to OS load, no FSP warning in cbmem console due to invalid VBT signature.
Change-Id: Iba882ee4d9e83dcd88bdf7dd2f5591f66005a3fe
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27169
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Change-Id: I7358ee34df873098a86d692cc8a909b0ec5023a8
Signed-off-by: Enrico Granata <egranata@chromium.org>
Reviewed-on: https://review.coreboot.org/27172
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
This adds a new driver for the SX9310 proximity detector device.
The purpose of this is to enable the device's calibration information
to be stored in firmware, and then transferred over to the kernel
via ACPI.
This device has more than 10 individual configuration parameters,
so they would not fit in the generic driver's properties table.
Change-Id: Id8c434eec9fe2da731e142442503a12e88db2236
Signed-off-by: Enrico Granata <egranata@chromium.org>
Reviewed-on: https://review.coreboot.org/27173
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Some older CPUs have a fixed size of 2048 bytes for microcode total size.
Change-Id: Ia50c087af41b0df14b607ce3c3b4eabc602e8738
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/27090
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Alternative buffer communication support for PTT is no longer
needed for CNL onwards and coreboot does not need to reserve additional
4KiB memory for PTT support.
Change-Id: I11993cef77fd5e879eedabc1ed344f91f8257c90
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/27176
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
SoC users from IOTG team is looking forward for a solution to skip
coreboot AP initialization flow and make use of FSPS-UPD to
perform AP reset.
TEST=Assign use_fsp_mp_init=1 to ensure coreboot is not bringing APs
out of reset.
Change-Id: Ibc8cd411e802fb682436a933073922b2693ba994
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/26644
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Adds missing PCI IDs to allow tool to dump the
C220 PCH (8 series) southbridge.
Intel Document 328904 is the datasheet for this PCH.
Change-Id: I07a8f2e9cb0ee8677c8fe2c51881147ed81c1a35
Signed-off-by: Quan Tran <qeed.quan@gmail.com>
Reviewed-on: https://review.coreboot.org/27168
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
The packge uuid-devel doesn't provide the required files,
but libuuid-devel does.
Change-Id: I61d537e4f1fca0d7172c129a75e13aa58452763f
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/27136
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
Use SPI_BASE_ADDRESS instead of PRERAM_SPI_BASE_ADDRESS like
big core in order make common code implementation straightforward.
Change-Id: Ibcb013fc95de29234253e89c9ca100cc468d44f6
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/27097
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Select all Kconfig belongs into Intel SoC Family basecode/stage files
and include required headers from include/intelbasecode/ files.
BUG=None
BRANCH=none
TEST=Code is compiling with cannonlake configurations and also booting
on cannonlake RVP.
Change-Id: Iac99b4346e8bf6e260b00be9fefede5ad7b3e778
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/25734
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Change-Id: I61fb3b01ff15ba2da2ee938addfa630c282c9870
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/27043
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
Change-Id: I2fe8d8388cb96e42af4f9be251a41cceeb2e4710
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/27042
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
No Change in BUILD_TIMELESS.
Change-Id: I634526269d45ebdc6c31cdc28d9ec846b397211d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/27041
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
In the end it does not look like RCBA register offsets are fully
compatible over southbridges.
This reverts commit d2d2aef6a3222af909183fb96dc7bc908fac3cd4.
Is squashed with revert of "sb/intel/common: Fix conflicting OIC
register definition" 8aaa00401b68e5c5b6c07b0984e3e7c3027e3c2f.
Change-Id: Icbf4db8590e60573c8c11385835e0231cf8d63e6
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/27038
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
Change-Id: Ibe54096f275a05bda745ae2cc76c0109281c0c4b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/27095
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
PM registers used for generating SWS values are being stored in a static
variable within southbridge.c. In order to have it available for any source
involved in building the platform, move the storage to cbmem, using id
CBMEM_ID_POWER_STATE. Also add a variable that informs from which state
the system is waking from, extracted from register ACPI_PM1_CNT_BLK. This
variable will later be useful in detecting failed S3 resume.
BUG=b:80119811
TEST=Add code to print SWS parameters and state it's waking from. Build
and boot grunt, suspend and resume, check output for valid values. Remove
the print code.
Change-Id: Ib27a743b7e7f8c94918caf7ba5efd473f4054986
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/27109
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Is unused in the tree.
Change-Id: I8a5308b6c7773d791d47832e620558394f1d727e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/22132
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Upstreaming Chromium commit 0bc6c43:
Lili: Update Memory IDs
TEST=Build and boot up on lili board
Original-Change-Id: I6da1e97820b1bf2e751102384eed07236143fe2b
Original-Signed-off-by: Ren Kuo <Ren.Kuo@quantatw.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/956782
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Change-Id: Icf6588582da3b4a7861bced539d51a914b011dc4
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27135
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
`freetype-config` is gone and was obsolete for a long time.
Change-Id: Id3058e55b1630f43225d3cd1ad91801c4085874f
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/26822
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
Adds the CMOS option for Dual Graphics, as is present in more Lenovo models
already. Enabling this option ensures that the NVIDIA GPU is powered.
More PCI devices can be observed when activating this setting. It was verified
on a W520, also by loading a VGA option ROM and achieving a working Dual
Graphics system.
The CMOS default has been kept to 'Integrated Only', as the usage of Dual
Graphics requires an option ROM and drains the battery more quickly.
Change-Id: I41ccabd4554ca019684edd6f8b1c23679212c59f
Signed-off-by: Nico Rikken <nico@nicorikken.eu>
Reviewed-on: https://review.coreboot.org/26114
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
|
|
- add K4E6E304EC-EGCF and K4EBE304EC-EGCF to memory strapping table
- add SPD files for K4E6E304EC-EGCF and K4EBE304EC-EGCF
BUG=b:110277021
BRANCH=none
TEST=none
Change-Id: If1322311bd91842d6d32725822d91fd6d9e8077c
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/27123
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
When played Left Only Audio and Right Only Audio, we observed that Audio
got swapped. Left Data played on Right Speaker and Viceversa.
This patch fixes the above issue.
BUG=b:73635449
TEST=Play Left only & Right only Audio and cross check Audio.
Change-Id: Ie9c417ad0634a76fc8a4126ee75886603f1b3da0
Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Reviewed-on: https://review.coreboot.org/27167
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
C1E is disabled by the kernel driver intel_idle at boot. This does not
address the S3 resume case, so we lose state and C1E is enabled after S3
resume.
Disable C1E for SKL and KBL. This gives a coherent state before
and after S3 resume.
TEST='iotools rdmsr cpu 0x1fc'. Returns the same value after boot and S3
resume with bit [1] set to zero (0x20005d).
Change-Id: I1343f343bfac9b787f13c15b812c0a201dcccb38
Signed-off-by: Cole Nelson <colex.nelson@intel.com>
Reviewed-on: https://review.coreboot.org/27125
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The entire StdHeader field is really supposed to
be forked from a template for each entry into the
AGESA API. Current code assumes only Callout would
be relevant, which is not quite the case.
Change-Id: I0cc66d01d62fa8dc6bb7c9f9fab6fa4753827554
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/27111
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
|
|
Set register speed_shift_enable=0 in devicetree to disable
p-states in coreboot as a temporary workaround for an SoC hang.
BUG=b:79666828
BRANCH=none
TEST="emerge-nocturne depthcharge coreboot chromeos-bootimage",
flash spi image onto nocturne, boot to kernel and verify device
stays alive and responsive for several minutes without locking up.
Change-Id: I71ed4c80c109b28ffa85d48338ce3a62396d272e
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/27156
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
DRAM_DMA section is used for the special SPI NOR controller on legacy
SOC. Remove it since no driver need it currently and we don't have the
special SPI NOR controller on mt8183.
BUG=b:80501386
BRANCH=none
TEST=Boots fine on Kukui
Change-Id: I6ba0757adbf4f1f8d2688e5ab1a36007e4e0d0fd
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/27113
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
|
|
Using common watchdog timer (WDT) code for reset. Set up watchdog timer
in mtk_wdt_init() to get reset status and disable auto-reboot. Link
common do_hard_reset() to support hard reset.
BUG=b:80501386
BRANCH=none
TEST=both mtk_wdt_init() and do_hard_reset() work on Kukui.
Change-Id: I4be3a133dbb8a64604133cefb0c5f02d01afd0d4
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/27026
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Move watchdog timer (WDT) code which can be reused into a common
directory under soc/mediatek.
BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Elm
Change-Id: Icbeb04f775c3c0fdc18dd198df8591f5c4b6ddce
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/27025
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Refactor watchdog timer (WDT) code which will be reused among similar
SOCs.
BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Elm
Change-Id: I745c2f204924d9eee1941c0f3e9b6ba45cfb1958
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/27024
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This is a temporary hack to test camera presence before we have full
camera support implemented. Basically, we can now probe the camera
over i2c to verify that it's connected and the camera LED turns on.
BUG=b:80106316
BRANCH=none
TEST=camera LED comes on and camera can be probed over i2c.
Change-Id: Ibaabf6c6f6a1dabaddd2fc47c820e090ca5984a5
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/27128
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This adds the necessary config to enable touchscreen sensor in linux.
BUG=b:110286344,b:110286345
BRANCH=none
TEST=verified touch functionality using eval board
Change-Id: I21efafda3f2ae1dcea19e44f8d66f6dfaac1bb12
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/27127
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
We plan to use i2c-hid compatible trackpads on atlas, so this switches
the trackpad config to i2c-hid.
BUG=b:80662079
BRANCH=none
TEST=used trackpad to verify motion tracking
Change-Id: I2702e61a6aa96250c0c09ea4bd15d0c671eedadc
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/27126
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This change defines SAR sensor device into devicetree.cb.
Since only LTE sku has SAR sensor, we will use GPP_B20 as a device_present_gpio.
BUG=None
BRANCH=poppy
TEST=Verified SAR sensor device is loaded by driver in Chrome OS
Change-Id: Ib4969e4b82d18b1b1a599de8226c2d7d4bda7915
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/27149
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Nautilus 2nd SKU has a leakage voltage at GPP_D0 in S5 state. We need to set this to LOW when entering S5 for clear the leakage.
BUG=None
BRANCH=poppy
TEST=Verified the leakage is gone after update coreboot
Change-Id: I054e707b2bc2e63d6f99cd2fd8a57be20615f111
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/27148
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
For supporting new SKU, we need to override GPIO table and device configuration.
The board ID of 2nd SKU of nautilus is started from 9, so we would determine SKU with it.
BUG=b:80052672
BRANCH=poppy
TEST=emerge-nautilus coreboot
Change-Id: I7242f23f47010664cc29ea86a126e63c9dd62ccd
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/27147
Reviewed-by: Enrico Granata <egranata@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This patch adds a file for uncore ASL code that is common among
Broadwell-DE mainboards but is currently copy + pasted in each of
their dsdt.asl files.
This is only for clean-up purposes. It is unclear if the code itself is
really necessary, but until we can do further investigation and testing
it will be left in.
Change-Id: I188e5e46dfa7c2ed3991fb97f2c1b5e062e2212d
Signed-off-by: David Hendricks <dhendricks@fb.com>
Reviewed-on: https://review.coreboot.org/27155
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
Collected timestamps indicate LZMA decompression of ramstage
is 4x slower when ROM is marked WP-cacheable, in contrast to
having ROM as US. A simple copy WP->WB with uncompressed
ramstage also appeared to be twice as slow as UC->WB copy.
It should be noted that if POSTCAR_STAGE was removed from build,
un-lzma takes 130 seconds instead of 45 milliseconds.
Change-Id: I2cf995395ef2d303ad0bc044dbfa160990a705d0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/27164
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
Change-Id: Ic6e2a350a976a3fcb421d47a0bf5600df994edc2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/27163
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
This change fixes the following issues with EC_IN_RW signal:
1. EC_IN_RW is an input signal to the SoC. Configure it accordingly in
GPIO table for baseboard and bip.
2. GPIO_EC_IN_RW is passed in coreboot tables so that payload can
re-sample the GPIO at runtime.
BUG=b:110084012
TEST=Verified that EC_IN_RW signal is read correctly in depthcharge.
Change-Id: I1c5f5b4b914ced98e89a571dc398df5ba1fe8460
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27166
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
|
|
This change adds Synaptics device to phaser project.
BUG=b:110236590
TEST=emerge-octopus coreboot chromeos-bootimage
reflash the coreboot to DUT,make sure the Synaptics Touchpad can work.
Change-Id: Icc1e8c35a9de54ed04187fcf219a72a592d3bd81
Signed-off-by: Xingyu <wuxy@bitland.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/27159
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
* Add LinuxBoot support
* Add u-root mode
* Download kernel and u-root from upstream sources.
* Add customization options
* Clean kernel only if directory exists
Change-Id: I3a25ff6812e046acc688cbbb203cf262ad751659
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/23071
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
* Add support for parsing and booting FIT payloads.
* Build fit loader code from depthcharge.
* Fix coding style.
* Add Kconfig option to add compiletime support for FIT.
* Add support for initrd.
* Add default compat strings
* Apply optional devicetree fixups using dt_apply_fixups
Starting at this point the CBFS payload/ can be either SELF or FIT.
Tested on Cavium SoC: Parses and loads a Linux kernel 4.16.3.
Tested on Cavium SoC: Parses and loads a Linux kernel 4.15.0.
Tested on Cavium SoC: Parses and loads a Linux kernel 4.1.52.
Change-Id: I0f27b92a5e074966f893399eb401eb97d784850d
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25019
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
|
|
* Add documentation for CN81XX SoC
* Add documentation for CN81XX EVB SFF mainboard
* Add documentation for BDK
* Add documentation for BOOTROM and BOOTBLOCK behaviour
* Alphabetically sort vendors
Change-Id: Ibfcd42788e31f684baed658dc3c4dfe1b8e4f354
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/27150
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
|
|
Import from https://chromium.googlesource.com/chromiumos/platform/depthcharge
Coding style and coreboot integration will be done in a separate commit.
Change-Id: Iee56db328d7eeffb0eaf829841243b0b9195c199
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25739
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
|
|
Set the payload argument in selfload, as other (non self) payloads, are
going to set a different argument.
Change-Id: I994f604fc4501e0e3b00165819f796b1b8275d8c
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25861
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Due to schematic, we need to correct USB OC pin configuration.
- OC0 for Type-C Port 1
- OC1 for Type-C Port 0
- OC2 for Type-A Port
- OC3 to NC
BUG=NONE
BRANCH=poppy
TEST=emerge-nautilus coreboot
Change-Id: Ic71baef646926cc6aadcc5dda7cb14f00e8d3687
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/27099
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
This change adds ACPI properties for SYTS7817 device.
BUG=b:110013532
Change-Id: Ifdec4efce169c066f212a393df21089d43d8e4d6
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27044
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
This creates a fleex variant for octopus. Nothing is set in the variant
files here; everything is picked up from baseboard.
BUG=b:110085182
TEST=None
Change-Id: Ia8b8bb757f67bea997b7f43489c38cac62f7682d
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/27105
Reviewed-by: Jett Rink <jettrink@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The endian conversion function be32toh() is defined in
src/include/endian.h, however this file is not used for cbfstool
compilation. Currently the one provided by the host is used and if the
host does not provide this endian.h file, the build will fail.
However, we do have endian conversion functions in commonlib/endian.h
which is available for cbfstool compilation.
Switch from be32toh() to read_be32() in order to avoid relying on a
host provided include file.
We use functions from commonlib/endian.h already in cbfstool.
Change-Id: I106274cf9c69e1849f848920d96a61188f895b36
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/27116
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
