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2014-12-17edid: Change static variables to auto variables.Hung-Te Lin
To support parsing multiple EDID blobs, the static "decode results" flags should be changed to auto variables inside decode_edid. This is done by packaging static variables into a structure inside decode_edid. We also revised some functions (manufacturer_name, do_checksum) to avoid accessing global variables directly. Extension (and detail block) parsing may need to access and return all parsed context so we pass the whole structure to it. BRANCH=none BUG=none TEST=emerge-nyan coreboot chromeos-bootimage # See EDID parsed correctly on Nyan. Original-Change-Id: Ieca93d446bacf655c145dffdfa6cc6f5dc87ac26 Original-Signed-off-by: Hung-Te Lin <hungte@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/195372 Original-Reviewed-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit ed45909df24c05a0cb8b2ff662fdd2d7a39012f0) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I17cdfa770181a6eaac9d1050d340c8e052572b4a Reviewed-on: http://review.coreboot.org/7834 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-17southbridge/sis: Spelling/comment fixesMartin Roth
Change-Id: I6a0f5406fb3bc3e8aa3a1111b1d702f530c9329b Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/7733 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-12-17elog: Use the RTC driver interface instead of reading CMOS directly.Gabe Black
Use the RTC driver interface to find the timestamp for events instead of reading the CMOS based RTC directly on x86 or punting on ARM. This makes timestamps available on both architectures, assuming an RTC driver is available. BUG=None TEST=Built and booted on nyan_big and link and verified that the timestamps in the event log were accurate. BRANCH=nyan Original-Change-Id: Id45da53bc7ddfac8dd0978e7f2a3b8bc2c7ea753 Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/197798 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 493b05e06dd461532c9366fb09025efb3568a975) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I8481adde86d836b5f0b019c815bada6d232a4186 Reviewed-on: http://review.coreboot.org/7833 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-17elog: Isolate some x86-ismsDavid Hendricks
This attempts to isolate/fix some x86-isms: - Translate flash offset to memory-mapped address only on x86. - Guard ACPI-dependent line of code - Use a Kconfig variable for SPI bus when probing the flash rather than assuming the bus is always on bus 0. - Zero-out timestamp on non-x86 until we have a better abstraction. (note: this is based off of some of Gabe's earlier work) BUG=none BRANCH=none TEST=needs testing Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: I887576d8bcabe374d8684aa5588f738b36170ef7 Original-Reviewed-on: https://chromium-review.googlesource.com/191203 Original-Commit-Queue: David Hendricks <dhendrix@chromium.org> Original-Tested-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 1fc7a75f8c072098e017104788418aeed0705e93) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ida4b211cf21ecdde9745d4dbef6a63ffb9fbba8d Reviewed-on: http://review.coreboot.org/7832 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-17elog: Do not attempt to init SPIDavid Hendricks
This severs a dependency the eventlog code has on initializing chipset/SoC SPI controller. Currently elog_init() calls spi_init() as a catch-all. This worked for x86 since the SPI controller is only used for one thing on existing platforms. As we add eventlogging support to non-x86 platforms we need to consider the more generalized case where the assumptions about how SPI works on x86 are no longer valid. BUG=none BRANCH=none Signed-off-by: David Hendricks <dhendrix@chromium.org> TEST=built and booted on Link, Beltino and Rambi. See below for "mosys eventlog list" output on Link showing boot and suspend/resume events (including lid close/open) added successfully. localhost ~ # mosys eventlog list 0 | 2014-04-14 13:52:44 | Log area cleared | 4096 1 | 2014-04-14 13:52:44 | System boot | 50 2 | 2014-04-14 13:52:44 | EC Event | Power Button 3 | 2014-04-14 13:52:44 | SUS Power Fail 4 | 2014-04-14 13:52:44 | System Reset 5 | 2014-04-14 13:52:44 | ACPI Wake | S5 6 | 2014-04-14 13:53:25 | ACPI Enter | S3 7 | 2014-04-14 13:53:35 | ACPI Wake | S3 8 | 2014-04-14 13:53:35 | Wake Source | RTC Alarm | 0 9 | 2014-04-14 13:53:49 | ACPI Enter | S3 10 | 2014-04-14 13:54:00 | EC Event | Lid Open 11 | 2014-04-14 13:54:00 | ACPI Wake | S3 12 | 2014-04-14 13:54:00 | Wake Source | GPIO | 15 Original-Change-Id: I26e25c0a856f7b8db5ab6b8e7e1acae291d2eadc Original-Reviewed-on: https://chromium-review.googlesource.com/194526 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Commit-Queue: David Hendricks <dhendrix@chromium.org> Original-Tested-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 2971d20b6ebdd9803b05ccbbaeefe1bde1a21af4) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ia5f2913fd8e4fee6e741e6d1e39d32bb86525cb3 Reviewed-on: http://review.coreboot.org/7831 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-17tegra124: change PLLD VCO calculation algorithmKen Chang
The current algo sets dc shift clock divider to 5 and PLLD DIVP to 0, this is causing VCO out of the characterized range for some panels. This CL changes the dc shift clock divider to 1 and calculates a proper DIVP to have the VCO inside the characterized range, i.e., 500MHz ~ 1000MHz. BRANCH=none BUG=none TEST=Verify on below panels the pixel clock frequencies are correct. 1. AUO B133XTN01.3 (69.5 MHz) pixelclk(MHz), pll_d(MHz), m/n/p without: 69.5 695 12/695/0 with: 69.5 139 3/139/2 2. AUO B140HTT01.0 (141 MHz) pixelclk(MHz), pll_d(MHz), m/n/p without: VCO (1410000000) out of range. Cannot support. with: 141 282 2/94/1 3. LG LP140WH8 (76.32 MHz) pixelclk(MHz), pll_d(MHz), m/n/p without: 76.32 763.2 5/381/0 with: 76.3125 152.625 8/407/2 4. N116BGE-EA2 (76.42 MHz) pixelclk(MHz), pll_d(MHz), m/n/p without: 76.40 764 3/191/0 with: 76.375 152.75 12/611/2 Original-Change-Id: Id4b3a4865acde37a97d7346ec88406f5237304eb Original-Signed-off-by: Ken Chang <kenc@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/195534 Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org> (cherry picked from commit 1b56566786aa86c14f691fa3858b878f27b6b4de) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ia9de93420e60323f143a42db842febdd3706fe44 Reviewed-on: http://review.coreboot.org/7773 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2014-12-16spi: Add support for Winbond W25Q32DWDavid Hendricks
Similar to the W25Q64DW, the W25Q32DW has basically the same attributes as the earlier W25Q32 parts but with a different value in the MSB of the ID. BUG=none BRANCH=none TEST=tested on nyan, now SPI flash commands actually work. Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: I697768a443c98515d893f9cf8f8b4258ae0f159d Original-Reviewed-on: https://chromium-review.googlesource.com/191205 Original-Tested-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: Gabe Black <gabeblack@chromium.org> Original-Commit-Queue: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 35f03f4f4f21c470d172ce7cce257517b959346d) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I73606737835e4f8ea00d2c331ca37957e4abd953 Reviewed-on: http://review.coreboot.org/7755 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2014-12-16spi: Make idcode debug print more usefulDavid Hendricks
The old print simply said "Got idcode". This makes it actually display what it got. BUG=none BRANCH=none TEST=tested on nyan Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: I8f1c8fde6e4ac00b12e74f925b7bcff83d1f69f3 Original-Reviewed-on: https://chromium-review.googlesource.com/191204 Original-Tested-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: Gabe Black <gabeblack@chromium.org> Original-Commit-Queue: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 5f13789be77d038d3c1602037afe29a0351f72ee) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I65d0d51c17b3bda62351532aac1756b630433ea3 Reviewed-on: http://review.coreboot.org/7754 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-12-16blaze: Change samsung RAMCODE to samsung-2GB-204/samsung-4GB-204Neil Chen
hynix-2GB-204MHz/hynix-4GB-204MHz are not workable with Samsung RAMCODE. To replace them by samsung-2GB-204/samsung-4GB-204 for bring up purpose. BRANCH=none BUG=chrome-os-partner:27682 TEST=emerge-nyan_blaze coreboot builds OK; flash to blaze board and boot to kernel successfully with all the RAMCODE Original-Change-Id: I7c2a96e84e6988dd739a9621ff93edc01703306a Original-Signed-off-by: Neil Chen <neilc@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/195396 Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org> Original-Reviewed-by: Katie Roberts-Hoffman <katierh@chromium.org> (cherry picked from commit dc028c408be58f036fe125abc2e49e2c0cde0aa8) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ieeb0250e42fb48c6089bc8dc95550c9b1694d7f8 Reviewed-on: http://review.coreboot.org/7772 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2014-12-16tegra124: Allow "best" PLLD parameters for unmatched pixel clock.Hung-Te Lin
The pixel clock for some panel (ex: CMN N116BGE-EA2: 76420000) cannot be matched by our PLLD params finding algorithm, after VCO/CF limitations are applied. To support these panels, we want to allow "best matched" params. BRANCH=nyan BUG=none TEST=emerge-nyan_big coreboot chromeos-bootimage; emerge-nyan coreboot chromeos-bootimage; # Successfully brings up display on Nyan_Big EVT2 and Nyan Norrin. Original-Change-Id: If8143c2062abd2f843c07698ea55cab47bf1e41a Original-Signed-off-by: Hung-Te Lin <hungte@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/195327 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> (cherry picked from commit 8aa66e659e3c60296f05e59b4343496a850ea019) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I623db44de35fecee5539e4d72f93f28b5fa0b59c Reviewed-on: http://review.coreboot.org/7771 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2014-12-16tegra124: Always enable DC when attaching SOR.Hung-Te Lin
We found that without enabling DC in tegra_dc_sor_enable_dc, kernel would have problem showing the text console before graphics interface is initialized, for example "chromeos factory install shim (text only)" or the "splash screen". BRANCH=none BUG=chrome-os-partner:28082 TEST=emerge-nyan coreboot chromeos-bootimage Boots factory install shim and see text console. Original-Change-Id: I6fce963ceddd125dd52789d2ec843cc2ee05f1f5 Original-Signed-off-by: Hung-Te Lin <hungte@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/195388 (cherry picked from commit 375a86be9b23650cd96e46b07c7a0b5c10970797) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ib75e3ffac9b216c7486845cb8459dd8952d51fe6 Reviewed-on: http://review.coreboot.org/7770 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2014-12-16nyan*: debug: Add sor registers dump functionJimmy Zhang
Dump all SOR registers for debug purpose. By default, this function is not being built in. BRANCH=none BUG=chrome-os-partner:27413 TEST=build nyan and nyan_big. Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Change-Id: I7f44709b8572b9eac33c2193b92a65bf2b22aa76 Original-Reviewed-on: https://chromium-review.googlesource.com/194738 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Commit-Queue: Tom Warren <twarren@nvidia.com> Original-Tested-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org> (cherry picked from commit d08c0f7c5e8ac094987b09fae96e8133ed9c08c5) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I1341bbbd0ea6277e5a1b286d6f088f2961070416 Reviewed-on: http://review.coreboot.org/7769 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2014-12-16tegra124: clock: Enforce PLL constraints for VCO and CFJulius Werner
This patch adds some documentation to the additional PLL divisor constraints on the intermediary VCO and CF values that we just found out about. PLLC divisors for some oscillators had to be adjusted accordingly. It also adds a new clock_get_pll_input_khz() function to replace clock_get_osc_khz() in cases where you want to factor in the built-in predivider for 38.4 and 48 MHz oscillators. BUG=None TEST=Still boots. Original-Change-Id: Ib6e026dbab9fcc50d6d81a884774ad07c7b0dbc3 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/194474 Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org> (cherry picked from commit 3f1f565baf100edcd486055e4317c675c882396f) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I091f42bf952a4b58ef2c30586baa5bf7496fa599 Reviewed-on: http://review.coreboot.org/7768 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2014-12-16nyan*: Set SOR_NV_PDISP_SOR_DP_SPARE0 registerJimmy Zhang
This register needs to be set properly during display init. BRANCH=none BUG=chrome-os-partner:27413 TEST=build nyan and nyan_big. nyan display works fine. nyan_big display works as well. However, the mode setting needs to be based on either devicetree or EDID. Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Change-Id: I93c69d8042a3f3c19f4e24801423b73246e37031 Original-Reviewed-on: https://chromium-review.googlesource.com/194739 Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org> Original-Commit-Queue: Hung-Te Lin <hungte@chromium.org> Original-Tested-by: Hung-Te Lin <hungte@chromium.org> (cherry picked from commit ee9a3c472c5621edebefcc8882582c6fc01255e2) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ie642a008eaf6c4ab68ede1dde98ff4268f51fc9c Reviewed-on: http://review.coreboot.org/7767 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2014-12-16nyan*: merge a couple of sor setting difference from kernel driverJimmy Zhang
BRANCH=none BUG=chrome-os-partner:27413 TEST=build nyan and nyan_big. nyan display works fine. nyan_big display still does't work until all related patches are built in. (CL:194739) Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Change-Id: Ic5d977f695be127693f1ecc3ba52d478f524d20f Original-Reviewed-on: https://chromium-review.googlesource.com/194737 Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org> Original-Commit-Queue: Hung-Te Lin <hungte@chromium.org> Original-Tested-by: Hung-Te Lin <hungte@chromium.org> (cherry picked from commit ef3208d8ff3c3dcfaeda9c0146bf1ae920682dea) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ide1cd28ecc0ae1cd4d8603a52975592daee4bce8 Reviewed-on: http://review.coreboot.org/7766 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2014-12-16nyan*: Apply sor fix from kernel dc driverJimmy Zhang
Correct SOR attaching sequence. https://chromium-review.googlesource.com/190300 BRANCH=none BUG=chrome-os-partner:27413 TEST=build nyan and nyan_big. nyan display works fine. nyan_big display still doesn't work until all related patches are built in. (CL:194737 and CL:194739) Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Change-Id: I8aaf65db90e5e45bd9097c9d38b231bd7d41d997 Original-Reviewed-on: https://chromium-review.googlesource.com/194403 Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org> Original-Commit-Queue: Hung-Te Lin <hungte@chromium.org> Original-Tested-by: Hung-Te Lin <hungte@chromium.org> (cherry picked from commit fea9d288b98dcc6fc32dc93212fa7c4185603646) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I6646816809e29c63de65caa7e7146cd3d02902cf Reviewed-on: http://review.coreboot.org/7765 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2014-12-16tegra124: Initialize display panel by EDID.Hung-Te Lin
Tegra124 family products may want to use many different display panels with various timing settings. To support them, we should initialize display panel by EDID instead of hard-coded values. BUG=none TEST=emerge-nyan coreboot chromeos-bootimage BRANCH=none Original-Change-Id: Ib125a7f9cb1e6c8cf2d79e0baab525acfd1b7a6e Original-Signed-off-by: Hung-Te Lin <hungte@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/192730 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 43ecd473419aa0fbdd22487416b0b6cfea6a20d1) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I6af47db113035e9440e663a769318776c7b6b70b Reviewed-on: http://review.coreboot.org/7764 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2014-12-16edid: remove float usePatrick Georgi
First, we don't want floats in our code base. Second, the calculation of the aspect ratio was wacky, using a value guaranteed to be 0 for aspect ratio calculation. While at it, define the aspect_* fields to be in tenths, to provide some additional resolution. They were like that already but we now also commit to that. Change-Id: I5511adf4bf76cdd6a69240491372f220ef1aa687 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/7803 Reviewed-by: Marc Jones <marc.jones@se-eng.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins)
2014-12-16Drop SC520 and related boardsStefan Reinauer
There is no Cache As Ram for these boards, let's get rid of them. Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Change-Id: Ia70befc59708c360ad02ed7e3a49d3b0f95dc707 Reviewed-on: http://review.coreboot.org/7119 Reviewed-by: Marc Jones <marc.jones@se-eng.com> Tested-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-16Drop obsolete SuperIOs used by GX1 systems onlyStefan Reinauer
Drop two SuperIOs that were only used by GX1 systems, and are not used anymore. * winbond/w83977f * nsc/pc87351 Change-Id: I8a8eacb0f862b5d08ccfd87f8db503b0ab3c5700 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/7118 Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-12-16Drop GX1, CS5330 and related boardsStefan Reinauer
There is no Cache As Ram for these boards, let's get rid of them. Change-Id: Ib41f8cd64fc9a440838aea86076d6514aacb301c Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/7117 Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-12-16CBMEM console: Fix boards with BROKEN_CAR_MIGRATEKyösti Mälkki
There is no need to call cbmemc_reinit() exclusively in romstage, that is done as part of the CAR migration of cbmem_recovery(). CBMEM console for romstage remains disabled for boards flagged with BROKEN_CAR_MIGRATE, but with this change it is possible to have it for ramstage. Change-Id: I48c4afcd847d0d5f8864d23c0786935341e3f752 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7592 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <gaumless@gmail.com>
2014-12-16Intel FSP: Move to DYNAMIC_CBMEMKyösti Mälkki
Flag the boards with BROKEN_CAR_MIGRATE, as testing for EARLY_CBMEM_INIT is not enough to disable CBMEM console for romstage on these platforms. To have CBMEM early in ramstage, define get_top_of_ram() on sandy/ivy. Change-Id: Ieefc12099a0e043eb1a7e14bdc7c6e3d209b3d8f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7468 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Martin Roth <gaumless@gmail.com>
2014-12-16amd/agesa/f*/Lib/amdlib.c: Integer overflow in loop constructEdward O'Callaghan
As is the case in commit: 3312ed7 amd/agesa/f1?/Lib/amdlib.c: Integer overflow in loop construct The semantics of this loop relies on an integer overflow in Index >=0 that implies a return value of (UINT8)-1 which around wraps to 0xFF, or VOLT_UNSUPPORTED. Also fix an infinite loop. Change-Id: Iced3eff3ae7b8935db3bdd6147372cf3b540883c Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7676 Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-12-16southbridge/amd/pi/avalon/pci_devs.h: Correct define `EHCI3_DEV`Paul Menzel
It appears the decimal value was used instead of the hexadecimal value. Apply commit 59919ad1 (southbridge/amd/agesa/hudson: Correct incorrect #define) to AMD Avalon, whose `pci_devs.h` was copied from AMD Hudson. The incorrect define was introduced in commit 2093c4f7 (AMD/agesa: Add functions for AMD PCI IRQ routing). Change-Id: I7ccc060e8fa032080375259c3b11d39e2deb8e9e Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/7800 Tested-by: build bot (Jenkins) Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2014-12-16inteltool: Start adding Bay TrailMartin Roth
- Add silvermont (Bay Trail core) MSRs - these are shared with rangeley/avoton. - Add GPIO values and GPIO muxing information. - Add Bay Trail to the PM list. Still to do: - Northbridge functionality (RCBA, Memory timings, etc.) - Add Graphics registers Change-Id: I9fe0c0f1efe5f4344aeb3bad3f13037555109060 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/7711 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-16i2c: Replace the i2c API.Gabe Black
The new API is in use in depthcharge and is based around the "i2c_transfer" function instead of i2c_read and i2c_write. The new function takes an array of i2c_seg structures which represent each portion of the transfer after a start bit and before the stop bit. If there's more than one segment, they're seperated by repeated starts. Some wrapper functions have also been added which make certain common operations easy. These include reading or writing a byte from a register or reading or writing a blob of raw data. The i2c device drivers generally use these wrappers but can call the i2c_transfer function directly if the need something different. The tegra i2c driver was very similar to the one in depthcharge and was simple to convert. The Exynos 5250 and 5420 drivers were ported from depthcharge and replace the ones in coreboot. The Exynos 5420 driver was ported from the high speed portion of the one in coreboot and was straightforward to port back. The low speed portion and the Exynos 5250 drivers had been transplanted from U-Boot and were replaced with the depthcharge implementation. BUG=None TEST=Built and booted on nyan with and without EFS. Built and booted on, pit and daisy. BRANCH=None Original-Change-Id: I1e98c3fa2560be25444ab3d0394bb214b9d56e93 Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/193561 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Tested-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 00c423fb2c06c69d580ee3ec0a3892ebf164a5fe) This cherry-pick required additional changes to the following: src/cpu/allwinner/a10/twi.c src/drivers/xpowers/axp209/axp209.c Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I691959c66308eeeec219b1bec463b8b365a246d7 Reviewed-on: http://review.coreboot.org/7751 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-12-15x86: Set BOOT_MEDIA_SPI_BUSDavid Hendricks
BOOT_MEDIA_SPI_BUS is a Kconfig variable used on some ARM-based platforms to set up CBFS media. It turns out it can also be helpful for setting up the eventlog which is intended to reside on the same SPI flash as CBFS. Setting it for x86 will allow us to remove an assumption about which SPI bus is used for this flash device. Long term this can go away as we come up with a better abstraction for the eventlog's backing store. This is only intended to help us get from here to there. BUG=none BRANCH=none TEST=built and booted on Link Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: I1d84dc28592fbece33a70167be59e83bca9cd7bc Original-Reviewed-on: https://chromium-review.googlesource.com/191202 Original-Tested-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: Gabe Black <gabeblack@chromium.org> Original-Commit-Queue: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 200aa7c5b1b1f4c74412893cf7231a12e2702463) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: If988bcff5244ec6a82580203471b25fac49c45ef Reviewed-on: http://review.coreboot.org/7752 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2014-12-15elog: Probe for SPI flash on bus indicated by Kconfig variableDavid Hendricks
This replaces a hard-coded bus number of 0 with a Kconfig variable, CONFIG_BOOT_MEDIA_SPI_BUS. This removes an assumption made for x86 where this value is always 0 and makes it easy to add support for other platforms where the bus number for the backing SPI flash is more arbitrary. BUG=none BRANCH=none TEST=tested on Nyan (bus=4) and Link (bus=0) Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: I1e878a1628af7f4ccc2f39a70b2190192767e536 Original-Reviewed-on: https://chromium-review.googlesource.com/194854 Original-Tested-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: Gabe Black <gabeblack@chromium.org> Original-Commit-Queue: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 371c6c14d8d4b98004eebce7049a88a219682bc4) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ie105b4654e028098f2137c96e4309b8d85f096df Reviewed-on: http://review.coreboot.org/7753 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-15arm: Add support for a preram_cbmem_console symbol.Gabe Black
This symbol is set using a config variable which can be set to something appropriate by the SOC. If it isn't, the symbol is set to 0 which should be caught by checks in the cbmem console itself. BUG=None TEST=Built for nyan with a cbmem buffer location set. Built for peach_pit without a location set. BRANCH=None Original-Change-Id: I92cd65bb6767a67637faf1dd3cdbe03e433724a9 Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/193165 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 4f38c073bfe469a753e168391787fdd7bc5c34d9) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I979037fe8cda885cc516d79f3151ca1fc77adca3 Reviewed-on: http://review.coreboot.org/7746 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-15arm: Fix minor mistake in cache maintenance assemblyJulius Werner
Turns out that when you clear 28 bits starting with bit 3, you leave bit 31 standing. Ooops... This shouldn't really matter since that bit is reserved/SBZ in CLIDR anyway, but it's still nice to fix it. This whole thing should really be an AND for clarity anyway in my opinion. Bug found in upstream NetBSD (who would've thought...). BUG=None TEST=Still boots. Change-Id: Ic826e82d58fd1ce984971afea3dfa9296f746d9f Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/193300 Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit d270c0ec18b74b272451c456cbf07e99d95896cb) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/7745 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-15armv7: provide compiler options for rmodulesAaron Durbin
In order to build rmodules for armv7 boards, the default compiler options need to be set so the assembler sources can correclty compile. For now assume rmodules for arm devices use the ramstage compiler options. BUG=chrome-os-partner:27094 BRANCH=None TEST=Built vboot as rmodule for nyan. Original-Change-Id: I8d12a2a57944b187cbdff2f22176de5b4de87a54 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/190926 (cherry picked from commit cd091ae8ced30e6e2543f36bdb5c14518e7879c3) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I24706f7d72a53f71abd2770f0d12de8c6ed31f63 Reviewed-on: http://review.coreboot.org/7744 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-15tegra124: set MOT bit for I2C-over-AUXKen Chang
According to DP version 1.2a, The MOT (Middle-of-Transaction) bit must be set when the I2C transaction does not stop with the current AUX transaction. Thus the correct steps for an I2C read shall be: 1. I2C command write with MOT set to 1 2. I2C command read to the same address with MOT set to 0 BUG=chrome-os-partner:27679 TEST=EDID data read from LP140WH8 panel is correct while it's a repeated pattern of the first 16 bytes without this CL BRANCH=none Original-Change-Id: I0526beffb8852fbbe0eb5bb80e370261617a59b8 Original-Signed-off-by: Ken Chang <kenc@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/194915 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org> (cherry picked from commit 466ab0e00744f79ae3720474140d95e5f0828de9) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ic8ad38b4b08989dd7178d59151e1e276b8a58439 Reviewed-on: http://review.coreboot.org/7763 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-15tegra124: Setup clock PLLD by approximating display panel pixel clock.Hung-Te Lin
PLLD, the clock for display, was previously hard-coded to 306MHz. To support more different panels, we should calcualte PLLD by panel pixel clock configuration. Note existing pixel clock configurations for nyan* boards won't work (they used to rely on hard-coded approximated values) so the device trees are also modified. BRANCH=none BUG=chrome-os-partner:25933 TEST=emerge-nyan_big coreboot chromeos-bootimage See panel correctly initialized and got DEV screen. Original-Change-Id: I8d592f0cc044e7c4e4803c45955642e791210ad3 Original-Signed-off-by: Hung-Te Lin <hungte@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/193565 (cherry picked from commit 4f9b793633ebb2d104b0544e3b72fa0d105951c4) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ib2cabbad60af010e872505e888eab485ba8c2916 Reviewed-on: http://review.coreboot.org/7762 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-15tegra124: Release DMA channel at end of transactionDavid Hendricks
This adds a missing dma_release() at the end of DMA transfers. It probably doesn't matter since we don't do many DMA transfers, though I wouldn't want to hit some corner case with EFS and eventlog. BUG=none BRANCH=none TEST=tested on nyan Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: I79b30455babe75a13aac827caac88bf7053ec9e4 Original-Reviewed-on: https://chromium-review.googlesource.com/194479 Original-Tested-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: Gabe Black <gabeblack@chromium.org> Original-Commit-Queue: David Hendricks <dhendrix@chromium.org> (cherry picked from commit dc7dc1d25bd88873b4c1198a6f3723d27c914ddc) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I8c5da4e104328fd8bce71942e6eda458a37bfe06 Reviewed-on: http://review.coreboot.org/7761 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-15tegra124: Use correct mask for APB bus widthDavid Hendricks
It worked earlier since the APB and AHB bus widths occupy the same bits in their respective registers. BUG=none BRANCH=none TEST=tested on Nyan Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: I9b18c648c60dcc4ad62ca1f514d253f8cccaeee7 Original-Reviewed-on: https://chromium-review.googlesource.com/194478 Original-Tested-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: Gabe Black <gabeblack@chromium.org> Original-Commit-Queue: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 1d912302e9dcc9c6ba69e15434bb1841e1196208) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I2ea7ac83d3501876df52018aed467ec33074817e Reviewed-on: http://review.coreboot.org/7760 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-15nyan*: pinmux: fix PWM1/2 conflictsTom Warren
GPIO_PU4/PH1 and _PU5/PH2 were set to use the same PWM1/2 SFIO. Even though no problems were caused by this, correct it here so we get a conflict-free pinmux map. BUG=chrome-os-partner:27091 BRANCH=none TEST=Built and booted on Nyan, ran TegraShell "pinmux check" and saw no conflicts. Original-Change-Id: Ib16341aa0c92b9a078d7f3254d4151e9592f40b0 Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/194582 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit e06a5a62d381f803dd6574787795a51ce1f1fe74) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I055359dc80c0c878ba5f5faac17884a5506a826c Reviewed-on: http://review.coreboot.org/7759 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-15tegra124: set safe values for href_to_sync and vref_to_syncJimmy Zhang
href_to_sync and vref_to_sync are chip specific settings. Currently they are set to 1/2 of hfront_porch and vfront_porch respectively. However, to support EDID (CL192730), per David Ung, the safe values for both are 1 (the same settings as in kernel). BUG=none BRANCH=none TEST=built and booted on nyan. Original-Change-Id: Ifb8898e720a160ba044e2b526de2a4d17bc63672 Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/193504 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org> Original-Commit-Queue: Hung-Te Lin <hungte@chromium.org> Original-Tested-by: Hung-Te Lin <hungte@chromium.org> (cherry picked from commit a7128a533ba6083ddfeeca3ba0828962cc2c8ab6) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I6954a5b49c798ebdffb20e3ebc9099cd17591b79 Reviewed-on: http://review.coreboot.org/7758 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-15nyan: Enable the cbmem console on nyan and allocate space for it in SRAM.Gabe Black
This change takes about 8K of space away from the cbfs cache and repurposes it for the cbmem console buffer. This is a little more than twice the space we currently need for the bootblock and ROM stage to give us some room to grow and for extra debug output if needed. BUG=None TEST=Built and booted on nyan. Checked the cbmem output. BRANCH=None Original-Change-Id: I6543bf5efddcf2377528a273f846b8090cd8be55 Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/193169 Original-Reviewed-by: Gabe Black <gabeblack@chromium.org> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 32e9ea6f9ecaa9b5441c91acab96514222f3af2c) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ia9e5cc7a4b561bd89137cdc8b594584b272d9fab Reviewed-on: http://review.coreboot.org/7757 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-15nyans: prepare for vboot verification of ramstageAaron Durbin
Set the appropriate config options and make the appropriate calls to perform vboot verification. The flashmap offset as well as the TPM information needs to be properly set. Lastly, call into vboot_verify_firmware() to perform the vboot verification when it is enabled. BUG=chrome-os-partner:27094 BRANCH=None TEST=Built vboot verification on nyan. Original-Change-Id: I6113badd6143008ceb2b80f0ec0832e1addd03d7 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/190928 Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org> (cherry picked from commit 8c6c48c7823738bf9b029a467b077d2ee20d04e5) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I2a442b1b0fff55e737df2e96740c05c1726502d5 Reviewed-on: http://review.coreboot.org/7743 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-15blaze: Change RAMCODE 0010 to hynix-2GB-792MHzNeil Chen
RAM module for RAMCODE 0010 (K4B4G1646Q) does not work with hynix-2GB-204MHz configuration. We need to replace it by hynix-2GB-792MHz. Also updated hynix-2GB-792MHz configuration from Nyan board folder. This commit is only for bring up stage. Once finish dram stress test, will update it again. BRANCH=none BUG=chrome-os-partner:27682 TEST=emerge-nyan_blaze coreboot builds OK; flash to blaze board and boot to kernel successfully Original-Change-Id: Idfc503c944ac6120c92a4cf329f3fbe63b2c2a1c Original-Signed-off-by: Neil Chen <neilc@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/193737 Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org> (cherry picked from commit 91f21aa0cf9251b825e42d946d8cd41849c57447) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I6293fa638c5b2577e502ba34a3cc6e6d5b7f2fdb Reviewed-on: http://review.coreboot.org/7742 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-15nyan*: Fix unexpected symbol (CR) when converting DOS-formatted BCT config.Neil Chen
There are some unexpected symbol at the end of each line in the generated .inc file when the config file is in DOS format (CR+LF). Modify cfg2inc to support DOS format cfg file by removing carriage return symbols from the end of each line. BUG=chrome-os-partner:27614 TEST=sudo cfg2inc.sh XXX.cfg # make a expected inc file BRANCH=nyan Signed-off-by: Neil Chen <neilc@nvidia.com> Original-Change-Id: I68b0f4b3805fcb5a6b633653c95afbafcb880a93 Original-Reviewed-on: https://chromium-review.googlesource.com/192697 Original-Tested-by: Neil Chen <neilc@nvidia.com> Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org> Original-Commit-Queue: Neil Chen <neilc@nvidia.com> (cherry picked from commit 38e90ab0d9110d3ede39c70e27961b833813a7d4) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I30737600fa8ac12a45ad0fbc6086a624993794e7 Reviewed-on: http://review.coreboot.org/7741 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2014-12-15uart8250mem: Add wrapper for MMIO register accessKyösti Mälkki
For some UART hardware registers are 32 bits wide, so we will need base_port + reg << 2 instead. Prepare for that change and unification of MMIO between ARM and x86. Change-Id: I5fa2c2f7ee4872499a01754c1ba872a8addf499c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7793 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-12-15blaze: set 8 default BCT as hynix-2GB-204MHzNeil Chen
To set the 8 different BCT as hynix-2GB-204 first. Once the corresponding BCT release from AE, change it. BRANCH=none BUG=None TEST=emerge-nyan_blaze coreboot builds OK Signed-off-by: Neil Chen <neilc@nvidia.com> Original-Change-Id: Ia42a4a5b85c561421ab8ae9aaf21c46a3c0a3513 Original-Reviewed-on: https://chromium-review.googlesource.com/191682 Original-Tested-by: Neil Chen <neilc@nvidia.com> Original-Reviewed-by: Artiste Hsu <chhsu@nvidia.com> Original-Reviewed-by: Katie Roberts-Hoffman <katierh@chromium.org> Original-Commit-Queue: Neil Chen <neilc@nvidia.com> (cherry picked from commit 27792db4a90ae00e066bb0b88968cf5f187edb1d) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ia648c8bdbbbc82bbc8508bead6ab24d8d0aa3fb2 Reviewed-on: http://review.coreboot.org/7740 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-15nyan*: Reduce the EC SPI bus frequency to 3 MHz.Gabe Black
The EC doesn't seem to be able to handle its bus running at 4 MHz or higher. To avoid it not being able to keep up, we reduce the frequency of that bus on all nyan derivatives to 3 MHz. Because PLLP can't be divided that low, we switch the clock source to CLKM. BUG=chrome-os-partner:22849 TEST=Built and booted on nyan. BRANCH=None Original-Change-Id: I8f31b41098d64634427b4686f5333012f643fada Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/193349 Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> Original-Reviewed-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit c215c50a5bb982b0e671c951e2fe8df06db85db2) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ia60513d118aed8881927e9d52f170e27655ea8e7 Reviewed-on: http://review.coreboot.org/7739 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-15tegra124: More improvements to the clock initialization macros.Gabe Black
Consolidate the register setting clrsetbits_le32 call to simplify the macros. Add a check for bits of the divisor being dropped. The clock source registers will throw away bits that aren't supported, so we can check for divisor overflow by checking for dropped bits. BUG=None TEST=Purposefully tried to set a clock to a rate which overflows its divisor. Verified that the check triggered. Booted on nyan. Verified the TPM i2c bus frequency was still correct. BRANCH=None Original-Change-Id: I3b1b6ba57f6b7729f303d15a16b685a48751d41f Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/193348 Original-Reviewed-by: Gabe Black <gabeblack@chromium.org> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 9cd79dd974d8a3c31398f8fbd62750b194867891) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Id4d8ecfeff52737cdd68999028b37cbdedb0d116 Reviewed-on: http://review.coreboot.org/7738 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-15tegra: spi: Read the command1 register to ensure the write to it completes.Gabe Black
To ensure that the command1 write which sets the "go" bit completes before other reads to the device. Otherwise, there's a race condition where those register values might still have their values from the last transfer. With different SPI clock frequencies, that could lead to spi_delay being told there were negative bytes still to send. Its expected delay would wrap to a negative value, that was passed to udelay, and the system would sit there for 4 seconds not doing anything. BUG=None TEST=Built and booted on nyan. Set the SPI bus frequency to a value which was causing the 4+ second delay and verified that it no longer happened. BRANCH=None Original-Change-Id: I8b4090efc69f34d0413e3f63c59c1825dd151cec Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/193347 Original-Reviewed-by: Gabe Black <gabeblack@chromium.org> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit d7ea9febdf2c5942f81607ee6ded786c9a8954bb) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I095bfc745eda37b8e666475ceb41684152f3709a Reviewed-on: http://review.coreboot.org/7737 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-15tegra124: A couple clock fixes.Gabe Black
This fixes two problems with the clock configuration on tegra124. First, the macro which set up the i2c clocks tried to account for the fact that the i2c divisor's lsb represents 1.0 where it normally represents 0.5 by multiplying the target frequency by 2. That doesn't work, unfortunately, because the divisor is actually n + 1, and what n + 1 means depends on where the one's place is in the divisor. Also, when calculating the divisor, the standard C division operator uses truncation to deal any remainder which tends to make the divisor smaller. That has the effect of making the output frequency higher than what was requested. Since it's usually safer to undershoot a frequency than overshoot it, this change makes those divisions round up instead. Finally, the hand tuned temporary UART clock configuration was adjusted so that it still ends up with the same divisor. Without that, very early output from the bootblock is garbled, specifically the coreboot welcome banner, build timestamp, etc. BUG=chrome-os-partner:27220 TEST=Built and booted on nyan. Used a logic analyzer to verify that the TPM i2c bus ran at 400KHz instead of 660KHz, and that the divisor was the expected value. Measured boot time with and without EFS and verified that there was no change. Spot checked the output for errors and verified that none of the bootblock output was garbled. BRANCH=None Had to add the stdlib.h from 89ed6c that hadn't been merged correctly. Original-Change-Id: I7e948c361ed4bf58c608627d32f2e3424faea1fb Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/193362 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 164f7010a47d3bbdbc8bb572106140ae186f3807) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I317b66eda929c0e5a5832adca267b8b54c6aae34 Reviewed-on: http://review.coreboot.org/7736 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-15tegra124: Add tegra_dc_i2c_aux_read to allow reading EDID.Hung-Te Lin
To read EDID, we need to access I2C via DP AUX channel. BRANCH=none BUG=chrome-os-partner:25933 TEST=emerge-nyan coreboot chromeos-bootimage Original-Change-Id: I2666b5d46843485b79265a537f19bd8eab5e1a26 Original-Signed-off-by: Hung-Te Lin <hungte@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/188858 Original-Reviewed-by: Gabe Black <gabeblack@chromium.org> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 8f8e98ff5038b57f89332aee75573095c3933dd2) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I5b1b6ab2940c8265483059fd94a2c4db2a41144a Reviewed-on: http://review.coreboot.org/7735 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-15tegra124: Skip display init when vboot says we don't need it.Gabe Black
If EFS is enabled and vboot didn't tell us it's going to use the display, we can skip initializing it and save some boot time. BUG=chrome-os-partner:27094 TEST=Built and booted on nyan without EFS in recovery mode and normal mode. Built and booted on nyan with EFS in recovery mode and normal mode. Verified that in normal mode with EFS the display initialization was skipped and boot time was essentially the same as when display initialization was simply commented out. BRANCH=None Original-Change-Id: I1e2842b57a38061f40514407c8fab1e38b75be80 Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/192544 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit a672d18c3570e6991a1c1c0089697112a4cd71d0) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I95e8bd7a447876174305f755cc632365ed6f5a30 Reviewed-on: http://review.coreboot.org/7734 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-15buildgcc: Fix msys2 crossgcc build failScott Duplichan
A leading double slash can result when $DESTDIR/$TARGETDIR is expanded in the libelf portion of buildgcc. The leading double slash causes buildgcc to fail when run from Windows/Msys2. Replace $DESTDIR/$TARGETDIR with $DESTDIR$TARGETDIR to avoid the problem. Change-Id: Ide2bae41c07c1566f80104c3a2e2acab53de0d17 Signed-off-by: Scott Duplichan <scott@notabs.org> Reviewed-on: http://review.coreboot.org/7788 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-12-15southbridge/amd/agesa/hudson: Correct incorrect #defineDave Frodin
It appears the decimal value was used instead of the hex value. Change-Id: I04acde9e5b2a9e08ed01b0564c3d561b0385a392 Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/7799 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-12-14.gitignore: add the doxygen directory.Martin Roth
The doxygen directory is created by running 'make doxygen' - this results in a huge number of new files that swamps graphical git tools. Since this directory is a product of a build, it should be safe to ignore. Change-Id: I871dd2a36433d4dd46b231ebc7398e85d0278f27 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/7798 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-13AMD AGESA boards: Prevent passing duplicate obj names to arScott Duplichan
For some of the boards using AMD processors, the Agesa Makefile.inc is processed twice, causing the list of obj files passed to the ar command to be added twice. This does not break the build, but does make the ar command line unnecessarily long. Change-Id: I02a7e6fc617e337ca2e2dceeff3d4db9995bfe16 Signed-off-by: Scott Duplichan <scott@notabs.org> Reviewed-on: http://review.coreboot.org/7787 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-12-13AMD model fxx powernow_acpi.c: Fix incorrect loop countScott Duplichan
powernow_acpi.c array TDP has 20 entries, yet the loop that reads it processes 21 entries. This causes a gcc 4.9.2 build failure. Limit processing to 20 entries. Change-Id: Ice173b276293184386cd8943a3213f3154f86458 Signed-off-by: Scott Duplichan <scott@notabs.org> Reviewed-on: http://review.coreboot.org/7791 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-12Makefile: Tone down some clang warnings, some are unproductiveEdward O'Callaghan
Too many false positives, not useful enough for us at the moment at the cost of not having the whole tree build without warnings as errors. Change-Id: I9f9910b7f66ebf3a82d42e7732e413ba27dbbbe7 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7778 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2014-12-12vendorcode/amd/pi/00730F01/Lib/amdlib.c: Remove optimize attributeBruce Griffith
Remove '__attribute__((optimize("Os")))' as it is unlikely to be necessary as it is not used in other families that have the same code and only hides deeper issues. Change-Id: Ica890812ebc2fb659b9c3e46b40cf3f6534b3cf2 Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/7689 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-11abuild: Don't print "Using payload ..." message in quiet modeAlexandru Gagniuc
It's not useful in quiet mode, and is very distracting. Change-Id: I59dc8caa22b66980560d5afb76eae801efaa29ad Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/124 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-10AMD 00730F01: Topology changes required by KaveriPI v1.1.0.7 updateBruce Griffith
The updated KaveriPI binary, upgrading to v1.1.0.7, requires changes to define the PSP device (PCI 0:08.0) and the IOMMU device (PCI 0:00.2). In the new AGESA binary, the IOMMU device is enabled and must be disabled in devicetree.cb and agesawrapper_amdinitenv() to maintain the same level of functionality. Change-Id: I3f47e0bd5a75729ec1e4b7b11885d0622c474342 Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/7727 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-10crossgcc: clean up aarch64 target integrationPatrick Georgi
We already have aarch64 targets. Extend the "all" target. Change-Id: I74d9bf5123695318c15b73c89f170f3ebb20aa80 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/7729 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2014-12-10vendorcode/amd/agesa/f16kb/*/PcieComplexDataKB.c: Implicit truncationEdward O'Callaghan
Clang complains: "implicit truncation from 'int' to bitfield changes value from -1 to 15" -1 is define in 'c11std 6.3.1.3p2' as: [Signed and unsigned integers] Otherwise, if the new type is unsigned, the value is converted by repeatedly adding or subtracting one more than the maximum value that can be represented in the new type until the value is in the range of the new type.60) FOOTNOTE.60 The rules describe arithmetic on the mathem... This is "0xFF" on Mullins and "0xF" in this case. Clang seems to complain about this two's complement in a bitfield as being truncated. As the bitfield is 4 bits wide, (a maximum of 15 decimal), we set the field as '0x0F'. Ideally this field /should/ be set to 'UINT8_MAX' however we still have silly truncation warnings. Change-Id: Ib7476d453ffd932bb911e638117cf9f56f71f269 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7719 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2014-12-10northbridge/amd/gx2,lx: Treat MSR constant as unsigned longEdward O'Callaghan
Clang complains that a signed shift result (0x210000000) requires 35 bits to represent, but 'int' only has 32 bits. However, we write the high bits separately and so this is a spurious warning. Change-Id: I3e1c57334077feb50004d7b39abff4bd84ca095b Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7673 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2014-12-10abuild: update output so multithreaded is decipherableMartin Roth
- add a 'quiet' mode that only prints important messages - add vendor/mainboard to all strings printed With quiet on, multithreaded looks like this: skipping google/storm because we're missing compilers for (arm armv4 armv7) iwill/dk8_htx built successfully. (took 5s) jetway/j7f2 built successfully. (took 6s) iwill/dk8x built successfully. (took 8s) iwill/dk8s2 built successfully. (took 8s) jetway/j7f4k1g5d built successfully. (took 10s) With quiet off, single threaded now looks like this: Building intel/emeraldlake2 Creating config file for intel/emeraldlake2... intel/emeraldlake2 (blobs, ccache) intel/emeraldlake2 config created. Compiling intel/emeraldlake2 image... intel/emeraldlake2 built successfully. (took 5s) And quiet off multithreaded looks like this: Building iwill/dk8_htx Creating config file for iwill/dk8_htx... iwill/dk8_htx (blobs, ccache) intel/mohonpeak config created. Compiling intel/mohonpeak image on 1 cpu... intel/minnowmax config created. --- snip --- intel/mtarvon built successfully. (took 4s) Building iwill/dk8s2 Creating config file for iwill/dk8s2... iwill/dk8s2 (blobs, ccache) intel/mohonpeak built successfully. (took 5s) Building iwill/dk8x Change-Id: Ib7b9a625d77bb8e0663afc00d7133e415866ecec Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/7716 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-09spi: Eliminate the spi_cs_activate and spi_cs_deactivate functions.Gabe Black
They were only used internal to the SPI drivers and, according to the comment next to their prototypes, were for when the SPI controller doesn't control the chip select line directly and needs some help. BUG=None TEST=Built for link, falco, and rambi. Built and booted on peach_pit and nyan. BRANCH=None Original-Change-Id: If4622819a4437490797d305786e2436e2e70c42b Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/192048 Original-Reviewed-by: Gabe Black <gabeblack@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 1e2deecd9d8c6fd690c54f24e902cc7d2bab0521) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ida08cbc2be5ad09b929ca16e483c36c49ac12627 Reviewed-on: http://review.coreboot.org/7708 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2014-12-09spi: Remove the spi_set_speed and spi_cs_is_valid functions.Gabe Black
spi_set_speed was never implemented, and spi_cs_is_valid was only implemented as a stub and never called. BUG=None TEST=Built for rambi, falco, and peach_pit. BRANCH=None Original-Change-Id: If30c2339f5e0360a5099eb540fab73fb23582905 Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/192045 Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 98c1f6014c512e75e989df36b48622a7b56d0582) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Iebdb2704ee81aee432c83ab182246d31ef52a6b6 Reviewed-on: http://review.coreboot.org/7707 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2014-12-09spi: Factor EC protocol details out of the SPI drivers.Gabe Black
The SPI drivers for tegra and exynos5420 have code in them which waits for a frame header and leaves filler data out. The SPI driver shouldn't have support for frame headers directly. If a device uses them, it should support them itself. That makes the SPI drivers simpler and easier to write. When moving the frame handling logic into the EC support code, EC communication continued to work on tegra but no longer worked on exynos5420. That suggested the SPI driver on the 5420 wasn't working correctly, so I replaced that with the implementation in depthcharge. Unfortunately that implementation doesn't support waiting for a frame header for the EC, so these changes are combined into one. BUG=None TEST=Built and booted on pit. Built and booted on nyan. In both cases, verified that there were no error messages from the SPI drivers or the EC code. BRANCH=None Original-Change-Id: I62a68820c632f154acece94f54276ddcd1442c09 Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/191192 Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 4fcfed280ad70f14a013d5353aa0bee0af540630) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Id8824523abc7afcbc214845901628833e135d142 Reviewed-on: http://review.coreboot.org/7706 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <gaumless@gmail.com>
2014-12-09vboot: allow for non-memory-mapped VBOOT regionsAaron Durbin
Depending on the platform the underlying regions vboot requires may not be accessible through a memory-mapped interface. Allow for non-memory-mapped regions by providing a region request abstraction. There is then only a few touch points in the code to provide compile-time decision making no how to obtain a region. For the vblocks a temporary area is allocated from cbmem. They are then read from the SPI into the temporarily buffer. BUG=chrome-os-partner:27094 BRANCH=None TEST=Built and booted a rambi with vboot verification. Original-Change-Id: I828a7c36387a8eb573c5a0dd020fe9abad03d902 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/190924 Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org> (cherry picked from commit aee0280bbfe110eae88aa297b433c1038c6fe8a3) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ia020d1eebad753da950342656cd11b84e9a85376 Reviewed-on: http://review.coreboot.org/7709 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-12-09x86: provide symmetry between arm for cache_sync_instructions()Aaron Durbin
The arm architecture currently exports cache_sync_instructions() in <arch/cache.h>. In order for rmodule loading to work on arm architectures the cache_sync_instructions() needs to be called to sequence the instruction cache. To avoid sprinkling #ifdefs around just add an empty cache_sync_instructions() definition. BUG=chrome-os-partner:27094 BRANCH=None TEST=Built and booted nyan and rambi. Original-Change-Id: I1a969757fffe0ca92754a0d953ba3630810556e3 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/191551 Original-Reviewed-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit fda20947b928ee761d5ed15e414636af419970a6) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I3e8ca12e1d82ccedf1ff9851ae3c5c80cda2dd5f Reviewed-on: http://review.coreboot.org/7710 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-12-09aarch64: Add aarch64-elf toolchain to crossgcc MakefileMarcelo Povoa
BUG=None BRANCH=none TEST=Build crosgcc for aarch64-elf Signed-off-by: Marcelo Povoa <marcelogp@chromium.org> Original-Change-Id: Ifc886b6bd125552855ad1cf49ee7c1b7a0350895 Original-Reviewed-on: https://chromium-review.googlesource.com/186413 Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Original-Tested-by: Marcelo Póvoa <marcelogp@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Commit-Queue: Marcelo Póvoa <marcelogp@chromium.org> (cherry picked from commit 9959047c82c96108f4bdedad1db0219fcdc85378) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I5e781443bb11a7db3420bb8cfc447de8494b1d24 Reviewed-on: http://review.coreboot.org/7661 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-12-09aarch64: Fix 64-bit pointer related castsMarcelo Povoa
BUG=None BRANCH=none TEST=Ran image in foundation model Signed-off-by: Marcelo Povoa <marcelogp@chromium.org> Original-Change-Id: I80a92673c163b3df312ce632eb52e5bb1e7ab1db Original-Reviewed-on: https://chromium-review.googlesource.com/185273 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Marcelo Póvoa <marcelogp@chromium.org> Original-Tested-by: Marcelo Póvoa <marcelogp@chromium.org> (cherry picked from commit e2f19689acb973aedee6e4b324ed27b64f2d47de) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Icc3fc82779d18963f0fe8d5fb655f96027164a18 Reviewed-on: http://review.coreboot.org/7660 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2014-12-09aarch64: Add ELF supportMarcelo Povoa
BUG=None BRANCH=none TEST=Build coreboot Signed-off-by: Marcelo Povoa <marcelogp@chromium.org> Original-Change-Id: I38684794fdf5bd95a32f157128434a13f5e2a2d5 Original-Reviewed-on: https://chromium-review.googlesource.com/185271 Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Tested-by: Marcelo Póvoa <marcelogp@chromium.org> Original-Commit-Queue: Marcelo Póvoa <marcelogp@chromium.org> (cherry picked from commit 67b74d3dc98a773c3d82b141af178b13e9bb6c06) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Id82a31dc94bb181f2d24eddcbfbfb6d6cdc99643 Reviewed-on: http://review.coreboot.org/7659 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-12-09ARM: API to Map Physical Address to Wipe Memory above 4GBDaisuke Nojiri
TEST=Booted nyan in normal and recovery mode. Created a map, filled it with some chars, then verified they can be read from the pointer returned. BUG=chrome-os-partner:25587 BRANCH=None Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Change-Id: Id1f1be4f6d2d5734d87bf3452d4806d0fe3fda88 Original-Reviewed-on: https://chromium-review.googlesource.com/188894 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> Original-Tested-by: Daisuke Nojiri <dnojiri@chromium.org> (cherry picked from commit 7fda3885f51c8d383585a80e99ab3df9c789d872) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I6255d11396c87f40b0ae12ceab0fd152f2478529 Reviewed-on: http://review.coreboot.org/7658 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-12-09libpayload: ARM: Keep track of the CPSR when exceptions happen.Gabe Black
Use the SPSR to extract and inject CPSR values when an exception happens and pass that information to exception hooks. The register structure GDB expects when using its remote protocol has a spot for the CPSR. BUG=None TEST=Built and booted on link, nyan. BRANCH=None Original-Change-Id: Id950fb09d72fb0f81e4eef2489c0849ce5dd8aca Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/180253 Original-Reviewed-by: Gabe Black <gabeblack@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 8e7014f24a580f84c91fa7b0369dfa922918adcc) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I49357fb6a65edeff7a9a48d54254308a6b0efdb7 Reviewed-on: http://review.coreboot.org/7657 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-12-09libpayload: Make it possible to install callbacks for particular exceptions.Gabe Black
To support a GDB stub, it will be necessary to trap various exceptions which will be used to implement breakpoints, single stepping, etc. BUG=None TEST=Built and booted on Link with hooks installed and saw that they triggered when exceptions occurred. Built and booted on nyan. BRANCH=None Original-Change-Id: Iab659365864a3055159a50b8f6e5c44290d3ba2b Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/179602 Original-Reviewed-by: Gabe Black <gabeblack@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 8db0897b1ddad600e247cb4df147c757a8187626) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I5e7f724b99988cd259909dd3bd01166fa52317ec Reviewed-on: http://review.coreboot.org/7656 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-12-09libpayload: arm: Pass the coreboot table location to the payload.Gabe Black
To find the coreboot tables, the payload has historically searched for their signature in a predefined region of memory. This is a little clumsy on x86, but it works because you can assume certain regions are RAM. Also, there are areas which are set aside for the firmware by convention. On x86 there's a forwarding entry which goes in one of those fairly small conventional areas and which points to the CBMEM area at the end of memory. On ARM there aren't areas like that, so we've left out the forwarding entry and gone directly to CBMEM. RAM may not start at the beginning of the address space or go to its end, and that means there isn't really anywhere fixed you can put the coreboot tables. That's meant that libpayload has to be configured on a per board basis to know where to look for CBMEM. Now that we have boards that don't have fixed amounts of memory, the location of the end of RAM isn't fixed even on a per board level which means even that workaround will no longer cut it. This change makes coreboot pass the location of the coreboot tables to libpayload using r0, the first argument register. That means we'll be able to find them no matter where CBMEM is, and we can get rid of the per board search ranges. We can extend this mechanism to x86 as well, but there may be more complications and it's less necessary there. It would be a good thing to do eventually though. BUG=None TEST=Built and booted on nyan. Changed the size of memory and saw that the payload could still find the coreboot tables where before it couldn't. Built for pit, snow, and big. BRANCH=None Original-Change-Id: I7218afd999da1662b0db8172fd8125670ceac471 Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/185572 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit ca88f39c21158b59abe3001f986207a292359cf5) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Iab14e9502b6ce7a55f0a72e190fa582f89f11a1e Reviewed-on: http://review.coreboot.org/7655 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-12-09spi/macronix: Add support for MX25L3239EDave Frodin
Also update comment for the MX25L3236D part. Change-Id: Ifaeeb71e7672a8db55bbb66e6ce7316e2893478d Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/7631 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-12-09gizmosphere/gizmo2: Add the gizmo2 IRQ routingDave Frodin
Change-Id: Ic00790eedd48a2b78620fea329464701cd294cbb Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/7723 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-09gizmosphere/gizmo2: Changes to make it gizmo2Dave Frodin
The preceding patch copied gizmo2 from the amd/olivehill board. This commit includes the changes required to make the code reflect the gizmo2 hardware: - Update the vendor Kconfig to add gizmo2 - Update the mainboard Kconfig - Update devicetree - Add support in for the soldered down DDR3 - Update the CODEC verb data - Update the graphics connector settings - Adjust the temperature thresholds for the fan What's missing: - Interrupt routing tables Gizmo2 can boot DOS and Ubuntu 14.10. Change-Id: I3d7202957c082974689f2a8c04d8cd33dbdc1a89 Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/7722 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-09UCB RISCV: Switch to DYNAMIC_CBMEMKyösti Mälkki
Change-Id: Iaaf68fd19f7b9a5b6849fffde3a9c68cb7862367 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7619 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-12-09mainboard/siemens/sitemp_g1p1/mainboard.c: Fix implicit conversionEdward O'Callaghan
Clang warns of an implicit conversion from 'double' to 'int' e.g. changes value from '26.67' to '26'. Thus take the floor() of the array and not change orginal behaviour. Change-Id: Ifcc7bbfe8d627451b82053f53a885f315e2550ec Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7725 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2014-12-09southbridge/amd/sr5650/sr5650.c: Fix bitwise logic and mask in loopEdward O'Callaghan
Correct mask to select bits 4-6 inclusively as per comment and use bitwise operations while working with bits. Be sure to write back out the data on the retrain. See: commit cab9efb2 southbridge/amd/rsXY0/cmn.c: Fix bitwise logic and mask in loop Change-Id: I95d1799514157b7849f3e473837aaf2fd9bd59b9 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7692 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins)
2014-12-09mainboard/{iwill,amd/serenget_*}: Fix ptr discards const qualifierEdward O'Callaghan
Change-Id: I22e55eb2b7fe06c416e5e4fd322045bc7031ed63 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7693 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2014-12-09utils: Remove references to tracker from manpagesMartin Roth
abuild, inteltool, and superiotool's manpages still referenced reporting bugs to tracker.coreboot.org. Remove that url and change the message to point to the coreboot mailing list instead. Change-Id: I7a85bc2b36ccdb7f3798a39a08345c1a02a67e65 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/7712 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-09fsp platfoms: add prototype & consolidate main entry-pointMartin Roth
- In '-ffreestanding' main() is just as any other function and so it needs a type-signature. Fixes a clang warning. - Bay Trail and Rangeley have the updated romstage.c with the code moved into the chipset, put the prototype in romstage.c. - The sandybridge code has not been updated, so the prototype for it goes into chipset_fsp_util.h, next to the prototype for romstage_main_continue. - Correct the return value of baytrail main() from void * to void and remove the unnecessary asmlinkage tag. I'm surprised that this didn't generate a warning... Change-Id: I85ac0797d1e55d2b7ffdca039a52820d7827e704 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/7724 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-12-09mainboard/gizmosphere/gizmo2: Start adding new mainboardDave Frodin
This is a direct copy of the amd/olivehill mainboard which will be the starting point for this port. Change-Id: I6a643f7ac35d89e21df0ffdf4e61a2da46e19b82 Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/7721 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-12-08drivers/intel/fsp/fsp_util.c: Remove attribute,optimize("O0")Edward O'Callaghan
This is not actually required. Tested on 'minnow max' hardware as well as compared the asm of the optimized and non-optimized. Thanks Martin! Change-Id: I06e71876c3a3a15101013623797c2ebbf449756d Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Found-by: Clang Reviewed-on: http://review.coreboot.org/7694 Reviewed-by: Martin Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-12-08northbridge/amd: Add the audio device to the PCI devicesDave Frodin
Change-Id: I826f98e450c9a614930a5e83c7c6bfb4ccdc5984 Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/7630 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2014-12-08mainboard: Fix correct index variable usage in double loop constructEdward O'Callaghan
Change-Id: I672c532c3f7179038d41f269bba434b8703e254b Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Found-by: Clang Reviewed-on: http://review.coreboot.org/7718 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-12-08edid: fill reserved bits fields in cb_framebufferPatrick Georgi
If it's a 4 byte format (as per documentation), there are some reserved bits, so let's mark them as such... Change-Id: I50f12cfff2c9bb9d082a5f3c3ac54c0d514d862b Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/7674 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-12-08mainboard/siemens/sitemp_g1p1/mainboard.c: Remove unicode in stringEdward O'Callaghan
Remove illegal character encoding in string literal. Change-Id: I3c8dc67363705a2160e8266d1cea78c0d34d076f Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7713 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-12-08vendorcode/amd/agesa/fam10: Build as a static libraryEdward O'Callaghan
Following the same reasoning as commit ee905a8 vendorcode/amd/agesa/fam15tn: Build as a static library Since AGESA is stage-independent, we can build it just once, and use the resulting static library in both rom and ram stages. Change-Id: I8fbb318daacf64a14a71022705eb040a01c34fa8 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7699 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-12-08vendorcode/amd/agesa/fam15: Build as a static libraryEdward O'Callaghan
Following the same reasoning as commit ee905a8 vendorcode/amd/agesa/fam15tn: Build as a static library Since AGESA is stage-independent, we can build it just once, and use the resulting static library in both rom and ram stages. Change-Id: I7798b689db3e582649eb4af4ccd1877bb1d49063 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7698 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-12-08intel/baytrail: Spelling fixesMartin Roth
Change-Id: Ideb58634a029d55746421ad1ea4b80811bca403c Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/7705 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-08intel/fsp_baytrail: Spelling fixesMartin Roth
Change-Id: Ica9e3a91718a7e490ff80e5029fc29650355eb47 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/7704 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-08samsung/exynos5420: Spelling FixesMartin Roth
Change-Id: I966645c83ae78943a7dbb9dc05af4fded6f4e5b5 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/7703 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-08intel/broadwell: Spelling fixesMartin Roth
Change-Id: I2f970c6970b4996fcefbde89332210f5a1afe836 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/7702 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-07vendorcode/amd/agesa/f1{5,5tn,6kb}: Silence empty loop warnEdward O'Callaghan
Add decorations to specify that empty loop is intended so. Change-Id: Ia3e40d341eca5e26da3832edc733cf1ccc96c136 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Found-by: Clang Reviewed-on: http://review.coreboot.org/7688 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-12-07mainboard/google/samus: Fix usage of GNU field designator extEdward O'Callaghan
Following the reasoning in, 8089f17 mainboard/lenovo/x230 Fix usage of GNU field designator extension In C99 we defined a syntax for this. GCC's old syntax was deprecated. Change-Id: Id3b16872f62660393d938d6f95977a4e3842d0d1 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7690 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-12-07southbridge/dmp/vortex86ex/southbridge.c: Silence bitwise op warnsEdward O'Callaghan
Silence some useless Clang warns in this case. Change-Id: I202a85f7dec52c65d80e2bc56f7d9e4eb3e61d48 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7696 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2014-12-07Kconfig: Remove ACPI_SSDTX_NUM.Vladimir Serbinenko
Its scope is limited to a single mainboard and is only to go through ifdef. Kill it and move the value to the code. Change-Id: I76a87e2790d57dee8f37b51e33d0689fffd3a59d Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7135 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-27 20:50:56 +0000