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2022-10-22soc/amd/morgana/mca: Update for morganaFred Reitberger
Update the MCA bank names for morgana per PPR #57396, rev 1.52 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: If0082bd5362bdead3f9dc693d1e338e8cda224f0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68683 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-22mb/google/brask/var/kuldax: Revise PsysPL2 to 150W for Pentium CPUDavid Wu
Pentium CPU will use 150W adaptor, this change revises PsysPL2 to 150W based on fw_config. BUG=b:253542746 TEST=Check CPU PsysPL2=150W in AP log with Pentium CPU. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I63b2a9d79454b20b60ba1317a8eebb3c10eff9d6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68665 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-10-22mb/google/brya: Enable SaGv for brask variantsDerek Huang
SaGv is enabled for all brya variants, so it should be harmless to enable it for brask variants to save some power. BUG=254374912 TEST=Build and boot to Chrome OS Signed-off-by: Derek Huang <derekhuang@google.com> Change-Id: Ib5d1e39b3f901606e2f1449e4ed40d53696562ed Reviewed-on: https://review.coreboot.org/c/coreboot/+/68646 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-10-22mb/google/skyrim/var/baseboard: Update gpio setting for touchscreen IRQFrank Wu
The touchscreen IRQ has been configured as LEVEL_LOW in skyrim projects. Therefore, update the gpio.c to be consistent with the configuration. BUG=b:253506651, b:251367588 BRANCH=None TEST=FW_NAME=frostflow emerge-skyrim coreboot Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: Iccfe5b01f10899c43151762e4730a05990afa602 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68638 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Chao Gui <chaogui@google.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2022-10-22payloads/edk2: Disable the CPU Timer Lib unless supportedSean Rhodes
For recent X86 CPUs, the 0x15 CPUID instruction will return Time Stamp Counter Frequence. For CPUs that do not support this instruction, EDK2 must include a different library which is the reason why this must be configured at build time. If this is enabled, and the CPU doesn't support 0x15, it will fail to boot. If is not enabled, and the CPU does support 0x15, it will still boot but without support for the leaf. Consequently, disabled it by default. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I4f0f43ce50c4f6f7eb03063fff34d015468f6daa Reviewed-on: https://review.coreboot.org/c/coreboot/+/65950 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-10-22payloads/edk2: Add the recipes to assemble UniversalPayloadSean Rhodes
Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Id6363c92f8155007e05c682694d7413fd4630b6d Reviewed-on: https://review.coreboot.org/c/coreboot/+/65932 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-10-22soc/intel/systemagent: Rewrite using new resource APIArthur Heymans
Working with resources in KB is tedious and the base_k / size_k variable naming was simply wrong in one case. Change-Id: Ic5df054e714d06c9003752ed49dc704554e7b904 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68406 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-22soc/intel/systemagent.c: Fix memory type reportingArthur Heymans
TOLUD stands for top of lower usable dram. Memory between cbmem_top and TOLUD, even if stolen for another device/purpose can still be marked WB cacheable. This will result in a cleaner MTRR setup. Change-Id: Ic3d6f589c60e44a3dce9122d206397cac968647f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68405 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-10-22mb/siemens/mc_ehl: Add FIVR config to devicetree for all variantsWerner Zeh
Add a config for FIVR in devicetree for both, mc_ehl1 and mc_ehl2 variants in order to provide the real delay value for the VCC supply rail. This delay is needed to enable proper switching between different VCC levels based on current system state. Change-Id: Ibccb8ea1b42ccd2ff0a37cbd9651528a2a55ebd6 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68666 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-22arch/x86/include/arch: fix assembly clobber for 64bitMatei Dibu
the "x86 PIC code ebx" workaround done previously by commit 689e31d18b0f ("Make cpuid functions usable when compiled with PIC") does not work for x86_64 (the upper dword of rbx is set to 0) the GCC bug that needed the workaround was fixed in version 5 (see GCC bug 54232) Change-Id: Iff1dd72c7423a3b385a000457bcd065cf7ed6b95 Signed-off-by: Matei Dibu <matdibu@protonmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66345 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-10-22mb/siemens/mc_apl*: Enable early PCI bridge before FSP-MAngel Pons
Apollo Lake seems to start with PCIe root ports unusable/uninitialized before FspMemoryInit() is called and FSP-M properly initializes these root ports. However, we need the root ports accessible before FspMemoryInit() in certain cases, such as emitting POST codes through a PCIe device. For the initialization to happen properly, certain register writes specified in Apollo Lake IAFW BIOS spec, vol. 2 (#559811), chapter 3.3.1 have to be done. BUG=none TEST=Boot on siemens/mc_apl2 with NC_FPGA_POST_CODE enabled and check that the POST codes are emitted before FspMemoryInit(). Change-Id: If782bfdd5f499dd47c085a0a16b4b15832bc040e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Signed-off-by: Jan Samek <jan.samek@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68223 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-22soc/intel/alderlake_n: Enable FIVR VCCST ICCMax ControlV Sowmya
Enable the VCCST ICCMax Control for the ADL-N display flicker issue. Please refer the Doc with ID 742988 for more details. BUG=b:248249033 TEST=Verified that the display flicker issue is fixed. Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: I10709ee8653563b397e8408e8e24ef8e656b02e5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68252 Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Baieswara Reddy Sagili <baieswara.reddy.sagili@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-10-22nb/intel/i945/raminit: Use 'bool' for do_resetElyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I692b86bba28853186185846f63dad1dcbfce1eea Reviewed-on: https://review.coreboot.org/c/coreboot/+/68217 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-22nb/intel/i945/raminit: Use 'bool' for clkcfg_bit7Elyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Ia87fbbeb9ecb57ee2f4879404cbae5403de9bfc7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68216 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-22smbios.h: Add High Bandwidth Memory Generation 3Elyes Haouas
Add HBM3 according to SMBIOS 3.6.0: https://web.archive.org/web/20221012222420/https://www.dmtf.org/sites/default/files/standards/documents/DSP0134_3.6.0.pdf Change-Id: Id8473e8c4b5006b53b5ff9de7825d15595f2a616 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65356 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-22nb/intel/i945/raminit: Use 'size_t' for banksize[]Elyes Haouas
Change-Id: I4fb845bb4145d47aea39d7e5493d854d00e289aa Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68213 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-22vc/amd/fsp: Get rid of last "sabrina" referenceMartin Roth
We still had a lingering reference to the old sabrina codename in the vendorcode directory. Searching through the code now, the only places the sabrina codename is seen is in the release notes, as is proper. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I41762880b45a85ce7cd4210b8ce623076d874c06 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68645 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-22soc/amd/*/i2c.h: Make definition more accurateFred Reitberger
Make GPIO_I2C_MASK macro more accurate by using the GPIO_I2Cx_SCL definitions instead of BIT(x). Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I13fc376552068a64768fe1cf9f1c09cca1768aed Reviewed-on: https://review.coreboot.org/c/coreboot/+/68682 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-22mb/google/nissa: Disable SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRYReka Norman
On nissa, the pre-x86 time is not part of the 1s firmware boot time target. Including the pre-x86 timestamps causes confusion since the boot time appears to be greater than 1s, so disable the Kconfig on nissa. We're not doing any analysis or optimisation of the pre-x86 time on nissa anyway, this work will start from MTL onwards. Also, the Kconfig is already disabled on the brya firmware branch, so this will result in the same behaviour as brya. Before: Total Time: 1,205,840 After: Total Time: 995,300 BUG=b:239769532 TEST=Boot nivviks, check "1st timestamp" is the first timestamp. Change-Id: I885071c9e0ff9c8fac9444b382567d38a19c3c15 Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68553 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-22mb/lenovo/*/mainboard.c: Clean up includesElyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I406f21c0c05e6af357e45e718422be94c6fd5408 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68017 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-10-22mb/google/kahlee: Fix audio ACPI inclusionMatt DeVillier
Not all kahlee variants use the RT5682 audio codec, so split the baseboard audio ACPI into two parts and only include the asl for the codec(s) actually needed for a given variant. TEST=build/boot aleena, liara variants and verify no ACPI present for RT5682 codec (which is not present on the boards). Change-Id: Icb7df4f8e51495ad3cb40113cd00810fd27dcd00 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68583 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-22vc/intel/fsp: Update ADL N FSP headers from v3301.00 to v3343.04Shaik Shahina
Update generated FSP headers for Alder Lake N from v3301.00 to v3343.04. Changes include: - FspsUpd.h: 1. Add PchFivrVccstIccMaxControl UPD BUG=b:254374913 BRANCH=None TEST=Build using "emerge-nissa intel-adlnfsp" and boot Nissa. Change-Id: I20b13d3dff2951e6ec3aa754c8954989a3b4e176 Signed-off-by: Shaik Shahina <shahina.shaik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68424 Reviewed-by: Reka Norman <rekanorman@google.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: V Sowmya <v.sowmya@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-21mb/google/skyrim: Enable genesyslogic gl9755 for frostflowFrank Wu
Enable DRIVERS_GENESYSLOGIC_GL9755 support for frostflow BUG=b:253506651, b:251367588 BRANCH=None TEST=FW_NAME=frostflow emerge-skyrim coreboot Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: I1db598c68687ed17fd9baa3567ab8fdd3e4fb6a8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68483 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-10-21soc/amd/*/smi.h: Use BIT() for clarityFred Reitberger
Use the BIT() macro for single-bit constants. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I490f0093d55813260fcdb7303a94accfa90e75e4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68548 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-10-21util/amdfwutil: Fix adding microcode binariesArthur Heymans
Change-Id: I726df4ff97688f4c48961e6e61672cef6c3b7aff Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68573 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-21soc/amd/*/uart: cleanup includesFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I59ab9c2eaa65d974d418123e87e9afe65b1168cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/68633 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-21mb/gigabyte/ga-h61m-series: Add GA-H61M-DS2Angel Pons
Built from a mixture of autoport output, other variants, schematics and expert guesswork. I don't have this board, but the code has been tested by someone else and boots successfully (first try) with TianoCore. It's reasonable to assume most things work, as this board is very similar to the already-supported variants. Change-Id: I3d8df483e5573f77782b7d18b1410b391bfe387d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61541 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-21arch/x86/include: Split msr access into separate fileMartin Roth
To allow testing of code that uses msr calls, separate the actual calls into a separate header file, This allows the tests to emulate the msr access without replacing the rest of the msr.h definitions. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I102709fec346f18040baf9f2ce6e6d7eb094682d Reviewed-on: https://review.coreboot.org/c/coreboot/+/67917 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-21MAINTAINERS: Remove Andrey Petrov from Apollo LakeSean Rhodes
Andrey doesn't seem to have interacted with APL or coreboot 2+ years, so remove him and mark Apollo Lake as orphaned. Add myself for Odd Fixes. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I6cb2f2da63dda3cb841786d53f89b583a9df9791 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68588 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-21mb/lenovo/t{410,60}/dock.h: Fix header guardsElyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I7b279cf2c69f62b47ef497edd372034f148fff03 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68020 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-21soc/mediatek: Unify PLL function namesRex-BC Chen
For consistency with the PLL function naming: - Rename edp_mux_set_sel() to mt_pll_edp_mux_set_sel(). - Rename mux_set_sel() to pll_mux_set_sel(). BUG=none TEST=build pass. BRANCH=corsola Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: Ifc7b14bf0db5a5461037e2fbf41756d1542ca945 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68622 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-21mb/google/corsola: Initialize MT6315 for MT8186TSen Chu
Initialize MT6315 for powering on big cores on MT8186T. BUG=b:249436110 TEST=build pass. BRANCH=corsola Signed-off-by: Sen Chu <sen.chu@mediatek.corp-partner.google.com> Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: Ib1d71d4f1689ba1e7ea5f798503ef11eff423fff Reviewed-on: https://review.coreboot.org/c/coreboot/+/68621 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-21soc/mediatek/mt8186: Add support for PMIC MT6315Sen Chu
On MT8186T, the big cores are powered on by MT6315 via PMIF. This patch adds the following changes. - Add MT6315 settings. - Configure PMIC PMIF for MT6315. BUG=b:249436110 TEST=build pass. BRANCH=corsola Signed-off-by: Sen Chu <sen.chu@mediatek.corp-partner.google.com> Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: Id01931e564b0b5002b8d6b9d13d4f32cdf0ae708 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68620 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-21soc/mediatek: Move SPMI interface configuration to SoC folderSen Chu
The SPMI interface configuration is SoC-dependent. - MT8192 and MT8195 are the same. - MT8186 does not need to implement this. - MT8188 is different from MT8195, and we will submit another patch to fix this. BUG=b:249436110 TEST=build pass. BRANCH=corsola Signed-off-by: Sen Chu <sen.chu@mediatek.corp-partner.google.com> Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I4cf508a0690995a7fe7b7316269d07cb7a799191 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68619 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-21soc/mediatek/mt8186: Add PMIF_SPMI_IOCFG_DEFAULT_SETTING Kconfig optionRex-BC Chen
For MT8186, PMIF_SPMI mode is the hardware default setting, so we don't need to configure PMIF SPMI IO pins. Add a config to control that. BUG=b:249436110 TEST=build pass. BRANCH=corsola Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I92b54e8379a5dec55ef95cbd72ce03abd3a4954b Reviewed-on: https://review.coreboot.org/c/coreboot/+/68578 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-21soc/mediatek/mt8186: Add PWRAP_WITH_PMIF_SPMI Kconfig optionRex-BC Chen
On MT8186, PMIC interface supports PWRAP and PMIF_SPMI while other MediaTek SoCs support PMIF_SPMI and PMIF_SPI. BUG=b:249436110 TEST=build pass. BRANCH=corsola Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I20efa6d84975d781972af9143c0c7e3a272653e0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68577 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-21soc/mediatek/mt8186: Add support for reading CPU IDRex-BC Chen
MT8186 has two slightly different versions: MT8186G and MT8186T (turbo version). Add get_cpu_id() to identify different CPUs. BUG=b:249436110 TEST=cpu id is correct. BRANCH=corsola Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I0612dd589e11853dbddc1d99526e9c9bf170acec Reviewed-on: https://review.coreboot.org/c/coreboot/+/68576 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-21mb/lenovo/s230u/mainboard.c: Replace comma with semicolonElyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I9e8ad533e939553a93e76f1dbb37fc98b53f06d6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67970 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-21arm64/armv8: Use 'enum cb_err'Elyes Haouas
Change-Id: Ic4ce44865544c94c39e8582780a7eca7876f5c38 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68370 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-10-21soc/amd/morgana/aoac: Remove to-do after reviewFred Reitberger
Reviewed files and values match morgana ppr #57396, rev 1.52 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I6772b21110f74a77eef285da3e1f313ec6326cc8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68580 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-21soc/amd/morgana/i2c: Remove to-do after reviewFred Reitberger
Reviewed files and values match morgana ppr #57396, rev 1.52 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I9d058b0f61b4784a1d83289e75705a6415405d0b Reviewed-on: https://review.coreboot.org/c/coreboot/+/68547 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-21soc/amd/morgana/include/soc/iomap.h: Remove to-do after reviewFred Reitberger
Reviewed file and values match morgana ppr #57396, rev 1.52 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I8f914432e0f55aa8050728e8cf41a3dee20990e8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68542 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-21mb/google/skyrim/port_descriptors: update DDI for MDN and ChausieJason Nien
Add two new types for MDN DDI descriptor BUG=b:228284940 TEST=Normal boot and S0i3 cycles Signed-off-by: Jason Nien <finaljason@gmail.com> Change-Id: I02793f032f9855dac202a5aca8666c26426d6cb2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66847 Reviewed-by: Bao Zheng <fishbaozi@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
2022-10-21nb/x4x/dq_dqs.c: Use 'enum cb_err'Elyes Haouas
Change-Id: I94dd6b1bb81bbc38ac5f89469b3ed7c83ca2a498 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68579 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-21nb/intel/x4x/raminit.c: Use 'enum cb_err'Elyes Haouas
Change-Id: I22d7e724e69b41c9fabdef785276dc428be2b400 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68558 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-21soc/intel/apollolake: Skip SMI lockdown on ApollolakeMatt DeVillier
Commit d9ef02ce (soc/intel/apollolake: Lock down Global SMI) breaks SMM/SMI on Apollolake (but not Geminilake), so guard it accordingly. TEST=build/boot google/reef, verify SMM/SMI/SMMSTORE functional. Change-Id: I00cbe046b61e6c342f7961670478d0ca8d365c2e Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68549 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-21util/lint: Fix linting outside of git reposMartin Roth
If the coreboot code is not in a git repository, the linters switch from using `git ls-files` to find. This requires some changes to prevent the linters from looking at the wrong files which are automatically excluded by git. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I81d138760c29a7c476280bb9d963f6be99c75d6d Reviewed-on: https://review.coreboot.org/c/coreboot/+/68475 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-21nb/intel/i945/rcven.c: Use read32p()Elyes Haouas
Tested on unsupported mainboard (945g-m4). Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I1935308cc50abd651b52d6290d66180905c6a521 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68087 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-10-20mb/google/brya: Create gladios ADL variantKevin Chiu
Create the gladios variant of the brask reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:239513596 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_gladios Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Change-Id: I3dc99d97d8e30d9641f56616222dd68e3a0d548d Reviewed-on: https://review.coreboot.org/c/coreboot/+/68569 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-20soc/amd/morgana/smi: Update smi definitions for morganaFred Reitberger
Update the SMI definitions for morgana per PPR #57396, rev 1.52 Remove references to dropped SMITYPE_XHC2_PME in xhci.c to fix compile errors. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I6a9f05bcc6a6e4c94114ccbd07628629bdfabcba Reviewed-on: https://review.coreboot.org/c/coreboot/+/68477 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-20Docs/releases: Finalize relnotes for the 4.18 releaseMartin Roth
The coreboot 4.18 release has been tagged, so the release notes can now be finalized. Updated with known issues. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I77676ddc42488e9635f1e6f995386490dca441c0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68467 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-10-20nb/intel/i945/i945.h: Drop useless guardElyes Haouas
i945.h file is not used to generate asl files. Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I93bf96f8a86a2652a88f3a129ec197048dd914a4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68215 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-20arch/x86/include: Split CPUID access into separate fileMartin Roth
To allow testing of code that uses CPUID calls, separate the actual calls into a separate header file, This allows the tests to emulate the cpuid access without replacing the rest of the cpu.h definitions. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ic5ee29f1fbb6304738f2eb7999cbcfdf8f7d4932 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67916 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-20soc/amd/morgana: Add TODOs for common code to KconfigMartin Roth
This allows us to see which of the common code blocks have been verified and which have not. Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Change-Id: Icb9eba5838013de75c408c28a4a7d3afacdf0674 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68555 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-20nb/intel/i945: Clean up includesElyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I0e5f102d75647c9c184cb7422af30c9196503882 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68211 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-20intel/i945: Use 'bool' for dual_channel and interleavedElyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I055847c9b08795683fe2e1dfd7fcde49901fc973 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67925 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-20drivers/tpm: Move TPM init to end of device init phaseMatt DeVillier
Boards which use an I2C TPM and do not use vboot will not have the I2C bus initialized/ready at the start of the device init phase. If TPM init is called before the bus, init will fail with I2C transfer timeouts and a significantly lengthened boot time. Resolves: https://ticket.coreboot.org/issues/429 TEST=build/boot google/reef w/o vboot, verify successful TPM init. Change-Id: Ic47e465db1c06d8b79a1f0a06906843149b6dacd Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68550 Reviewed-by: Alexandru Stan <amstan@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-10-20mb/google/(guybrush|skyrim): Use a variable for APCB filenameMartin Roth
We use the name of the APCB file repeatedly, so put it into a variable so that it's easier to update. Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Change-Id: I8684db2f7b2d68f0354e37bd8cdfc4f9cab44b8a Reviewed-on: https://review.coreboot.org/c/coreboot/+/67501 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-20mb/google/rex: Skip sending the MBP HOB to save boot timeWonkyu Kim
This change is to skip sending the MBP HOB since coreboot doesn't use it and also helps to reduce the boot time by ~40 ms. Boot time data Before: * 955:returning from FspSiliconInit 1,656,985 (274,416) After: * 955:returning from FspSiliconInit 1,593,036 (233,286) BUG=b:252410202 TEST=Verified that boot time is reduced by ~40 msec. Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: I0d4f66940529b8d38d9658c769feba8b5c9b715e Reviewed-on: https://review.coreboot.org/c/coreboot/+/68418 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-10-20soc/intel/meteorlake: Add support to skip the MBP HOBWonkyu Kim
This patch adds the support to enable/disable skipping MBP HOB from the devicetree based on mainboard requirement. Porting the feature from commit 2bc54e7c001c ("soc/intel/alderlake: Add support to skip the MBP HOB") TEST=Build and boot to verify that the right value has been passed to the FSP. Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: I360d33617b9d2626fce5600e861214b0747f57b4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68416 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-10-20soc/amd/*/uart: commonize UART code and MMIO device driverFelix Held
Now that the SoC-specific UART controller data and the common code part are cleanly separated, move the code to the common AMD UART support block folder. The code is identical to the UART code in Cezanne, Mendocino, Morgana and Picasso while Stoneyridge doesn't use the parts related to the MMIO device driver. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id9429dac44bc02147a839db89d06e8eded7f1af2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68561 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-20soc/amd: move set_uart_config prototype to common UART headerFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I97860292fd3cd0330fec40edb31089cd6608906b Reviewed-on: https://review.coreboot.org/c/coreboot/+/68560 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-20soc/amd: move all AOAC function prototypes to amdblocks/aoac.hFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3deae150cd1e20fff6507a0f0ba6a375fca430e5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68559 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-20soc/amd/stoneyridge/uart: introduce and use soc_get_uart_ctrlr_infoFelix Held
Introduce and use soc_get_uart_ctrlr_info to access the uart_info array to further decouple uart_info from the code as preparation to factor out most of the code to a common implementation. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I813483bc0421043dc67c523f0ea2016a16a29f60 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68538 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-20soc/amd/morgana/uart: introduce and use soc_get_uart_ctrlr_infoFelix Held
Introduce and use soc_get_uart_ctrlr_info to access the uart_info array to further decouple uart_info from the code as preparation to factor out most of the code to a common implementation. In order to slightly reduce the number of function calls, pass the size of and pointer to uart_info to get_uart_idx as a parameter instead of calling again soc_get_uart_ctrlr_info in get_uart_idx despite all callers already having the information form the soc_get_uart_ctrlr_info call. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I80278f1a098b389d78f8e9a9fb875c4e466dc5db Reviewed-on: https://review.coreboot.org/c/coreboot/+/68537 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-20soc/amd/mendocino/uart: introduce and use soc_get_uart_ctrlr_infoFelix Held
Introduce and use soc_get_uart_ctrlr_info to access the uart_info array to further decouple uart_info from the code as preparation to factor out most of the code to a common implementation. In order to slightly reduce the number of function calls, pass the size of and pointer to uart_info to get_uart_idx as a parameter instead of calling again soc_get_uart_ctrlr_info in get_uart_idx despite all callers already having the information form the soc_get_uart_ctrlr_info call. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8cfea274f4c9e908c11429199479aec037a00097 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68536 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-20soc/amd/cezanne/uart: introduce and use soc_get_uart_ctrlr_infoFelix Held
Introduce and use soc_get_uart_ctrlr_info to access the uart_info array to further decouple uart_info from the code as preparation to factor out most of the code to a common implementation. In order to slightly reduce the number of function calls, pass the size of and pointer to uart_info to get_uart_idx as a parameter instead of calling again soc_get_uart_ctrlr_info in get_uart_idx despite all callers already having the information form the soc_get_uart_ctrlr_info call. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iab1aec44c55570aa8085aeaf68ec69fe6de0f2ba Reviewed-on: https://review.coreboot.org/c/coreboot/+/68535 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-20soc/amd/picasso/uart: introduce and use soc_get_uart_ctrlr_infoFelix Held
Introduce and use soc_get_uart_ctrlr_info to access the uart_info array to further decouple uart_info from the code as preparation to factor out most of the code to a common implementation. In order to slightly reduce the number of function calls, pass the size of and pointer to uart_info to get_uart_idx as a parameter instead of calling again soc_get_uart_ctrlr_info in get_uart_idx despite all callers already having the information form the soc_get_uart_ctrlr_info call. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I474e47059eaebcf0b9b77f66ee993f1963ebee77 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68534 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-20soc/amd/stoneyridge: initialize GPIOs for serial consoleFelix Held
Initialize the two GPIOs of the SoC UART if it's used for serial console to be sure that the I/O mux is configured correctly without having to rely on the bootblock_mainboard_early_init call to do this. This brings Stoneyridge more in line with the other AMD SoCs. Since this code will be factored out to the common AMD SoC code in a follow-up patch, the function prototype is added to southbridge.h instead of creating a new uart.h header file. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id4aa6734e63dad204d22ce962b983cde6e3abd62 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68533 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-20soc/amd/*/uart: add missing soc/iomap.h includeFelix Held
soc/iomap.h provides the UART base address information used in the uart_info struct. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I7defd135dc888cfc7d6e1c106d72116425560576 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68532 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-20soc/amd/stoneyridge/uart: add and use uart_info arrayFelix Held
Introduce and use an array of soc_uart_ctrlr_info to align Stoneyridge with the other AMD SoCs in order to allow commonization of the AMD SoC UART code. Since the current Stoneyridge code doesn't provide or use UART MMIO device operations, only the base addresses of the UART controllers from this array are used for now. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie868cd3e2f77b0f7253c9f6d91dd3bbc3e4b6b0e Reviewed-on: https://review.coreboot.org/c/coreboot/+/68531 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-20soc/amd: introduce and use common soc_uart_ctrlr_info structFelix Held
The SoC's uart_info structs all use the same anonymous uart_info struct definition, so create a named struct for this in the common AMD SoC UART header and use it in the SoC code. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id183a3c838c6ad26e264c2a29f3c20b00f10d9be Reviewed-on: https://review.coreboot.org/c/coreboot/+/68530 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-20soc/amd/morgana/uart: separate data and codeFelix Held
The goal of this is to be able to move most of the code over to the common AMD blocks. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib893720911114d61ee6b3fbbf1a2a3594500bcfc Reviewed-on: https://review.coreboot.org/c/coreboot/+/68529 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-20soc/amd/mendocino/uart: separate data and codeFelix Held
The goal of this is to be able to move most of the code over to the common AMD blocks. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5077681b64dd68351340bd179838a174d8df1701 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68528 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-20soc/amd/cezanne/uart: separate data and codeFelix Held
The goal of this is to be able to move most of the code over to the common AMD blocks. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0e585370a0de56787340788acfecc7931820566d Reviewed-on: https://review.coreboot.org/c/coreboot/+/68527 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-20soc/amd/picasso/uart: separate data and codeFelix Held
The goal of this is to be able to move most of the code over to the common AMD blocks. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia496a4b29b25d4438ed8fc09bfe6f83e3fb768d9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68524 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
2022-10-20soc/qualcomm/sc7280: Remove NVMe initShelley Chen
We are required to boot with eMMC enabled in the BIOS to store modem calibration data. Thus, it doesn't make sense to enable NVMe at boot time since we will never boot from NVMe w/o eMMC. We may as well take the boot time reduction (~100ms) by eliminating NVMe initialization. BUG=b:185426670, b:254281839 BRANCH=None TEST=Boot after disabling NVMe and make sure that it still boots Note that we are able to see a little over 100ms in boot time savings with this change. Before: 40:device configuration 824,021 (102,701) After: 40:device configuration 717,402 (44) Cq-Depend: chromium:3964185 Change-Id: I94f614ba0369c073617949285c0781aef5c6263f Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68562 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-10-20mb/google/herobrine: Remove NVMe from device treeShelley Chen
We need to boot eMMC for modem calibration, there is not need for BIOS to initialize NVMe anymore as the kernel will do so. Removing the pci device from the device tree as a first step. BUG=b:185426670, b:254281839 BRANCH=None TEST=Boot after removing from the herobrine device tree. Change-Id: I802dd1361bc56a24ab3d65e6782bc611b7b75ee3 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68571 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-10-20mb/google/skyrim/var/frostflow: Update GPIO settingsFrank Wu
Configure GPIOs based on GPIO_20221014.xlsx of frostflow. BUG=b:253506651, b:251367588 BRANCH=None TEST=FW_NAME=frostflow emerge-skyrim coreboot Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: I02272801c85a7c30d24c834a840e026225956fb8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68481 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-10-20mb/google/skyrim/var/frostflow: Generate RAM IDs for new memory partsFrank Wu
Add new memory parts in the mem_parts_used.txt and generate the SPD ID for the parts. The memory parts being added are: DRAM Part Name ID to assign MT62F512M32D2DR-031 WT:B 0 (0000) H9JCNNNBK3MLYR-N6E 0 (0000) MT62F1G32D4DR-031 WT:B 1 (0001) H9JCNNNCP3MLYR-N6E 1 (0001) MT62F2G32D8DR-031 WT:B 2 (0010) H9JCNNNFA5MLYR-N6E 3 (0011) BUG=b:250470704, b:247683159 BRANCH=None TEST=FW_NAME=frostflow emerge-skyrim coreboot Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: I34584092c938539c91d65501ebe34b00212b34d4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68388 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-10-20spd/lp5: Add new memory configuration of H9JCNNNFA5MLYR-N6EFrank Wu
Add Hynix H9JCNNNFA5MLYR-N6E in the memory_parts.json and re-generate the SPD. BUG=b:250470704 BRANCH=None TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5 Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: I9926a5859cf060e0bfa903f47d8a98c8d6115579 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68154 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Chao Gui <chaogui@google.com>
2022-10-20Revert "drivers/intel/dptf: Add multiple fan support under dptf"Sumeet Pawnikar
This reverts commit 672bd9bee5c0045694ef20fe3e2f7a003bef0edd. Reason for revert: Gmeet resolution dropped. When system starts Gmeet video call, it uses the hardware accelerated encoder as per the expectation. But, as soon as another system connects to the call, the immediate fallback observed from hardware to software encoder. Due to this, Gmeet resolution dropped from 720p to 180p. Currently, this issue observed on AlderLake-N SoC based fanless platforms. This issue is not seen on fan based systems. BUG=b:246535768,b:235254828 BRANCH=None TEST=Built and tested on Alderlake-N systems. With this revert Gmeet resolution drop not observed. Change-Id: Idaeaeaed47be44166a7cba9a0a1fac50d2688e50 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68568 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Baieswara Reddy Sagili <baieswara.reddy.sagili@intel.com> Reviewed-by: V Sowmya <v.sowmya@intel.com>
2022-10-20mb/google/nissa/var/craask: Remove redundant ELAN TouchscreenTyler Wang
Remove redundant touchscreen "ELAN6915". BUG=b:254328657 TEST=emerge-nissa coreboot Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: I8f90b071b053858cf720de5ac2a71031fe623d70 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68497 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-20mb/google/nissa/var/craask: Remove SAR Proximity SensorVictor Ding
Craask does not have a SAR proximity sensor. BUG=b:253387689 TEST=Dump ACPI SSDT and verify SX9324 related entries are not present. Change-Id: Ia0e3eb6dba82594ca27040d6ab0197da6095f510 Signed-off-by: Victor Ding <victording@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68564 Reviewed-by: Reka Norman <rekanorman@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-20src/vendorcode: Add a README.md fileMartin Roth
This README.md file specifies the expectations and agreements implied by contributing code to the coreboot src/vendorcode directory. Licenses, structure, formatting and the like are all the responsibility of the contributors, however as the code is a part of the coreboot codebase, members of the coreboot community are allowed to modify the code to the extent deemed necessary. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ib7e2aedce9383158d03be342cb10ae18d85146ae Reviewed-on: https://review.coreboot.org/c/coreboot/+/67485 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-20mb/google/drallion/hda_verb: add verbs for GPU HDMI audioMatt DeVillier
Test: cbmem reports verb table loaded for codec #2 Change-Id: I4db044535c95ccd3e81a67bb5e58e6f04ee8d12f Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68552 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-20mb/google/drallion: Add default FMAP for non-ChromeOS buildsMatt DeVillier
Test: build/boot google/drallion with non-ChromeOS build, Tianocore payload. Windows 10, Linux 5.10.x booted successfully Change-Id: I6358b1d5c71eee065fed96b7bca31e37f30d3a8f Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58405 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-20purism/librem_cnl: Add Kconfig to enable Mini UARTJonathon Hall
Librem Mini has a UART (accessible with soldering), which is very useful for work on coreboot. It can be used for coreboot/SeaBIOS/Linux boot logs, or as a general purpose UART. Change-Id: I38ad5f19da6af5ed286ad3583f34b824a3660916 Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68551 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-20mb/prodrive/hermes: Allow using the Intel iGPU as primaryArthur Heymans
Configure the Intel iGPU as primary video adapter if enabled according to EEPROM settings. The default is to use the ASPEED BMC as primary video adapter, which only has a VGA output and the remote KVM output. For now, use the FSP GOP driver to light up the iGPU. There are several issues with libgfxinit on the Hermes, probably due to the unusual setup of the iGPU's display outputs. They are routed to a mezzanine connector for a piggy-back sub-board, of which there are two models. The Poseidon piggy-back has two DisplayPort outputs and an HDMI output coming from a MegaChips LSPCON. The Avalanche piggy-back routes all three DisplayPort outputs from the iGPU into a FPGA, which acts as a DisplayPort sink. Note that the FSP GOP only initializes at most 2 iGPU display outputs. However, all three outputs function properly once OS (Windows, Linux) graphics drivers take over. Additionally, update the config file that Prodrive uses to build coreboot images so that the iGPU can be used as primary. TEST=Verify that the iGPU's outputs work properly in pre-OS, Windows and Linux, on both the Poseidon and Avalanche piggy-backs. Change-Id: I24d9ebc2055dc246e7f257aa2f3853b22c8af370 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62649 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-20vc/intel/fsp/mtl: Update header files from 2344_00 to 2364_00Subrata Banik
Update header files for FSP for Meteor Lake platform to version 2364_00, previous version being 2344_00. FSPM: 1. Address offset changes FSPS: 1. Address offset changes BUG=b:251733481 TEST=emerge-rex intel-mtlfsp Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I8e4f62890b812f68dffe215e51c433510fca018f Reviewed-on: https://review.coreboot.org/c/coreboot/+/68491 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-20Kconfig: Allow x86 to compress pre-ram stages if not run XIPArthur Heymans
On the intel/glkrvp compressed: - romstage: 29659 - verstage: 31303 non compressed: - romstage: 46244 - verstage: 47012 On qemu (with some additional patch to not run XIP) compressed: - romstage: 11203 non compressed: - romstage: 13924 Even with a small romstage the size improvements are substantial, which should result in a speedup when loading the stage. On the up/squared loading romstage is sped up by 9ms. TESTED: successfully boot the up/squared & google/vilboz. Change-Id: I6906c8b6df45f2433d92d2ff1d1748cc4926c73a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67749 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-10-20arch/x86: Only use .bss from car.ld when running XIPArthur Heymans
Some platform run early stages like romstage and verstage from CAR instead of XIP. This allows to link them like other arch inside the _program region. This make in place LZ4 decompression possible as it needs a bit of extra place to extract the code which is now provided by the .bss. Tested on up/squared (Intel APL). Change-Id: I6cf51f943dde5f642d75ba4c5d3be520dc56370a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48156 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Nico Huber <nico.h@gmx.de>
2022-10-20soc/intel/alderlake: Drop local `ufs.asl`Subrata Banik
This patch drops `ufs.asl` from the local SoC directory. BUG=none TEST=Able to build and boot Google/Kano. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I84e0b51e74e2d6a7120f1d990152bc27e37a501f Reviewed-on: https://review.coreboot.org/c/coreboot/+/68302 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.com>
2022-10-20soc/intel/alderlake: Use `ufs.asl` from common code acpi blockSubrata Banik
This patch includes UFS ASL entry from common block ACPI code. BUG=none TEST=Able to build and boot Google/Kano. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ia77ea1c915d0dec991afa5b977af78487ae6a8b2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68301 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.com>
2022-10-20soc/intel/cmn/block/acpi: Create common ASL entry for UFSSubrata Banik
This patch migrates UFS ASL entry from Alder Lake SoC to common block ACPI code to be able to be utilized across different IA SoCs. Additionally, migrate to ASL2.0. BUG=none TEST=Able to build and boot Google/Kano. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I2e803138a20fd1fc3cdcd5c0fbbb1254663bb8dc Reviewed-on: https://review.coreboot.org/c/coreboot/+/68300 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.com>
2022-10-20mb/google/reef: Demote NHLT log messages from error to infoMatt DeVillier
Change-Id: I1c00322d2b22e1fafffd6ebd66f2df14bcedbd89 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68461 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-20ec/google/wilco/acpi: Hide CrOS-specific devices from OSMatt DeVillier
Set _STA to 0xB for GOOG000C/GOOG000E devices to prevent showing as missing drivers under Windows. Change-Id: I0887fd6e18528d2c8523e7bc66db9efaa31adf5d Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68462 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-20mb/google/volteer: add VBTs for lindar variantMatt DeVillier
Add VBT data files, ensure secondary VBTs compiled in as needed, select INTEL_GMA_HAVE_VBT. TEST=build/boot lindar variant with FSP/GOP display init, edk2 payload Change-Id: I81022670fabda7994e292d333c999b508e61b469 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68465 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-20mb/google/dedede: add VBTs for drawcia, mangolor variantsMatt DeVillier
Add VBT data files, ensure secondary VBTs compiled in as needed, select INTEL_GMA_HAVE_VBT. TEST=build/boot drawcia, mangolor variants with FSP/GOP display init and edk2 payload Change-Id: I58a2ed59bd858ce772e92f6659d341036823b11a Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68464 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-20mb/google/nissa/var/nivviks: Change ISH name to adl_ish_lite.binReka Norman
The ISH build target used for nissa is called adl_ish_lite: CL:3925007, and by default the binary is installed as /lib/firmware/intel/adl_ish_lite.bin We could change the installed name, but it's nicer to keep it consistent with the build target, so change the name in coreboot instead. BUG=b:234776154 TEST=Build and boot nirwen, check firmware name is updated in SSDT Change-Id: I983a38d08e758cf5a12a3f91a601c7e57d42c0cb Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68466 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-25 05:30:53 +0000