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2019-07-26util/testing: Factor out abuild options in what-jenkins-doesPatrick Georgi
The abuild command line can vary a lot depending on options and the line became unwieldy (plus, it's on two lines because we run abuild twice), so factor it out into a variable. Change-Id: I102756fb95c93f542d534610bf9737a13ac1ad62 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34566 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
2019-07-26libpayload/serial/qcs405: Mark uart console as suchPatrick Georgi
depthcharge prefers knowing where its input comes from BUG=b:137378326 BRANCH=none TEST=ctrl-d / enter to enter dev-mode works now. Change-Id: I74b5be18c3583be17c73950ced93fad883690090 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34451 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-07-26src/device/oprom: Fix bootsplash display code for optionromsJohanna Schander
So far the bootsplash is only correctly rendered if the framebuffer is set up as 1024x768@16. Different resolutions did not show anything, differnent depth resulted in the distorted images. This commit removes this limit by using the actual framebuffer resolutions and combines the code for x86 and yabel. For the moment the bootsplash is still limited to VGA-OptionROM framebuffer init. It was tested in 1280x1024@32 on the wip razer blade stealth using the intel vgabios. Change-Id: I5ab7b8a0f28badaa16e25dbe807158870d06e26a Signed-off-by: Johanna Schander <coreboot@mimoja.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34537 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-26oprom/yabel: Fix comment to fix the buildKyösti Mälkki
Old comment did not match the pattern required to not flag the fall-through as an error. Change-Id: I2afaca969c295a5dc4389dad0ce898c87bb841a6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34578 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-by: Johanna Schander <coreboot@mimoja.de> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-07-25payloads/external/Yabits: Pass XGCCPATHNico Huber
Pass `XGCCPATH` instead of individual programs as that is what the Makefile expects. Change-Id: I3267ec5259e9d37b2f3b0b8c126d173fc8b5a3ca Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34556 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Martin Roth <martinroth@google.com>
2019-07-25xcompile: Store XGCCPATHNico Huber
It can be useful to pass along to external projects, e.g. payloads. Change-Id: I61c7bb162e2737a562cbef08b32ebbafd9cf1cb0 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34555 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Martin Roth <martinroth@google.com>
2019-07-25crossgcc: Add nasm to toolchainMartin Roth
Tianocore payload uses nasm. Supply it in the coreboot toolchain instead of relying on system version. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I086cbe6c46f7c09b2a7a83e177b32fd1bdf99266 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33024 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-25crossgcc: Upgrade CMake to 3.15.0Elyes HAOUAS
Changes: https://cmake.org/cmake/help/v3.15/release/3.15.html Change-Id: Ic9db9050bec45d33d56ee53e3692276494f306de Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33053 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-25crossgcc: Upgrade acpica to version 20190703Elyes HAOUAS
Changes: https://acpica.org/node/171 Change-Id: I3883718623e4a23a901a446f738a9e8c988d8433 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34067 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-07-25crossgcc: Upgrade Expat to version 2.2.7Elyes HAOUAS
Change-Id: If3611494228a9228b0b323038ba1e884a1bde10f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33825 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-25crossgcc: Upgrade Python to version 3.7.4Elyes HAOUAS
Change-Id: I2d4a93fa43cf662685d4c439bcff04e338d51375 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32077 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-25crossgcc: Upgrade GDB to version 8.3Elyes HAOUAS
Change-Id: I7a85ad171fa259e0dcb0019941d735ef41511737 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32754 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-25ec/google/wilco: Hide wilco symbols when unusedElyes HAOUAS
This cleans up .config file from unused wilco symbols. Change-Id: I813d3fe57b97e2c1ba67e1e3674de256c2529029 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34539 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-25soc/intel/fsp_broadwell_de: Fix use of config_of()Kyösti Mälkki
Change-Id: I96d423720fbe67c067373436ad250edf37939e99 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34547 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-07-25soc/intel: Guard remaining SA_DEV_ROOT definitionKyösti Mälkki
Prevent implicit cast to pointers. The compiler doesn't warn about the conversion from integer to pointer without a cast, because SA_DEV_ROOT is literally '0' and there seems to be an exception for that conversion. Change-Id: I64fc156e3b9f578414ad03a00edb7cf3e33205c1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34544 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-07-25soc/intel/broadwell: Fix case of SA_DEV_ROOTKyösti Mälkki
Commit 71756c2 soc/intel: Expand SA_DEV_ROOT for ramstage removed SA_DEV_ROOT expanding to device pointer. We missed the case here, use __SIMPLE_DEVICE__ instead for the file. Change-Id: I4331298837afa3b8c8321da610f99f8f5fa54737 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34546 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-07-25mb/purism/librem_skl: use SOC_INTEL_COMMON_BLOCK_HDA_VERBMatt DeVillier
Remove old hda_verb.c code copied from intel/kblrvp7, as it's been superseded by the common block HDA implementation. Fixes a null pointer error preventing the HDA codecs from being initialized, as found in Coverity CID 1403651. Test: build/boot Librem 13v2, verify functional audio Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Change-Id: I2fd5363aad027f215f93964bc6a85f00fea86c88 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34531 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-25mb/getac/p470: Remove unneeded whitespacesElyes HAOUAS
Change-Id: I8e36dc1553faa618aa852c06861029b4c0bdb27a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34474 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-07-25soc/{qualcomm,rockchip}: Use 'include <stdlib.h>' when appropriateElyes HAOUAS
Also including <types.h>, is supposed to provide stdint and stddef. Change-Id: Iab605f6be4a48c10fa5aae7a1222520149ad1392 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33691 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-07-25soc/mediatek: Use 'include <stdlib.h>' when appropriateElyes HAOUAS
Also including <types.h>, is supposed to provide stdint and stddef. Change-Id: Id6d881055826044d04843ba165641131b9111342 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33690 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-07-25soc/nvidia: Use 'include <stdlib.h>' when appropriateElyes HAOUAS
Also including <types.h>, is supposed to provide stdint and stddef. Change-Id: I812d468c68b31917da5d406e2fb3b84bc6331b69 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33687 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-07-25soc/qualcomm/ipq806x: Remove unnecessary allocationJacob Garber
The bus variable doesn't live outside the scope of this function, and is only used as a convenient way for passing the pointers to all the sub-functions, so it doesn't need to be allocated. Put it on the stack instead. Change-Id: I4370d77445952731d20f7d9a91803612f4d21aef Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1294801 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34499 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-07-25soc/intel/cannonlake: Split the "internal PME" wake-up into more detailPaul Fagerburg
The "internal PME" wake-up source could be from integrated LAN, HD audio/audio DSP, SATA, XHCI, CNVi, or an ME maskable host wake. chromium:1680839 adds USB port details to the wake-up when the XHCI causes the wake-up. Expand the logging for wake-up details to identify and log the other wake-up sources with more details. Note that wake on Integrated LAN (GbE), SATA, and ME Maskable Host Wake are not in use on Hatch, so these will not be tested. BUG=b:128936450 BRANCH=none TEST=``FW_NAME=hatch emerge-hatch chromeos-ec depthcharge vboot_reference libpayload coreboot-private-files intel-cmlfsp coreboot-private-files-hatch coreboot chromeos-bootimage`` Ensure /build/hatch/firmware/image-hatch.serial.bin has been built. Program image-hatch.serial.bin into the DUT using flashrom. Switch the DUT to the console (Ctrl-Alt-F2, or use the AP console via servo). XHCI USB 2.0 * Plug a USB keyboard into a USB-A port * ``powerd_dbus_suspend`` * Verify low power mode by issuing the ``powerinfo`` command on the EC console (via servo). Expect to see ``power state 4 = S0ix``. * Press a key on the USB keyboard * ``mosys eventlog list`` shows: 12 | 2019-06-26 14:52:23 | S0ix Enter 13 | 2019-06-26 14:53:07 | S0ix Exit 14 | 2019-06-26 14:53:07 | Wake Source | PME - XHCI (USB 2.0 port) | 3 15 | 2019-06-26 14:53:07 | Wake Source | GPE # | 109 CNVi (connected to Wi-Fi): * Enable wake on disconnect via ``iw phy0 wowlan enable disconnect`` * Set up a hotspot on an Android phone * Connect the Chromebook to th hotspot * ``powerd_dbus_suspend`` * Verify low power mode by issuing the ``powerinfo`` command on the EC console (via servo). Expect to see ``power state 4 = S0ix``. * Turn off the hotspot on the phone * ``mosys eventlog list`` shows: 8 | 2019-07-11 10:58:17 | S0ix Enter 9 | 2019-07-11 10:59:17 | S0ix Exit 10 | 2019-07-11 10:59:17 | Wake Source | PME - WIFI | 0 11 | 2019-07-11 10:59:17 | Wake Source | GPE # | 109 XHCI USB 3.0 * TBD HD Audio * TBD Change-Id: I2c71f6a56b4e1658a7427f67fa78af773b97ec7f Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34289 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-25mb/google/poppy/variant/nami: add sku ids of bardRen Kuo
add two sku ids of bard: 0x1009CE0 0x1009CE2 BUG=b:137892804 TEST=emerge-nami coreboot Change-Id: I299ccb36739d83e38f37e0b2cbba44c34343c975 Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34430 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-07-25soc/nvidia/tegra210: Prevent unintended sign extensionJacob Garber
The perennial problem with u16 << 16 strikes again - the u16 is implicitly promoted to an int before the shift, which will then become negative if the highest bit of the u16 was set. Normally this isn't much of a problem, but in this case tegra_dsi_writel() expects a 64 bit integer for that argument, and so it will be sign-extended to a very large unsigned integer if it is negative. Cast bytes to a u32 beforehand to prevent the implicit promotion and thus this problem. Change-Id: Iaf0fb1040ccafafde0093e9bb192c802b86cb2ac Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1294800 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34529 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-25soc/nvidia/tegra210: Add null pointer checkJacob Garber
Check that tx is not null before accessing it, similar to the previous if statements. Change-Id: I820cb670026bb12a54c63227aa04e778fd49c66a Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1294805 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34530 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-07-25soc/rockchip/rk3399: Use 64 bits in multiplicationJacob Garber
This multiplication is of the form u64 = u32 * u32. Despite being stored in a 64 bit variable, the intermediate value is still calculated using 32 bit math, which could possibly overflow. Cast one of the variables to a u64 to ensure it uses 64 bit math instead to avoid this. Change-Id: Ib08624812e933fdca5a51150ab36d3be49383326 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1375443 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34524 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-07-25mb/*/chromeos.c: Remove some ENV_RAMSTAGE and __SIMPLE_DEVICE__Kyösti Mälkki
Use explicit simple PCI config accessors here. Change-Id: Ifa3814fdd7795479ca5fdbfc4deb3fe8db9805f3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34519 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-07-25soc/intel/icelake: Add ENABLE_DISPLAY_OVER_EXT_PCIE_GFX kconfigSubrata Banik
This patch creates new kconfig option to bring display over external PCI based GFX card. This kconfig to select required kconfig which are not default selected by VGA_ROM_RUN to launch legacy oprom from pci based GFX card. Change-Id: I8ebde69e38defbe3321eb5e5bbd632c209ae2cd8 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33738 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: V Sowmya <v.sowmya@intel.com>
2019-07-24Documentation/releases: Make sure lists look like lists in markdownPatrick Georgi
Add bullet points for to achieve that. Change-Id: Iea6811147ddad4e6e3372ca1ccd8fdaf8bb5cb77 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34502 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-07-24Documentation/releases: Also mention RELOCATABLE_RAMSTAGE in deprecationsPatrick Georgi
We plan to retire that symbol after 4.11 as well, with relocatable ramstage becoming the normal mode of operation. Change-Id: I36029215e5c8726f7dcc268bddc0d2b0161e3c40 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34500 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-07-24device: Default to VESA/linear framebuffer for ChromeOSNico Huber
Building for ChromeOS implies the use of Depthcharge which doesn't support legacy text mode. Change-Id: I7fd82bfed1e59de2de75419cfaea6f0c19cfdf5e Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34483 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-24soc/intel/common: Set controller state to active in GSPI initMeera Ravindranath
Set the controller state to D0 during the GSPI sequence,this ensures the controller is up and active. BUG=b:135941367 TEST=Verify no timeouts seen during GSPI controller enumeration sequence for CML and ICL platforms. Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Change-Id: I2f95059453ca5565a38650b147590ece4d8bf5ed Reviewed-on: https://review.coreboot.org/c/coreboot/+/34449 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
2019-07-24soc/intel/common: Set controller state to active in uart initUsha P
Set the controller state to D0 during the uart init sequence, this ensures the controller is up and active. One more argument struct device *dev has been added to uart_lpss_init function for the same. BUG=b:135941367 TEST=Verify no timeouts seen during UART controller enumeration sequence in CML and ICL platforms. Signed-off-by: Usha P <usha.p@intel.com> Change-Id: I0187267670e1dea3e1d5e83d0b29967724d6063e Reviewed-on: https://review.coreboot.org/c/coreboot/+/34447 Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-233rdparty/blobs: Update submoduleJulius Werner
Uprev the 3rdparty/blobs submodule to the newest HEAD, which contains the SSPM binary for MT8183 platforms ( https://review.coreboot.org/c/blobs/+/32698 ). Change-Id: I8a4dfa7eaace1ea473f5970596c3201342e48927 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34494 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-23include/spi-generic: Append unit to macro namesUwe Poeche
This patch appends a unit (milliseconds) to time-out macro names for better understanding the code which is using the macros. Change-Id: Ibc4beda2660a83fd5f0ed325b2ee3148c6d96639 Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34384 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-23sb/intel/common/spi: Increase flash erase timeoutUwe Poeche
This patch provides an increased timeout (60ms -> 1s) for SPI HW-sequencing flash erase operations. Without that the erase for MRC cache writing on siemens/mc_bdx1 sometimes goes wrong because the timeout stops waiting for flash cycle completion. It was found during continuous integration. Investigation showed that the used flash type takes sporadic (e.g. 5% of the test cycles) more time for completion of erasing operation if the ambient temperature increases. The measured time values are in range of data sheet of SPI flash. 60ms is a typical value. So increasing the value is necessary. tested on siemens/bdx1; measured time values with increased ambient temperature of flash were always smaller than worst case value of 1s. Change-Id: Id50636f9ed834ffd7810946798b300e58b2c14d2 Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34173 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-07-23include/spi-generic: move common flash timeoutsUwe Poeche
This patch moves SPI_FLASH time-outs from spi/spi_flash_internal.h for SPI SW-sequencing to include/spi-generic.h to provide also for SPI HW-sequencing. tested on siemens/bdx1 and checked if all includes of spi_flash_internal.h on other places provide an include of spi-generic.h before Change-Id: I837f1a027b836996bc42389bdf7dbab7f0e9db09 Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34345 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-07-23mb/google/octopus/variants/fleex: Remove gpio NC setting for enabling I2C0Frank Wu
Enable I2C0 in fleex then verify EMR function successfully BUG=b:135968368 BRANCH=octopus TEST=EMR function working normally with I2C0 in Grob360S. Change-Id: I784ff32418bc839bcec14fbfd7236f708828690e Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34364 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marco Chen <marcochen@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2019-07-23vboot: relocate call to vboot_save_recovery_reason_vbnvJoel Kitching
Relocate call to vboot_save_recovery_reason_vbnv and rename vb2_clear_recovery_reason_vbnv for consistency. BUG=b:124141368, b:124192753 TEST=make clean && make test-abuild BRANCH=none Change-Id: I111cc23cf3d4b16fdb058dd395ac17a97f23a53f Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33551 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-07-23vboot: deprecate vboot_handoff structureJoel Kitching
vboot_handoff is no longer used in coreboot, and is not needed in CBMEM or cbtable. BUG=b:124141368, b:124192753 TEST=make clean && make runtests BRANCH=none Change-Id: I782d53f969dc9ae2775e3060371d06e7bf8e1af6 Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33536 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-23util/*/Makefile: Rename -W to -WextraJacob Garber
-W is the old name for -Wextra, so let's rename it to be consistent with the rest of the utility Makefiles. Change-Id: I0e50f13d2617b785d343707fc895516574164562 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34455 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-07-23libpayload/libc: Use size_t for lengths and indicesJacob Garber
size_t is the natural integer type for strlen() and array indices, and this fixes several integer conversion and sign comparison warnings. Change-Id: I5658b19f990de4596a602b36d9533b1ca96ad947 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33794 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-23libpayload/libc: Tidy utf16le_to_asciiJacob Garber
- Constify the string argument - Change int to size_t, which is what xmalloc expects Change-Id: I8b5a13319ded4025f883760f2b6d4d7a9ad9fb8b Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33793 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-07-23libpayload/libc: Correct strlcat return valueJacob Garber
The documented return value for strlcat is horribly wrong, as is the return value itself. It should not return the number of appended bytes, but rather the length of the concatenated string. From the man page: The strlcpy() and strlcat() functions return the total length of the string they tried to create. For strlcpy() that means the length of src. For strlcat() that means the initial length of dst plus the length of src. While this may seem somewhat confusing, it was done to make truncation detection simple. This change is more likely to fix existing code than break it, since anyone who uses the return value of strlcat will almost certainly rely on the standard behaviour rather than investigate coreboot's source code to see that we have a quirky version. Change-Id: I4421305af85bce88d12d6fdc2eea6807ccdcf449 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33787 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-07-23src/lib/hexdump: Use size_t for indicesElyes HAOUAS
Spotted out using -Wconversion gcc warning option. Change-Id: I29a7ae8c499bb1e8ab7c8741b2dfb7663d82a362 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33799 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
2019-07-23mb/google/hatch: Add FP MCU to helios device treePhilip Chen
BUG=b:136606255 Change-Id: I8fa29dc96e7a066f6708ede6b7bee2382c7008cb Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34465 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-07-23mediatek/mt8183: Add md power-off flowYanjie Jiang
SRCCLKENA holds 26M clock, which will fail suspend/resume, and the SRCCLKENA is not used by mt8183, so we can simply release it for suspend/resume to work. BUG=b:80501386 BRANCH=none Test=Boots correctly on Kukui, suspend test pass. Change-Id: Ib6e11faeb6936a1dd6bbe8b1a8b612446bf51082 Signed-off-by: Yanjie.jiang <yanjie.jiang@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32666 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-22Documentation: Add 4.10/4.11 release notesPatrick Georgi
For 4.11 that's obviously just the release notes template. Change-Id: I44c15bcaedf1367d745c533cc0a4acebdd2f812e Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34469 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-07-22soc/mediatek/mt8183: Support SSPMErin Lo
SSPM is "Secure System Power Manager" that provides power control in secure domain. The initialization flow is to load SSPM firmware to its SRAM space and then enable. BUG=b:80501386 BRANCH=none Test=Build pass Change-Id: I4ae6034454326f5115cd3948819adc448b67fb1c Signed-off-by: Erin Lo <erin.lo@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31516 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-22soc/intel/broadwell: Change variable back to u32Jacob Garber
commit bde6d309df (x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointer) accidentally changed the type of reg32 to a u8 *, so change it back to a u32. Change-Id: If6beff17ed3ddf85889aba5f41d1ba112cd74075 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1402160 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34486 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2019-07-21mediatek/mt8183: support more EMCP LPDDR4X DDR bootupHuayang Duan
Support SANDISK SDADA4CR-128G, SAMSUNG KMDP6001DA-B425, KMDV6001DA-B620 EMCP LPDDR4X DDR bootup. BUG=b:80501386 BRANCH=none TEST=Boots correctly on EMCP DRAM Change-Id: I7de4c9a27282d3d00f51adf46dcb3d2f3984bfff Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33838 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-07-21mb/google/kukui: Introduce a new 'Jacuzzi' familyHung-Te Lin
The 'Jacuzzi' is a different base board that will share most of Kukui design. For AP firmware, there will be only a few changes expected, mostly in display (for MIPI bridge) and EC/keyboard so we want to create it as variants inside Kukui folder, not forking a new directory. BUG=b:137517228 TEST=make menuconfig; select 'krane' and build; select 'jacuzzi' and build. Change-Id: Ic2b04e01628dc3db40f79f9bbdd5cc77d9466753 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34344 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-21mediatek/mt8183: Calibrate RTC eosc clockRan Bi
Calibrate RTC eosc clock which will be used when RTC goes into low power state. BUG=b:133872611 BRANCH=none TEST=Boots correctly on Kukui Change-Id: Ie8fd6f4cffdcf7cf410ce48343378a017923789c Signed-off-by: Ran Bi <ran.bi@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33907 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: You-Cheng Syu <youcheng@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-07-21src/cpu/intel: Add sanity check for cpu turbo mode capabilityJohn Zhao
It is proper to check cpu turbo mode capability after it is selected to be enabled. If processor exhibits the presence of hardware support for turbo, turbo global state will be updated with TURBO_ENABLE. Otherwise, TURBO_UNAVAILABLE is applied to turbo global state. TEST=Validated turbo state on GLK and WHL devices. Change-Id: Ib1bc37fb339b4a0bb6a7cdc6cd4391575b22b55a Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34145 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-21MAINTAINERS: Add Portwell M107 maintainersFrans Hendriks
Add maintainers to Portwell PQ-M107 boards. BUG=N/A TEST=N/A Change-Id: I9171a9dd56bba7cc4836a7d2c2e314b910229cb9 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34445 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-07-21soc/intel: Expand SA_DEV_ROOT for ramstageKyösti Mälkki
We do not want to disguise somewhat complex function calls as simple macros. Change-Id: I298f7f9a1c6a64cfba454e919eeaedc7bb2d4801 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34411 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-07-21soc/intel: Change file to __SIMPLE_DEVICE__Kyösti Mälkki
All the PCI accesses in the file are now accessed without SA_DEV_ROOT expanding to function call. Change-Id: I30d331e9c18a486ea971e8397a6e20a0f82d5f84 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34410 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-07-21soc/intel: Fix chip_info for PCH_DEV_PMCKyösti Mälkki
Since PCH_DEVFN_PMC device is a PCI device that may be hidden from enumeration, use SA_DEVFN_ROOT instead to locate the SOC configuration. Change-Id: I4b5195827fb32ec1dbd0bd6c9e243f4f9a4775ca Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34327 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-07-21util/cbfstool/flashmap: Fix memory leaks on failureJacob Garber
Fix several memory leaks on failed printing or tests. These don't matter much, but it keeps Coverity happy. Change-Id: Ie750acb50ae1590c3aea533338a8827c03459c1a Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 130245{1,2,3} Reviewed-on: https://review.coreboot.org/c/coreboot/+/34412 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-07-21mb/google/hatch: Remove hatch_whlPhilip Chen
Hatch_whl variant is deprecated. BUG=b:137180390 Change-Id: I88fa201398ad5fb70da48d022f1ae86fecafa660 Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34432 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-21mainboard/google/kahlee: create treeya variantChris Wang
This is based on the grunt variant. BUG=b:135551210 BRANCH=none TEST=emerge-grunt coreboot chromeos-bootimage Ensure that image-treeya.*.bin are created Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Change-Id: I40f3c9de87350777b02dd91d8c5b9dbe2eb9f6b5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34435 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-07-21soc/intel/common: gpio_defs: set trig to disable in PAD_CFG_GPO*Maxim Polyakov
According to the documentation [1], by default the RX Level/Edge Trig Configuration set to disable (2h = Drive '0') for each pad. Since this setting doesn't matter for the GPO pad, there is no need to change the default value for such pads. The patch updates PAD_CFG_GPO* macros to set trig to disable. It also resolves some problems of creating the PCH/SoC pads configuration based on information from the inteltool dump [2,3] [1] page 1429,Intel (R) 100 Series and Intel (R) C230 Series PCH Family Platform Controller Hub (PCH), Datasheet, Vol 2 of 2, February 2019, Document Number: 332691-003EN https://www.intel.com/content/dam/www/public/us/en/documents/ datasheets/100-series-chipset-datasheet-vol-2.pdf [2] https://review.coreboot.org/c/coreboot/+/34337 [3] https://github.com/maxpoliak/pch-pads-parser/issues/1 Change-Id: I39ba83ffaad57656f31147fc72d7a708e5f61163 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34406 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-07-21soc/intel/common: add PAD_CFG_NF_BUF_TRIG macroMaxim Polyakov
In the case there is no the circuit diagram for motherboard, the PCH/SoC GPIOs config is based on information from the inteltool dump. However, available macros from gpio_defs.h can't define the pad configuration from this dump: 0x0440: 0x0000002084000500 GPP_A8 CLKRUN# 0x0448: 0x0000102184000600 GPP_A9 CLKOUT_LPC0 0x0450: 0x0000102284000600 GPP_A10 CLKOUT_LPC1 To convert these raw DW0/DW1 register values to macros, the following parameters must be set: func - pad function, pull - termination, rst - pad reset config, trig - rx level/edge configuration, bufdis - rx/tx (in/output) buffer disable. The patch resolves the above problem by adding a new macro for the native function configuration: PAD_CFG_NF_BUF_TRIG(pad, pull, rst, func, bufdis, trig) These changes were tested on Asrock H110M-DVS motherboard [2]. It also resolves the problem of automatically creating pads configuration [3,4] [1] page 1429,Intel (R) 100 Series and Intel (R) C230 Series PCH Family Platform Controller Hub (PCH), Datasheet, Vol 2 of 2, February 2019, Document Number: 332691-003EN https://www.intel.com/content/dam/www/public/us/en/documents/ datasheets/100-series-chipset-datasheet-vol-2.pdf [2] https://review.coreboot.org/c/coreboot/+/33565 [3] https://github.com/maxpoliak/pch-pads-parser/issues/1 [4] https://github.com/maxpoliak/pch-pads-parser/commit/215d303 Change-Id: If9fe50ff9a680633db6228564345200c0e1ee3ea Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34337 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-21mb/google/hatch/var/kindred: Implement variant_devtree_update()David Wu
This change provides an implementation of variant_devtree_update() for kindred that disable eMMC controller when SKU ID = 1 or 3 BUG=b:132918661 TEST=Verify eMMC is disabled when SKU ID = 1 or 3 Change-Id: I8ccb4dae54f223881e0ced9e034bf45b994cc6f2 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-07-21mb/google/hatch: expose get_board_sku() as globalDavid Wu
BUG=None TEST=emerge-hatch coreboot chromeos-bootimage Change-Id: I217e13acd337034554ff055e8bf5011558d1f8bf Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34431 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-07-21mb/google/hatch: Add support for variant_devtree_update()David Wu
This change adds support for variant_devtree_update() that allows variant to update device tree. BUG=None TEST=emerge-hatch coreboot chromeos-bootimage Change-Id: I0e9ad360b6c02c83fe49387ce7bc66d56448ffb9 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34399 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-07-21mb/google/eve: Enable wake from MKBP events in S3Aseda Aboagye
We would like to wake eve up in suspend from an MKBP event. This commit simply enables MKBP events to wake the system in suspend using the existing host event interface. There is an accompanying series of patches in the EC firmware for eve that will allow a MKBP wake mask to be configured. BUG=chromium:786721 BRANCH=firmware-eve-9584.B TEST=Build and flash eve, generate MKBP events on the EC and verify that the system wakes up in suspend. Change-Id: I75b05c83a4204d55df11589299a7488d04bbd073 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34454 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-21soc/intel/skylake: Enable Energy/Performance Bias controlMatthew Garrett
Bit 18 of MSR_POWER_CTL is documented as reserved, but we're setting it on Haswell in order to enable EPB. It seems to work on SKL/KBL as well, so do it there too. Signed-off-by: Matthew Garrett <mjg59@google.com> Change-Id: I83da1a57a04dac206cc67f2c256d0c102965abc2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34458 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-07-21soc/amd/picasso: Remove dead SPD size Kconfig symbolMarshall Dawson
DIMM_SPD_SIZE is no longer used and should have been removed in 78025f6 "soc/amd/picasso: Remove all AGESA references". Change-Id: Iae15998835e4d8afdb44cca77d2c9009b7e3947a Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34419 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-07-21soc/amd/picasso: Enable stage cache only with ACPI resumeMarshall Dawson
Make the option match the change in I7c3b3ec. "stoneyridge/Kconfig: Enable stage cache based on HAVE_ACPI_RESUME" Change-Id: I7fa13428ec0119b61f429116a52986067e833bdf Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34418 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-07-21pci_ids: Add AMD Family 17h host bridgeMarshall Dawson
Add the ID for Picasso's D0F0. Change-Id: Id83dfecd628a6ee67bf61e390569da6cfc455a7d Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34417 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-07-21nb/amd/trinity: Rename PCI ID of the IOMMUMarshall Dawson
Make the Trinity IOMMU ID naming consistent with other products. Change-Id: Id5a03d44a2ca21061bb22f9e61b26e42d91f9d96 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34416 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-07-21pci_ids: Reorder AMD internal northbridge and IOMMU IDsMarshall Dawson
Put the devices in Family/Model order instead of a mostly chronological order. Change-Id: I425736012b3bb68c9e0b417e90ff5261d1193aba Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34415 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-07-21soc/amd: Move SPI base alignment define into commonMarshall Dawson
The decision to leave the alignment in stoneyridge was driven because of a spec difference with picasso. AMD has checked the design materials and has confirmed there was no change. TEST=Build Grunt successfully BUG=b:130343127 Change-Id: If3a1d5a41dc175c9733fd09ad28627962646daf9 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34414 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-07-21libpayload: Enable -Wimplicit-fallthroughJacob Garber
Add comments to intentional fall throughs and enable the warning. Change-Id: I93e071c4fb139fa6e9cd8a1bfb5800f5f4eac50b Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34457 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-07-20mb/,sb/intel/i82801gx: Merge `ide_legacy_combined` into `sata_mode`Nico Huber
Functional changes were already done in 5eb81bed2e (sb/intel/i82801gx: Detect if the southbridge supports AHCI) but we forgot to update the `chip.h` and devicetrees. Change-Id: I0e25f54ead8f5bbc6041d31347038e800787b624 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34462 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-19mb/getac/p470: Null-terminate ec_id string bufferJacob Garber
The EC ID of the ECDT needs to be null-terminated (see ACPI specification, section 5.2.15), which currently isn't being done due to an off-by-one error. strncpy() is bug-prone exactly because of issues like this, so just skip it entirely and use memcpy() instead. Change-Id: I0b62e1f32177c9768fa978053ab26bca93d7248d Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1402104 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34374 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-07-19device/device_util.c: Correct format specifierJacob Garber
path.mmio.addr is a uintptr_t, which is an unsigned long. Change-Id: I5e43e0ab65cf59819abe1dde43143ff98e4553b0 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1402110 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34370 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-07-19mb/google/octopus: Disable unused USB devicesKarthikeyan Ramasubramanian
Disable unused USB devices in the device tree so that the concerned ACPI objects do not get exported to the OS. BUG=b:133513961 BRANCH=octopus TEST=Boot to ChromeOS. Ensure that the USB devices are disabled based on port status and the concerned ACPI objects are not exported. Change-Id: I0faccdfb8a9df9ec52130437433b15973e3d6f1a Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34291 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-07-19mb/google/octopus: Add ACPI configuration for USB devicesKarthikeyan Ramasubramanian
Add devicetree configuration for USB devices so that USB Port Capabilities (_UPC) and Physical Location of Device (_PLD) ACPI objects can be exported to the OS. BUG=b:133513961 BRANCH=octopus TEST=Boot to ChromeOS. Ensure that the _UPC & _PLD ACPI objects are exported for the configured USB devices in the SSDT table. Change-Id: I832ffe305d256296b7447035c5e5dcafb7c296d9 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33378 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-07-19soc/intel/common/block/xhci: Add API to disable USB devicesKarthikeyan Ramasubramanian
Add API to disable USB devices that are not present but are configured in the device tree either after probing the concerned port status or as explicitly configured by the variants. BUG=None BRANCH=octopus TEST=Boot to ChromeOS. Change-Id: Ied12faabee1b8c096f2b27de89ab42ee8be5d94d Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33377 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-19soc/intel/common: Add SOC specific function to get XHCI USB infoKarthikeyan Ramasubramanian
It feels appropriate to define SoC specific XHCI USB info in SoC specific XHCI source file and an API to get that information instead of defining it in elog source file. This will help in other situations where the information is required. BUG=None BRANCH=None TEST=Boot to ChromeOS. Change-Id: Ie63a29a7096bfcaab87baaae947b786ab2345ed1 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34290 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-19device/oprom: List all supported vesa mode by opromSubrata Banik
This patch lists all supported vesa mode by oprom using Function 0x4F00 (return vbe controller information). This information might be useful for user to select correct vesa mode for oprom. TEST=Enabling external pcie based graphics card on ICLRVP Case 1: with unsupported vesa mode 0x118 Now coreboot will show below msg to user to know there is a potential issue with choosen vesa mode and better users know the failure rather going to depthcharge and debug further. Calling Option ROM... ... Option ROM returned. VBE: Getting information about VESA mode 4118 VBE: Function call invalid with unsupported video mode 0x118! User to select mode from below list - Supported Video Mode list for OpRom are: 0x110 0x111 0x113 0x114 0x116 0x117 0x119 0x11a 0x165 0x166 0x121 0x122 0x123 0x124 0x145 0x146 0x175 0x176 0x1d2 0x1d4 Error: In vbe_get_mode_info function Case 2: with supported vesa mode 0x116 Calling Option ROM... ... Option ROM returned. VBE: Getting information about VESA mode 4116 VBE: resolution: 1024x768@16 VBE: framebuffer: a0000000 VBE: Setting VESA mode 4116 VGA Option ROM was run Change-Id: I02cba44374bc50ec3ec2819c97b6f5027c58387f Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34284 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-19drivers/i2c/dw: Don't try to generate unselected speeds in ACPI tableTim Wawrzynczak
When generating entries in SSDT for DesignWare I2C controllers, only use the speed selected in the devicetree, instead of trying all of them. This quiets a message which looks like a bug ("dw_i2c: bad counts"), later on in this driver when checking rise/fall times. BUG=b:137298661 BRANCH=none TEST=Boot and verify that I2C controllers still function, and the nastygram message is gone. Change-Id: I07207ec95652e8af1a42bfe31214f61a183a134e Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34385 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-19google/nocturne: Add MKBP events as a wake sourceAseda Aboagye
We would like to wake nocturne up in suspend from an MKBP event. On Nocturne, MKBP events are notified to the host via a GPIO from the EC, EC_INT_L. However, the AP cannot wake from suspend from this GPIO. Therefore, we'll use the host event interface to wake the system instead. This commit simply enables MKBP events to wake the system in suspend. BUG=chromium:786721 BRANCH=firmware-nocturne-10984.B TEST=Build and flash nocturne, generate MKBP events on the EC and verify that the system wakes up in suspend. Change-Id: I6aff4d38051c939257533229fd0085e42c01d02f Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34388 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2019-07-19MAINTAINERS: Add arbitration board members for the code of conductPatrick Georgi
Since they're in charge of enforcing it, they should also get to see when somebody attempts to change it. Change-Id: I8c12dd0c27f7c3661e9755a5181db08563c8561f Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34393 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-07-19Documentation/code_of_conduct: Update arbitration teamPatrick Georgi
Marc found more interesting things to do (yay, Marc!) and Martin offered to volunteer on the arbitration board in his place. Change-Id: Ic5bf00735afdf8942e543043238890011a82c890 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34392 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-07-19Documentation/code_of_conduct: Emphasize definition of community org.Patrick Georgi
The paragraph starts talking about community organizers. By making their definition a separate paragraph it's hopefully easier to find what this means. Change-Id: Icb9abbbd05b59bd4ee741d10f4c9c1a8c321b430 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34391 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-07-19Documentation/code_of_conduct: Highlight the reporting processPatrick Georgi
Make it a separate section, emphasize that people should get support early, note that personal interaction and email are the two best ways to seek help. Change-Id: I8cb613fefe1a7b4db1ee948fb9927a38f0421011 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34390 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2019-07-19sb/intel/{bd82x6x|ibexpeak}: Drop p_cnt_throttling_supportedPatrick Rudolph
The processor P_BLK doesn't support throttling. This behaviour could be emulated with SMM, but instead just update the FADT to indicate no support for legacy I/O based throttling using P_CNT. We have _PTC defined in SSDT, which should be used in favour of P_CNT by ACPI aware OS, so this change has no effect on modern OS. Drop all occurences of p_cnt_throttling_supported and update autoport to not generate it any more. Change-Id: Iaf82518d5114d6de7cef01dca2d3087eea8ff927 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34351 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-07-19Documentation: Add Intel TXTPatrick Rudolph
Change-Id: I9e9606d0e4294ad3552ec3b3b44629f9e732d82b Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33416 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-07-19Documentation/code_of_conduct: Assume the best as long as you canPatrick Georgi
"Always assume" is rather final and (in some readings) invalidates the need for the rest of the text. Change-Id: Ibf6f776494367d012ce69a64fa928c1dd4206c0e Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34389 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-07-19device/pci_rom.c: Fix out of bounds readJacob Garber
run_rom->data is a uint16_t, so use the appropriate read function. Change-Id: Icc14421412885495df90c90ed7da6e7d2eba4182 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1402145 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34372 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-19sb/amd/sb800: Remove bit shift that does nothingJacob Garber
This bit shift attempts to set bits 8 and 9 of the byte variable (counting from 0). However, as the name suggests, this variable is only 8 bits wide, so the shift does nothing. Reading section 7.5 of the AMD SB800-Series Southbridges Register Programming Requirements manual, bits 8 and 9 are already set by default, so we can remove the bit shift. (Alternatively, we could try setting the corresponding bits one byte higher in 0xF1 if needed.) Change-Id: I645236441e02925ee01339378d213cb343027363 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1229582 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34395 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-07-19nb/via/vx900: Ensure framebuffer size is within limitsJacob Garber
- Use log2() when rounding down size_mb to the closest power of 2. Do a sanity check beforehand that size_mb is nonzero, else log2() will return -1 and there will be an undefined integer shift. - The framebuffer size needs to be between 8 and 512 MiB, so check after all the calculations are done to make sure this is the case. Change-Id: I3962e5cdc094c8da22d8dbadf16637e02fa98689 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1391086 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34355 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-07-19Makefile.inc: Enable -Wimplicit-fallthroughJacob Garber
Change-Id: Ic81ed9eb2ed5255a221082326b81c375456a6499 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34300 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-19src: Make implicit fall throughs explicitJacob Garber
Implicit fall throughs are a perpetual source of bugs and Coverity Scan issues, so let's squash them once and for all. GCC can flag implicit fall throughs using the -Wimplicit-fallthrough warning, and this should ensure no more enter the code base. However, many fall throughs are intentional, and we can use the following comment style to have GCC suppress the warning. switch (x) { case 1: y += 1; /* fall through */ case 2: y += 2; /* fall through - but this time with an explanation */ default: y += 3; } This patch adds comments for all remaining intentional fall throughs, and tweaks some existing fall through comments to fit the syntax that GCC expects. Change-Id: I1d75637a434a955a58d166ad203e49620d7395ed Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34297 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-07-19nb/intel/pineview: Remove dead code in switchJacob Garber
This switch was likely copy-pasted from the one right above it. However, the MEM_CLOCK_800MHz case isn't needed, since that is explicitly checked and avoided before the while loop. With that gone, only the 667MHz/default case is left, which we don't need to switch over anymore. Change-Id: Idfb9cc27dd8718f627d15ba92a9c74c51c2c1c2d Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1347372 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33407 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-07-19security/tpm/tss/tcg-2.0: Add TPM2 function tlcl_getcapability()Frans Hendriks
Add function tlcl_getcapability() to return TPM2 capability. To support TPM2 capability TPM_CAP_PCRS handling is added to unmarshal_get_capability(). BUG=N/A TEST=Build binary and verified logging on Facebook FBG-1701 Change-Id: I85e1bd2822aa6e7fd95ff2b9faa25cf183e6de37 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30826 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-18 18:11:22 +0000