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2014-07-21board_status.sh minor fixes - no functional changesMartin Roth
- Update some comments - Whitespace fixes - change from backticks to $() format for getting command data. Change-Id: Iaf424224abfd30a3581d0e43a1689cc7c887beec Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/6261 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-07-21board_status.sh: Read coreboot boot log from a serial deviceMartin Roth
- Read the boot log from a serial device. Change-Id: I9daf97fd9b7fc55d0d56d815b185f9b4e3ef9f5a Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/6260 Reviewed-by: Mike Loptien <mike.loptien@se-eng.com> Tested-by: build bot (Jenkins)
2014-07-21board_status.sh: name temp dir and print the nameMartin Roth
- give a template to the temp dir so they're recognizable. - show the location of the temp files again at the end of the script. Change-Id: Ieb031ee249043697f6a75e42284c23d0b9bad1b3 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/6259 Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: build bot (Jenkins)
2014-07-21board_status.sh allow cmd() to not save outputMartin Roth
- allow for cmd() to be run, but not pipe to a file. Change-Id: I3e1650e421a49a06218e082ceb5a60b7b4808ce8 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/6258 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-07-20build system: avoid warning about missing .xcompilePatrick Georgi
That file will be generated, but not before make managed to complain about it. So let's just generate it if missing - it won't hurt the dependency tracking some lines later which is looking at time stamps. Change-Id: I615f38457eb27a8ffb4352b5234e262ee95d84ac Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/6305 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-19src/device/Kconfig: fix typo in label "1024x768 256-color"Daniele Forsi
It had an extraneous digit after 768. Change-Id: Ie415e365f3eac0ed326786cea4c4628c002c4762 Signed-off-by: Daniele Forsi <dforsi@gmail.com> Reviewed-on: http://review.coreboot.org/6306 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-19nehalem: Move cbmem_recovery call to raminit.Vladimir Serbinenko
Currently cbmem_recovery is done in raminit only on non-S3-resume path do it on both paths to reduce confusion. Change-Id: I16161ad449b9802a855fcf834aa721f4f65c0bb4 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/5954 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins)
2014-07-19intel/model_2065x: Remove dead code.Vladimir Serbinenko
nehalem uses gm45-like approach to resume backup so this code is never used. Change-Id: Ic32aa73f8d5b164b1c57815f6f44b2732fdbdcdb Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/5975 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-07-19lenovo/x60: Support digitizer on X60t and X201t.Vladimir Serbinenko
Change-Id: I5b0399a8edca3b73aa7d515d2c446c31b3239fa5 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/5239 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-07-19device/pci_early.c: Mixes up variants of a typedefs to 'u32'Edward O'Callaghan
Unfortunately coreboot has to deal with ROMCC's short comings which has lead to a little bit of confusion due to typedefs. Essentially, coreboot defines four typedefs: * 'typedef struct device * device_t' in ramstage not in SIMPLE_DEVICE mode * 'typedef u32 device_t' in romstage or when SIMPLE_DEVICE is defined * 'typedef u32 pnp_devfn_t' * 'typedef u32 pci_devfn_t' Some early functions make use of 'device_t' over 'pci_devfn_t' and since the C type-checker does not enforce typedefs to the same type 'u32' these are never noticed. Fix these so that 'device_t' does not conflict in romstage for later work. We later plan to have 'pnp_devfn_t' and 'pci_devfn_t' as the only variants of 'u32' and 'device_t' to be a struct pointer type exclusively. Change-Id: I948801f5be968a934798f1bad7722649758cd4d3 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6225 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-18superio/f71869ad: fix documentation of io_info mask valuesFelix Held
Change-Id: I5d0a945de45f8f4a77193135e63f480af14a0136 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: http://review.coreboot.org/6279 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-18mainboard: Trivial - drop trailing blank lines at EOFEdward O'Callaghan
Change-Id: If29a70be4fb56ebb0dbf6d510412cbe2f34480ef Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6291 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-07-18src/superio/smsc/lpc47m15x: Avoid #include early_serial.cEdward O'Callaghan
Provide proper header and function type-signatures for Super I/O romstage component. Fix mainboard's bogous romstage component to match. Change-Id: Icd02199690d0c428b2daadf702d50714dc367692 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5924 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-07-18superio/smsc: Add some missing header guardsEdward O'Callaghan
Change-Id: Id3f85929024208b150c378d7636607a0c9b8617c Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6302 Reviewed-by: Idwer Vollering <vidwer@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-07-18google/panther: general cleanup, file organization (non-functional)Matt DeVillier
acpi_tables.c: consolidate/organize headers chromeos.c: consolidate/organize headers; move header, #defines outside of #ifdef fadt.c: organize headers gpio.h: rename include guard; add comment to trailing #endif had_verb.h: add include guard; replace manual array size calculation with std header macro lan.c: remove conditional header inclusion; organize headers; remove pre-processor directive indentations mainboard.c: remove conditional header inclusion; organize headers; replace spaced indentations with tab(s); add comment to trailing #endif onboard.h: move fn prototype after #defines; add comment to trailing #endif romstage.c: consolidate/organize headers smihandler.c: organize headers; remove commented-out/dead code; add comment to trailing #endif thermal.h: add comment to trailing #endif Change-Id: Iadafdd1092108c3f52435831fa0103f2457066f1 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: http://review.coreboot.org/6270 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-18src/superio/ite/it8772f: Separate mainboard from SIO at obj levelEdward O'Callaghan
Remove #include early_serial.c and rename to early_init.c as no actual UART configuration is done here. Note that this SIO component still hard codes its base address to 0x2e. Change-Id: Ieef32ac7285246717f0519ffed4314ba28cd47dc Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6271 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-18mainboard: Make use of ARRAY_SIZE in buildOpts.c on AGESA platformsEdward O'Callaghan
Found using coccinelle. Change-Id: I406de6cfe25d3b471dbb6f98d9c62addae008de3 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6195 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-18vendorcode/amd/agesa: Use macros already defined in stdlib.hEdward O'Callaghan
We already have these macros define in 'stdlib.h'. Make good use of them here to avoid redefinition conflicts of the pre-processor depending on header inclusion ordering. This has the nice side-effect of syncing up AGESA families in this particular regard. Change-Id: Icf911629a4a1a82b01062fe16af4c8f812b05717 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6199 Tested-by: build bot (Jenkins) Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2014-07-17AMD get_bus_conf(): Drop bus_type arrayKyösti Mälkki
Only ever used as lvalue, so no point creating the array. Change-Id: I6699dfae9377a895e9bc4a52579d00ddcfa60a9f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6277 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2014-07-17drivers/spi: Sanitize headers from preprocessor abuseEdward O'Callaghan
Continuing on from the rational given in: a173a62 Remove guarding #includes by CONFIG_FOO combinations Change-Id: I35c636ee7c0b106323b3e4b90629f7262750f8bd Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6114 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-17intel/lynxpoint/Kconfig: Remove duplicate option `IFD_BIN_PATH`Paul Menzel
Currently `IFD_BIN_PATH` is shown twice. Commit 5218e616 (intel/lynxpoint: Allow building without IFD (descripter.bin)) [1] accidentally added the option another time. So fix up the commit and remove one of the two options `IFD_BIN_PATH`. Keep the one which depends on `!HAVE_IFD_BIN` and is around the IFD options. [1] http://review.coreboot.org/6046 Change-Id: Id46f01ab8ee2e752e337e687a2ef0dfa374f44a5 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/6269 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <gaumless@gmail.com>
2014-07-17mainboard,Makefile.inc: Trivial - drop trailing blank lines at EOFEdward O'Callaghan
Change-Id: I6a95debbe86fddcaf94270dd380bc73ce3172e58 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6283 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-07-17northbridge,Makefile.inc: Trivial - drop trailing blank lines at EOFEdward O'Callaghan
Change-Id: Id1fcd3d1cd8a156a76e1a9a3ca4c7b4004c2c015 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6289 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-07-17southbridge,Makefile.inc: Trivial - drop trailing blank lines at EOFEdward O'Callaghan
Change-Id: Ied03e8814ea13f0e677a1d34da19efe6dfebf72f Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6288 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-07-17cpu,Makefile.inc: Trivial - drop trailing blank lines at EOFEdward O'Callaghan
Change-Id: I7e8866d76d7f286e10160d7dc4f21f01a913bfee Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6286 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-07-17device,Makefile.inc: Trivial - drop trailing blank lines at EOFEdward O'Callaghan
Change-Id: I73fe6f37c363f4bff332ca90178a236590067170 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6287 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-07-17drivers,Makefile.inc: Trivial - drop trailing blank lines at EOFEdward O'Callaghan
Change-Id: I2d1f6a571166924c929452fd0f70192670904220 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6285 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-07-17soc,Makefile.inc: Trivial - drop trailing blank lines at EOFEdward O'Callaghan
Change-Id: I6db4eada5be5f9a4340d9edb942924e2fd18b5ca Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6284 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-07-17superio,Makefile.inc: Trivial - drop trailing blank lines at EOFEdward O'Callaghan
Change-Id: Ia452e22af9491c1681c859691eb4ac1868eeb938 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6282 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-07-17mainboard,ASL: Trivial - drop trailing blank lines at EOFEdward O'Callaghan
Change-Id: Ib531a54db7df6b49a6218f689dcaab712e9dfb01 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6292 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-07-17misc,ASL: Trivial - drop trailing blank lines at EOFEdward O'Callaghan
Change-Id: I5060052e268c6a6303d77fdf4380a55ac2ad5ae2 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6296 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-07-17soc,ASL: Trivial - drop trailing blank lines at EOFEdward O'Callaghan
Change-Id: If70f5ad26d639d7366772f4468a25bca83ac0857 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6295 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-07-17northbridge,ASL: Trivial - drop trailing blank lines at EOFEdward O'Callaghan
Change-Id: I8d4bf17fe9fd82499b1515a8e85dff9cba498350 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6294 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-07-17southbridge,ASL: Trivial - drop trailing blank lines at EOFEdward O'Callaghan
Change-Id: I8ef5f1571ad14ead2d4cc0d61b6b7133d7fc8550 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6293 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-07-16intel/i945/raminit.c: Remove trailing whitespace from `printk()`Paul Menzel
Remove a trailing space after the ellipse in the debug messages. Setting Graphics Frequency... FSB: 667 MHz Voltage: 1.05V Render: 250Mhz Display: 200MHz Change-Id: Iac8a5e89179104685dc54975ae7f833c1f3de69d Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/6280 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-15superio/fintek/f71869ad: config struct should be const qualifiedEdward O'Callaghan
The 'superio_fintek_f71869ad_config' struct packed by devicetree.cb should have its type declared with the 'const' qualifier. Change-Id: Ieb86861ee821e77680cc4d0de202dbd7535b844d Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6224 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-15southbridge/intel/bd82x6x/me_8.x.c: Trivial - space to tab fixEdward O'Callaghan
Change-Id: I5b6d0a1f5f96a8d6cfc5a14baaa0f9267339b072 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6268 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-15drivers/intel/fsp/fsp_util: 'long unsigned int' is 'unsigned long'Edward O'Callaghan
This is a bit of strange way to write 'unsigned long', fix that. Change-Id: I17caf971dac840e0f35f883dacfbd5c94d8c03d6 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6196 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-07-15build system: fix another cbfstool racePatrick Georgi
It just doesn't work to have files depend on their parent directory: As soon as the files are written, the time stamp of the directory changes, too. This led to spurious updates of cbfstool and rmodtool, and related "permission denied" errors when linker and build system ran into each other. Change-Id: I44a7d7b4b1d47a1567ece1f57dfd6745d05ee651 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/6276 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-07-15build system: create .xcompile dependencyPatrick Georgi
It's probably safe to say that .xcompile needs an update if util/xcompile/xcompile changed, so tell make about this dependency. Updates are honored immediately due to GNU make's feature of reinterpreting everything when an included file changes. See "How Makefiles Are Remade" in the GNU make documentation for details. Change-Id: Ide2f028eaddcee66028c6403688cc83e1622fa6b Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/6255 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-15util/xcompile: Print fatal error messages to stderr instead of stdoutDaniele Forsi
This uses die() which was previously unused. Before this change an unhelpful error message was printed when make tried to parse English text as if it was part of the makefile: .xcompile:1: *** missing separator (did you mean TAB instead of 8 spaces?). Stop. After this change the first error message at least mentions that iasl is missing: ERROR: no iasl found make: -print-libgcc-file-name: Command not found make: -print-libgcc-file-name: Command not found make: -print-libgcc-file-name: Command not found /bin/sh: 0: Illegal option - Makefile.inc:36: *** Please use the coreboot toolchain (or prove that your toolchain works). Stop. Change-Id: I79d5de5993e3828460130192df376daa55f32aa0 Signed-off-by: Daniele Forsi <dforsi@gmail.com> Reviewed-on: http://review.coreboot.org/6272 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <gaumless@gmail.com>
2014-07-15board_status.sh add non-fatal test_cmdMartin Roth
- add a non-fatal option to test_cmd. Change-Id: If74693ea7ec8ea24104d5836e4c24bfb135ef0e1 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/6257 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-07-15AGESA hudson: Fix SPI writesKyösti Mälkki
Only yangtze has longer FIFO in SPI controller. This was overlooked in commit 9f0a2be AMD SPI: Optimise for longer writes which broke SPI writes and caused CBFS errors with fam15tn. Change-Id: I821e3f1fa186d2383b30eab9c5d52797c2ef22c5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6273 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-07-14AGESA Hudson: Fix typecasts in Fch_Oem_config()Kyösti Mälkki
Like many other (but not all) BiosCallouts, StdHeader is also passed as ConfigPtr argument. Use that instead to make no assumptions of the real type of FchData as it changes depending of the StdHeader. Change-Id: Ibdf01d08e63b9e1b8e99ac16abb7f807d37a056e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6240 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-14AGESA boards: Use IS_ENABLED() for HUDSON_LEGACY_FREEKyösti Mälkki
Change-Id: Ib2a015dac82cec8538f8b1a1c2d45b20b05747bc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6239 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Martin Roth <gaumless@gmail.com>
2014-07-14AGESA fam15: Fix entry to cimx/sb900Kyösti Mälkki
Move SB900 call to match comments and changes already made for family14 et al. Change-Id: I22aa0bbeeabf9cff929c49c23014005bc3d53ccb Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6238 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-14AGESA CIMx: Move late init out of get_bus_conf()Kyösti Mälkki
Followup deals further with Fam15 case. For unknown reasons calls were commented out for amd/dinar and they remain that way. Change-Id: Ie0a25fbb6f5378019fbf0f19a02acf024d79817e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6237 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-14AGESA fam12: Fix entry to cimx/sb700Kyösti Mälkki
Move SB700 calls to match comments and changes already made for family14 et al. Change-Id: I20a84e487ba346f63dd4454447077e0d2fd12c89 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6222 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-14AGESA: Trace execution with AGESAWRAPPER()Kyösti Mälkki
Implement logging just once to have uniform output. Change-Id: I8db694a3bf6b1af459bdf98f7acb99edf4dd07f7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6180 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-14AGESA: Fix error status code return type to enum from UINT32Edward O'Callaghan
AGESA correctly uses the enum AGESA_STATUS type whereas boards use a mess of UINT32 typecasts. Also no need to shout VOID. We are not that careful on changing all cases of VOID->void or whitespace issues as these files will get merged with follow-ups. Change-Id: I16ccfcc73cda6b917c7ff5fd42ee2cd04e7dc0dd Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6182 Tested-by: build bot (Jenkins)
2014-07-14AMD SPI: Optimise for longer writesKyösti Mälkki
Leave it to the implementation of flash->write() to split the writes to match SPI controller and SPI flash part restrictions. This allows for some optimisation for auto-address-increment (AAI) commands. Kconfig AMD_SB_SPI_TX_LEN can be kept as local. Change-Id: I4a8bc55ab7eb0eeda8f25003a8f5ff2a643ab7a7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6164 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-14SPI: Split writes using spi_crop_chunk()Kyösti Mälkki
SPI controllers in Intel and AMD bridges have a slightly different restriction on how long transactions they can handle. Change-Id: I3d149d4b7e7e9633482a153d5e380a86c553d871 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6163 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-14SPI flash: Fix alignment checks in Page Program commandsKyösti Mälkki
There are two separate restrictions to take into account: Page Program command must not cross address boundaries defined by the flash part's page size. Total number of bytes for any command sent to flash part is restricted by the SPI controller capabilities. Consider CONTROLLER_PAGE_LIMIT=64, page_size=256, offset=62, len=4. This write would be split at offset 64 for no reason. Consider CONTROLLER_PAGE_LIMIT=40, page_size=256, offset=254, len=4. This write would not be split at page boundary as required. We do not really hit the second case. Nevertheless, CONTROLLER_PAGE_LIMIT is a misnomer for the maximum payload length supported by the SPI controller and is removed in a followup. Change-Id: I727f2e7de86a91b6a509460ff1f374acd006a0bc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6162 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-12libpayload: find source of input charactersLuigi Semenzato
This change makes it possible for vboot to avoid an exploit that could cause involuntary switch to dev mode. It gives depthcharge/vboot some information on the type of input device that generated a key. BUG=chrome-os-partner:21729 TEST=manually tested for panther BRANCH=none CQ-DEPEND=CL:182420,CL:182241,CL:182946 Change-Id: I87bdac34bfc50f3adb0b35a2c57a8f95f4fbc35b Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://chromium-review.googlesource.com/182357 Reviewed-by: Luigi Semenzato <semenzato@chromium.org> Tested-by: Luigi Semenzato <semenzato@chromium.org> Commit-Queue: Luigi Semenzato <semenzato@chromium.org> Reviewed-on: http://review.coreboot.org/6003 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-12google/panther: adjust critical tempMatt DeVillier
Set critical temp to match newer devices Change-Id: I11f32297a9b8c9a3554821b5d1cd723d8d9e2b69 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: http://review.coreboot.org/6023 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-12google/panther: Force enable ASPM on PCIe Root Port 4Stefan Reinauer
BUG=chrome-os-partner:21535 BUG=chrome-os-partner:25990 BRANCH=panther TEST=manual: Boot on Panther and look in /sys/firmware/log for the string "PCIe Root Port 4 ASPM is enabled" Change-Id: I294571c113a8909adb2e97afca92aef9a1af917c Signed-off-by: Stefan Reinauer <reinauer@google.com> Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/187153 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: Stefan Reinauer <reinauer@chromium.org> Commit-Queue: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: http://review.coreboot.org/6007 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-12google/panther: acpi: Fix unstable fan behavior on boot + resumeStefan Reinauer
FLVL is used to keep track of which thermal zones are active, but it is not initialized upon boot / resume. An initial value of zero corresponds to all zones being active, which causes the fan to spin at max speed until the OS changes zones. Fix this annoyance by initializing FLVL to the lowest temperature zone. Also, fix a related bug where FLVL may jump to an undesired value. For example, if FLVL=3 (zones 3 + 4 active), and zone 0 is set to off (it's already off!), FLVL would previously become 1 (zones 1 + 2 + 3 + 4 active!). Fix this by not taking zone ON / OFF actions if our zone is already ON / OFF. BUG=chrome-os-partner:25766, chrome-os-partner:24775 TEST=Suspend / resume on Panther 20 times, verify that thermal zone after resume matches expectation based upon temperature. Also, stress system and verify thermal zones become active according to temperature increase. Change-Id: Ic60686aa5a67bf40c17497832b086ba09d56111a Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/186455 Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org> Tested-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/186669 Commit-Queue: Stefan Reinauer <reinauer@chromium.org> Tested-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: http://review.coreboot.org/6006 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-12google/panther: Fix RW ramstage indexStefan Reinauer
Without this patch coreboot will always use the read-only version of ramstage, even if there is a read-write version available. BRANCH=panther BUG=chrome-os-partner:25870 TEST=Install different RO and RW version, check in cbmem log that coreboot's romstage and ramstage have different timestamps in their banners. Change-Id: I723a3d4479d59534660728d891a9f40a077b4ef0 Signed-off-by: Stefan Reinauer <reinauer@google.com> Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/186664 Commit-Queue: Stefan Reinauer <reinauer@chromium.org> Tested-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/6005 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-12google/panther: Add new thermal valuesMohammed Habibulla
Based on latest thermal report BUG=chrome-os-partner:24532 TEST=boot tested on panther BRANCH=panther Change-Id: I4b8639f926fc3cf57eb5329818b9b912bfbe222d Signed-off-by: Mohammed Habibulla <moch@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/186113 Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: http://review.coreboot.org/6004 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-12google/panther: Avoid shutdown when thermal sensor is unavailableStefan Reinauer
When the thermal sensor on Panther is unavailable (early on resume) it will return 0x80 which causes our AML thermal code to overflow, which causes the system to shut down. Instead, return a reasonable value in those cases so that the system will continue running until the sensor gets back on its feet. BUG=chrome-os-partner:24918 BRANCH=panther TEST=suspend_resume_test survived more than 100 iterations on Panther Change-Id: Ib2d714c39d353ce2415361bc6590784a3f6837d2 Signed-off-by: Stefan Reinauer <reinauer@google.com> Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/182369 Tested-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Commit-Queue: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: http://review.coreboot.org/6002 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-12google/panther: Re-read temperature if current reading would cause power-offStefan Reinauer
Sometimes the SuperIO seems to provide wrong readings, especially early on after a resume from suspend. This will cause the system to power off. If that happens, wait for 1s and read again, to make sure the high temperature value was not just a flaky read. BUG=chrome-os-partner:24918 BRANCH=panther TEST=Boot tested on Panther. Change-Id: Ib3768528d90e34448e96ad587b2503d8d8b1a775 Signed-off-by: Stefan Reinauer <reinauer@google.com> Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/182188 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: Stefan Reinauer <reinauer@chromium.org> Commit-Queue: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: http://review.coreboot.org/6001 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-12google/panther: Disconnect speaker and mic in verb tableStefan Reinauer
There is no speaker and no builtin microphone in this system, hence disable them in the verb table. BRANCH=panther BUG=chrome-os-partner:24230 TEST=Boot Panther, see Microphone and Speaker disappear in Audio Settings Change-Id: I32bacec38ba3ba0c2359a8fc94e12af64f576012 Signed-off-by: Stefan Reinauer <reinauer@google.com> Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/182006 Reviewed-by: Dylan Reid <dgreid@chromium.org> Commit-Queue: Stefan Reinauer <reinauer@chromium.org> Tested-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: http://review.coreboot.org/6000 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-12google/panther: Disable DEVSLP for SATAStefan Reinauer
Some SSD modules don't support DEVSLP correctly due to their firmware. Since the power savings are minimal, don't use DEVSLP to prevent potential problems. Some of the symptoms are that sometimes this causes USB devices to not work properly. BUG=chrome-os-partner:23186, BRANCH=panther TEST=Boot tested on Panther Change-Id: Iba3f721c73e0e760b6a9861ca23480ddb923df40 Signed-off-by: Stefan Reinauer <reinauer@google.com> Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/181957 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/5999 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-12google/panther: Add ACPI code to support wake-on-lanStefan Reinauer
There needs to be an ACPI linkage to provide the power resource needed to wake this device so the kernel will enable the SCI before going to suspend. A link is added for both NIC and WLAN, but it is only tested on the NIC. This is a forward port from Duncan's beltino patch. BUG=chrome-os-partner:24657 BRANCH=panther TEST=build and boot on panther, suspend and wake with etherwake Change-Id: I2804d2e904e26d6e34f5a177f0dabc1aaa3f0288 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/181752 Commit-Queue: Stefan Reinauer <reinauer@chromium.org> Tested-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: http://review.coreboot.org/5998 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-12google/panther: Update Fan PolicyStefan Reinauer
Update fan policy according to Panther thermal report. CPU Temp. Readings | PWM -------------------+------ 40C | 42% 50C | 42% 83C | 80% 90C | 90% 96C | 100% BUG=chrome-os-partner:24532 BRANCH=panther TEST=boot tested on Panther Change-Id: I60f04d8b038c561b87dad505bbf058100119cc23 Signed-off-by: Stefan Reinauer <reinauer@google.com> Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/181666 Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Commit-Queue: Stefan Reinauer <reinauer@chromium.org> Tested-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: http://review.coreboot.org/5997 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-12google/panther: Disable power-failure gating for the PSON# signalStefan Reinauer
When the system loses AC power, the system will power back on automatically as soon as the AC power is reapplied. BUG=chrome-os-partner:24066 BRANCH=firmware-panther-4920.24.B TEST=boot tested on panther Change-Id: I37ddc5a162afcce01c2df5f509bfd7f2d0c15ba1 Signed-off-by: Stefan Reinauer <reinauer@google.com> Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179537 Commit-Queue: Stefan Reinauer <reinauer@chromium.org> Tested-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/5996 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-12google/panther: Configure USB_ILIM_SEL to lowMohammed Habibulla
(panther port of Ib980100c648ae7472eac6f97e47f8ef3cbe72c7e) BUG=none BRANCH=none TEST=boot tested on Panther Change-Id: Iedcc107a43be170762d42d515c7e2a16ec395452 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://chromium-review.googlesource.com/177474 Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Commit-Queue: Mohammed Habibulla <moch@google.com> Tested-by: Mohammed Habibulla <moch@google.com> Reviewed-on: http://review.coreboot.org/5995 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-12google/panther: Set default interrupt value for Environmental ControllerMohammed Habibulla
This writes the default value to the register, but it gets rid of the error that disturbs some of our tests: ERROR: PNP: 002e.4 70 irq size: 0x0000000001 not assigned (panther port of Ieab1c776b553c996a7d06e4059110943aaf41338) BRANCH=none BUG=chrome-os-partner:23945 TEST=boot test on Panther Change-Id: Id45c3bdc0d2feaf6f75d984c41d1f6ffef592d4d Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://chromium-review.googlesource.com/177468 Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Commit-Queue: Mohammed Habibulla <moch@google.com> Tested-by: Mohammed Habibulla <moch@google.com> Reviewed-on: http://review.coreboot.org/5994 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-12google/panther: Make sure the S5 power status is on trackMohammed Habibulla
(panther port of I933c475f693b0271f86b5166eb2c9b3873f1c2c6) BUG=none BRANCH=none TEST=boot test on panther Change-Id: I5958a8d701901706eaa38df4323120c8352fea5c Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://chromium-review.googlesource.com/176563 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Commit-Queue: Mohammed Habibulla <moch@chromium.org> Tested-by: Mohammed Habibulla <moch@chromium.org> Reviewed-on: http://review.coreboot.org/5993 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-12google/panther: Disable LPSS I2C controllersMohammed Habibulla
There is nothing attached to these devices so we can disable them as well as the function 0 DMA controller. Also remove the EC SMI/SCI mappings since there is no EC. (panther port of Iedfe711058676f7ee118b0b66ab0f8a1e792ea87) BUG=chrome-os-partner:23563 TEST=none BRANCH=panther Change-Id: Ie66f9b66744db98f8638495c05f3a075b6fa6db9 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://chromium-review.googlesource.com/174944 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Commit-Queue: Mohammed Habibulla <moch@chromium.org> Tested-by: Mohammed Habibulla <moch@chromium.org> Reviewed-on: http://review.coreboot.org/5992 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-12google/panther: Fix thermal zone to use SIO PWM/TACH port 2Mohammed Habibulla
Fan is attached to port 2 instead of 3. (panther port of I9878063a24b0b908c74522580f776a4ce7d03d75) BUG=chrome-os-partner:23563 TEST=none BRANCH=panther Change-Id: I028e0e5a748fa0a20d34e27e870e14ed8c75e4d1 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://chromium-review.googlesource.com/174984 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Commit-Queue: Mohammed Habibulla <moch@chromium.org> Tested-by: Mohammed Habibulla <moch@chromium.org> Reviewed-on: http://review.coreboot.org/5991 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-12google/panther: Use ISO C99 syntax for designated initializersMatt DeVillier
In C99 we defined a syntax for this. GCC’s old syntax is deprecated. Modelled after commit 8089f178 (mainboard/lenovo/x230 Fix usage of GNU field designator extension) [1]. [1] http://review.coreboot.org/5392 Change-Id: I51c72252800be64b9420d845e330fc0481c66470 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: http://review.coreboot.org/6024 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-12mainboard: Add new board Google PantherMohammed Habibulla
(Panther clone of Ia41af8425ab6c24746253abd025acd3365dd5a18 by reinauer) BUG=chrome-os-partner:23563 TEST=emerge-panther chromeos-coreboot-panther [pg: Drop configs/, which is chromeos stuff, adapted libpayload's config.panther to work with upstream] [pm: Add HAVE_IFD_BIN and HAVE_ME_BIN Kconfig options] [pm: rebase to master branch of coreboot upstream] [md: don't use FMAP to get MAC address if CONFIG_CHROMEOS not set] Change-Id: I50fd5c02da154e424dfefbe2020f4ce7ef9a4f8f Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://chromium-review.googlesource.com/174555 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Mohammed Habibulla <moch@chromium.org> Tested-by: Mohammed Habibulla <moch@chromium.org> Reviewed-on: http://review.coreboot.org/5990 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-11asus/f2a85-m: Switch off automatic fan control for fan2Rudolf Marek
The fan2 (chasis fan) was set to automatic mode, but the registers for smart guardian have still default value which will stop it. Run it in manual mode for now. Change-Id: Ic2c2414ac88abba77a9e7a129788f9777e7e5ad5 Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Reviewed-on: http://review.coreboot.org/6217 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-11intel/lynxpoint: Allow to always route USB3 ports to XHCIStefan Reinauer
This will make USB keyboards connected to USB3 ports work in libpayload on Beltino. BUG=chrome-os-partner:23396 BRANCH=none TEST=Use USB keyboard on Beltino in dev mode screen Change-Id: I70b03d733bd9e4c8be5673b48bd2196effa8a5e7 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: https://chromium-review.googlesource.com/173640 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Commit-Queue: Stefan Reinauer <reinauer@chromium.org> Tested-by: Stefan Reinauer <reinauer@chromium.org> [pm: rebase to master branch of coreboot upstream] Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/6018 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-11intel/lynxpoint: Work around XHCI resume issuesDuncan Laurie
When USB3 devices are attached while in suspend, or two USB3 devices that are both plugged in are switched to the other port while in suspend the kernel does not seem to notice this -- despite the cold attach status bit. This results in the devices showing up in the USB list at the old enumerated device numbers and higher layers continuing to think they are present but not reseponding. With the kernel workaround to deal with devices that are logically disconnected it is possible for firmware to send a warm port reset to devices that are in this state and then the kernel will see them disappear and handle it properly. This same issue exists in the EFI firmware on the Whitetip Mountain 2 reference board so it is not specifically a coreboot bug. If this behavior is fixed in the kernel then this workaround could be removed since it is in RW firmware. BUG=chrome-os-partner:22818 BRANCH=falco,peppy,wolf,leon TEST=manual: 1) attach two USB3 devices 2) suspend system 3) switch the ports that the USB3 devices are attatched to 4) resume system 5) confirm that the devices are re-enumerated and come up properly Original-Change-Id: Ifba3ffc94a06dc0b2436d7d7d464d824657362af Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/170335 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 203d200268f4af6445224962190cbc66ad2a83e4) Change-Id: I54fd2847ee25a60f25c2cefebdc1a3c18455464a Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/170579 [pm: rebase to master branch of coreboot upstream] Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/6017 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-11intel/lynxpoint: xhci: Revert suspend/resume changesDuncan Laurie
I have been attempting to work around USB3 issues that appear in the kernel with hacks in the firmware, but this is resulting in more headaches in the kernel. Instead remove all the work that was being done at resume time and undo the change that was issuing a warm reset to all ports at suspend time. The bad device behavior will be dealt with at the kernel level to handle devices that get stuck in polling state after enable/disable sequence. BUG=chrome-os-partner:22754 BRANCH=falco,peppy,wolf,leon TEST=manual: suspend/resume with several misbehaving devices: Kingston USB3 Media Reader Transcend USB3 Media Reader Various ADATA USB3 drives Various Kingston USB3 sticks Original-Change-Id: I0894454af42d2ced456fe0da921d74c9e74902d0 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/170107 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit c2abb4d0dad6ed00e1e230d604c4c0a76eb4eef7) Change-Id: Ib215d9c230f90a1c9f34bf29254bb9feec28c67e Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/170578 [pm: rebase to master branch of coreboot upstream] Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/6016 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-11kontron/ktqm77: Clean up int15 handlerPatrick Georgi
Worked out the purpose of more int15 calls and let them return appropriate values. Also remove handlers for copy-pasted calls never observed on this board. Change-Id: I3d8c4ec5542bd19baca1dca83badc9b568779e1b Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/6249 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-11kontron/ktqm77: Improve W83627DHG's GPIO configNico Huber
Fix some outputs of the super i/o that should be GPIOs and make variables out of magic values that configure LVDS. Change-Id: Ib9eef065980cefff0046485549a68cf8f070d5b9 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/6248 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-11YABEL: Initialize global `biosmem` pointer for VBENico Huber
The global pointer `biosmem` defined in vbe.c was never set. Thus, VBE calls didn't work within YABEL. Change-Id: I63c1c77755f9c442cfec227a495332595ce2b70c Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/6250 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-11southbridge/amd/rsXY0/cmn.c: Trivial - Style fixesEdward O'Callaghan
Remove some ASCII art past 80 columns. Change-Id: I00ad79f2e1ddd78935efcfab19d9e166f0349ae3 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6155 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-11src: Make use of 'CEIL_DIV(a, b)' macro across treeEdward O'Callaghan
The objective here is to tighten coreboot up a bit by not repeating common helpers. This makes the code base more consistent and unified/tight. Change-Id: Ia163eae68b4a84a00ed118125e70308fab1cea0c Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6215 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-07-11vendorcode/amd/agesa/f15tn: Fix erratum #712Rudolf Marek
Implement the fix for the erratum #712. - Processor May Hang During Graphics Memory Controller Sequencing The processor may hang during a graphics memory controller (GMC) sleep state transitioning. The failure may be processor specific and may be sensitive to temperature. Potential Effect on System: System hang. Suggested Workaround: BIOS should set D18F2x408_dct[1:0] bit 31 = 1b. See Publication # 48931 Revision: 3.08 Change-Id: I4346fd4ef3cf554ffdaaad5ab6fc84e73532e885 Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Reviewed-on: http://review.coreboot.org/6216 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <gaumless@gmail.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-10build system: avoid more race conditionsPatrick Georgi
In an abuild run, cbfstool is built in a shared directory using "make tools". Unfortunately the build system doesn't actually use that binary directly but creates a per-board copy (for convenience purposes when editing the image later) and uses that. With this change the build system uses the original file but still creates the copy for the user, avoiding the race while ensuring convenience. Change-Id: I38c603a7eca5ef859875ad3031bf7a850189645f Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/6242 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-07-10libpayload: Drop obsolete setting of reg_base in [oex]hciNico Huber
Setting of `controller->reg_base` is of no use here, as it is never read (in another function) later. Looks like this pattern originated from uhci.c where it makes sense. By removing the indirection through `reg_base` we also fix a possible truncation to u32. Change-Id: I5c99c5bf1f5b1d6c04bd84d87fd3e275fd7d0411 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/6251 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-10libpayload: Catch null-pointer dereference in xHCINico Huber
Fix a possible null-pointer dereference (hopefully) before anyone runs into this. Also don't switch ports to xHCI if initialization failed. Change-Id: I5dbaeb435a98ead0b50d27fde13c9f1433ea3e81 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/6245 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-07-10libpayload: xHCI: Always initialize controller->pcidevNico Huber
As the controller structure is never fully cleared, this one wasn't initialized for non-pci controllers (but checked for non-null later). Change-Id: I852671c5f55650bdb6cd97f4ec74b1f95ee894c7 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/6246 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-07-10libpayload: Use unsigned long for BARs in *hci_init()Nico Huber
Using void* for physical addresses leads to much casting and confuses developers when to convert from physical to virtual addresses or the other way around. When using plain integers for physical addresses and pointers for virtual addresses things become much cleaner and we won't ever end up dereferencing a physical address. Change-Id: I24cd53b81c7863b6d14f0cbb4ce8937728b37c1c Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/6244 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-10libpayload: Keep physical addresses in console driversNico Huber
Like done in FILO, libpayload's console drivers might be initialized before a relocation. So keep physical pointers in there which won't break on relocation. Change-Id: I52e5d9d26801a53fd6a5f3c7ee03f61d6941d736 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/6247 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-07-10libpayload: Remove redundant phys_to_virt() from xHCI driverNico Huber
Remove a redundant phys_to_virt() that sneaked in the initialization of PCI xHCI controllers. The use of casts from void* to u32 (and vice versa) prompts for things going wrong here. That will be addressed in a later commit. Change-Id: Ibc71ed6ee7016529c0e3a51559aaec07aaaba315 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/6243 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-07-10include/stdlib.h: Extend common macro collectionEdward O'Callaghan
Add the following useful macros: * Absolute Value Macro * Taking ceiling of (a / b) * Check if value x is a power of 2 or not Change-Id: I4e9a326aea3cdd963f13548d1fb63331a57d84b1 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6198 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-10AGESA Hudson: Fix build without HAVE_ACPI_RESUMEKyösti Mälkki
If one commented out HAVE_ACPI_RESUME in Kconfig file for a board using agesa/hudson the build failed. Change-Id: Ifbad8f6e23ce4b5431e596bf67e6ab108fedb4ce Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6253 Reviewed-by: Dave Frodin <dave.frodin@se-eng.com> Tested-by: build bot (Jenkins)
2014-07-10northbridge/amd: Fix the family15tn option rom mappingDave Frodin
Family15tn video bioses internal have a PCI ID of 1002/9901. The vendor/device mapping in the family15tn/northbridge.c file needs to map to 1002/9901 and not to 1002/9900. This was tested on the amd/parmer mainboard. Change-Id: I0153e9b522e847099c6054d91bf73b50966ed838 Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/6252 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-10intel/haswell: add vmx support w/Kconfig optionMatt DeVillier
patch based on VMX support in intel/fsp_model_206ax and intel/model_6fx tested/verified working on google/panther Change-Id: I61232fdc2a29c53aa3bea5ea78b2fdc41fd7396a Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: http://review.coreboot.org/6223 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-10vendorcode/amd/agesa/f14: Trivial - drop whitespaces in .hEdward O'Callaghan
Change-Id: Ic63c456e775ad0863ea773abd957d9399e8e2a13 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6191 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-07-10vendorcode/amd/agesa/f14: Trivial - drop trailing whitespacesEdward O'Callaghan
Change-Id: I716253fe8532a4215e5770cd901ee3b3c4963d3d Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6187 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-07-10vendorcode/amd/agesa/f12: Trivial - drop whitespaces in .hEdward O'Callaghan
Change-Id: Iace2ccfe95bd7f7e5dabbbc69ee4249d80d1cb84 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6190 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-07-10vendorcode/amd/agesa/f12: Trivial - drop trailing whitespacesEdward O'Callaghan
Change-Id: Ieca3358a2a459016b7a38dce7f717100b55baba5 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6186 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-07-10vendorcode/amd/agesa/f10: Trivial - drop whitespaces in .hEdward O'Callaghan
Change-Id: Ie8d74970ef8969cf65b40970cb234399c3db8e56 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6189 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-07-10vendorcode/amd/agesa/f10: Trivial - drop trailing whitespacesEdward O'Callaghan
Change-Id: I8f4b2b555d71dd30f134e41ce998c946c4ac0280 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6185 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-26 08:22:36 +0000