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2017-03-13soc/intel/apollolake: Fix unsigned warningsLee Leahy
Fix the following warning detected by checkpatch.pl: WARNING: Prefer 'unsigned int' to bare use of 'unsigned' TEST=Build for reef Change-Id: Ifc45ce90d466d087cd20af72ddfc8486d2f1492c Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/18724 Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-13soc/intel/apollolake: Remove unnecessary bracesLee Leahy
Fix the following warnings detected by checkpatch.pl: WARNING: braces {} are not necessary for any arm of this statement WARNING: braces {} are not necessary for single statement blocks TEST=Build for reef Change-Id: Ifab09c023faa7da215945f1aedd391f4b2a1a04c Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/18723 Tested-by: build bot (Jenkins) Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-13soc/intel/apollolake: Indent code using tabsLee Leahy
Fix the following error and warnings detected by checkpatch.pl: ERROR: code indent should use tabs where possible WARNING: please, no spaces at the start of a line WARNING: please, no space before tabs TEST=Build for reef Change-Id: Id7a758463b95274c5e8bbdd67da0955f1ae78aac Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/18721 Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-13soc/intel/apollolake: Fix spacing around operators and commasLee Leahy
Fix the following errors detected by checkpatch.pl: ERROR: spaces required around that '==' (ctx:VxO) ERROR: space required before that '-' (ctx:OxV) ERROR: spaces required around that '=' (ctx:VxW) ERROR: spaces required around that '=' (ctx:WxV) ERROR: spaces required around that '=' (ctx:VxV) ERROR: need consistent spacing around '+' (ctx:VxW) ERROR: space prohibited before that '++' (ctx:WxB) ERROR: space prohibited before that ',' (ctx:WxW) ERROR: space required after that ',' (ctx:VxV) TEST=Build for reef Change-Id: I37265a69fcb14fbf7c182ef29d823f70a5748ad8 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/18720 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-13soc/intel/apollolake: Fix space between type, * and variable nameLee Leahy
Fix the following errors detected by checkpatch.pl: ERROR: "foo * bar" should be "foo *bar" ERROR: "(foo*)" should be "(foo *)" TEST=Build for reef Change-Id: I4a762d8fa762057a06e601dfed10538adc5d8bc8 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/18719 Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-13soc/intel/apollolake: Move brace to beginning of lineLee Leahy
Fix the following error detected by checkpatch.pl: ERROR: open brace '{' following function declarations go on the next line TEST=Build for reef Change-Id: Icb92dc49c6e7b8dfea60bc0395f3db7316c4e34c Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/18722 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-13src/include: Wrap lines at 80 columnsLee Leahy
Fix the following warning detected by checkpatch.pl: WARNING: line over 80 characters Changed a few comments to reduce line length. File src/include/cpu/amd/vr.h was skipped. TEST=Build and run on Galileo Gen2 Change-Id: Ie3c07111acc1f89923fb31135684a6d28a505b61 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18687 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-13src/include: Add space after minus signLee Leahy
Fix the following error detected by checkpatch.pl: ERROR: need consistent spacing around '-' (ctx:WxV) TEST=Build and run on Galileo Gen2 Change-Id: Ib4c2c0c19dee842b7cd4da11a47215dc2f124374 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18686 Tested-by: build bot (Jenkins) Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-13src/include: Remove use of binary constantsLee Leahy
Fix the following warning detected by checkpatch.pl: WARNING: Avoid gcc v4.3+ binary constant extension: <...> TEST=Build and run on Galileo Gen2 Change-Id: Iab29c494060df3f60eff5317259e0fdbfea06f27 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18685 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-13src/include: Add spaces around :Lee Leahy
Fix the following error detected by checkpatch.pl: ERROR: spaces required around that ':' (ctx:ExV) TEST=Build and run on Galileo Gen2 Change-Id: Idb2ea29a6c7277b319e6600e8a9d7cb8285ae5df Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18684 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-13src/include: Fix indent for case labelsLee Leahy
Fix the following error detected by checkpatch.pl: ERROR: switch and case should be at the same indent TEST=Build and run on Galileo Gen2 Change-Id: I92f00254c7fcb79a5ecd4ba5e19a757cfe5c11fa Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18683 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-13src/include: Move constants to the right hand sideLee Leahy
Fix the following warning detected by checkpatch.pl: WARNING: Comparisons should place the constant on the right side of the test TEST=Build and run on Galileo Gen2 Change-Id: Id790e0034ea5c926fcaef95486319d6c0c936f28 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18682 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-13src/lib: Move asmlinkage before typeLee Leahy
Fix the following warning detected by checkpatch.pl: WARNING: storage class should be at the beginning of the declaration TEST=Build and run on Galileo Gen2 Change-Id: I7d3135466634a4bb84dcef16dbd68754f8d8d6c2 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18760 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-13src/lib: Fix brace positionsLee Leahy
Fix the following errors detected by checkpatch.pl: ERROR: open brace '{' following function declarations go on the next line ERROR: that open brace { should be on the previous line ERROR: open brace '{' following struct go on the same line ERROR: else should follow close brace '}' TEST=Build and run on Galileo Gen2 Change-Id: I971ada9ba9ba7ce5d8029323710fee1a6166570b Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18759 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-13src/include: Remove space between function name and parametersLee Leahy
Fix the following warning detected by checkpatch.pl: WARNING: Unnecessary space before function pointer arguments TEST=Build and run on Galileo Gen2 Change-Id: I2b56af20d5f74cc2625d3cb357fbb137bd440af0 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18660 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-13src/lib: Wrap lines at 80 columnsLee Leahy
Fix the following warning detected by checkpatch.pl: WARNING: line over 80 characters TEST=Build and run on Galileo Gen2 Change-Id: I5fa3f8e950e2f0c60bd0e8f030342dc8c0469299 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18758 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-13src/include: Move assignment out of if conditionLee Leahy
Fix the following error detected by checkpatch.pl: ERROR: do not use assignment in if condition TEST=Build and run on Galileo Gen2 Change-Id: I911d528bd85afcd9f3837241494f13d1f9f283ab Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18659 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-13src/include: Remove unnecessary typecastLee Leahy
Fix the following warning detected by checkpatch.pl: WARNING: Unnecessary typecast of c90 int constant TEST=Build and run on Galileo Gen2 Change-Id: I137efa55e945d1315322df2a38d70716a3807a1e Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18658 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-13src/include: Move storage class to beginning of declarationLee Leahy
Fix the following warning detected by checkpatch.pl: WARNING: storage class should be at the beginning of the declaration The following storage class attribute is not detected by checkpatch.py: static cbmem_init_hook_t init_fn_ ## _ptr_ __attribute__((used, \ section(".rodata.cbmem_init_hooks"))) = init_fn_; The following lines generates a false positive: (pound)define STATIC static src/include/cpu/amd/common/cbtypes.h:60: WARNING: storage class should be at the beginning of the declaration typedef asmlinkage void (*smm_handler_t)(void *); src/include/cpu/x86/smm.h:514: WARNING: storage class should be at the beginning of the declaration (pound)define MAYBE_STATIC static src/include/stddef.h:34: WARNING: storage class should be at the beginning of the declaration TEST=Build and run on Galileo Gen2 Change-Id: Ie087d38e6171b549b90e0b831050ac44746a1e14 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18657 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-13src/include: Remove space after function nameLee Leahy
Fix the following warning detected by checkpatch.pl: WARNING: space prohibited between function name and open parenthesis '(' TEST=Build and run on Galileo Gen2 Change-Id: I0ac30b32bab895ca72f91720eeae5a5067327247 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18656 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-13src/include: Fix space between type, * and variable nameLee Leahy
Fix the following errors detected by checkpatch.pl: ERROR: "foo * bar" should be "foo *bar" ERROR: "foo* bar" should be "foo *bar" ERROR: "foo*bar" should be "foo *bar" TEST=Build and run on Galileo Gen2 Change-Id: I5a3ff8b92e3ceecb4ddf45d8840454d5310fc6b3 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18655 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
2017-03-13src/lib: Fix spacingLee Leahy
Fix the following errors and warnings detected by checkpatch.pl: ERROR: spaces required around that '?' (ctx:WxV) ERROR: spaces required around that '=' (ctx:VxV) ERROR: spaces required around that '<' (ctx:VxV) ERROR: spaces required around that '+=' (ctx:VxV) ERROR: space required after that ',' (ctx:VxV) ERROR: space required before the open brace '{' ERROR: space required after that close brace '}' ERROR: need consistent spacing around '+' (ctx:WxV) ERROR: need consistent spacing around '*' (ctx:WxV) ERROR: need consistent spacing around '&' (ctx:VxW) ERROR: spaces required around that '?' (ctx:VxW) ERROR: spaces required around that ':' (ctx:VxW) ERROR: trailing whitespace ERROR: space prohibited before that '++' (ctx:WxO) ERROR: space prohibited before that ',' (ctx:WxW) ERROR: space prohibited after that '!' (ctx:BxW) ERROR: spaces prohibited around that '->' (ctx:VxW) ERROR: space prohibited after that '-' (ctx:WxW) WARNING: space prohibited before semicolon WARNING: unnecessary whitespace before a quoted newline WARNING: missing space after return type Note that lib/libgcov.c and lib/lzmadecode.c are providing false positives for ERROR: need consistent spacing around '*' (ctx:WxV) An example is: void __gcov_merge_add(gcov_type *counters __attribute__ ((unused)), unsigned int n_counters __attribute__ ((unused))) {} TEST=Build and run on Galileo Gen2 Change-Id: I0016327a5754018eaeb25bedf42338291632c7c1 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18733 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-13nvramcui: Add USB supportNicola Corna
Enable the USB during the initialization of nvramcui. Without it the USB keyboards don't work, which makes this payload pointless on the systems where a PS/2 keyboard port isn't available. Based on https://review.coreboot.org/#/c/17507/ Change-Id: I04697c5f582b41e6f6ffe98955bf59f4fe57f66e Signed-off-by: Nicola Corna <nicola@corna.info> Reviewed-on: https://review.coreboot.org/18765 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2017-03-13util/superiotool: Add support for Fintek F71808ANicola Corna
Default values taken from the datasheet and from the dump of an uninitialized F71808A on a Sapphire Pure Platinum H61. Both the control registers and the HWM configuration registers are added. Change-Id: Ia6e2a7c13a5086d19ebdb426f2f975b43220a273 Signed-off-by: Nicola Corna <nicola@corna.info> Reviewed-on: https://review.coreboot.org/18562 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2017-03-13soc/intel/common: Remove parenthesisLee Leahy
Fix the following error detected by checkpatch.pl: ERROR: return is not a function, parentheses are not required TEST=Build and run on Galileo Gen2 Change-Id: Idf7723d4fd48124a26bbb626afc310820f859f66 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18757 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-03-13soc/intel/common: Fix unsigned warningsLee Leahy
Fix the following warning detected by checkpatach.pl: WARNING: Prefer 'unsigned int' to bare use of 'unsigned' TEST=Build and run on Galileo Gen2 Change-Id: Ic266c077eb115e0c7d934c15bcc4cc9b9e530a39 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18756 Tested-by: build bot (Jenkins) Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-03-13soc/intel/common: Fix spacing issuesLee Leahy
Fix the following errors detected by checkpatch.pl: ERROR: spaces required around that '=' (ctx:VxV) ERROR: spaces required around that ':' (ctx:VxW) ERROR: space required after that ',' (ctx:VxV) ERROR: space required before the open parenthesis '(' ERROR: switch and case should be at the same indent ERROR: "foo ** bar" should be "foo **bar" TEST=Build and run on Galileo Gen2 Change-Id: I52ba2a3c1e0fffad7145eecd878aba8dc450ac0b Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18755 Tested-by: build bot (Jenkins) Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-03-13soc/intel/common: Indent code with tabsLee Leahy
Fix the following error detected by checkpatch.pl: ERROR: code indent should use tabs where possible TEST=Build and run on Galileo Gen2 Change-Id: I61c4f01216cb6c788cf6da988c414bbb9648d502 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18754 Tested-by: build bot (Jenkins) Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-03-13src/lib: Use tabs instead of spacesLee Leahy
Fix the following errors and warnings detected by checkpatch.pl: ERROR: code indent should use tabs where possible ERROR: switch and case should be at the same indent WARNING: Statements should start on a tabstop WARNING: please, no spaces at the start of a line WARNING: please, no space before tabs WARNING: suspect code indent for conditional statements WARNING: labels should not be indented TEST=Build and run on Galileo Gen2 Change-Id: Iebcff26ad41ab6eb0027b871a1c06f3b52dd207c Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18732 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-12google/poppy: Enable internal pull-up on PWRBTN#Shobhit Srivastava
Enable an internal pull-up on the power button input as short press is resulting in power button override being asserted. BUG=b:36111214 BRANCH=none TEST=tested on poppy board to ensure quick power button press does not result in a shutdown due to power button override. Change-Id: I3a25b78562e2302b6f7575e64c87ae8142690701 Signed-off-by: Shobhit Srivastava <shobhit.srivastava@intel.com> Reviewed-on: https://review.coreboot.org/18734 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-03-12src/lib: Remove space between function name and (Lee Leahy
Fix the following warning detected by checkpatch.pl: WARNING: space prohibited between function name and open parenthesis '(' TEST=Build and run on Galileo Gen2 Change-Id: I8f3c79302dc5eb1861ffb245617a27addf8653ef Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18731 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-12src/lib: Move trailing statements to next lineLee Leahy
Fix the following error detected by checkpatch.pl: ERROR: trailing statements should be on next line The remaining error is a false positive in libgcov.c where the if statement spans several lines with conditional compilation directives intertwined. TEST=Build and run on Galileo Gen2 Change-Id: I37fcef78e9323340bac1367ae1c5fde334f5ce10 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18730 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-12src/include: Remove braces for single statementsLee Leahy
Fix the following warning detected by checkpatch.pl: WARNING: braces {} are not necessary for single statement blocks TEST=Build and run on Galileo Gen2 Change-Id: I00b59f6a27c3acb393deaa763596363b7e958efd Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18654 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-03-12src/include: Open brace on same line as enum or structLee Leahy
Fix the following errors and warning detected by checkpatch.pl: ERROR: open brace '{' following enum go on the same line ERROR: open brace '{' following struct go on the same line ERROR: that open brace { should be on the previous line WARNING: missing space after struct definition TEST=Build and run on Galileo Gen2 Change-Id: I856235d0cc3a3e59376df52561b17b872b3416b2 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18653 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-03-12src/include: Remove spaces before tabsLee Leahy
Fix the following warning detected by checkpatch.pl: WARNING: please, no space before tabs TEST=Build and run on Galileo Gen2 Change-Id: If60a58021d595289722d1d6064bea37b0b0bc039 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18652 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-12src/include: Remove spaces before ( and after )Lee Leahy
Fix the following error messages found by checkpatch.pl: ERROR: space prohibited after that open parenthesis '(' ERROR: space prohibited before that close parenthesis ')' TEST=Build and run on Galileo Gen2 Change-Id: I2a9a0df640c51ff3efa83dde852dd6ff37ac3c06 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18651 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-11lenovo/t400/dock.c: Fix issues found by checkpatch.plPaul Menzel
Change-Id: If7ebab8af1ae0c048cb89c2feb5f6a65848b6952 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/18767 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-03-11lenovo/t400: Rewrite dock from t60Kyösti Mälkki
Old dock.c copied from x201 was incorrect. Do a rewrite of t60 dock code as pnp devices. Fixes USB and serial on the dock, if it is already connected when computer is powered on. DVI and ethernet worked without this patch. Hot-plug is yet to be fixed. Change-Id: Ib20a0eff10d0cde92dd089baf4fca28b117dc999 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18054 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2017-03-10src/include: Add space after +Lee Leahy
Fix the following error detected by checkpatch.pl: ERROR: need consistent spacing around '+' (ctx:WxV) Test: Build and run on Galileo Gen2 Change-Id: Idd5f2a6d8a3c8db9c1a127ed75cec589929832e3 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18650 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-10src/include: Add parenthesis around macrosLee Leahy
Fix the following error found by checkpatch.pl: ERROR: Macros with complex values should be enclosed in parentheses False positives are detected for attribute macros. An example is: ERROR: Macros with complex values should be enclosed in parentheses +#define BOOT_STATE_INIT_ATTR __attribute__ ((used, section (".bs_init"))) False positive also generated for macros for linker script files. An example is: ERROR: Macros with complex values should be enclosed in parentheses +#define CBFS_CACHE(addr, size) \ + REGION(cbfs_cache, addr, size, 4) \ + ALIAS_REGION(cbfs_cache, preram_cbfs_cache) \ + ALIAS_REGION(cbfs_cache, postram_cbfs_cache) False positives generated for assembly code macros. An example is: ERROR: Macros with complex values should be enclosed in parentheses +#define DECLARE_OPTIONAL_REGION(name) asm (".weak _" #name ", _e" #name ) False positive detected when macro includes multiple comma separated values. The following code is from src/include/device/azalia_device.h: #define AZALIA_SUBVENDOR(codec, val) \ (((codec) << 28) | (0x01720 << 8) | ((val) & 0xff)), \ (((codec) << 28) | (0x01721 << 8) | (((val) >> 8) & 0xff)), \ (((codec) << 28) | (0x01722 << 8) | (((val) >> 16) & 0xff)), \ (((codec) << 28) | (0x01723 << 8) | (((val) >> 24) & 0xff)) TEST=Build and run on Galileo Gen2 Change-Id: I6e3b6950738e6906851a172ba3a22e3d5af1e35d Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18649 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-10src/include: Add space before (Lee Leahy
Fix the following error detected by checkpatch.py: ERROR: space required before the open parenthesis '(' TEST=Build and run on Galileo Gen2 Change-Id: I6969e63f750f327afff1a0efa1aab56d477af0df Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18645 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-10commonlib: Remove space after *Lee Leahy
Fix the following error detected by checkpatch.pl: ERROR: "foo * bar" should be "foo *bar" TEST=Build and run on Galileo Gen2 Change-Id: If68dfa2b49c61d574f35192f94d1a6642069fa7f Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18752 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-03-10commonlib: Fix issues with { } and elseLee Leahy
Fix the following errors and warning detected by checkpatch.pl: ERROR: open brace '{' following struct go on the same line ERROR: else should follow close brace '}' WARNING: else is not generally useful after a break or return False positives are detected for the following checkpatch.pl error. ERROR: that open brace { should be on the previous line These false positives are in cbfs.c for two function definitions. TEST=Build and run Galileo Gen2 Change-Id: Ic679ff3a2e1cfc0ed52073c20165e05bf21d76f3 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18750 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-03-10commonlib: Wrap lines at 80 columnsLee Leahy
Fix the following error detected by checkpatch.pl: ERROR: code indent should use tabs where possible TEST=Build and run on Galileo Gen2 Change-Id: I3a44a02d4cd1be6b2bb2f52fc832e673a580e562 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18749 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-03-10commonlib: Fix spacing issuesLee Leahy
Fix the following errors and warnings detected by checkpatch.pl: ERROR: space required after that ',' (ctx:VxV) ERROR: space required after that ';' (ctx:VxV) ERROR: space prohibited after that open parenthesis '(' ERROR: space prohibited before that close parenthesis ')' WARNING: please, no spaces at the start of a line WARNING: please, no space before tabs TEST=Build and run on Galileo Gen2 Change-Id: I54877f60eb5fdf3f6d8729711c55ff5a284d22cf Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18748 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-03-10drivers/intel/fsp2_0: Switch from binary to decimalLee Leahy
Fix the following warning detected by checkpatch.pl: WARNING: Avoid gcc v4.3+ binary constant extension: TEST=Build and run on Galileo Gen2 Change-Id: Ied50b94ecae4d3bde5812f6b54bbe2421fd48588 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/18747 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-10drivers/intel/fsp2_0: Wrap lines at 80 columnsLee Leahy
Fix the following warning detected by checkpatch.pl: WARNING: line over 80 characters TEST=Build and run on Galileo Gen2 Change-Id: I0e5acef53d558948b7713cfe608cd346ddc5e9fe Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/18746 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-10drivers/intel/fsp2_0: Remove braces for single statementsLee Leahy
Fix the following warning detected by checkpatch.pl: WARNING: braces {} are not necessary for single statement blocks TEST=Build and run on Galileo Gen2 Change-Id: Ibd351703e60acebbacd6ae5b1a2fa1cb34fd3ff9 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/18745 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-10drivers/intel/fsp2_0: Fix spacing issuesLee Leahy
Fix the following errors detected by checkpatch.pl: ERROR: space prohibited before that close parenthesis ')' ERROR: space required before the open parenthesis '(' ERROR: space prohibited before open square bracket '[' ERROR: spaces required around that ':' (ctx:VxE) TEST=Build and run on Galileo Gen2 Change-Id: I085aaaa9e276c60eded6edf3be0325ed2402702a Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/18744 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-10drivers/intel/fsp2_0: Add space before *Lee Leahy
Fix the following error detected by checkpatch.pl: ERROR: "(foo*)" should be "(foo *)" False positives are generated by checkpatch for the following condition which is not properly detecting the variable type: ERROR: need consistent spacing around '*' (ctx:WxV) The false positives are found in debug.h and upd_display.c TEST=Build and run on Galileo Gen2 Change-Id: I0e871d64544ebf5eacbae46466cf7aefbfa701eb Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/18743 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-10drivers/intel/fsp2_0: Use tabs for indentLee Leahy
Fix the following warning detected by checkpatch.pl: WARNING: please, no spaces at the start of a line TEST=Build and run on Galileo Gen2 Change-Id: I7cb35c8b5d7ff97849e666ce7f75d4e4763bb2a7 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/18742 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-10soc/intel/common: Pass the minimum possible string length for strncpyBarnali Sarkar
In strncpy() function of dimm_info_fill(), the minimum possible size of Module Part Number of DIMM is passed as argument. BUG=chrome-os-partner:61729 BRANCH=none TEST=Build and boot KBLRVP to verify the type 17 DIMM info coming in SMBIOS Table from Kernel command "dmidecode". Change-Id: Icc7667149eae9705b91e271628af1b443eb8556e Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/18617 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-10google/sand: Add devicetree.cb file for sandKatherine Hsieh
It is a copy from baseboard/devicetree.cb (coreboot.org ToT) BUG=b:35775065 BRANCH=reef TEST=emerge-sand coreboot Change-Id: I5ba86e54ccfbf5af7bf0e9ad8fe7bf22020e48ee Signed-off-by: Katherine Hsieh <Katherine.Hsieh@quantatw.com> Reviewed-on: https://review.coreboot.org/18703 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-03-10mainboard/google/reef: Modify TCPU, TSR2 and TRT tableTim Chen
Update the DPTF parameters based on thermal test result. (ZHT_DPTF_EVT2_v0.5_20170306.xlsx) 1. Update DPTF TCPU critical trigger point. TCPU critical point: 105 2. Update DPTF TSR2 passive trigger point. TSR2 passive point: 58 3. Change thermal relationship table (TRT) setting. Change CPU Throttle Effect on CPU sample rate to 10secs. Change Charger Effect on Temp Sensor 2 sample rate to 30secs. Change CPU Effect on Temp Sensor 2 sample rate to 60secs. BUG=b:35583586 BRANCH=master TEST=build and boot on electro dut Change-Id: I85564ccdaf327eeaa13bf1f31d9a933609a21582 Signed-off-by: Tim Chen <Tim-Chen@quantatw.com> Reviewed-on: https://review.coreboot.org/18610 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-03-10soc/intel/broadwell: Rework IGD's CDClk selectionNico Huber
CDClk selection was wrong in some corner cases (e.g. ULX SKUs) and, for Broadwell, never took the devicetree config into account. Rewrite the selection with the following in mind: o cpu_is_ult() might return `true` for ULX SKUs, too, o ULX and Broadwell-ULT SKUs can be `overclocked` with additional cooling, so leave that as devicetree option. For Haswell, the following frequency selections are valid: o ULX: 337.5MHz by default, 450MHz optional o ULT: 450MHz only (maybe 337.5MHz too, documentation varies, it wasn't selectable before either) o others: 540MHz by default, 450MHz optional For Broadwell: o ULX: 450MHz by default, 337.5MHz / 540MHz optional o ULT: 540MHz by default, 337.5MHz / 450MHz / 675MHz optional o others: 667MHz by default, 337.5MHz / 450MHz / 540MHz optional Side effects: A too high setting in the devicetree results in the highest possible frequency now, Haswell non-ULT/ULX defaults to 540MHz instead of 450MHz. Change-Id: Iec12752f2a47bf4a5ae6077c75790eae9378c1b2 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/17768 Tested-by: build bot (Jenkins) Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-03-10ifdtool: Add SPI_FREQUENCY_50MHZ_30MHZ as a valid freqHannah Williams
Without this change, error "Unknown descriptor version: 4" will be returned if this frequency is selected (seen on GLKRVP) Change-Id: Ib5bfb996b85c7245d8f9c70988bfd5bbac882d74 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/18688 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-03-10soc/intel/skylake:Add _DSM method to reduce D3 cold delay for eMMC controllersowmyav
eMMC Controller is taking over 100ms to resume during runtime which results in I/O latency issues on the Skylake systems like Cave and Caroline. This patch adds _DSM method for eMMC comtroller for specifying the device readiness durations. Function index 9 returns package of five integers to set D3 cold delay to zero and ACPI constant Ones for the elements where overriding the default values is not desired. BUG=b:35774937 BRANCH=none TEST=update caroline coreboot and test i/o latency is under 100ms Change-Id: Iacc8aa8560897da8770fe559ca8cd17aaf6ebeba Signed-off-by: Sowmya V <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/18532 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-03-10device/dram/ddr2: Add common ddr2 spd decoderPatrick Rudolph
Decode DDR2 SPD similar to DDR3 SPD decoder to ease readability, reduce code complexity and reduce size of maintainable code. Rename dimm_is_registered to spd_dimm_is_registered_ddr3 to avoid compilation errors. Change-Id: I741f0e61ab23e3999ae9e31f57228ba034c2509e Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/18273 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins)
2017-03-10mainboard/google/reef: Configure SDCARD card detect pinVenkateswarlu Vinjamuri
This configures GPIO_177 as an input pin for SDCARD card detect. This also changes the ownership of the pin from ACPI to GPIO driver. Assign the sdcard card detect pin in devicetree for reef variants. CQ-DEPEND=448173 BUG=chrome-os-partner:63070 TEST=None Change-Id: Ia8aef60bd7d0ea36afb39f76fab051aa46a2ed64 Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Reviewed-on: https://review.coreboot.org/18497 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-10soc/intel/apollolake: Add PM methods to power gate SD cardVenkateswarlu Vinjamuri
This implements dynamic generation of sdcard GpioInt in SSDT. GpioInt in SSDT generation is based on the card detect GPIO if it is provided by the mainboard in devicetree. This implements GNVS variable to store the address of sdcard cd pin. GNVS used to store rxstate of the sdcard cd pin to get card presence. Add _PS0/_PS3 methods to power gate the sd card controller in S0ix and runtime PM. CQ-DEPEND=448173 BUG=chrome-os-partner:63070 TEST=Suspend and resume using 'echo freeze > /sys/power/state'. System should enter S0ix and resume with no issue. Change-Id: Id2c42fc66062f0431385607cff1a83563eaeef87 Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Reviewed-on: https://review.coreboot.org/18496 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
2017-03-10asus/m2v: Make _CRS methods serializedPaul Menzel
Address the iasl 20160108-64 (Ubuntu 16.04) warnings below. ``` Intel ACPI Component Architecture ASL+ Optimizing Compiler version 20160108-64 Copyright (c) 2000 - 2016 Intel Corporation dsdt.aml 245: Method (_CRS, 0, NotSerialized) Remark 2120 - ^ Control Method should be made Serialized (due to creation of named objects within) dsdt.aml 262: Method (_CRS, 0, NotSerialized) Remark 2120 - ^ Control Method should be made Serialized (due to creation of named objects within) dsdt.aml 277: Method (_CRS, 0, NotSerialized) Remark 2120 - ^ Control Method should be made Serialized (due to creation of named objects within) dsdt.aml 295: Method(_CRS, 0) { Remark 2120 - ^ Control Method should be made Serialized (due to creation of named objects within) ``` Change-Id: Id5b0f33fba8ea25e4a6aa4f01c69a69aaf5aef23 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/18323 Tested-by: build bot (Jenkins) Reviewed-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-10cpu/amd/agesa: Unify init filesPaul Menzel
The init files for the AMD families using the AGESA platform initialization code are quite similar. So reduce the differences, by using the same comments, variable names, console messages, and blank lines. Change-Id: Id4a3a5c3812a34627d726cdcbe8f4781a14be724 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/18507 Tested-by: build bot (Jenkins) Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-03-10.gitignore: ignore *.swo and option *.romsAlexander Couzens
Change-Id: I7403f548bae918ca813a9295bfb095a7c4c51e21 Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: https://review.coreboot.org/15220 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-10northbridge/intel/i440bx: Align codePaul Menzel
Change-Id: Idd4127f7491524121b4b65c6fb9511e2c8159912 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/18609 Tested-by: build bot (Jenkins) Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-09vboot/tpm2: enable nvmem commits on cr50 when writing firmware secdataAaron Durbin
cr50 by default delays nvmem commits internally from the point of reset to accumulate change state. However, the factory process can put a board into dev mode through the recovery screen. This state is stored in the TPM's nvmem space. When the factory process is complete a disable_dev_request and battery_cutoff_request is performed. This leads to disabling the dev mode in TPM, but the battery is subsequently cut off so the nvmem contents never stick. Therefore, whenever antirollback_write_space_firmware() is called we know there was a change in secdata so request cr50 to immediately enable nvmem commits going forward. This allows state changes to happen immediately. The fallout from this is that when secdata is changed that current boot will take longer because every transaction that writes to TPM nvmem space will perform a write synchronously. All subsequent boots do not have that effect. It should also be noted that this approach to the implementation is a pretty severe layering violation. However, the current TPM APIs don't lend themselves well to extending commands or re-using code outside of the current routines which inherently assume all knowledge of every command (in conflict with vendor commands since those are vendor-specific by definition). BUG=b:35775104 BRANCH=reef TEST=Confirmed disablement of dev mode sticks in the presence of: crossystem disable_dev_request=1; crossystem battery_cutoff_request=1; reboot; Change-Id: I3395db9cbdfea45da1f5cb994c6570978593b944 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/18681 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins)
2017-03-09drivers/spi/tpm: provide Kconfig to indicate CR50 usageAaron Durbin
Going forward it's important to note when a CR50 is expected to be present in the system. Additionally, this Kconfig addition provides symmetry with the equivalent i2c Kconfig option. BUG=b:35775104 Change-Id: Ifbd42b8a22f407534b23459713558c77cde6935d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/18680 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2017-03-09mainboard/google/reef: increase pre cbmem console size for Chrome OSAaron Durbin
verstage can be pretty chatty so bump the pre cbmem console size when building for Chrome OS so that all messages can be observed. BUG=b:35775104 BRANCH=reef TEST=Booted and noted no cutoff of console when sec data being saved. Change-Id: I0ce2976572dedf976f051c74a3014d282c3c5f4c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/18679 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-03-09lib/tpm2_marshaling: fix in correct buffer space semanticsAaron Durbin
marshal_blob() was setting an unsigned size (size_t) to a value of -1 when an error is determined. This is wrong for the current implementation of the code because the code assumes the buffer space gets set to 0. Setting an unsigned value to -1 effectively tells the library the buffer has unlimited amount of space. BUG=b:35775104 Change-Id: I677a1fd7528bef3ea7420d0a8d0a290e9b15cea3 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/18678 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2017-03-09google/poppy: Configure SRCCLKREQ4 as No ConnectNaresh G Solanki
SRCCLKREQ4 is unused, so configure SRCCLKREQ4 as NC (No Connect). Change-Id: I6e265b9c9faa0df20208bb82278cadbbbbe6c537 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/18589 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-03-09elog: Add all EC event codesFurquan Shaikh
Add the missing EC event codes in elog.h and correct the event code value for RECOVERY_HWREINIT. Change-Id: If9fb319cce1e4acce4b3d7c3a39365986856a9b4 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/18693 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-03-09src/lib: Add space before (Lee Leahy
Fix the following error detected by checkpatch.pl: ERROR: space required before the open parenthesis '(' TEST=Build and run on Galileo Gen2 Change-Id: I8953fecbe75136ff989c9e3cf6c5e155dcee3c3b Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18698 Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-03-09src/lib: Remove braces for single statementsLee Leahy
Fix the following warning detected by checkpatch.pl: WARNING: braces {} are not necessary for single statement blocks TEST=Build and run on Galileo Gen2 Change-Id: Ie4b41f6fb75142ddd75103a55e0347ed85e7e873 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18697 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins)
2017-03-09src/lib: Fix space between type, * and variable nameLee Leahy
Fix the following errors detected by checkpatch.pl: ERROR: "foo* bar" should be "foo *bar" ERROR: "(foo*)" should be "(foo *)" ERROR: "foo * const * bar" should be "foo * const *bar" TEST=Build and run on Galileo Gen2 Change-Id: I0d20ca360d8829f7d7670bacf0da4a0300bfb0c1 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18696 Tested-by: build bot (Jenkins) Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-03-09src/lib: Add "int" following "unsigned"Lee Leahy
Fix the following warning detected by checkpatch.pl: WARNING: Prefer 'unsigned int' to bare use of 'unsigned' The remaining 37 warnings in gcov-io.c and libgcov.c are all false positives generated by checkpatch detecting a symbol or function name ending in _unsigned. TEST=Build and run on Galileo Gen2 Change-Id: I9f1b71993caca8b3eb3f643525534a937d365ab3 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18695 Tested-by: build bot (Jenkins) Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-03-09google/pyro: Update DPTF settingsKevin Chiu
1. Update DPTF TSR1 passive trigger points. TSR1 passive point: 50 2. Update DPTF PL1 Minimum PL1 min: 2.5W BUG=b:35586881 BRANCH=reef TEST=emerge-pyro coreboot Change-Id: Ia2634f40098d026c4d228fab4b7c05501c1ff05f Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/18699 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-03-09src/include: Remove space after &Lee Leahy
Fix the following error detected by checkpatch.pl: ERROR: space prohibited after that '&' (ctx:ExW) TEST=Build and run on Galileo Gen2 Change-Id: Ied8b4c00fc57a35ed4d649264a5ff1b8dcc6a1cd Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18648 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-09src/include: Add space after commaLee Leahy
Fix the following error detected by checkpatch.pl: ERROR: space required after that ',' (ctx:VxV) TEST=Build and run on Galileo Gen2 Change-Id: I297bfc3d03dc95b471d3bb4b13803e81963841b5 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18647 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-09src/include: Indent code using tabsLee Leahy
Fix the following error and warning detected by checkpatch.pl: ERROR: code indent should use tabs where possible WARNING: please, no spaces at the start of a line TEST=Build and run on Galileo Gen2 Change-Id: I487771b8f4d7e104457116b772cd32df5cd721a6 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18646 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-09src/include: Add do { } while(0) around macrosLee Leahy
Fix the following error detected by checkpatch.py: ERROR: Macros with multiple statements should be enclosed in a do - while loop False positives are generated when assembly code is used in a macro. An example is: ERROR: Macros with multiple statements should be enclosed in a do - while loop +#define post_code(value) \ + movb $value, %al; \ + outb %al, $CONFIG_POST_IO_PORT False positives are also generated for linker script include files. An example is: ERROR: Macros with multiple statements should be enclosed in a do - while loop +#define SET_COUNTER(name, addr) \ + _ = ASSERT(. <= addr, STR(name overlaps the previous region!)); \ + . = addr; False positives are also generated for attribute macros. An example is: ERROR: Macros with multiple statements should be enclosed in a do - while loop +#define DISABLE_TRACE_ON_FUNCTION __attribute__ ((no_instrument_function)); TEST=Build and run on Galileo Gen2 Change-Id: I88abf96579e906f6962d558a3d09907f07d00b1c Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18644 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-09src/include: Move trailing statements to next lineLee Leahy
Fix the following error detected by checkpatch.pl: ERROR: trailing statements should be on next line TEST=Build and run on Galileo Gen2 Change-Id: I169f520db6f62dfea50d2bb8fb69a8e8257f86c7 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18643 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-09src/include: Fix unsigned warningsLee Leahy
Fix warning detected by checkpatch.pl: WARNING: Prefer 'unsigned int' to bare use of 'unsigned' BRANCH=none BUG=None TEST=Build and run on Galileo Gen2 Change-Id: I23d9b4b715aa74acc387db8fb8d3c73bd5cabfaa Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18607 Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-09soc/intel/skylake: Add GPIO macros for IOxAPIC and SCILi Cheng Sooi
Add two GPIO macros: 1. PAD_CFG_GPI_APIC_EDGE allows a pin to be route to the APIC with input assuming the events are edge triggered. 2. PAD_CFG_GPI_ACPI_SCI_LEVEL to route the general purpose input to SCI assuming the events are level triggered. Change-Id: I944a9abac66b7780b2336148ae8c7fa3a8410f3f Signed-off-by: Rahul Kumar Gupta <rahul.kumarxx.gupta@intel.com> Reviewed-on: https://review.coreboot.org/18533 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-03-09soc/intel/skylake: Add SKL SOC PCH H GPIO supportLi Cheng Sooi
Add SKL/KBL PCH-H GPIO settings referring from SKL PCH-H specifications to support sklrvp11. Split the gpio_defs.h into headers gpio_pch_h_defs.h and gpio_soc_defs.h for PCH-H specific and SOC specific GPIO defs respectively. Change-Id: I5eaf8d809a1244a56038cbfc29502910eb90f9f2 Signed-off-by: Li Cheng Sooi <li.cheng.sooi@intel.com> Signed-off-by: Rahul Kumar Gupta <rahul.kumarxx.gupta@intel.com> Reviewed-on: https://review.coreboot.org/18027 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-09AGESA: Use printk for IDS outputKyösti Mälkki
In all simplicity, with board/OptionsIds.h file having: IDSOPT_IDS_ENABLED TRUE IDSOPT_TRACING_ENABLED TRUE And src/Kconfig modified to: config WARNINGS_ARE_ERRORS default n With these settings AGESA outputs complete debugging log where-ever you have your coreboot console configured. Change-Id: Ie5c0de6358b294160f9bf0a202161722f88059c1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15320 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins)
2017-03-09AGESA f15: Disable IDS tracing by defaultKyösti Mälkki
We build with WARNINGS_ARE_ERRORS, while IDS tracing will raise various (non-fatal) printk() format warnings. Change-Id: I9dc81c89ee60d17a6556a412380fed1413af66bd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18560 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-03-09AGESA: Make eventlog more tolerant to failuresKyösti Mälkki
We have been forced to build AGESA with ASSERT() as non-fatal for some board, as hitting those errors is not uncommon. For the cases touched here, abort eventlog operations early to avoid further errors and dereference of null pointers. Change-Id: I1a09ad55d998502ad19273cfcd8d6588d85d5e0c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18543 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-03-09AGESA: Fix loop condition for eventlog readKyösti Mälkki
Do not evaluate AmdEventParams if AmdReadEventLog() fails. Change-Id: I2b8afe827ffe6757e64c00ab005d3bb8cc577321 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18611 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-03-09AGESA: Apply a threshold on event loggingKyösti Mälkki
Implement threshold as described in AMD.h, and do not add entries below STATUS_LOG_LEVEL in the eventlog. Change-Id: Ic9e45b1473b4fee46a1ad52d439e8682d961dc03 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18542 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-03-09AGESA: Log heap initialisationKyösti Mälkki
This is useful for debugging S3 issues and in general to understand AGESA memory allocator behaviour. Change-Id: I422f2620ed0023f3920b8d2949ee1c33a6c227e0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18535 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins)
2017-03-09AGESA: Log if memory training result cannot be storedKyösti Mälkki
A problem around CAR teardown time may result with missing training results at the time we want to save them. Record this in the logs for debugging purposes, it will not be possible to use S3 suspend if this happens. Change-Id: Id2ba8facbd5d90fe3ed9c6900628309c226c2454 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18534 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-03-09AGESA: Fix SSE regression and align stack earlyKyösti Mälkki
When allowing use of SSE instructions, stack must be aligned to 16 bytes. Adjust x86 entry to C accordingly, by pushing values to maintain the alignment. Fixes regression with new toolchain using GCC-6.3 and ec0a393 console: Enable printk for ENV_LIBAGESA For some builds, the above-mentioned commit emitted SSE instruction 'andps (%esp),%xmm0' with incorrectly aligned esp, raising exception and thus preventing boot. Change-Id: Ief57a2ea053c7497d50903838310b7f7800bff26 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18622 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-03-09toolchain: fix compilation of GMP on FreeBSDIdwer Vollering
Built on FreeBSD -CURRENT Obtained from FreeBSD: https://github.com/freebsd/freebsd-ports/commit/bbedec80e36fe22a4f55433c3e6c2a64828fd9da Change-Id: Ic6b6db8e3a9d86a30c50a09d58566846446031ea Signed-off-by: Idwer Vollering <vidwer@gmail.com> Reviewed-on: https://review.coreboot.org/18675 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-03-09cpu/intel/model_6{e,f}x: Unify init filesPaul Menzel
The init files for the Core Duo and Core 2 Duo are very similar. Reduce the differences, by using the same order for the include statements, the same blank lines, and the same comments. Change-Id: I0de060222a61a482377c760c6031d73c7e318edf Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/18506 Tested-by: build bot (Jenkins) Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-09mainboard/google/poppy: Enable cros_ec_keyb deviceFurquan Shaikh
This is required to transmit button information from EC to kernel. BUG=b:35774934 BRANCH=None TEST=Verified using evtest that kernel is able to get button press/release information from EC. Change-Id: I8f380f935c2945de9d8e72eafc877562987d02db Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/18642 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-03-09google/chromeec: Add support for cros_ec_keyb deviceFurquan Shaikh
This is required to pass button information from EC to kernel without using 8042 keyboard driver. 1. Define EC buttons device using GOOG0007 ACPI ID. 2. Guard enabling of this device using EC_ENABLE_MKBP_DEVICE. BUG=b:35774934 BRANCH=None TEST=Verified using evtest that kernel is able to get button press/release information from EC. Change-Id: I4578f16648305350d36fb50f2a5d2285514daed4 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/18641 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-03-09soc/intel/apollolake: Add check if FPFs are blownAndrey Petrov
Apollolake platform comes with FPF (field-programmable-fuses). FPF can be blown only once, typically at the end of the manufacturing process. This patch adds code that sends a request to CSE to figure out if FPFs have already been blown. Change-Id: I9e768a8b95a3cb48adf66e1f17803c720908802d Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/18604 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-03-09soc/intel/apollolake: Start using common CSE driverAndrey Petrov
Change-Id: If866453f06220e0edcaa77af5f54b397ead3ac14 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/18603 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-03-09soc/intel/common/block: Add HECI driverAndrey Petrov
Add common driver that can send/receive HECI messages. This driver is inspired by Linux kernel mei driver and somewhat based on Skylake's. Currently it has been only tested on Apollolake. BUG=b:35586975 BRANCH=reef TEST=tested on Apollolake to send single messages and receive both fragmented and non-fragmented versions. Change-Id: Ie3772700270f4f333292b80d59f79555851780f7 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/18547 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-03-09soc/intel/apollolake: Prepare to use common HECI driverAndrey Petrov
Change-Id: Ib284493d886b223e8c85607de5fdb56b698fe5fa Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/18546 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-09uti/lint/checkpatch: Fix __attribute__ struct errors for OPEN_BRACEMartin Roth
The __attribute__((weak)) lines on structs were being read as functions, causing a warning that the brace should be on the next line. Add a check to see if it's a struct with an attribute, and ignore it for the OPEN_BRACE check if it is. Change-Id: Ieb0c96027e8df842f60ca7c9de7aac941eed1dc2 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/18570 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Lee Leahy <leroy.p.leahy@intel.com>
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