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2017-12-14drivers/pc80/tpm: Remove unused ACPI opregionDuncan Laurie
The opregion and fields are left over from when ACPI ASL code was reading registers to determine the current setup. Now that the ACPI device is generated with the correct information already this code is not used at all and can be removed from the tree. Change-Id: If89d90cc7105ed21e2134ac99224f6f8214cc8ad Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/22854 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-12-14soc/intel/apollolake: add _RMV attributes to eMMC device ACPIPatrick Georgi
Required so Windows knows if the storage is removable or not. Change-Id: I0822d767ada872d55357ff229e47e08fbe778a36 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/22830 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-14soc/intel/common/block/i2c: fix orphaned Kconfig optionsAaron Durbin
The SOC_INTEL_COMMON_LPSS_I2C option is no longer used. Likewise, the SOC_INTEL_COMMON_LPSS_I2C_DEBUG option which is dependent on SOC_INTEL_COMMON_LPSS_I2C is by definition not used either. Therefore, remove SOC_INTEL_COMMON_LPSS_I2C and change the name/dependency for SOC_INTEL_COMMON_LPSS_I2C_DEBUG to SOC_INTEL_COMMON_BLOCK_I2C_DEBUG. BUG=b:70232394 Change-Id: Icd77f028b77d8f642690a50be4ac2c50d9ef511a Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/22874 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Chris Ching <chingcodes@chromium.org>
2017-12-14mainboard/intel/glkrvp: Configure Prmrr and Enable SGXPratik Prajapati
Configure PRMRR to allocate 128MiB for SGX enclave memory and enable SGX by default for GLKRVP platform. Supported PRMRR size options: 0x02000000 - 32MiB 0x04000000 - 64MiB 0x08000000 - 128MiB Change-Id: Ifa39df4a1da84bae49551a9626257bda0729752b Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/21278 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-14src/soc/intel/apollolake: include helpers.h in chip.hPratik Prajapati
include helpers.h in chip.h so that devicetree can use macros from helpers.h Change-Id: Idfdee637a9b66a30be31b9ed113e1a44e4032f34 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/22774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-12-14soc/intel/cannonlake: Fix UART2 serial log broken issueSubrata Banik
Cannonlake rvp serial log has been regressed with commit I7eea910e065242689e87adac41281131674b39af(soc/intel/cannonlake: Clean up UART code) because of common UART code is unable to link all __weak function implementation from SoC uart.c due to existing macro #define __SIMPLE_DEVICE__. Hence UART2 PCI device resource programming is different than what it's been programmed before. This patch ensures UART2 PCI device resource enumeration is working and we are getting serial log as expected. Change-Id: I1f9df5e8d6490090ed65b06bdd0b40f824d36a8a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22862 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-14mainboard/google/kahlee: Update overcurrent pinsMartin Roth
The overcurrent pins on kahlee weren't mapped correctly, causing the USB-A port to stop working. None of the EHCI only ports are used for external connectors, so all of the overcurrent pins should go to the XHCI connections. This is also true of the Grunt board. On Grunt, this also means that we don't need OC3, as it doesn't map to anything in the XHCI controller, as it's coming from an internal hub. BUG=b:70636233 TEST=Build & boot Kahlee, verify USB-A port is working again. Change-Id: I53336a18a26bd9be27c7265fddbcd780632656bf Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22860 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Daniel Kurtz <djkurtz@google.com>
2017-12-14mb/glkrvp: Enable TouchpadShaunak Saha
This patch enables the APLS touchpad in glkrvp platform. TEST= Boot and test touchpad works. Change-Id: I6f52f7db57ab52b5531e647bde2adbb78b40f76f Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/22627 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-12-14soc/amd/stoneyridge: Remove "\t" from name tableRichard Spiegel
Remove "\t" from name strings in soc/amd/stoneyridge/southbridge.c array irq_association[], and change the print string in soc/amd/common/amd_pci_util.c that use the names from "%s" to "%-20s". This sets a fixed field of 20 characters for the string name, allowing for variable length to the names (up to 20 characters), thus saving memory space used by the strings. BUG=b:70344551 TEST=Build and boot, record output of irq routing and verify alignment. Change-Id: I92dfac9b64932fb0cd3359abd4d1aac651535f1a Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22785 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-12-13src/soc/intel/cannonlake: Add _PRW for CNViBora Guvendik
Add _PRW so that wake on WLAN feature works. TEST=Boot to OS and check if WLAN device wakes host. Change-Id: Id6689754d1c4100615e4e4ae5a7f9846f4bf785f Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/22611 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2017-12-13mb/cannonlake_rvp: Enable TouchpadShaunak Saha
This patch enables the APLS touchpad in cnl-y platform. TEST= Boot and test touchpad works. Change-Id: I461b9d119b1cac6c8c6cb9b096697f58e00d80ad Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/22369 Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-13vc/amd/pi/0067F00: add option to add AGESA binary PI as stageAaron Durbin
Stage addition to CBFS allows relocation to happen on the fly. Take advantage of that by adding AGESA binary PI as a stage file so that each instance will be relocated properly within CBFS. Without this patch Chrome OS having multiple CBFS instances just redirects the AGESA calls back into RO which is inappropriate. BUG=b:65442265,b:68141063 TEST=Enabled AGESA_BINARY_PI_AS_STAGE and used ELF file. Booted and noted each instance in Chrome OS build was relocated. Change-Id: Ic0141bc6436a30f855148ff205f28ac9bce30043 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/22833 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-12-13soc/intel/skylake: make tcc_offset take effectmarxwang
Currently, "tcc_offset" defined in devicetree is overwritten by Intel FSP-S UPD "TccActivationOffset". This patch will make "TccActivationOffset" refer to "tcc_offset". TEST=check if MSR (0x1a2[29:24]) value is updated with "tcc_offset" by iotools (rdmsr 0 0x1a2). Change-Id: Ibc6f33bea19a1d59bc7e407815210942b38f0702 Signed-off-by: marxwang <marx.wang@intel.com> Reviewed-on: https://review.coreboot.org/22818 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-12-13soc/intel/apollolake: Remove set_subsystem() from SoCSubrata Banik
Intel common PCI driver is handle PCI subsystem ID programming, hence no need to have an explicit soc function to do the same. TEST=PCI subsystem id is getting programming during pci enumeration. Change-Id: I3eb362ff1f3f6d5c81a0dbe854d8ecd59d5a0453 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22770 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-12-13soc/intel/skylake: Remove set_subsystem() from SoCSubrata Banik
Intel common PCI driver is handle PCI subsystem ID programming, hence no need to have an explicit soc function to do the same. TEST=PCI subsystem id is getting programming during pci enumeration. Change-Id: Iead57a286b26d532e578cfff99f412c23fd4c2fe Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22769 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-12-13soc/intel/common/block: Add option to have subsystem_id in common pci driverSubrata Banik
This patch ensures all Intel common PCI devices can have subsystem ID programmed along with PCI resource enabling (.enable_resources) as part of PCI enumeration process. TEST=Build and boot KBL/CNL/APL/GLK to ensure PCI subsystem ID getting programmed. Example: Enabling resources... PCI: 00:00.0 subsystem <- 8086/590c PCI: 00:00.0 cmd <- 06 PCI: 00:02.0 subsystem <- 8086/591e Change-Id: I46307b0db78c8864c85865bd0f3328d5141971be Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22768 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-13device: Make pci_dev_ops_pci structure globalSubrata Banik
This patch makes pci_dev_ops_pci structure global so that caller can make use of this structure using extern. Change-Id: I8de919aacccbc062475fb04f59ffb4957d3460b9 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22814 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-12-13mb/google/poppy/variants/nami: Disable native SD card controllerFurquan Shaikh
This change selects Kconfig option to disable native SD card controller in ACPI tables, since it is not used on nami. BUG=b:70160119 Change-Id: I6180c2b342c69e6a7c357f10b6297d67ea0211d7 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/22825 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-13mb/google/fizz: Enable SATA on port 0David Wu
Enable SATA port 0 to support SATA HDD. BUG=b:69950854 BRANCH=None TEST=emerge-fizz coreboot and boot on fizz dut Change-Id: Ifbf5950151758286f8bff7250a68d9d0b3975ef9 Signed-off-by: David Wu <david_wu@quantatw.com> Reviewed-on: https://review.coreboot.org/22815 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-13soc/intel/skylake: Enable LPC IO Decoding on PCRpraveen hodagatta pranesh
According to the PCH BIOS Spec (Doc#549921/Rev-2.3.4), section 2.5.1.6, it is a requirement to program the same value programmed in LPC "PCI offset 82h" into "PCR[DMI]+2774h" to fully enable the Lpc IO enable decoding which is missing in current source. Without above changes, Skylake Saddlebrook platform with a SIO does not boot. Change-Id: Ief26e2718325b9d74ea0f83d47d2f917e0972173 Signed-off-by: praveen <praveenx.hodagatta.pranesh@intel.com> Reviewed-on: https://review.coreboot.org/22819 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-12util/cbmem: Print timestamp frequency in verbose modeMartin Roth
The code flow is changed slightly to print the timestamp frequency from either method of determining it. BUG=b:70432544 TEST=Build and test cbmem -t -V Change-Id: I02286fa67919e70a3592cdbcc1c9ca2991b7f385 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22821 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-12-12google/kahlee/grunt: Add SPD filesMarc Jones
MEM_ID SPD 0000 hynix-H5AN8G6NAFR-UHC 0001 hynix-H5ANAG6NAMR-UHC 0010 micron-MT40A51216JY-083E 0011 micron-MT40A1G16KNR-075E 0100 samsung-K4A8G165WB-BCRC 0101 samsung-K4AAG165WB-MCRC BUG=b:69268926 TEST=build test Change-Id: I1fd6335b3f8842252c42009a0a91a5b6ed3ea238 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/22748 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-12vc/amd/pi/00670F00: fix #include paths to only use <amdblocks/header.h>Aaron Durbin
Ensure that soc/amd/common/blocks/include is the only #include path for the AMD common code. This removes the duplicate soc/amd/common include as well using the correct #include header in AGESA.c. BUG=b:69262110 Change-Id: I50d85b28514fd905df415f0cc052b9924ee4e741 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/22828 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-12-12google/scarlet: support INNOLUX P097PFG panelLin Huang
Add INNOLUX P097PFG panel timing. According to Scalet schematic, if GPIO3_D4 get low status, it will use INNOLUX P097PFG panel; if GPIO3_D4 get high status, it will use KD097d04 panel. Change-Id: I43fa5d859a9a529a84c58a953b37d03953ce648a Signed-off-by: Lin Huang <hl@rock-chips.com> Reviewed-on: https://review.coreboot.org/22780 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-12-12soc/amd/common: Move AGESA related source filesRichard Spiegel
Move AGESA related source files in soc/amd/common under block directory. Folder soc/amd/common/block subfolders should mimic soc/intel/common/block subfolders (one subfolder per subject). BUG=b:69262110 TEST=Build with no error gardenia and kahlee (no code change, just folder reorg). Change-Id: I497cdefe64e8dff00aaff7153c4ffa9c57c9acf8 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22792 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-12soc/amd/common: Move Agesa related headersRichard Spiegel
Move AGESA related headers in soc/amd/common to soc/amd/common/block/include/amdblocks. BUG=b:69262110 TEST=Build with no error gardenia and kahlee (no code change, headers moved). Change-Id: I5d3064625ddf8caaf370aabaf93165c6817f1ca0 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22772 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-12-12nb/intel/x4x/rcven.c: Fix programming coarse offsetArthur Heymans
This fixes some bitwise logic errors that caused the coarse offset not to be programmed. This fixes a regression introduced by 6d7a8c "nb/intel/x4x/raminit: Rework receive enable calibration" where the coarse offset doesn't get programmed anymore. TESTED on Foxconn g41s-k on a DIMM where the final DQS receive enable delays are close but above and below the edge of a coarse delay setting. Change-Id: I41869815f782a2ea1178bdea006e3a7587441323 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/22816 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-12-12mb/lenovo/t400/blc.c: Add a new panel to the listArthur Heymans
Also adds a comment in the code to clarify what this array is about. Change-Id: I04b185a5dbd7a7ccb039820f19d2cb549b9a2eac Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/22809 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2017-12-12drivers/intel/gma: Power up legacy VGA block earlyNico Huber
This is required at least on Skylake to be able to configure text mode. 3rdparty/libgfxinit is also updated by the single commit: 42fb2d065d gma: Add procedure to power up legacy VGA block Change-Id: I2fe144765e2b2acd9f6b76db375cae5b8feb5489 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/21386 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-12-12mb/google/poppy/variants/nami: Implement variant_memory_paramsFurquan Shaikh
This change provides implementation of variant_memory_params for nami. Since it uses DDR4 memory, DQ-DQS mapping table is not required. Also, Rcomp resistor values are provided based on SDP v/s DDP memory. BUG=b:70188937 Change-Id: Ic1d0cfdb7d8b02fa0be0a4c54b20057a4c2fc3ce Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22779 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-11mb/google/poppy/variants/soraka: Tune I2C5 paramsFurquan Shaikh
This change updates scl_lcnt value for I2C5 to bring the bus frequency closer to 400kHz. BUG=b:65062416 TEST=Verified that I2C5 frequency is between 389-396kHz. Change-Id: Ibaccab0c797174332633cb75e30d18ff5af76a43 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22788 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-11soc/amd/common: Move files to common/blockRichard Spiegel
The following files need to be moved: amd_pci_util.c, amd_pci_util.h and spi.c. The remaining files are AGESA related and will be part of a separate issue/commit. BUG=b:62240201 TEST=Build with no error gardenia and kahlee (no code change, just folder reorg). Change-Id: I3f965afa21124d4874d3b7bfe0f404a58b070e23 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22765 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-12-11soc/intel/cannonlake: Add support for D0 steppingLijian Zhao
D0 stepping with CPUID 0x60663 need to be added in coreboot. TEST=Boot up with D0 stepping processor Change-Id: I3b0f2616843367d2bfbee1b5bf75772b9e83e931 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/22676 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-11google/gru: Stop mucking with unused I2S0 pins in codec configJulius Werner
Due to a schematic error, our code was written to configure more I2S0 pins than are actually used. We're also pinmuxing the whole bank of pins over to the I2S controller even though we don't need them all. Restrict the GPIO initialization and pinmuxing to the pins we really need so the other ones can be correctly used as SKU ID pins on Scarlet. Also, move the "audio" IO voltage domain selection to the other such selections in the bootblock, since that covers two whole banks of GPIOs and there's no guarantee that they're all used for audio (and thus not needed before ramstage). BUG=b:69373077 TEST=Booted Scarlet, confirmed correct SKU ID (7) was detected on rev2. Change-Id: I9314617e725fe83d254984529f269d4442e736f1 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/22791 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Schneider <dnschneid@chromium.org>
2017-12-11google/gru: Change Scarlet SKU ID pins to pull-upsJulius Werner
These pins need to be pull-ups. I forgot. BUG=b:69373077 Change-Id: I9314617e01d35898254984529f269d4442e736f1 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/22775 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-11mainboard/purism/librem_skl: Fix line length > 80 charactersMartin Roth
Make lint-stable was giving an error on this. Change-Id: I06d11d86151f683b82b6df537e3de8c52d33e8b4 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22811 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Youness Alaoui <snifikino@gmail.com>
2017-12-11soc/amd/common: Collect timestamps before and after AGESA callsMartin Roth
BUG=b:70432544 TEST=Build & boot kahlee. Look at timestamps. Change-Id: I8209160f8e23ab77987f8e515c7b00d94f68c8be Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22798 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-12-11commonlib: Add timestamp codes for AGESAMartin Roth
BUG=b:70432544 TEST=Build & boot kahlee. Look at timestamps. Change-Id: I3bf691a0fb1f5c09e7b6c9965c9e506393ec31f6 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22797 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-11google/nautilus: Add Maxim98357a supportNaveen Manohar
Adds Maxim98357a support for Nautilus using the generic driver in drivers/generic/max98357 BUG=b:68686020 TEST=With entire merged audio should be enabled on max98357 speaker codec. Change-Id: I958bf7c1395259b3e3fb30332882fd51a48dc0cc Signed-off-by: Naveen Manohar <naveen.m@intel.com> Reviewed-on: https://review.coreboot.org/22458 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-12-11mb/google/poppy/variants/nautilus: add SPK DMIC nhlt supportNaveen Manohar
Nautilus board uses max989357a speaker codec and 4CH DMIC. Select the appropriate NHLT blob to be packaged in CBFS. Also generate the required ACPI NHLT table for codec and the supported topology in nautilus. BUG=b:68686020 TEST=With the required driver support in kernel verify that the Audio plays on Speaker and captures on 4CH DMIC Change-Id: Ie90af02e0935029f53f9020bd78027b6eb31a187 Signed-off-by: Naveen Manohar <naveen.m@intel.com> Reviewed-on: https://review.coreboot.org/22457 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-12-11AMD fam10: Link southbridge/amd/rs780/early_setup.cArthur Heymans
Removes rs780_before_pci_init() since it was a no-op anyway. Removes get_nb_rev() since this function is provided via a macro in the header. This Makes a lot of function non-static since the header has prototypes for these. Change-Id: I8933516771d959583bbd59a5c1beee3e30a7004f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/20297 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-12-11intel: Use MSR_EBC_FREQUENCY_ID instead of 0x2cElyes HAOUAS
Change-Id: Ib1b761fc417f1bb000f408d3bed5e8666963f51d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/22603 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-12-11vc/amd/pi/00670F00/binaryPI: cache the AGESA dispatcherAaron Durbin
Instead of repeatedly walking cbfs for the AGESA blob and parsing it cache the resulting dispatcher value. There's only one dispatcher table so use it. The resulting change is that this work is done one time per stage. BUG=b:70401101 TEST=Booted and noted only one lookup per stage. Change-Id: Iaa4aecc384108d66d7c68fc5fb9ac1c3f40da905 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/22789 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2017-12-11soc/amd/stoneyridge: Enable SPI writesJohn E. Kabat Jr
- Change soc/amd/stoneyridge/Kconfig to set BOOT_DEVICE_SUPPORTS_WRITES BUG=b:65485690 TEST=Build & boot kahlee. Change-Id: I595a27ac27daa42c2499de1a343bc30be9a89fa6 Signed-off-by: John E. Kabat Jr <john.kabat@scarletltd.com> Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/22636 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-11soc/amd/common: Add amdblocks/spi.hMarc Jones
Add the spi header for spi function prototypes. Fixes spi.c build error for the missing header. Change-Id: I0dbb5bf84cc3462a7aa58a5531d6b8b8bc8ca4df Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/22793 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-12-10sb/intel/i82801jx: Hook up spi codeArthur Heymans
Change-Id: Ie83c800a0bcd12fa501c91a1c2b1ee756de9d732 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/21675 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-12-10sb/intel/common: Add SOUTHBRIDGE_INTEL_COMMON_SPIArthur Heymans
This introduces a Kconfig option to include common Intel SPI code. Change-Id: I970408e5656c0e8812b8609e2cc10d0bc8d8f6f2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/21674 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2017-12-09Documentation/Intel: Add NativeRaminit documentationPatrick Rudolph
Add documentation for Intel native raminit on Intel SandyBridge. Documented so far: * Register * Read training * Frequency selection * SMBIOS type 17 memory reporting * Various Kconfig options and features Change-Id: I3b977460ecb29c9a54e3fab82349982fca9918e7 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/22275 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-12-09mb/intel/glkrvp: Add gpio.h in dsdt.asl fileShaunak Saha
Add proper variants gpio.h in dsdt.asl where the GPE_EC_WAKE and EC_SCI_GPI is defined. Change-Id: Ideb6dd4d0ac496a81721cd883865218cb19583d9 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/22760 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-09nvramtool: Add dummy cmos-hw-unix accessor implementation for non-x86Paul Kocialkowski
The default implementation uses inb/outb, that is not available on ARM platforms and others. A dummy implementation allows building nvramtool on these platforms. Change-Id: I75e4a1a0cbd35ca40f7b108658686839ccf9784a Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-on: https://review.coreboot.org/22562 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-12-09soc/intel/skylake: add acoustic noise mitigation params for FSP 1.1Matt DeVillier
Adapted from Chromium commit d6655eb [Skylake: create UPD Interface for acoustic noise tuning] Add FSP 1.1 params needed for acoustic mitigation on google/caroline (to be upstreamed in a subsequent commit). TEST: build/boot google/caroline Change-Id: Ifb36ecef8c1735c63a5322d952929e9c34cddfb9 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/22524 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-12-09intel/i440bx: Correct RAM init programmingKeith Hui
Corrects MBSC/MBFS programming when initializing DRAM on boards with both 3 and 4 DIMM slots. Reformats comments to current coreboot standards. Drops some romcc "optimizations" no longer necessary. Boot tested on asus/p2b-ls, where it fixes a memory related hang after SeaBIOS resets the board with nothing to boot from. Change-Id: Ib8c21489338643e13f69bd58008d14733796d4d0 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/22687 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-12-09soc/amd/stoneyridge/include: delete amd_pci_int_types.hRichard Spiegel
Due to review 20b8c821e4 being abandoned and review 376dc82dca being merged, file amd_pci_int_types.h became orphaned (not included by any file), while an array similar to intr_types[] (but that also includes the associated register index) was created in southbridge.c replacing the original array functionality. Remove the header amd_pci_int_types.h from the repository. BUG=b:70328428 TEST=Build kahlee with no errors. Change-Id: I53a9d7ebb27edbc4e136c9b17f5c709930e35223 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22778 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-09google/cyan: fix FSP memory init paramsMatt DeVillier
In the original Chromium source, PcdMemorySpdPtr is only set for cyan, but none of the other Braswell variants. When upstreamed, it was left set for all boards as it didn't appear to be problematic. In wider testing, I came across one reks board for which it caused FSP memory init to fail, so restricting the parameter to cyan only as it was originally. TEST: build/boot google/reks with Micron EDF8132A3MA-JD-F RAM, observe board now successfully boots where it did not previously. Change-Id: Iacfbd4bc89fa04717baf85704181d346bca2ed2f Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/22782 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-09soc/intel/cannonlake: Clean up UART codeAamir Bohra
Clean up and move UART related code under a single uart.c file. Change-Id: I7eea910e065242689e87adac41281131674b39af Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/22771 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2017-12-09Update vboot submodule to upstream masterMarc Jones
Updating from commit id 3b80572: 2017-10-12 16:35:30 -0700 - (tlcl, tpmc: extend GetVersion to report vendor specific data) to commit id f6780a3: 2017-12-01 14:54:40 -0800 - (firmware: header tweaks for depthcharge) This brings in 19 new commits. Change-Id: I49b1349cfd9266cd815b68759ae89bdffdd0d74b Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/22777 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-09mainboard/google/kahlee: Update GPIOsMartin Roth
- The touchscreen interrupt was moved from the GPIO 3, as originally suggested to GPIO 11. This changes the gevent from 2 to 18. - Add EMMC reset on GPIO 93. - Add EMMC bridge PCIe reset on GPIO 40. - Set device enables to high. - Remove extra SCI comment from GPIO 130. - Set individual device PCIe reset pins to high. - Enable global PCIe reset on GPIO 26. - Mark LPC_CLK1 as unused. - Update net names based on latest schematics. - Set Direction and level/edge correctly for SCIs/SMIs. - Remove SCI for pen detect. - Add comments. BUG=b:70234300, b:69681660, b:69305596 TEST=build grunt Change-Id: Ib591e4278ed23d0963ecb19ad9c326498b4c7796 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22751 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-09mainboard/google/kahlee: Update PCIe port mapMartin Roth
- Grunt moved the EMMC chip to port 2, where Kahlee had the SD reader on PCIe port 1, so move the OemCustomize file into the variant directory. - Add comments in baseboard version so it's easier to understand. - Update reset pins, put the definitions in gpio.h BUG=b:70255003 TEST=Build and boot Kahlee. Build Grunt. Change-Id: I78ec72e9d6fd52b8ac75e7187bd01ee7ddc3ba2a Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22750 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-12-08src/mainboard/glkrvp: Turn on CPU fanSrinidhi Kaushik
On GLK EC does not support temperature reads and does not control the fans anymore, OS is responsible fan control through EC. This hack enables running of the fan for boards without External EC. Change-Id: I361e53d4fd53678f3abb8fe9862071aec6e149a7 Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Reviewed-on: https://review.coreboot.org/22235 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2017-12-08vendorcode/intel/fsp/fsp2_0/glk: Update header files as per v69_51Ravi Sarawadi
Update FSP header files to match FSP v69_51. UPD updates in FSP v69_51 are: - SGX Epoch - Sub/System Vendor ID - Remove deprecated UPD Change-Id: I7298615a6e051061b948814a1cd9cbd42f6574b5 Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-on: https://review.coreboot.org/22391 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-12-08mb/intel/glkrvp: Fix CLKRUN gpioShaunak Saha
This patch does not put CLKRUN in IOSTANDBY. Change-Id: I7fedd729d3bb66c2b52a63166e461f8760457721 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/22292 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-12-08soc/intel/apollolake/acpi/cnvi.asl: Add _PRW for CNViHannah Williams
Add CNVi GPE in _PRW for wake on WLAN from S3 Change-Id: I682c76b9c5c524face7b540ecb185a3d7b4b2da3 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/22639 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-12-08soc/intel/apollolake/acpi/pch_hda: Add _PRW for HD-AHannah Williams
Add GPE in _PRW for wake from S3 for HD-audio controller Change-Id: I6ad289be8c58e48ad0ec9d2ee0894fe16b8f2e1c Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/22637 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-12-08google/fizz: Set BJ max current and voltageDaisuke Nojiri
This patch makes coreboot set the max current and voltage for barrel jack adapters. BUG=b:64442692 BRANCH=none TEST=Boot Fizz. Use chgsup console command to verify the max current and voltage are set as expected. Change-Id: Ifebee09096e0935cc7d3e53920a251b0496d3c55 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://review.coreboot.org/22623 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-08chromeec: Add command to override charger limitDaisuke Nojiri
This patch adds EC_CMD_OVERRIDE_DEDICATED_CHARGER_LIMIT, which overrides the max input current and voltage when a barrel jack adapter supplies power. BUG=b:64442692 BRANCH=none TEST=Boot Fizz. Use chgsup console command to verify the max current and voltage are set as expected. Change-Id: I8c6fc54e519ce13e3db82ee2cecaa96c6eb42d8a Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://review.coreboot.org/22624 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-08cr50: Make EC clear AP_OFF before hibnernateDaisuke Nojiri
This patch makes AP send EC_REBOOT_HIBERNATE_CLEAR_AP_OFF, which makes EC clear AP_OFF flag then hibernate. This is needed to make Chromebox boot when cr50 toggles the EC's reset line after TURN_UPDATE_ON command. BUG=b:69721737 BRANCH=none CQ-DEPEND=CL:802632 TEST=Verify Fizz reboot after cr50 update. Change-Id: I5f590286393ac21382cab64afdccae92d3fc14ba Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://review.coreboot.org/22657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-08cbfstool: Add '-p' option for paddingDaisuke Nojiri
This patch adds '-p' to the 'add' command. It allows the add command to specify the size of the padding added with the file being added. This is useful to reserve an extra space in case the file is too big to be relocated. BUG=b:68660966 BRANCH=none TEST=emerge-fizz coreboot && cbfstool image.bin add -n ecrw -f EC_RW.bin -p 0x10 ... Verify image.bin has extra space in the file header. Change-Id: I64bc54fd10a453b4da467bc69d9590e61b0f7ead Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://review.coreboot.org/22239 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-12-08device/pciexp_device: Set values numerically instead of as bitmaskPatrick Georgi
As noted on linux-pci, we have a weird way to handling "value" and "scale" fields that are supposed to contain numerical values: we encode them as a bitfield. Instead define the two fields (offset and mask) and use numbers. Another issue, not fixed in this CL, is that we write hard-coded values while these fields really need to contain the max() of acceptable delays of the downstream devices. That way the controller can decide whether or not to enter a deeper power management state. It's noted as a TODO. Change-Id: I895b9fe2ee438d3958c2d787e70a84d73eaa49d2 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Found-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-on: https://review.coreboot.org/22740 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-12-08mb/google/reef: provide override GPIO table in coralChris Wang
Allow overriding specific GPIOs by SKU ID. Override two GPIO settings for nasher to save the power consumption when the system in S0ix. Change as below: AVS_DMIC_CLK_A1: IGNORE -> Tx1RXDCRx0. AVS_DMIC_CLK_B1: IGNORE -> Tx1RXDCRx0. BUG=b:69025557 BRANCH=master TEST=compile/verify the power consumption change from ~150mW to ~100mW on clamshell SKU and from ~200mW to ~100mW for convertible SKU. Change-Id: I9e0674f206426fddb3947273754774b310106334 Signed-off-by: Chris Wang <chriswang@ami.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/22752 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-12-08soc/intel/cannonlake: Add PCH ID support in bootblock/report_platform.cSubrata Banik
This patch ensures that all required information for pch/mch/igd deviceid and revision are available in single stage and makes use of local references. TEST=Build and boot cannonlake_rvp to get PCH information as below PCH: device id xxxx (rev xx) is Cannonlake-Y Premium Change-Id: I420e94043145e8a5adcf8bb51239657891915d84 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22767 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-08soc/intel/skylake: Clean up bootblock/report_platform.cSubrata Banik
This patch ensures that all required information for pch/mch/igd deviceid and revision available in single stage and make use of local references. TEST=Build and boot soraka/eve Change-Id: I6f7f219536831210750a486ee3b3308d6f285451 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22756 Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-08soc/intel/skylake: Remove pch_enable_dev() from SoCSubrata Banik
PCI resources MMIO space/bus master enabling is handled inside pch_dev_enable_resources() from common device code. Hence no need to have an explicit soc function to do the same. TEST=lspci from kernel console shows same pci device list without and without this patch. Change-Id: I005e486dd435e9c61ae3f5dfe3ff0e8f688d16e1 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22755 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-08soc/amd/stoneyridge: Add RO_REGION_ONLYMarc Jones
We only need the apu firmware in the RO region when building for ChromeOS. Adding it to the RW regions is a waste of space. BUG=b:70027919 TEST=Build kahlee and use cbfstool to check for "apu/amdfw" sections. Change-Id: Ieafe4a5ec4a5e3177e4e23fcf42afa2626a0b19f Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/22766 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-07mainboard/intel/glkrvp: Change gpio configuration for eSPIBora Guvendik
Skip LPC related gpio configuration if eSPI config option is selected. Change-Id: I15c5f769f36a1801217b1e3650379c7b181d814f Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/22757 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-07buildgcc: Hide stderr output of getopt testNico Huber
Change-Id: I03c38de3a3b88d569d629be7483eb53164cf136a Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/22738 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-12-07libpayload: Add pci_free_dev() and some boilerplateNico Huber
Add just enough code and boilerplate to keep it compatible with future libflashrom. Change-Id: If0d46fab141da525f8f115d3f6045a8c417569eb Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20955 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-12-07amd/stoneyridge: Delete early_setup.cRichard Spiegel
All preparation done, early_setup.c now useless. Delete early_setup.c, BUG=b:64033893 TEST=None. Change-Id: Ibe75a2d5cc46641e9d0af462a8a0ba5bb7a0f9c3 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22569 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-12-07google/scarlet: update Kingdisplay kd097d04 timingLin Huang
With the old timing, the hblank time isn't large enough, it may cause display artifacts. So fix it. BUG=b:70160653 TEST=panel work on Scarlet rev2 board Change-Id: Ib061f5e215611d20f59e3f24cfe3c7fbc507ebed Signed-off-by: Lin Huang <hl@rock-chips.com> Reviewed-on: https://review.coreboot.org/22746 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-12-07payloads/external/Makefile: Add missing dependencyNico Huber
The depthcharge .config only exists after depthcharge was built. Other possible `PAYLOAD_CONFIG` files most probably miss a rule, too. Change-Id: I8e6f79bb2bd07cbef1317f2623bbef9ca0e74880 Signed-off-by: Nico Huber <nico.huber@secunet.com> Tested-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/22137 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-12-07asus/p2b-ls: Disable SuperI/O ACPI logical deviceKeith Hui
This logical device is disabled in OEM BIOS. Disable here to match, since its support is currently incomplete anyway. Change-Id: I5c07136ec6a14a8ee8cb68537a2663b78fc0fa20 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/22145 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-12-07asus/p2b: Align ACPI tables with asus/p2b-lsKeith Hui
Updates ACPI tables with work done for asus/p2b-ls, including super I/O related declarations. Change-Id: Id2420da4ab04aa5f59ac0aa237d21477a03b826e Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/22473 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-12-07asus/p2b-ls: Add ACPI tablesKeith Hui
Add ACPI tables support that will be needed for soft-off and S3 resume in the future. Boot tested for soft-off. Change-Id: I28b559406bd53efc555dcbb8282dfe2bd6d1af87 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/21672 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-12-07sb/intel/i82371eb: Rework ACPI tablesKeith Hui
Rework ACPI tables based on a mix of previous work on asus/p2b, other boards in tree with better ACPI support, and OEM BIOS. To be pulled in by DSDTs of mainboards using this southbridge. Disable on-the-fly generation of mainboard _CRS node. It is not working as it should and causes runtime errors when booting Linux. This node to be included in mainboard DSDTs in followup patches. Change-Id: Idda424de7859a36e4cac168d5469f9365a6ad421 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/21671 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-12-07kahlee/ec.c: Use new wide IO functionRichard Spiegel
In preparation to deleting early_setup,c, change early_ec_init() to use new southbridge.c function sb_set_wideio_range and remove <#ifdef __PRE_RAM__>. BUG=b:64033893 TEST=Build, boot and check serial output, search for "Covered by wideIO xx", which should match earlier message "Range assigned to wide IO xx" generated within modified early_ec_init(). Change-Id: Iaea17f4f636aab6bd8b05b1b3bed53a677164e74 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22591 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-07amd/stoneyridge/lpc.c: Use new wide IO functionsRichard Spiegel
Use the new wide IO functions from southbridge.c to simplify code in functions set_child_resource and lpc_enable_childrens_resources. BUG=b:64033893 TEST=Boot to OS, check serial output against previously recorded serial output from an image without all 5 related changes. Change-Id: I8533e8ff766df8a8261298559aace7666487826d Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22574 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-07amd/stoneyridge: Create new wide IO functionsRichard Spiegel
Create new generic wide IO functions in southbridge.c. These new functions must be usable by kahlee/ec.c and amd/stoneyridge/lpc.c. BUG=b:64033893 TEST=Just build at this stage, full boot to OS and verify serial output at related change 14fdd03a83. Some extra outputs for testing removed when code was committed. Change-Id: Icd0841a1959f3e109b3c35fa35bb4b3c44099dc3 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22590 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-12-07mb/google/poppy/variants/nami: Add support for nami boardFurquan Shaikh
This change adds variant nami derived from baseboard poppy. BUG=b:70160119 Change-Id: Ic6795d49d3e6e98a32f4af0b621e8bb463041412 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22703 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-07mb/google/poppy: Add support for DDR4 memoryFurquan Shaikh
This change updates memory SPD handling code in baseboard poppy to allow variants to define either LPDDR3 or DDR4 memory types. In addition to that, it also updates the function to print SPD info considering offsets that might be different across the two memory types. BUG=b:70188937 Change-Id: Iefad01719c62264fb0d7e987904e77647d6026c2 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22745 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-07mb/google/poppy/variants/nautilus: Fix memory paramsFurquan Shaikh
Until now, nautilus was using the DQ-DQS mappings provided by the baseboard. However, based on schematics, these values are not correct. This change adds DQ-DQS mapping tables for nautilus. BUG=b:70188533 Change-Id: Ife6ba19b8fe8873ab8cca977ca8f34a4d86e8e6e Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22706 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: shkim <sh_.kim@samsung.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-07soc/intel/apollolake: add ability to enable eSPIBora Guvendik
Add config option to enable eSPI TEST=Boot to OS Change-Id: Ib4634690fe4fdb902fc0bc074a3b66b91921ddd5 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/22320 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Hannah Williams <hannah.williams@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2017-12-07soc/intel/apollolake: Clean up UART codeAamir Bohra
Clean up and move UART related code under a single uart.c file. Change-Id: I9a30258ba43ee5920f585c1bd06bc25773778ec4 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/22754 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2017-12-07soc/intel/skylake: Clean up UART codeAamir Bohra
Clean up and move UART related code under a single uart.c file. Change-Id: I7ed03fc5fe79e38350d7edc70ad55d54db780fed Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/22753 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2017-12-07soc/intel/cannonlake: Make use of Intel common Graphics blockSubrata Banik
TEST=Build and boot cannonlake rvp. Change-Id: Iaa1314ae3fcb4a8a3b55a314e79511f5dcba163d Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22617 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-12-07soc/intel/apollolake: Make use of Intel common Graphics blockSubrata Banik
TEST=Build and boot reef. Change-Id: I0edd7454912201598c43e35990e470ec18a32638 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22616 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-12-07soc/intel/skylake: Make use of Intel common Graphics blockSubrata Banik
TEST=Build and boot soraka/eve. Change-Id: I416226d0374700cea6eea602f839c3d17f1f39a6 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22615 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-07soc/intel/common/block: Add Intel common Graphics controller supportSubrata Banik
SoC need to select specific macros to compile common graphics code. Change-Id: Idbc73854ce9fc21a8a3e3663a98e01fc94d5a5e4 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22614 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-07intel/bd82x6x: Fix a small mistake in DIR_ROUTETobias Diedrich
The register is 16-bits wide. If the DIR_ROUTE call ordering was reversed the previous writes would get overwritten. See page 407ff on the Intel C216 datasheet, which says "Size: 16bits" with "Default: 3210h" for all DnnIR registers. This also makes sense given the register offsets: 3140h–3141h D31IR Device 31 Interrupt Route 3210h R/W [3142h would be D30IR] 3144h–3145h D29IR Device 29 Interrupt Route 3210h R/W 3146h–3147h D28IR Device 28 Interrupt Route 3210h R/W 3148h–3149h D27IR Device 27 Interrupt Route 3210h R/W 314Ch–314Dh D26IR Device 26 Interrupt Route 3210h R/W 3150h–3151h D25IR Device 25 Interrupt Route 3210h R/W [discontinuity in register addresses here] 315Ch–315Dh D22IR Device 22 Interrupt Route 3210h R/W [315Eh would be D21IR] 3160h–3161h D20IR Device 20 Interrupt Route 3210h R/W Change-Id: I970abbacbc2c59e86c1726171272b8779758e53e Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Reviewed-on: https://review.coreboot.org/22621 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2017-12-07intel/bd82x6x: Add missing IRQs in ACPI PIRQ link devicesTobias Diedrich
pch_pirq_init() sets all PIRQ links to route to irq 11. However in the ACPI data, on half the links irq 11 is missing. The other half is missing irq 10. This fixes a mostly cosmetic issue in the Linux messages: ACPI: PCI Interrupt Link [LNKA] (IRQs 3 4 5 6 7 10 12 14 15) *11 ACPI: PCI Interrupt Link [LNKB] (IRQs 3 4 5 6 7 *11 12 14 15) ACPI: PCI Interrupt Link [LNKC] (IRQs 3 4 5 6 7 10 12 14 15) *11 ACPI: PCI Interrupt Link [LNKD] (IRQs 3 4 5 6 7 *11 12 14 15) ACPI: PCI Interrupt Link [LNKE] (IRQs 3 4 5 6 7 10 12 14 15) *11 ACPI: PCI Interrupt Link [LNKF] (IRQs 3 4 5 6 7 *11 12 14 15) ACPI: PCI Interrupt Link [LNKG] (IRQs 3 4 5 6 7 10 12 14 15) *11 ACPI: PCI Interrupt Link [LNKH] (IRQs 3 4 5 6 7 *11 12 14 15) Change-Id: I002147d702cacf54a233196932b30732f6a433b3 Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Reviewed-on: https://review.coreboot.org/22600 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2017-12-07mainboard/intel/glkrvp: Ignore Audio DMIC IOSSTATESathyanarayana Nujella
Audio DMIC_CLK needs to be ON in S0ix to support Wake on Voice. So, configuring GPIO_171 to be as IGNORE IOSSTATE, so that clock is ON in S0ix state. BUG=None TEST=put DUT in S0ix, verified DMIC_CLK in scope when wov capture path is ON Change-Id: I147cf3c12acb11429c6cb234e8c511f57886b6b4 Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/22675 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-07Revert "soc/intel/skylake: Clean up SoC ASL code."Matt DeVillier
This partially reverts commit a7b97510aeb1652fd0006c9b2d10df6568f37e2e. For the internal eMMC to be used by Windows for installation, the CARD device and _RMV methods are required. Without them, Windows does not see/show the eMMC as a valid installation target. TEST: boot google/chell with Tianocore payload and install Windows 10 to the internal eMMC drive. Change-Id: I04819ff16ab4cb0d2ea6e1c7f47179f5dacb7cfd Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/22684 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-28 00:32:21 +0000