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2015-07-06libpayload: mark util/xcompile/xcompile executablePatrick Georgi
Change-Id: I97088df1550f580d4648c7cccbd81c696fcfe2dc Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10799 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-06veyron*: Kill SKIP_DISPLAY_INIT_HACKDavid Hendricks
Now that we have functioning display code for all platforms, we can just get rid of this ugly hack used on non-Chromebook veyrons. BUG=none BRANCH=none TEST=built for Brain, Rialto, Mickey, Romy Change-Id: Ibe248c7cc74940811345c249d66992d74fe85fe5 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 9c627b087ba9fc07b4ec4a6d55d2e0203bdd4ff5 Original-Change-Id: I946eddb4e8ce1dbaa20212a2bb417e71a31b2ba3 Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/282049 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/10785 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-07-06veyron_rialto: Use VOP_MODE_NONE for display init.David Hendricks
This uses VOP_MODE_NONE for display init on veyron_rialto and adds a mainboard_power_on_backlight() stub so that we can finally get rid of SKIP_DISPLAY_INIT_HACK. BUG=none BRANCH=none TEST=built for veyron_rialto Change-Id: Ia6b420a962fe266e773c804b8e5c68da35848753 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a290c938c163759a3672c07d8ec7c0a38057b13d Original-Change-Id: Iec2d7f03857198a4d6f7490db1e3e19c74f18c43 Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/282048 Reviewed-on: http://review.coreboot.org/10784 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-06cbfs: define libpayload_init_default_cbfs_media weaklyDaisuke Nojiri
To allow a payload to define its own libpayload_init_default_cbfs_media, default implementation needs to be defined weakly. BUG=none BRANCH=tot TEST=dumped a cbfs file from depthcharge cli on jerry Change-Id: Ice73ae5a63dfd49e79c0eeb92d4eade016d61c39 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 1f308177fffb0d525fdb50f8d024568bb9025352 Original-Change-Id: I4721139aea3169c62c10a2a26582bd9277e4cb83 Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/283061 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10783 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-06sysinfo: remove unused tag for struct spi_flashDaisuke Nojiri
This will conflict with struct spi_flash defined in spi_flash.h BUG=none BRANCH=tot TEST=built libpayload for veyron jerry Change-Id: I7e1be28cf430021944fc96890082a0704d093e9f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0f0b8a7ec114046335fb1a51b6a92e10e5a16520 Original-Change-Id: I6d4f8a8e93aeb055f7dd6e5e8fd5e6c6153ab837 Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/282588 Original-Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: http://review.coreboot.org/10782 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-06update common base header filesDaisuke Nojiri
IS_ENABLED is defined in kconfig.h, thus, should be included in libpayload.h. BUG=none BRANCH=tot TEST=built coreboot/libpayload for veyron_jerry Change-Id: I9c5879b6125ac66a75a507ab07a6816ab54ed0ba Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 51dcd58a841009081fdefcadf9aa74286152dde6 Original-Change-Id: I30e6d87c9de827a214a6100449cd716e773c2ba3 Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/282587 Original-Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: http://review.coreboot.org/10781 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-06t210: MTC cleanupFurquan Shaikh
1. Correct MTC weak function definitions. 2. Correct MTC message in case no training data is present. BUG=None BRANCH=None TEST=Compiles successfully and boots to kernel prompt on smaug. Change-Id: Iba3c994982da947af3fbd2d7e9a06dff7947f2b9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ce9a4cd7d824acd0da5615b33319869f6cf1cd56 Original-Change-Id: I037439246709c8ec0ec7f12ea109cbe0ae1073ae Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/278027 Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/10780 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2015-07-06rk3288: Add VOP_MODE_NONE for headless devicesDavid Hendricks
BUG=none BRANCH=none TEST=built w/ follow-up rialto patch Change-Id: I166c75673c199e8c6860f601db6759cdc3cb9c96 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ba0e0b639f12654ec54216d4366c688baa5b3253 Original-Change-Id: Id21c87ace2f4d381a1e374e1d5fe15cf1cd96da0 Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/282047 Reviewed-on: http://review.coreboot.org/10779 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-06veyron_brain: Add basic HDMI supportDavid Hendricks
This adds a configure_hdmi() function that drives the HDMI enable output high and configures the iomux. Calls to PMIC functions to enable HDMI power are moved here as well. BUG=none BRANCH=none TEST=with follow-up patches, we now get a dev screen on Brain. Change-Id: Ifd2648376c789fb29c9e2e4ab6bdb10ca439e4a2 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 91ec6a96edaf2042236aee0383e18715014f1013 Original-Change-Id: I0c6e9f8fc5e06f53a1a160d8ab2e32447168139e Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/282046 Reviewed-on: http://review.coreboot.org/10778 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-07-06lzma: Return correct amount of decompressed bytesJulius Werner
The LZMA functions are supposed to return the decompressed size, but what they actually return is just an unaltered field from the LZMA header that is *supposed* to contain the decompressed size. Apparently some encoders just overshoot that for no good reason. This patch changes the code such that the actual amount of decompressed bytes is returned. BRANCH=smaug BUG=None TEST=Printed output bytes when decompressing kernels with LZMA in depthcharge, noted that amounts now make sense. Change-Id: Icdd8f782aa87841f770eff4c14a08973530c7446 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 24b2fa8c9a342ca4288dad1430c8965395f00263 Original-Change-Id: Ib4cf8673846aedd34656e594ce7b8ea875b56099 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/282742 Original-Reviewed-by: Stefan Reinauer <reinauer@google.com> Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10777 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-06veyron_*: Set vop_mode in devicetree.cb filesDavid Hendricks
This avoids any ambiguity or breakage in case the vop_modes get shuffled around or changed in some future patch or copy+paste job. Brain and Rialto need some more work done so their devicetree.cb files will be updated in follow-up patches. BUG=none BRANCH=none TEST=compiled only (for danger, jerry, mickey, romy, speedy) Change-Id: I4fd549c82c8a5c31525c4e485fa8df73f33f2049 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: bd88973b53949058331613c7582650fbd4ea48db Original-Change-Id: I47da45c5fd9648544392de8d76f86af812de9093 Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/282610 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/10776 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-06rk3288: Auto-detect display.David Hendricks
We currently select either HDMI or EDP (default). This patch allows us to use HDMI as a fallback for devices that may have a display connected on either interface. It also renames the enums to sound a little more sensible in other contexts (more on that in the follow-up patches). VOP_MODE_AUTO is added to the mode enum which will make it explicit that a board can support either. In AUTO_MODE we will try EDP first and then fallback to HDMI. Other modes can be set to force a certain behavior such as HDMI-only on Mickey where it doesn't make sense to try EDP. A follow-up patch will add logic for when we explicitly don't want to probe for any display (headless devices). BUG=none BRANCH=none TEST=On veyron_danger, connected EDP and HDMI displays and saw dev mode screen appear on EDP display. Unplugged EDP and then dev mode screen showed up on HDMI. Change-Id: I22b38031c4ab3d79fbb182f7a906da1197f35543 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3f57ed3758c4e516d9fd226ad9499b102b81b423 Original-Change-Id: I352dcde16f7f3ebbf5796852b685685e541eb794 Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/281076 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/10775 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-06libpayload: usb: dwc2: support interrupt transferYunzhi Li
dwc2 host core do not have a periodic schedule list, so try to send an interrupt packet in poll_intr_queue() function and use frame number read from usb core register to calculate time and schedule transfers. BUG=None TEST=Tested on RK3288 with two USB keyboards(connect to SoC without USB hub), both work correctly. BRANCH=None Change-Id: I16f7977c45a84b37c32b7c495ca78ad76be9f0ce Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3d0206b86634bcfdbe03da3e2c8adf186470e157 Original-Change-Id: Ie54699162ef799f4d3d2a0abf850dbeb62417777 Original-Signed-off-by: Yunzhi Li <lyz@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/280750 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Commit-Queue: Lin Huang <hl@rock-chips.com> Original-Tested-by: Lin Huang <hl@rock-chips.com> Reviewed-on: http://review.coreboot.org/10774 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-06libpayload: arm(64): add read8/16/32 and write8/16/32Daisuke Nojiri
This applys the same change made by https://chromium-review.googlesource.com/261692 to libpayload. BUG=none BRANCH=tot TEST=built for veyron_jerry, rush_ryu, samus Change-Id: I26dd66d79cd1559a7852b3c9d252420f2fed5fa0 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d0d6f70aa805e18966e80618fbf9e9605274b030 Original-Change-Id: Ib0c199238f8fa58643d51782b17550dbd0d9ebd7 Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/282541 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10773 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-06rockchip: rk3288: correct ddr 300MHz clock settinghuang lin
CRU request (24MHz * nf) / nr > 440MHz, but now ddr 300MHz setting can't meet this request, so modify it BRANCH=None BUG=None TEST=Set ddr frequency to 300MHz and boot from mickey Change-Id: I00324f5864f5ce8c1a3768268e402e0beca214c6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3d292b67245e714cb03ed35ee28c9b838d514da5 Original-Change-Id: I885704542293ed55e429a0b4b30135af7978990f Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/282445 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/10772 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-06veyron_danger: EDP changes for v2David Hendricks
EDP-related hardware modifications for v2: - BL_EN moved from GPIO7_A3 to GPIO7_A2 - EDP_HPD added to GPIO7_B3 BUG=none BRANCH=none TEST=built and booted Danger v2 with EDP panel attached, saw dev mode screen come up Change-Id: I47383610082b371a612aced656e56f1bd1cfa098 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: fb939ff17cca7bbd24aabfdb3cbd444696a5a845 Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: Id271cdcfcde6fa84c1bb707b9842bddd77a7121b Original-Reviewed-on: https://chromium-review.googlesource.com/280855 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/10771 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-06libpayload: udc: dwc2: support force_shutdown() routineYunzhi Li
Add force_shutdown() routine for dwc2 udc driver to support disconnect and reconnect case when fastboot receiving data. BUG=chrome-os-partner:41687 BRANCH=None TEST=None Change-Id: I9ec204d8b7088cfafd3164c9779a6fd85d379dba Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 9238f87c065ba8a57bfb4a7e65fd1821ff2922f9 Original-Change-Id: I1e584aaf19efa14409bdfa26039c27fa7034b5f0 Original-Signed-off-by: Yunzhi Li <lyz@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/281130 Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> Original-Tested-by: Lin Huang <hl@rock-chips.com> Original-Commit-Queue: Jeffy Chen <jeffy.chen@rock-chips.com> Reviewed-on: http://review.coreboot.org/10770 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-05nvidia/l1_2pvv: whitespace: remove spaces that are followed by tabJonathan A. Kollasch
Change-Id: Ia84df2f4467e102fd5f675dba6432996584d78c1 Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: http://review.coreboot.org/10796 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2015-07-04Kconfig: Fix references to obsolete symbolsMartin Roth
These are all Kconfig symbols that have been removed or renamed. USE_PRINTK_IN_CAR was removed in commit 8c4f31b3 Drop the USE_PRINTK_IN_CAR option. It's a bogus decision... DYNAMIC_CBMEM was removed in commit e2b0affd Remove Kconfig variable that has no effect MAINBOARD_HAS_BOOTBLOCK_INIT was removed in commit 342535cc Remove Kconfig variable that has no effect CACHE_ROM was removed in commit 4337020b Remove CACHE_ROM. SMM_MODULES was removed in commit 44cbe10f smm: Merge configs SMM_MODULES and SMM_TSEG INCLUDE_MICROCODE_IN_BUILD was removed in commit eb73a218 soc/fsp_baytrail: Fix use of microcode-related Kconfig variables CAR_MIGRATION was removed in commit cbf5bdfe CBMEM: Always select CAR_MIGRATION REQUIRES_BLOB was removed in commit 70c85eab build system: Retire REQUIRES_BLOB CPU_MICROCODE_IN_CBFS was renamed to SUPPORT_CPU_UCODE_IN_CBFS in commit 66e0c4c8 - cpu: Rename CPU_MICROCODE_IN_CBFS to SUPPORT_CPU_UCODE_IN_CBFS CONSOLE_SERIAL_UART was renamed to CONSOLE_SERIAL in commit afa7b13b uart: Redefine Kconfig options CONSOLE_SERIAL8250MEM was renamed to DRIVERS_UART_8250MEM in commit afa7b13b - uart: Redefine Kconfig options Change-Id: I8952ca8c53ac2e6cec5f9c77d2f413f086bfab9d Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/10766 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-07-04intel raminit: rename registerPatrick Rudolph
Found while doing code review. Rename reg_4004_b30 to cmd_stretch. Found in 4th-gen-core-family-desktop-vol-2-datasheet.pdf chapter 4.2.1. Change-Id: Ib07059625ed458332708562e836803f2b587d5d8 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: http://review.coreboot.org/10789 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
2015-07-04buildgcc: Deal with gmp on 32bit Linux on 64bit CPUsPatrick Georgi
GMP is overeager to detect 64bit ABIs even if the entire running codebase is 32bit (but on a 64bit CPU). Enforce a 32bit build in that situation. Change-Id: I23e9e57f3c8b0e3ad2e4e1e3eb106f7830aa76a1 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/10792 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-04xcompile: ask for compiler runtime using appropriate CFLAGSPatrick Georgi
xcompile keeps two CFLAGS around now, for GCC and CLANG. Normally they're not required to request the libgcc/compiler-rt path, but with the multilib capable x86_64-elf target it's required to make it pick the right libgcc when used as i386-elf builder. Change-Id: I700e7aa5783dc36698dd2ab8a38642a144e80fe9 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/10795 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-07-04crossgcc: Fix binutils for aarch64Patrick Georgi
The gold linker didn't build. Change-Id: I93c26a7715e781b001a71978d8fadbf65fdfe427 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/10791 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-07-03hp/pavilion_m6_1035dx: Remove 'select USBDEBUG_IN_ROMSTAGE'Kimarie Hoot
Since USBDEBUG is not selected by this platform, there is no benefit to selecting USBDEBUG_IN_ROMSTAGE in the mainboard Kconfig. Further, using a 'select' for USBDEBUG_IN_ROMSTAGE prevents the value from being modified by a user in menuconfig. Change-Id: I67b71a724a8614882cff4bb43b042f0c092d11d2 Signed-off-by: Kimarie Hoot <kimarie.hoot@se-eng.com> Reviewed-on: http://review.coreboot.org/10671 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-07-03Kconfig whitespace cleanup: Change leading spaces to tabsMartin Roth
Change-Id: Icab6bd9f55f086da7b51ae463f34e29366d50e1a Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/10764 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-03SeaBIOS: Change clean to just 'rm -rf seabios/out'Martin Roth
When running 'make clean' if the seabios directory is present, we get warnings about not having IASL installed or that the C compiler can't be executed. It fails to actually run the clean because we're not correctly passing in the toolchain. Just do what the SeaBIOS clean does directly and delete the 'out' directory without actually calling the SeaBIOS clean. Here were the previous warnings: % make clean Unable to execute the C compiler (). Please install a working compiler and retry. Makefile:104: *** "Please upgrade the build environment". Stop. or % make clean The SeaBIOS project requires the 'iasl' package be installed. Many Linux distributions have this package. Try: sudo yum install iasl Or: sudo apt-get install iasl Please install iasl and retry. Makefile:106: *** "Please upgrade the build environment". Stop. Change-Id: Ice41376bc242f1f622d849e7628f8a9b6ef47404 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/10655 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-03storm: Enable DRIVER_UART since we use CONSOLE_CBMEM_DUMP_TO_UARTStefan Reinauer
This fixes the build with CONSOLE_CBMEM_DUMP_TO_UART. Change-Id: Ibe79239c5799a5c4a08ed195fce4d0c63d629ca4 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10769 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-03libpayload: update xcompile scriptPatrick Georgi
Copy from coreboot. at some point it probably should just reuse coreboot's version. Change-Id: Iee905a9060983ff85e2e70bde69a221c64a07cbc Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10756 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-02tegra124: verified boot fixupsStefan Reinauer
This patch fixes up verified boot (vboot2) configuration of all tegra 124 bases boards in the tree. Change-Id: I81f2e83821cbfdbe2a55095543e7447efdde494e Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10761 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-07-02sandy/ivybridge: use LAPIC timer in SMMStefan Reinauer
This fixes an issue with using the flash driver in SMM for writing the event log through an SMM call. Change-Id: If18c77634cca4563f770f09b0f0797ece24308ce Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10762 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-02purin: chromeos.c also needed in romstageStefan Reinauer
Otherwise the Chrome OS build won't succeed. Change-Id: Idf93a09f53d08b6c201f1de140f0fff35f928dcc Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10760 Reviewed-by: Marc Jones <marc.jones@se-eng.com> Tested-by: build bot (Jenkins)
2015-07-02ME/IFD binaries: Implement sane defaults for file pathsStefan Reinauer
Change-Id: I81298aca07c18359e8e4bf5b2d8926d6b45a30c5 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10763 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <gaumless@gmail.com>
2015-07-02ifdfake: Add prompts and help for the regions in KconfigMartin Roth
Update the ifdfake region questions in Kconfig with help descriptions and prompts to allow values to be entered and not just use pre-defined default values. Change-Id: Ifdffadc3d74ec49492c2ded66623a1be6945425f Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/10649 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-02Intel Firmware Descriptor: Add Lock ME Kconfig questionMartin Roth
Add the Kconfig question to allow the user to lock the ME section using ifdtool. Change-Id: I46018c3bc9df3e309aa3083d693cbebf00e18062 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/10648 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-02Move baytrail & fsp_baytrail to the common IFD interface.Martin Roth
- Add the common/firmware subdir to the baytrail & fsp_baytrail makefiles and remove the code it replaces. - Update baytrail & fsp_baytrail Kconfigs to use the common code. - Update the IFD Kconfig help and prompts for the TXE vs ME. - Whittle away at the CBFS_SIZE defaults. All the fsp_baytrail platforms have their own defaults. Change-Id: I96a9d4acd6578225698dba28d132d203b8fb71a0 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/10647 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-02Intel Firmware Descriptor Kconfig: remove USES_INTEL_MEMartin Roth
When I added the common IFD Kconfig and Makefile, My thinking was that I could use this symbol to differentiate between the ME and the TXE, and to exclude the ME questions from platforms that use the IFD, but don't use an ME, like Rangeley. In practice this made things a lot more complicated and isn't worth it. Change-Id: I4428744e53c6bb7fc00a4fa4f0aa782c25fc9013 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/10678 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-01coreinfo: use coreboot's kconfigStefan Reinauer
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Change-Id: I99e612dca3c2e5678d43b3e85eaf2f51d8f693e7 Reviewed-on: http://review.coreboot.org/10715 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-01tegra132: adjust vboot2 memlayout to make coreboot compileStefan Reinauer
romstage didn't fit in it's region anymore. Change-Id: I5a2f41cb0e0a87339dbf61906ee2060e132cc394 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10759 Reviewed-by: Marc Jones <marc.jones@se-eng.com> Tested-by: build bot (Jenkins)
2015-07-01google/veyron_minnie: Add new boardPatrick Georgi
Copied from speedy, with changes to mainboard.c (and speedy -> minnie renames across the directory) Change-Id: Ib38f0b15da8306984869e7ee7b4ddf366b0df82c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10757 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-07-01libpayload: always compile with -ffunction-sectionsStefan Reinauer
Always compile with -ffunction-sections and -fdata-sections This does not hurt, and it allows the linker to produce much smaller binaries in some circumstances. Change-Id: Ibf9f24c210d6d2ed40451b4cf0d68ce88220bc5f Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10750 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-01nvidia/tegra210: Drop unused Kconfig symbolPatrick Georgi
The deleted symbols aren't used anywhere in the coreboot tree and come from the downstream chromeos-2013.04 branch. Change-Id: I0ebc2936dff400cf8fe68794c86ac583aba2a14b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10752 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-01linker scripts: Fix symbol handling for pre-RAM cbmem consolePatrick Georgi
Some ld versions (eg. the one used in the chromium build system) mis-handled the redefined symbol in romstage.ld, so use the feature that exists for precisely that purpose. Change-Id: I184310ab20a02f6b3d569798448eac78b13e88a3 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10754 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-01rockchip/rk3288: Initialize CPU in bootblockPatrick Georgi
Some basic MMU setup is required to allow unaligned memory accesses that happen across our entire codebase. Change-Id: If5a84e19a7a3e47d6009fd073b1323dfb25e6a06 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Found-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/10753 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner@chromium.org>
2015-07-01libpayload: Fix compilation on ARM with GDB enabledStefan Reinauer
Without this, gdb_enter() is not defined. Change-Id: I067dce371ee817d6ac77387fcbe42a9a7deb6438 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10755 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2015-07-01libpayload: Keep stack boundary small on x86Stefan Reinauer
There is no measurable performance impact, but this positively impacts the memory used by payloads. Change-Id: Ib2bdba4a7bf2a4c2391a20b3225bbb44422d3194 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10751 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-01tegra210: Include correct include filesStefan Reinauer
Some include files were unnecessary, and program_loading.h was missing. Change-Id: Ief3d970af5fbbb6b79da06ba3ea1d8613bfc314f Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10749 Reviewed-by: Marc Jones <marc.jones@se-eng.com> Tested-by: build bot (Jenkins)
2015-07-01coreinfo: Use IS_ENABLED() to query Kconfig variablesStefan Reinauer
This will make the code work with the different styles of Kconfig (emit unset bools vs don't emit unset bools) Roughly, the patch does this, and a little bit of fixing up: perl -pi -e 's,ifdef (CONFIG_.+?)\b,if IS_ENABLED\($1\),g' `find . -name *.[ch]` perl -pi -e 's,ifndef (CONFIG_.+?)\b,if !IS_ENABLED\($1\),g' `find . -name *.[ch]` Change-Id: Ia461a33541f58ff39e984119c44ece7e6c05608a Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10713 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-30nvidia/tegra210: reserve more room for the romstage in vboot buildsPatrick Georgi
Change-Id: I11c2e270179c54af8687435ff662a509ac714505 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10733 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-06-30google/foster: roll up fixes to compile with vbootPatrick Georgi
Change-Id: I796e0fa64f9a858a54b09a82fbec1f0576e7e124 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10732 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-06-30google/smaug: roll up fixes to compile with vbootPatrick Georgi
Change-Id: I256410ff6c0107bbbaaf49b909d63ca61e88a22c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10731 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-06-30coreinfo: Drop local Kconfig copyStefan Reinauer
Change-Id: Ice29e63149b97de1b943b3655b984b0ce13a42ba Reviewed-on: http://review.coreboot.org/10714 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-06-30google/smaug: add new mainboardPatrick Georgi
This is an nvidia t210 based board. This includes Chrome OS downstream up to Change-Id: Ic89ed54c. Change-Id: I4d77659f4f2d21b1bbdcfc3467e1a166c02ddd47 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10635 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-30google/foster: add new mainboardPatrick Georgi
This is an nvidia t210 based board. This includes Chrome OS downstream up to Change-Id: Ic89ed54c. Change-Id: I8630e86a4b0e8756693f8989ce147d6d762cefe1 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10634 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-30kconfig: Fix defconfig targetsStefan Reinauer
The syntax of "conf" has changed, but we never adapted our Kconfig Makefile since we are not typically using those targets (except for coreinfo) Change-Id: Ib95b53d255d7456cc6d6bcc7048fcaa0db1ce142 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10716 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-06-30nvidia/tegra210: add new SoCPatrick Georgi
This includes Chrome OS downstream up to Change-Id: Ic89ed54c. Change-Id: I81853434600390d643160fe57554495b2bfe60ab Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10633 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-30google/peach_pit: disable Chrome OS supportPatrick Georgi
The Exynos SoC code and vboot really don't get along and things are not even in a good shape in Chrome OS' top of tree. Disable but don't rip out the support functions, so it could be revived. Change-Id: I982c5a3731b527fd1f1579e9de353819da656452 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10730 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-30google/nyan: remove timestamp leftovers from upstreamingPatrick Georgi
Initializing timestamps and writing the "start romstage" timestamp already happens earlier. One question to sort out is what to do about the migration into cbmem, but at least this compiles again. Change-Id: Ie8a0b7998c6c9da71f036857987f3c781385034f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10729 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-30drivers/i2c/tpm: move tpm driver around a bit more.Patrick Georgi
The many different places to put vboot support in can be confusing. Instead of using libverstage (which isn't enough since those functions are sometimes called outside that, too), mention all stages where it can resides explicitly. Change-Id: Idddb9f5e2ef7bcc273f429d9f432bd37b4573567 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10728 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-30google/link: implement get_write_protect_statePatrick Georgi
Current vboot wants that function. Change-Id: I9d3a592c448cf2af10f76cae4518341cbc0a6f41 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10727 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-30samsung/stumpy: implement get_write_protect_statePatrick Georgi
Current vboot wants that function. Change-Id: Ie3b49aa716d9711223ec71a142878e847eedfe4e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10726 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-30samsung/lumpy: implement get_write_protect_statePatrick Georgi
Current vboot wants that function. Change-Id: I08590739112a7fcce7a983b6d77ff500692ef7d3 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10725 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-30intel/sandybridge: initialize variablePatrick Georgi
Otherwise cache_base may be uninitialized. Change-Id: Ie91f9567cea24114723a5362f52052d6ec22a6b8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10724 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-30google/jecht: Fix compiling GPIO table codePatrick Georgi
A lot changed here between Chrome OS and upstream, and these changes are needed to reflect that. Change-Id: I7195861465388d0f6a7cb540ebf4e410e38c260a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10723 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-30vboot: move vbnv_* sources around a bit more.Patrick Georgi
The many different places to put vboot verification in can be confusing. Instead of using libverstage (which isn't enough since those functions are sometimes called outside that, too), mention all stages where it can resides explicitly. Change-Id: I9360face822ada7018a1cfdfced8da29b347cbb4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10722 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-30libpayload: Makefile: Use variables defined for KconfigStefan Reinauer
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Change-Id: Ia451e8250307ad1944cb0429bdfee4bdf18c706b Reviewed-on: http://review.coreboot.org/10712 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-30libpayload: Drop duplicate copy of KconfigStefan Reinauer
It's perfectly fine to have one single copy of kconfig in the tree. Change-Id: Icfe32f0249dfc1c223009d6e7136462f8f8a7248 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10521 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-30libpayload: Make Kconfig bools use IS_ENABLED()Stefan Reinauer
This will make the code work with the different styles of Kconfig (emit unset bools vs don't emit unset bools) Roughly, the patch does this, and a little bit of fixing up: perl -pi -e 's,ifdef (CONFIG_LP_.+?)\b,if IS_ENABLED\($1\),g' `find . -name *.[ch]` perl -pi -e 's,ifndef (CONFIG_LP_.+?)\b,if !IS_ENABLED\($1\),g' `find . -name *.[ch]` Change-Id: Ib8a839b056a1f806a8597052e1b571ea3d18a79f Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10711 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-30Makefile: Use variables defined for KconfigStefan Reinauer
Change-Id: I72df5fef187e12d1c3c2409449dc9d9b7b80a5e2 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10709 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-30libpayload: Swap the macros of VT100_CURSOR_ON and VT100_CURSOR_OFFHouse Chou
The macros of VT100_CURSOR_ON and VT100_CURSOR_OFF are exchanged Change-Id: Ifdae186ae0503a915d695a9e3fd24bdf65d8428a Signed-off-by: House Chou <hoare.tw@gmail.com> Reviewed-on: http://review.coreboot.org/10718 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-30util/scripts: add some support scriptsPatrick Georgi
These scripts were bit-rotting on my box and may be useful for somebody else. no-fsf-addresses.sh removes various FSF addresses from license headers find-unused-kconfig-symbols.sh points out Kconfig variables that may be unused. There are some false positives, but it serves as a starting point. Change-Id: I8ddb5bea5fe87d39eed5f39f32077944b37d0665 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10675 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-30lib: add delay.c to bootblock if I2C_TPM driver is enabledPatrick Georgi
Change-Id: I752fcc3b8687e4f861c3977322ebb6439f14fac4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10708 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-30drivers/i2c/tpm: push tpm driver from verstage to libverstagePatrick Georgi
That way it's available wherever the verstage code ends up, bootblock, verstage or romstage. Change-Id: I0665e297f199acd60cff93e1b39812f183115d33 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10707 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-30chromeos: push vbnv_* accessors from verstage to libverstagePatrick Georgi
That way they're available wherever the verstage code ends up, bootblock, verstage or romstage. Change-Id: I6e59a40761f95a98d96a9b72e3bbcc59caae9b1a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10706 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-30google/cosmos: romstage needs the accessor functions for buttonsPatrick Georgi
In Chrome OS mode, the romstage tries to interpret the various buttons on the device, so it needs access to the accessor functions. Change-Id: Iecfd37e79883d826e15c474d77095fbbbb2b7cea Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10705 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-30google/storm: romstage needs the accessor functions for buttonsPatrick Georgi
In Chrome OS mode, the romstage tries to interpret the various buttons on the device, so it needs access to the accessor functions. Change-Id: I59a4f892ca84d475d8f46c8f8c1906dae10ad32d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10704 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-30qualcomm/ipq806x: Fix uart in verstagePatrick Georgi
An old Kconfig symbol from Chrome OS survived into the Makefile (but is nowhere declared or used). Use the same symbol as for uart.c in the other stages. Change-Id: I7a6f1b82254e888d6f2d65d6cff87c4d546ec097 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10703 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-06-30qualcomm/ipq806x: centralize vboot configurationPatrick Georgi
vboot configuration (separate stage or not, which stage loads romstage) depends on SoC properties (eg. amount of SRAM), not on board specifics, so move this part of the configuration to the SoC. Change-Id: I70b4cd1794ddf2aba7cdae94859ea1d76ae019f4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10702 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-30google/veyron: Fix building with CHROMEOS enabledPatrick Georgi
romstage requires some button accessor functions for the Chrome OS boot flow. Change-Id: I3f90d66b103e0610931c183dd5f5679ca6f910f6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10697 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-06-30arch/arm64: Avoid race condition when building bl31Patrick Georgi
The arm-trusted-firmware build system may not create the final bl31.elf file atomically, confusing our make to try to use it before it's ready. Hence insert a (hopefully, but not guaranteed to be atomic) file move. Change-Id: Iffc80467e0f4bbc96fc62414d4abfaa7b42634f4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10700 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-06-30mainboard: Add Veyron_SharkJulius Werner
This patch adds the Veyron_Shark mainboard as a clean copy of Veyron_Speedy. - board-ID differentiation removed, see mainboard.c - speedy -> shark rename BRANCH=None BUG=None TEST=Compiled. Change-Id: I3b743a97f152f49647eee87be8f1497377ccacb4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ac2ca328adf7e0dd879f51bbeae3cc11bceebf86 Original-Change-Id: I8a7cc9acb199ecf23b388c66f6885931ea3ec219 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/276490 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/10699 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-06-30hardwaremain: Move init_timer() call to before console initDuncan Laurie
The 8250 MMIO uart driver calls udelay, and if that is the first call then it will also call printk in init_timer() which can result in a deadlock trying to acquire the console lock. There are a few options to prevent this: 1) remove the printk in init_timer which removes a useful debug message 2) change the udelay() to cpu_relax() in uart8250mem.c 3- move the init_timer() call in ramstage main() to be called earlier Since hardwaremain.c:main() already has an explicit call to init_timer() on x86 it is an easy change to move this to happen before the console is initialized. BUG=chrome-os-partner:40857 BRANCH=none TEST=boot on glados with serial output through ramstage Change-Id: I8a8d8cccdd0b53de9de44600076bfad75e4f5514 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 744610f72628a944582925933b286f65bde630d9 Original-Change-Id: Ic1fdafaea5541c6d7b1bb6f15399c759f484aa74 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/275157 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10698 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-06-30arch/arm64: Fix compilation without CONFIG_SMPPatrick Georgi
Compilers aren't happy with a declaration of boot_cpu() after defining boot_cpu to 1. Change-Id: I22d0db61646f3e226e5996fa94223ffbb6b760e5 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10696 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-30t210: Set UTMIP_PCOUNT_UPDN_DIV to 0Stephen Barber
Improve USB device mode stability as per suggestion by Laurent. BUG=chrome-os-partner:40929 BRANCH=smaug TEST=flash firmware and check that USB device mode is still functional. Change-Id: Id6dd7bb2e1632c512cfdf7d38a16de26a8f71471 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4298741ef4440c8bd8dac4a9f9eaa55ba560cbfb Original-Change-Id: I07d6c46d215f2ccf2c76c580f59c4fa0d519eaa5 Original-Signed-off-by: Stephen Barber <smbarber@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/278030 Original-Reviewed-by: Benson Leung <bleung@chromium.org> Original-Tested-by: Benson Leung <bleung@chromium.org> Reviewed-on: http://review.coreboot.org/10695 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-30arm64: Fix Kconfig issues for secure OS loadingFurquan Shaikh
BUG=chrome-os-partner:40713 BRANCH=None TEST=Compiles successfully with and without SECURE_OS config selected Change-Id: I93e9726712a1992f1788d60891d5f6917bba3767 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 535ac9ffd1199b047734da0a9ee257d468b3fbb1 Original-Change-Id: Ic70a0b57816a5f3af548edafd82ba3783825a174 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/274416 Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/10694 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-30arm64: Add support for loading secure osFurquan Shaikh
Add support for loading secure os and pass its entrypoint as bl32 params to bl31 stage. BUG=chrome-os-partner:40713 BRANCH=None TEST=Compiles successfully and loads secure os Change-Id: I1409ccb7344c1d1b1ddc2b321fdae1beea2f823d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d3dc19025ff11c1e0590306230df7654ef9ad086 Original-Change-Id: Iafd540bf2906d10b5ee009e96179121fecbf5e11 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/273719 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/10693 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-30Add Kconfig flag to specify if there's a lid switchPatrick Georgi
Not all devices have a lid switch, so we need to state this somehow. Since the alternative would be to extend get_lid_switch()'s semantics to become a tri-state (open, closed, N/A), do this through Kconfig. BRANCH=none BUG=chromium:446945 TEST=none Change-Id: Icc50f72535f256051a59925a178fb27b2e8f7e55 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d20a1d1a22d64546a5d8761b18ab29732ec0b848 Original-Change-Id: Ie8ac401fbaad5b5a9f1dec2b67847c81f4cc94aa Original-Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/273850 Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Original-Tested-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Queue: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10692 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-30Expose get_lid_switch() in romstagePatrick Georgi
The function was used locally and in ramstage to set some coreboot tables. It's also needed in romstage to deal with "lid closed" behaviour. BRANCH=none BUG=chromium:446945 TEST=none Change-Id: I8ad7061328c45803699321aa9f5edb0ed2288a8d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 78281a104fb9d79696a6ceb2a9a89a391146a424 Original-Change-Id: I56314b9dc9062dd61671982e7ec0ff15d7eb1bae Original-Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/273609 Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Original-Tested-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Queue: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10691 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-30cbfstool: Handle elf with different virtual and physical addressFurquan Shaikh
Adds support in cbfstool to adjust the entry field based on the virtual and physical address in program header. BUG=chrome-os-partner:40713 BRANCH=None TEST=Verified correct entry point address. Trusty loads and boots correctly. Change-Id: I215b0bea689626deec65e15fb3280e369d816406 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 32a740f0b628c124d3251cc416e2fc133bb15c57 Original-Change-Id: Ia999b5c55887c86ef1e43794ceaef2d867957f4d Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/274087 Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/10690 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-30libpayload: add UDC driver for Designware controllerhuang lin
Found in rockchips rk3288 as used in google/veyron. BUG=None TEST=None BRANCH=None Change-Id: I2f2c36c5bea3986a8a37f84c75608b838a8782ae Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 59a0bcd97e8d0f5ce5ac1301910e11b01e2d24b1 Original-Change-Id: Ic89ed54c48d6f9ce125a93caf96471abc6e8cd9d Original-Signed-off-by: Yunzhi Li <lyz@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/272108 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Commit-Queue: Lin Huang <hl@rock-chips.com> Original-Tested-by: Lin Huang <hl@rock-chips.com> Reviewed-on: http://review.coreboot.org/10689 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-30EC: Add new EC host event for FASTBOOT_MODE requestFurquan Shaikh
BUG=None BRANCH=None TEST=Compiles successfully Change-Id: Id24b87e03097eb93c0b4316c853575629e5502aa Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: cf80de709d2bf310a3a37b9897063d2d833933b9 Original-Change-Id: Ia5d42efd81b59c1b99d3be5be6d0c770ad602429 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/280879 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/10688 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-30UDC: Correct cleaning out memory for string descriptorsFurquan Shaikh
BUG=chrome-os-partner:41687 BRANCH=None TEST=Compiles successfully and fastboot devices reports correct serial number even after re-connection. Change-Id: I4741a5d6333523eb47c27b4a20c4ef3f1e853d76 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 6249b1e35391550d788f56a7b3e7a49ae19f0c93 Original-Change-Id: I1348c33f354d11e3c29ccd9da9948cfbeb60aa9e Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/281192 Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/10687 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-30udc/chipidea: Allow force_shutdown of connectionFurquan Shaikh
Allow force shutdown operation of the connection in case where the cable is disconnected and reconnected back. BUG=chrome-os-partner:41687 BRANCH=None TEST=Compiles successfully and fastboot works fine even with reconnection of cable Change-Id: I8eb1217b4a9ad6ce8a2a40db329eca1930eda089 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3d7ab65c459caa4ec526b99a1aee1a31e9cb80da Original-Change-Id: I354c44e0ed2211cb2c4c1ae653d201b7d15ea932 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/281066 Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/10686 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-30veyron_danger: Update SDMMC power on/off code for v2David Hendricks
This re-factors SDMMC power on/off to make corrections and take differences between board versions into account. To avoid similar- but-different case switch statements in romstage.c and mainboard.c, power on/off functions for SDMMC are split into their own .c file. BUG=none BRANCH=none TEST=built and booted of micro-SD card on Danger v2 Change-Id: Ib3069c35ceff1ff98b49579a6298681c1390beee Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: eecfee4a5dd39073b5f966a25991a594b3c4b519 Original-Change-Id: Id86ae7f40687e843ffc4e7769309d4678ad54f49 Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/280853 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/10685 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-30veyron_danger: Add basic HDMI supportDavid Hendricks
This adds a configure_hdmi() function that drives the HDMI enable output high and configures the iomux. We'll add EDP/HDMI auto-detection in an upcoming patch. BUG=none BRANCH=none TEST=set vop_mode to 1 in Danger's devicetree.cb and saw dev mode screen output to HDMI display. Change-Id: I2a208059fee74d436b5a5bedbc677bc59525f935 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 721f326319f727afcf73a0c21d20d26cb463ad71 Original-Change-Id: I139d39749963d4121aaeec0c3da37d825ffa94ac Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/280849 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/10684 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-29vboot2: Enable VBOOT_DYNAMIC_WORK_BUFFER on x86Stefan Reinauer
Change-Id: Iaadbd52d948000d1ed46865b83bdb0f4926ca429 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10677 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-29vboot2: consolidate vboot2 buffer initializationPatrick Georgi
Instead of calling the init function to clear out vboot2 data structures in multiple places, move the function and call close to verstage_main(). Change-Id: If42e18a8e4581f22f7a7aced70ccbe3188bb0cd5 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10701 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-06-29mainboard/msi/ms7135: DSDT: fix PCI and AGR interruptsJonathan A. Kollasch
Tested with interrupting AGP card in AGR slot. PCI slots tested with 3-function OHCI/EHCI USB 2.0 card, covering the INTA-INTC lines in each. Change-Id: I0f8aeba90890a76a7cf9cbee9be7bcf919d1e39a Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: http://review.coreboot.org/10644 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-29mainboard/msi/ms7135: only #include necessary headers in acpi_tables.cJonathan A. Kollasch
Change-Id: I0837a2d1e0d8e233f6ef7d7212ce76f2223d19b9 Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: http://review.coreboot.org/10641 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-28intel raminit: check correct registers in channel_testPatrick Rudolph
Found while doing code review. No actual problem was observed. Test system: * Intel IvyBridge * Gigabyte GA-B75M-D3H Verify byte-lane error count registers 0 to 7 instead of verifying byte-lane error count register 0 eight times in a row. Change-Id: Ife6ac6558b2f65ad947870cde5f15d90560ce6d9 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: http://review.coreboot.org/10664 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-28intel raminit: properly handle DDR3 DIMMs with address mirroringPatrick Rudolph
Issue observed: DDR3 DIMM with address mirroring enabled doesn't work when placed in slot 1 and slot 0 is empty. It does work when placed in slot 0 and slot 1 is empty. Test system: * Intel IvyBridge * Gigabyte GA-B75M-D3H * Kingston KVR1066D3N7/4G (address mirroring enabled DIMM) Problem description: The address mirror enable bit is slot-swapped in the DIMM mapping code, but none of the remaining code is aware of DIMM mapping. Removing the code, that is swapping the mirror enable bit, results in the correct behaviour. The DIMM is now working in every slot. Change-Id: I7a51bbc8d156209449fd67c954930835814a40ee Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: http://review.coreboot.org/10652 Reviewed-by: Nicolas Reinecke <nr@das-labor.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-29 13:03:50 +0000