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2020-04-25include/device/azalia: Add enums and MACROsPatrick Rudolph
Instead of only using magic values add enums and defines to allow writing the codec init sequence in human readable form. This will replace the magic numbers in mainboards HDA verb tables. Change-Id: Icad07c2b550657b879ad9328a70ba44629a0c939 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39694 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-25soc/intel/tigerlake: Fix FSP SPD index for DDR4Furquan Shaikh
For DDR4, FSP expects channel 0 to set SPD for index 0 and channel 1 to set SPD for index 4. This change adds a helper macro to translate DDR4 channel # to the index # that the FSP expects. BUG=b:154445630 TEST=Verified that memory initialization for DDR4 is successful. Change-Id: I2b6ea2433453a574970c1c33ff629fd54ff5d508 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40588 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kane Chen <kane.chen@intel.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2020-04-24soc/intel/xeon_sp/cpx: Calculate number of threads based on socketsAndrey Petrov
Assuming given system is populated with multiple CPUs of same SKUs, calculate number of threads based on MAX_SOCKET. This is a stop gap solution until proper way of identifying total number of sockets is determined. Change-Id: I7ebad3d57c47b9eeb7d727ffb21bc0a1a84734fd Signed-off-by: Andrey Petrov <anpetrov@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40671 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
2020-04-24soc/intel/xeon_sp/cpx: Bump MAX_CPUSAndrey Petrov
Some dual-socket socket systems offer over 100 threads available. Other multi-socket configurations potentially offer even greater numbers of CPUs (over 9000!). Bump MAX_CPUS to 255. Change-Id: I50a181b89f40777a9f7b3881280c7bacf1b947cb Signed-off-by: Andrey Petrov <anpetrov@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40556 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-24soc/intel/xeon_sp/cpx: Work around FSP-M issuesAndrey Petrov
Currently FSP-M does not implement the spec completely, e.g it is unable to use user-provided heap location in CAR. While this is being resolved, this workaround is a stop-gap solution that allows multi-socket usage. TEST=tested on OCP Sonora Pass EVT and Intel Cedar Island CRB Change-Id: Ia2529526a8724cf54377b0bd2339b04fa900815a Signed-off-by: Andrey Petrov <anpetrov@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40555 Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-24mb/intel/cedarisland_crb: Add dummy mainboard_memory_init_params()Andrey Petrov
Add a dummy implementation (currently FSP defaults are meant for CRB). It is needed only to prevent build breakage. Change-Id: I67b1a693886a29bdaf23f1f3f249da52ba65451a Signed-off-by: Andrey Petrov <anpetrov@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40553 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
2020-04-24soc/intel/xeon_sp/cpx: Allow motherboards to set FSP-M parametersAndrey Petrov
We need to allow motherboards to configure certain parameters that are specific to it. Hence, invoke this function. Also, provide a weak motherboard implementation that does nothing. Change-Id: Ifa2824811273236a66e742404856fbe17d4cf496 Signed-off-by: Andrey Petrov <anpetrov@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40552 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-24drivers/ti/tps65913: Hide RTC driver from Kconfig menusPatrick Georgi
It's supposed to be selected by default on devices that ship with the device, while there's little need to add it on other devices. Change-Id: I57badee9ce1e8a3c8df313953aba02cc3489ff97 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40660 Reviewed-by: Michael Niewöhner Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-24drivers/ams: Hide RTC driver from Kconfig menusPatrick Georgi
It's supposed to be selected by default on devices that ship with the device, while there's little need to add it on other devices. Change-Id: I2747c4f825601b2fbffc908821035e4f66c5a3b8 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40659 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-24mb/google/hatch: Change baseboard EC wake & SCI masks to match kohakuTim Wawrzynczak
1) Allows MKBP events from the EC to wake the system from suspend states. 2) Remove EC_HOST_EVENT_MKBP from the EC_SCI_EVENTS mask, so that MKBP events don't generate an SCI. The EC is also being changed to use host events to wake up the system, and use the EC_INT_L line for MKBP IRQ signalling. Otherwise, there would be two IRQs generated for MKBP events. BUG=b:148976961 BRANCH=firmware-hatch-12672.B TEST=Verify MKBP events wake system TEST=Verify MKBP IRQs are run Change-Id: I8420a996cb1975007cbbbefe9e2f8f1fca91b666 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38735 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Shelley Chen <shchen@google.com>
2020-04-24soc/amd/picasso/i2c: don't initialize I2C4 as master and refactor codeMartin Roth
I2C0&1 are either not available or not functional. Add place holders instead, so that the array index matches the I2C controller number. I2C4 is slave device only, so do not initialize it as I2C host controller. Also do some slight refactoring. BUG=b:153152871 BUG=b:153675916 Change-Id: I397b074ef9c14bf6a4f6680696582f5173a5d0d3 Signed-off-by: Martin Roth <martinroth@chromium.org> Signed-off-by: Paul Ma <magf@bitland.corp-partner.google.com> Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1897071 Reviewed-on: https://chromium-review.googlesource.com/2057468 Reviewed-on: https://chromium-review.googlesource.com/2094855 Reviewed-on: https://chromium-review.googlesource.com/2149870 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40247 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-24soc/intel/tigerlake: Add ACPI GPIO opAlex Levin
Add acpigen methods which generate operations to get/set/clear RX/TX GPIOs. Verify it matches https://doc.coreboot.org/acpi/gpio.html. BUG=b:149588766 TEST=confirmed with touchscreen gpios. Signed-off-by: Alex Levin <levinale@chromium.org> Change-Id: Id9fe26f14a606ceedb9db02d76fe8d466d3a21af Reviewed-on: https://review.coreboot.org/c/coreboot/+/40550 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Jes Klinke <jbk@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-24vc/eltan/security/verified_boot/vboot_check.c: Correct code styleFrans Hendriks
Remove double space and limit lines to 96 column. BUG=N/A TEST=Build and boot Facebook fbg1701 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Change-Id: Ib6373bbf9b666540304e8a2bdaa9add9914476bc Reviewed-on: https://review.coreboot.org/c/coreboot/+/40528 Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-24mb/google/hatch: Make Kconfig LAPTOP knob transitively selectEdward O'Callaghan
BUG=b:154071868 BRANCH=none TEST=builds Change-Id: I9c602476a80a97438af01e3c48fac385532373a4 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40510 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Daniel Kurtz <djkurtz@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-24mb/google/hatch: Add Duffy variant specific DPTF parametersEdward O'Callaghan
Copy over DPTF parameters from Puff. BUG=b:153589525 BRANCH=none TEST=none Change-Id: Ic619826205be06f30055fbbc537f3d302dd039bd Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40423 Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Daniel Kurtz <djkurtz@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Chen <tim-chen@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-24mb/google/hatch: Add Kaisa variant specific DPTF parametersEdward O'Callaghan
Copy over DPTF parameters from Puff. BUG=b:153589525 BRANCH=none TEST=none Change-Id: I7270db1283a9c0ee4746da038020e432aeb6dc5e Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40422 Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Daniel Kurtz <djkurtz@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Chen <tim-chen@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-23mb/google/nyan*: Always add RTC driverPatrick Georgi
The device is always there, the Chromium OS configs always enable it, so let's mirror that here for a better out of the box experience. Change-Id: Ia2073ee7ecbdb37473e1f1002bc9ae0f7df58e42 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40657 Reviewed-by: Michael Niewöhner Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-23mb/google/smaug: Always add RTC driverPatrick Georgi
The device is always there, the Chromium OS config always enables it, so let's mirror that here for a better out of the box experience. Change-Id: Ic43a314aaed635ae2943df02abc5d163cc3c4ffd Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40658 Reviewed-by: Michael Niewöhner Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-23src/mainboard: Const'ify pci_devfn_t devicesElyes HAOUAS
Change-Id: I5bb1a819475383719dbda32d9b5fea63da1e6713 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40611 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-23mb/gigabyte/ga-g41m-es2l: Remove unused variable 'dev'Elyes HAOUAS
Change-Id: I9ebba0ee9e59cb7d18b5ce89b048f591a4402543 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40613 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-23mb/google/puff: Switch USB2 port1 and port3Tim Chen
Switch USB2 port1 and port3 for duffy and kaisa due to circuit change. BUG=b:153682207, b:154451230, b:154445635 BRANCH=None TEST=emerge-puff coreboot chromeos-bootimage boot on puff board Change-Id: I9c0cbcbefd045085fb70cf4f41869ab9b98103c4 Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40301 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2020-04-23rules.h: Rename ENV_VERSTAGE to ENV_SEPARATE_VERSTAGEJulius Werner
When CONFIG_SEPARATE_VERSTAGE=n, all verstage code gets linked into the appropriate calling stage (bootblock or romstage). This means that ENV_VERSTAGE is actually 0, and instead ENV_BOOTBLOCK or ENV_ROMSTAGE are 1. This keeps tripping up people who are just trying to write a simple "are we in verstage (i.e. wherever the vboot init logic runs)" check, e.g. for TPM init functions which may run in "verstage" or ramstage depending on whether vboot is enabled. Those checks will not work as intended for CONFIG_SEPARATE_VERSTAGE=n. This patch renames ENV_VERSTAGE to ENV_SEPARATE_VERSTAGE to try to clarify that this macro can really only be used to check whether code is running in a *separate* verstage, and clue people in that they may need to cover the linked-in verstage case as well. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I2ff3a3c3513b3db44b3cff3d93398330cd3632ea Reviewed-on: https://review.coreboot.org/c/coreboot/+/40582 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-04-23vboot: Add permission check for kernel spaceDaisuke Nojiri
This patch restores the permission check for the kernel space which was dropped when read_space_kernel was moved from Depthcharge by CL:2155429. BUG=chromium:1045217, chromium:1020578 BRANCH=none TEST=none Signed-off-by: dnojiri <dnojiri@chromium.org> Change-Id: If6d487940f39865cadc0ca9d5de6e055ad3e017d Reviewed-on: https://review.coreboot.org/c/coreboot/+/40579 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-23Puff: Enable VBOOT_EARLY_EC_SYNCDaisuke Nojiri
Romstage is now where software sync is performed for chromebooks. EFS2 has been ported to romstage from Depthcharge. Puff should follow. This patch enables CONFIG_EARLY_EC_SYNC and disables CONFIG_VBOOT_EC_EFS. EFS2 will be done in romstage. BUG=b:147298634, chromium:1045217 BRANCH=none TEST=Verify software sync succeeds on Puff. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Change-Id: I8d7c25f8281496c7adb282f5d4e0fc192d746e3e Reviewed-on: https://review.coreboot.org/c/coreboot/+/40390 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-23Update vboot submodule to upstream masterDaisuke Nojiri
Updating from commit id 46ff62c3: vboot: stop reading from ACPI for wpsw_boot to commit id 55154620: vboot: Add screens for recovery using disk This brings in 37 new commits. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Change-Id: Ie184cbe6cc18cea540966d5801472ae821ea3e86 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40503 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-22device: Add helper function to find matching device on busFurquan Shaikh
This change adds a helper function dev_find_matching_device_on_bus() which scans all the child devices on the given bus and calls a match function provided by the caller. It returns the first device that the match function returns true for, else NULL if no such device is found. Change-Id: I2e3332c0a175ab995c523f078f29a9f498f17931 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40543 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-22ec/google/chromeec: Add driver for i2c_tunnel device under Chrome ECFurquan Shaikh
This change enables support for generating ACPI nodes for I2C tunnel for any GOOG0012 device that is sitting behind the Chrome EC. It accepts a config "remote_bus" which allows mainboard to configure the id of the remote bus that is being tunneled. BUG=b:154290952 BRANCH=None TEST=Verified that SSDT node for I2C tunnel behind Chrome EC is generated correctly. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: Icfc0ec3725d7f1d20bcb5cb43a0a23aac72bf4eb Reviewed-on: https://review.coreboot.org/c/coreboot/+/40515 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-04-22arch/x86/acpigen_ps2_keybd: Add JP and UK specific keymapsRajat Jain
Add keymaps for keys that are not present in US keyboards. Change-Id: I1ad4c483e81438456533b4c071a4a56cbee88f9c Signed-off-by: Rajat Jain <rajatja@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40542 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-04-22ec/google/chromeec: Add .scan_bus() callback for Chrome EC deviceFurquan Shaikh
This change adds scan_static_bus() as .scan_bus() callback for Chrome EC device which allows scanning of devices sitting behind the EC using the topology provided by mainboard's devicetree.cb. BUG=b:154290952 TEST=Verified with follow-up changes that devices behind EC are scanned correctly. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: Id3630db56774fba1e3fc53bf349588c4c585773b Reviewed-on: https://review.coreboot.org/c/coreboot/+/40514 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-22ec/google/chromeec: Fix acpi_name() for Chrome EC deviceFurquan Shaikh
In ACPI tables, Chrome EC device (CREC - HID GOOG0004) is a child of EC device (EC0 - HID PNP0C09). However, in coreboot device tree, there is no separate chip/device for EC0. Thus, acpi_name() needs to return EC0.CREC as the ACPI name for the Chrome EC device. By returning the ACPI name as EC0.CREC, all devices that live under Chrome EC device can simply call acpi_device_path()/acpi_device_scope() to emit the right path/scope. In the future, if we ever add a special chip driver for handling EC0 (HID PNP0C09), then the ACPI name for Chrome EC can be fixed to return CREC. BUG=b:154290952 TEST=Verified that acpi_device_path()/acpi_device_scope() return the correct name for Chrome EC device. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: Iec4b0226d1e98ddeb0f8ed8b89477fc4f453d221 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40513 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-22device: Add a helper to find device behind a PCI-to-PCI bridge deviceFurquan Shaikh
This change adds a helper function to find PCI device with dev# and function# behind a PCI-to-PCI bridge device. BUG=b:153858769 BRANCH=None TEST=None Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: Ie5672b35cda66431a0f1977f217bdf61d3012ace Reviewed-on: https://review.coreboot.org/c/coreboot/+/40474 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-22device: Add checks for NULL in device_const.c functionsFurquan Shaikh
This change checks to ensure that device/path passed into any of the functions in device_const.c is not NULL. Since NULL is not expected to be passed into these functions, this change adds a die() call in case the assumption is broken. Change-Id: I1ad8d2bcb9d0546104c5e065af1eeff331cdf96d Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40475 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-22mb/google/kukui: kakadu: update the EDID and sequenceScott Chao
The EDID and command sequence are from BOE, the vendor. BUG=b:148997748 TEST=Boots on Chromebook Kakadu and displayed developer firmware screen successfully. Change-Id: Ieb510cb28882afc5b8023c2a57b31187e4a09fbd Signed-off-by: Scott Chao <scott.chao@bitland.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40396 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-22util/scripts/ucode_h_to_bin.sh: Fix .inc-lines with just commentWerner Zeh
There are microcodes in .inc format out in the wild which contains lines with just a comment. So these files look like the following example: ; External header dd 000000001h dd 00000001bh ... ; Data dd 000000000h ... The lines with just a comment starts with a ';' and will break the current awk formatting which is performed to reformat the content into C code style. As we are just interested in the data we can simply drop all lines that start with a ';' which sed can do pretty easy. Change-Id: I9ff5db51667672cffd9d776fb9497962b4a6083a Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40566 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-22util/scripts/ucode_h_to_bin.sh: Drop disruptive quotesWerner Zeh
The double quotes around the remaining shell parameters '${@:2}' causes that the provided *.h files in $(CONFIG_CPU_MICROCODE_HEADER_FILES), which is a space separated list, cannot be broken down to every single file as needed but stay as a single parameter in the for-loop. Therefore, the called function 'include_file' will get a single parameter with all files which will lead to a broken C code in terms of a wrong #include-syntax. This causes the script to fail. To fix this remove the double quotes which works just fine. Change-Id: Iab7b0dc8d850973d6af764899907d383e9ec7743 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40565 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-22util/scripts/ucode_h_to_bin.sh: Replace whitespace with TABsWerner Zeh
Newly added code in commit CB:25546 contains spaces instead of TABs for line indent. Replace every 4 spaces by a single TAB to match our coding guides. Change-Id: Ie3633bb42643f4abb5f1a8827a7dc2c9e023d6aa Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40564 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-22amd/agesa: Make BottomIo position configurableMike Banon
Some PCI peripherals, such as discrete VGA adapters, require a great amount of memory mapped IO. This patch allows the user to select at build time the bottom IO to leave enough space for such devices. We cannot calculate this value at runtime because it has to be set before the PCI devices are enumerated. 0x80000000 has been successfully boot-tested on A88XM-E (fam15tn), G505S (fam15tn) and AM1I-A (fam16kb). Signed-off-by: Mike Banon <mikebdp2@gmail.com> Change-Id: Ie235631231bcb4aeebaff2e0026da2ea9d82f9d0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38472 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2020-04-22configs/config.facebook_fbg1701: Rename fileFrans Hendriks
Jenkins does not build using .config.facebook_fbg1701 on new patches. Rename the config file adding '.mboot_vboot'. Now FACEBOOK_FBG1701 and FACEBOOK_FBG1701_MBOOT_VBOOT are included in Jenkins test result. BUG=N/A TEST=Build and boot Facebook fbg1701 Change-Id: Ib54cc29e7ff34553c19fa3502872d6e7aee5fbe8 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40557 Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-22mb/google/puff: comment schematics changes for USBKangheui Won
USB routing has changed on reference schematics after Puff rev1 has built. This may confuse people trying to c&p devicetree from the Puff. So add comment to clearly note that there was change, hopefully preventing c&p errors. BUG=b:153682207 BRANCH=None TEST=None Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: I5c43a5c04c81b6708c9eeabc48ef11961d7c8561 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40546 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-22mb/google/deltaur: Correct SPD SMBus addressEric Lai
SMBus uses 7-bits address, change it from 8-bits to 7-bits. BUG=b:151702387 TEST=Check Memory SPD data is correct in console log. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I1720b4d6aa0bc785ad86234b3523bb0676ec5c82 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40519 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-04-22mb/google/deltaur: Remove GbE FMAP regionTim Wawrzynczak
Deltan will be using the integrated Intel GbE for LAN functionality. Deltaur will not have a LAN port, and so does not need the GbE region. This patch adds a new FMAP descriptor file which explicitly supports the GbE region (chromeos-gbe.fmd), and removes the GbE region from chromeos.fmd. Deltan is then assigned chromeos-gbe.fmd, and Deltaur is assigned chromeos.fmd. BUG=b:150165131 TEST=emerge-deltaur coreboot chromeos-bootimage and use ifdtool -p tgl -t image-delta{ur,n}.bin to make sure FMAP aligns with IFWI Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ib93d5ba7f8dbf273ba7c1163022661ede1f44ab4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40501 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-22soc/intel/tigerlake: Configure TCSS power managementJohn Zhao
Add Type-C subsystem power management support for RTD3. BUG=b:140290596 TEST=Include "tcss.asl" in platform "dsdt.asl" for coreboot build with the firmware CM. Added acpi debug and booted to kernel. Probed devices PM_STATE transition from D0 to D3 entry/exit while system at S0. TBT PCIe root ports: 00:07.0/00:07.1/00:07.2/00:07.3, offset:0xA4, PM_STATE:D3HT. xhci:00:0d.0, offset:0x74, PM_STATE:D0D3. dma:00:0d.2/00.0d.3, offset:0x84, PM_STATE:PMST. Verified xhci/dma/pcie root ports power runtime_status to be suspended and suspended time tick through /sys/bus/pci/devices/bus:device:func/power. Change-Id: I127d3700ad426a44639ee93b4477be6638b42e1b Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39785 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-04-22nb/intel/haswell: Deprecate WDB params in pei_dataAngel Pons
The WDB (Write Data Buffer) is a data region in CAR, used as a scratchpad in the read and write training algorithms of memory initialization. Both SNB and IVB use this buffer, but HSW does not. Unlike earlier chipsets, Haswell contains much more in-hardware memory training machinery, known as REUT (Robust Electrical Unified Testing). Among other changes, the REUT hardware has a pattern storage buffer, which renders the need for a pattern storage buffer in CAR obsolete. Deprecate the WDB-related parameters in the pei_data structure for Haswell, as they are leftovers from the previous generation's MRC. Remove them from the mainboards, and explain why they are not required. Because the MRC ABI has to remain the same, the layout of pei_data must not be changed, so rename the WDB parameters instead of deleting them. Tested on Asrock B85M Pro4, still boots with the MRC from Google Wolf. Change-Id: I7acc9353a22f8c6f9fe6407617162f35849a79dd Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40406 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-04-21sc7180: Add I2C driversatya priya
Add I2C functionality in coreboot. Change-Id: I61221ffff8afe5c7ede5abb9e194e242ab0274d8 Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36830 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-21sc7180: Add SPI QUP driverT Michael Turney
This implements the SPI driver for the QUP core. Change-Id: I86f4fcff6f9537373f70a43711130d7f28bd5e09 Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36517 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-21sc7180: Add UART supportT Michael Turney
This implements the UART driver in SoC Developer/Reviewer, be aware of this patch from Napali: https://review.coreboot.org/c/coreboot/+/25373/78 Change-Id: I6494daa108197c030577ac86dab71f9ca6c21bdb Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35500 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-21sc7180: Add QUPv3 FW load & configT Michael Turney
UART driver requires firmware loading Developer/Reviewer, be aware of this patch from Napali: https://review.coreboot.org/c/coreboot/+/25372/78 https://review.coreboot.org/c/coreboot/+/27483/58 Change-Id: I4d91dd10488931247f81a87b0bdcc598f4bceb31 Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35499 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-04-21sc7180: clock: Define the UART frequency for QUPV3Taniya Das
The frequency to be used by UART client is 7.3728MHz, thus define it in the clock header to be used by the driver. Tested: UART frequency request by client driver. Change-Id: I1ced350fe9826ea05b03ffc11aced2c21fe85c9e Signed-off-by: Taniya Das <tdas@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40329 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-04-21mb/intel/jasperlake_rvp: Enable Wifi and BTMaulik V Vaghela
Enable Wifi and Bluetooth for Jasper Lake RVP with following changes: 1. Enable related pci root ports for WLAN and BT 2. Disable unused root ports and clkreq for unused clocks 3. Configure GPIOs properly for M.2 port BUG=None BRANCH=None TEST=Code compiles and able to detect Wifi/BT module on board. Change-Id: Ifbd07022c05769c04ecd49c81a4430947125b32a Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39933 Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-21mb/intel/jasperlake_rvp: Configure WWAN GPIOsMaulik V Vaghela
M.2 WWAN interface has GPIOs which requires coreboot to configure all related GPIOs as per board schematics. BUG=None BRANCH=None TEST=code compiles and WWAN device is detected in OS Change-Id: I8ad978a619b50e16ad754177f1eb05cf7670b79f Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39877 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-04-21mb/google/puff: configure USB PLD groupsPeter Marheine
Each physical port should have the same group and position for both USB2 and USB3, but puff and its variants use different layout than the baseboard so they must override PLD. Ports are split into two groups for front and back, with positions in each group numbered from left to right. BUG=b:151579409 BRANCH=none TEST=PLD_GroupToken and PLD_GroupPosition are set as expected in SSDT. Change-Id: Ibe19e4faa1fbc7117687d789e9bd5584852a48c0 Signed-off-by: Peter Marheine <pmarheine@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40516 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-04-20ec/google/chromeec: Fill up SSDT for EC provided PS2 keyboardRajat Jain
Query the EC to get the top row layout, and if it provides one, generate the SSDT for the PS2 keyboard. Signed-off-by: Rajat Jain <rajatja@google.com> Change-Id: I75d2eee32c82b9bee73436b08b5f615d1b388148 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40032 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-20google/chromeec: Add wrapper for EC_CMD_GET_KEYBD_CONFIGRajat Jain
Add a wrapper command for the subject command Signed-off-by: Rajat Jain <rajatja@google.com> Change-Id: I29a4021c2ea0d1cbb4a72f56bf2232d8f9c80ac3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40313 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-04-20arch/x86/acpi: Add code to generate ACPI for PS2 keyboardsRajat Jain
Add new file to generate ACPI _DSD code for PS2 keyboards. The following 2 device properties are generated as needed: function-row-phymap: A list of ordered scancodes for function row. linux,keymap: Symantically, this is an array of "scancode,keycode" tuple entries. Each entry teaches linux the keycode corresponding to a scancode. Signed-off-by: Rajat Jain <rajatja@google.com> Change-Id: I5ee05173106a125793e91c263610731543c85472 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40031 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-04-20libpayload: Make 8250 UART driver relocation safeNico Huber
`lib_sysinfo->serial` is a virtual pointer into coreboot tables. It's not valid across relocation. Accessing the wrong value during relocation of FILO resulted in a hang with DEBUG_SEGMENT and UART console enabled. Work around that by caching the whole table entry locally. An alternative would be to revise `sysinfo`, to contain no virtual pointers to anything outside the payload. Change-Id: I03adaf57b83a177316d7778f7e06df8eb6f9158e Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37513 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reto Buerki <reet@codelabs.ch> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-20security/vboot, mb/google: Fix build errorsPatrick Georgi
There have been two cases of incompatibilities between overlapping changes, and they need to be resolved in a single commit to unbreak the tree: 1. CB:40389 introduced a new use of write_secdata while CB:40359 removed that function in favor of safe_write. Follow the refactor of the latter in the code introduced by the former. 2. CB:39849 changed google_chromeec_get_usb_pd_power_info()'s interface and adapted all its users. Except for duffy and kaisa which were only added in CB:40223 and CB:40393 respectively, so reapply the patch to puff's mainboard.c to their mainboard.c files. Change-Id: Ib8dfcd61bb79e0a487eaa60e719bd93561f2d97a Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40518 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2020-04-20mb/google/hatch/vr/puff: Add psys_pmax calculationGaggery Tsai
This patch adds psys_pmax calculation. There are two types of power sources. One is barrel jack and the other is USB TYPE-C. The voltage level is fixed for a barrel jack while TYPE-C may vary depending on power ratings. We need to get voltage information from EC and calculate correct psys_pmax value. The psys_pmax needs to be set before FSP-S since FSP-S will handle the setting passing to pcode, so move the routine ahead to variant_ramstage_init. BUG=b:151972149 TEST=emerge-puff coreboot chromeos-bootimage check firmware log and ensure psys_pmax is passed to FSP check the data from dump_intel_rapl_consumption in the OS and ensure the power data is close to an external power meter. Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Change-Id: I8ea01f856411e05a533489280fc2b4a46a1440c5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39850 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-04-20Doc,util: Update list of utilitiesJacob Garber
Remove entries for old utilities and add entries for new ones. Generated using util/util_readme, with some tweaks to preserve the markdown. Change-Id: I3a4d8a6bf15a677aa07aa72b8809328110fb72da Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40504 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-20mb/asus/p8h61-m_lx3_r2_0: Add new mainboardAngel Pons
This is a micro ATX board with a LGA1155 socket and two DDR3 DIMM slots. Porting was done using autoport and then doing a bunch of manual edits. Actually, I have the PLUS variant, but they use the same PCB. The only difference is the capacitor quality. Working: - Both DIMM slots - PS/2 keyboard - S3 suspend/resume - Rear USB ports - Integrated graphics (libgfxinit) - VGA - All PCIe ports - Realtek GbE (coreboot must set the MAC address) - SATA ports - Native raminit - Flashing with flashrom - Rear audio output - VBT - Arch Linux using CorebootPayloadPkg Untested: - PS/2 mouse - The other audio jacks - EHCI debug - Front USB headers - Non-Linux OSes Change-Id: I385ee72673202d896041209ff2911995307cb6af Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39099 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-04-20mb/google/deltaur: Add memory topology SODIMM and MEMORYDOWNEric Lai
Update memory topology for spd info. Deltan supports SODIMM and Deltaur supports MEMORYDOWN. BUG=b:151702387 Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: If314894325d6f222807030a36f8c4cefecfe5bd3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40486 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-04-20Doc/mb/hp: rename the document about HP laptops with KBC1126Iru Cai
Later EliteBooks use different EC chips and have different EC firmware interfaces, so rename the document elitebook_series.md to a more precise name and also do some rewriting. A link to the code review page for 8760w is also added because the port for this laptop is not merged yet. Change-Id: I2f9b8c4e52ed760c16977d16838cca9e490cda05 Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40315 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-20google/chromeec: Revise parameters of EC USB PD API callGaggery Tsai
This patch adds voltage and curent parameters in google_chromeec_get_usb_pd_power_info and remove power parameter. Caller could use the voltage and current information to calculate charger power rating. The reason for this change is, some applications need the voltage information to calculate correct system power eg PsysPmax. BUG=b:151972149 TEST=emerge-puff coreboot; emerge-fizz coreboot Change-Id: I11efe6f45f2f929fcb2763d192268e677d7426cb Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39849 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-04-20soc/intel/tigerlake: Update iDisp Link UPD settingsSrinidhi N Kaushik
Remove explicit setting of iDisp Link parameters. These settings are related to configuration for the link between HD-Audio controller and Display unit for purposes of HDMI/DP Audio playback. During PO, observed that without setting these params display part was not binding. With the latest code verified that we dont need to explicitly set these parameters anymore. HDMI/DP audio playback works fine with default settings. BUG=b:151451125 BRANCH:none TEST= build and boot volteer/ripto and verify HDMI/DP audio playback Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: Ie003d119918d363e2ff9172936b70416fd73c7f4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40263 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Jairaj Arava <jairaj.arava@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-20soc/amd/stoneyridge/memmap: fix bug in bert_reserved_regionFelix Held
Changing the local pointer "start" has no effect. Changing the value it points to has. Change-Id: I1b689896fcf255b795b27d7a7163849d6dfdb00e Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40506 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-04-20mb/asus/p2b*: Switch to overridetreeKeith Hui
All variants will use the same lid/thermal-polarity config as a result, which looks the same for all recently boot-tested variants anyway. Change-Id: Iaaae4eae41ab0037e72375b255d9d1c3eca8d383 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39905 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-20mb/google/deltaur: Correct H1 I2C gpio pin settingEric Lai
H1 uses I2C3 in the HW schematics and connects to GPP_H6 and GPP_H7. Previous setting was wrong so correct it. BUG=b:150165131 Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I43c18baea66b927d51689579a40a53f72b94ef36 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40487 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-20mb/google/volteer: add ec device entry to devicetreeNick Vaccaro
BUG=b:154279851 TEST=none Change-Id: Ibb56d97d5180ab199c52119135f7eff265908667 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40494 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-04-20soc/amd: replace remaining license headers with SPDX onesFelix Held
Change-Id: Ib45e93faebc2d24389f8739911419dfec437bd59 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40505 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-20soc/intel/common: Add _DSM methods for LPIT tableVenkata Krishna Nimmagadda
This patch adds _DSM Method in LPIT table for entering and exiting S0ix. This method get injected into DSDT table and called from kernel. LPIT table is hardcoded in this patch but the proper way to implement is to use inject_dsdt to make the _DSM methods available for soc's to implement. Calling the LPIT table from mainboard here so that with the current implementation the platforms which do not have lpit support throw compilation error. BUG=b:148892882 BRANCH=none TEST="BUILD" Signed-off-by: Venkata Krishna Nimmagadda <venkata.krishna.nimmagadda@intel.com> Change-Id: Ib58f2e33a33bac9cc5f6aca28e85a8066413a5cf Reviewed-on: https://review.coreboot.org/c/coreboot/+/40259 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Venkata Krishna Nimmagadda <Venkata.krishna.nimmagadda@intel.com>
2020-04-20mb/google/dedede: Disable dynamic clock gating for cr50's GPIOIan Feng
Disable dynamic clock gating for the community cr50's IRQ lives on. That IRQ is pulsed very quickly, and with clock gating enabled pulses tend to be missed. This is expecially true on the default 0.0.22 firmware that cr50 comes with out of the factory. BUG=b:154178408 b:154293730 BRANCH=None TEST=build waddledoo successful and Linux has no TPM IRQ timeout error. Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: I2b1b3ee59ebf6adce0653e7550b457e02d3c87df Reviewed-on: https://review.coreboot.org/c/coreboot/+/40480 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-04-20mb/google/dedede: Read DRAM population strapKarthikeyan Ramasubramanian
Configure DRAM population strap GPIO according to the schematics. Configure an internal pull-up to support the boards in which the strap is not populated. Read the strap and pass that information to FSP for memory initialization. BUG=b:152275658, b:154301008 TEST=Build and boot the mainboard. Ensure that the strap information is read as expected and passed to FSP. Change-Id: I69583f35ffc219bae9ce06bd4ba9898ed0d4d21d Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39812 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-20mb/asus/am1i-a/buildOpts.c: set a board type to AMD_PLATFORM_DESKTOPMike Banon
Original AMD_PLATFORM_MOBILE is incorrect because this board is a desktop one. Signed-off-by: Mike Banon <mikebdp2@gmail.com> Change-Id: I02adedffe8624c38e7b93fadd0449ddf094388fd Reviewed-on: https://review.coreboot.org/c/coreboot/+/33919 Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-20mb/asus/am1i-a/buildOpts.c: guard UMA-related options with CONFIG_GFXUMAMike Banon
Looks like the guard was dropped by mistake. Signed-off-by: Mike Banon <mikebdp2@gmail.com> Change-Id: Ie73c4d6cb557820ae7427fef15ca8110722c5b68 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33916 Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-20mb/asus/am1i-a/buildOpts.c: return the removed commentsMike Banon
These comments exist in other buildOpts.c files, but not in this one. Tested with BUILD_TIMELESS=1, hashes do not change. Signed-off-by: Mike Banon <mikebdp2@gmail.com> Change-Id: Ic0aab06f1956bc0bf9f96d6176643c113a1e4cc5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33915 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2020-04-20mb/asus/am1i-a/buildOpts.c: Use fully-qualified paths on includesMike Banon
This makes it easier to know which files are being included. Tested with BUILD_TIMELESS=1, hashes do not change. Signed-off-by: Mike Banon <mikebdp2@gmail.com> Change-Id: Ic096848f23910e2ad9183e44d882450ab8d4fdf1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33914 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-20mb/asus/am1i-a/buildOpts.c: reorder lines for comparison convenienceMike Banon
Reorder lines to make it more similar to buildOpts.c of Lenovo G505S. This improves diff results, which is convenient for debugging. Tested with BUILD_TIMELESS=1, hashes do not change. Signed-off-by: Mike Banon <mikebdp2@gmail.com> Change-Id: I1674252fab2fc6fbf9be2b37e97a6f5ff97a04b3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33913 Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-20soc/intel/tigerlake: Merge the recent change from other platformsWonkyu Kim
Merge the recent change from other platform(ICL/JSL). - Update SKpMpInit setting - Update APIs for getting dev info - Update IGD related setting - Update debug interface setting BRANCH=none TEST=build and boot ripto/volteer Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: Ie4dd4bcef3d8afc71ae4a542dbe8e4ba385593cd Reviewed-on: https://review.coreboot.org/c/coreboot/+/40349 Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-20mb/google/volteer: Update devicetree based on EDSWonkyu Kim
Update device enable/disable based on PCH EDS#576591 vol1 rev1.2 BRANCH=none BUG=b:154037185 TEST= boot up OS in volteer and check and check lspci Unsupported IP should be visable from lspci result Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: I61a328da1014ab7584c3ec789971a106c7a0a403 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40394 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-20mmio: Fix failure in bit field macro when accessing >30 bitsHung-Te Lin
For bit fields with 31 bits (e.g: DEFINE_BITFIELD(MYREG, 30, 0) ), the calculation of mask value will go overflow: "error: integer overflow in expression '-2147483648 - 1' of type 'int' results in '2147483647'". And for bit fields with 32 bits (e.g: DEFINE_BITFIELD(MYREG, 31, 0) ), the error will be: "error: left shift count >= width of type [-Werror=shift-count-overflow]" To fix these issues, the bit field macros should always use unsigned integers, and use 64bit integer when creating mask value. Change-Id: Ie3cddf9df60b83de4e21243bfde6b79729fb06ef Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40404 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-04-20mb/google/dedede: remove samsung-K4U6E3S4AA-MGCL.spd.hexMarco Chen
The samsung-K4U6E3S4AA-MGCL.spd.hex is not used and planed by anyone yet. On the other hand, the spd content is not correct based on JSL spec as well. BUG=b:153426401 TEST=build waddledoo and waddledee successfully. Change-Id: If71e3ef2e3385378633549bf8709a1cd6ecc0dd3 Signed-off-by: Marco Chen <marcochen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40433 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-04-20drivers/pc80/rtc: Reorganize prototypesKyösti Mälkki
Change-Id: Idea18f437c31ebe83dd61a185e614106a1f8f976 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38199 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-20drivers/pc80/rtc: Move CMOS_POST_BANK_x definitionsKyösti Mälkki
Change-Id: I8b56df6de7529772b0f1a59002f92c4f31486bf0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38196 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-20drivers/pc80/rtc: Drop CMOS_POST_EXTRA optionKyösti Mälkki
Change-Id: I379a5664776624600ff1c2919bffa77c877d87ab Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38191 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-20drivers/pc80/rtc: Clean up post_log_path()Kyösti Mälkki
Change-Id: I605d39d907e083e73af4c72607216384e7ce166a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38190 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-20drivers/elog,pc80: Move cmos_post_log()Kyösti Mälkki
Do this to remove elog header dependency from pc80/ and remove some preprocessor guards. Change-Id: I98044a28c29a2b1756fb25fb593f505e914a71c0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38189 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-20mb/intel/jasperlake_rvp: Add SD Card gpio config for JSLRVPRonak Kanabar
Configure write protect and card detect SD Card GPIO for JSLRVP as per schematics. BUG=None BRANCH=None TEST=Build, boot JSLRVP and verified SD Card detection. Change-Id: I8114d6980a2a542538b05f812ca2cffc15c88c22 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39492 Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-20util/cbfstool: Allow use of non-ASCII longoptFurquan Shaikh
CB:29744 ("util/cbfstool: Add optional argument ibb") added support for non-ASCII characters for long_options. However, there is a check later on which errors out since this character is not one of the commands[i].optstring. This change adds a function valid_opt() which does the following things: 1. Checks if the returned optchar is among the list of optstring supported by the command. 2. Checks if the returned optchar is a valid non-ASCII option. Currently, we do not maintain a list of non-ASCII options supported by each command. So, this function returns true if the optchar returned by getopt_long falls within the allowed range. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I27a4f9af9850e4c892573202904fa9e5fbb64df6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40375 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-04-20Makefile: Set FMAP size to 0x200 for non-x86 boards with default fmdFurquan Shaikh
This change updates FMAP_FMAP_SIZE for non-x86 boards using default fmd file to be 0x200 just like for x86 boards. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I3f58696b26fbb5363d67bec4056653da83485776 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40374 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-04-20Makefile: Simplify calculation of region base with default fmd filesFurquan Shaikh
When using default fmd files, base of the fmap region is currently calculated based on the size and base of previous fmap regions. Since the existence of any fmap region is dependent on the selection of certain CONFIG_* parameters, these calculations get complicated. Every time base is calculated for a region, there need to be checks to see which of the previous regions really exist. As the regions in default fmd file are increased, these calculations and the conditional checks get even more complicated. This change introduces a Makefile variable FMAP_CURRENT_BASE which is updated every time a new region is allocated space. This allows using the same steps for determining the base of any fmap region irrespective of the state of previous regions. The way the code is organized it should be possible in the future to also add a macro to perform the same steps (in case that is possible). TEST=Verified that coreboot image generated remains unchanged for x86 and ARM boards using the default fmd files. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I2a109462928b6e8b7930bbcc1a1ba45fa85de6ac Reviewed-on: https://review.coreboot.org/c/coreboot/+/40373 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-04-20vboot/secdata: remove retries, readback, and CRC checkJoel Kitching
Depthcharge trusts that our TPM driver is working reliably, and so should we. Also remove CRC check -- the value returned by antirollback_read_space_firmware() is dropped in vboot_logic.c verstage_main(), and vboot handles this check internally. BUG=b:124141368, chromium:972956 TEST=make clean && make test-abuild BRANCH=none Change-Id: I5d3f3823fca8507fd58087bb0f7b78cfa49417ab Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40359 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-04-20vboot: remove leftover TPM_PCR_GBB constantsJoel Kitching
These constants were left behind after the code using them was relocated in CB:34510. BUG=b:124141368, chromium:972956 TEST=make clean && make test-abuild BRANCH=none Change-Id: I6ce7c969a9e9bdf6cdce3343ba666a08b3521f27 Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40358 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-04-20mb/tglrvp: Configure intel common configWonkyu Kim
Configure lockdown and i2c speed setting. BUG:b:151161585 BRANCH=none TEST=build and boot tglrvp and check FSP logs to lockdown parameters Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: Id7a1e9bd94ff86faa390b5de0518e8b3cb668bff Reviewed-on: https://review.coreboot.org/c/coreboot/+/40116 Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-20mb/google/deltaur: Enable Cirque touchpad for DeltanEric Lai
Reference Arcada to add device tree for Cirque touchpad. BUG=b:152931802 Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ia354702c8054b5826d45896f7bff268335726028 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40114 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-04-20mb/google/drallion: Increase Melfas touchscreen stop delay to 115msJohn Su
Modify stop_delay as 115ms to waiting for Melfas device I2C interface ready after touch fw auto update and rebind driver. BUG=b:153708773 BRANCH=drallion Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: Ib392190d2b4188ee228d8ca4873e03176d2f127f Reviewed-on: https://review.coreboot.org/c/coreboot/+/40357 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Mathew King <mathewk@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-19nb/intel/sandybridge: Refactor get_mem_min_tckAngel Pons
It is not necessary to pass its value around various function calls. Move it closer to where it is actually used, so as to make it static. Also, use config_of_soc and flip the branches of the first conditional. Tested on Asus P8Z77-V LX2, still boots. Change-Id: I5c49c943c87218d4d40d3168bd8b7b900b0ec2e9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39851 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-18drivers/pc80/rtc: Turn comment into warning messageNico Huber
Change-Id: I80786042b1c464268cae8093bd5d3e8d73be5aee Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40320 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-18mb/qemu-i440fx,q35: Fix option tableNico Huber
Reserve bytes 50 and 55 as they are handled as century bytes by QEMU. Change-Id: I9271253bce560d4ec8a51a24c45473acec469187 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40319 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-18mb/qemu-q35: Select `HAVE_CMOS_DEFAULT`Nico Huber
Change-Id: If4c4dc9467154a18168550538fc8e655636e87a0 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40318 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-18mb/intel/harcuvar: Fix board_id() return typeJacob Garber
The weak definition of board_id() in coreboot_table.c returns a uint32_t, so update this function to match. This fixes a compiler error when using LTO. Change-Id: I6ad03ecedcf4a4d9f0c917cdc760f81ddde06d11 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39015 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Guckian Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-18vc/amd/agesa/f15tn,f16kb: Fix array typesJacob Garber
These variables are declared to be arrays of MICROCODE_PATCHES_4K (which is a struct containing a UINT8 array). However, the actual definitions of these arrays ignore the wrapping struct and just use the underlying UINT8 arrays directly, which causes a compiler error when using LTO because of the type mismatch. Fix the type declaration so that it matches. Change-Id: I6bef27507092fe72fe2f836c427ebb2c19009e78 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40436 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>