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2015-10-09northbridge/intel/sandybridge: Enable PEG clock-gating on demandPatrick Rudolph
Activate PEG clock-gating only if all PEG devices are disabled. Fixes system hang when trying to access PEG registers. Test system: * Intel Pentium CPU G2130 * Gigabyte GA-B75M-D3H Change-Id: I7d62fbb83c16741965639cea1a0e4978d4e3d6da Signed-off-by: Patrick Rudolph <siro@das-labor.org> Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/11059 Tested-by: build bot (Jenkins)
2015-10-08cbfstool: allow printable characters in image nameAndrey Petrov
Currently cbfstool would reject non-alpanumeric characters in image names. Underscore is not alphanumeric and is used in some default fmaps. This change allows image names to contain all "printable" characters except spaces. Change-Id: I6ba2b581d5623f5b028149ece0169892ea63fd04 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: http://review.coreboot.org/11807 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-08arch/x86/bootblock: Do not include non-code files in bootblock.SAlexandru Gagniuc
Since we now have more freedom in the bootblock linking step it no longer makes sense to use a monolithic bootblock.S. Code segments must still be included as the order in bootblock.S determines code flow. However, non-code flow related assembly stubs don't need to be directly included in bootblock.S Change-Id: I08e86e92d82bd2138194ed42652f268b0764aa54 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/11792 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-10-08arch/x86: Link walkcbfs.S instead on including it in bootblock.SAlexandru Gagniuc
The code flow doesn't fall through to walkcbfs, as it does in the rest of bootblock.S. Instead, walkcbfs is called (albeit via a jmp). The linker cannot know this when walkcbfs.S is included directly. When we use a CAR bootblock, we lose several hundred bytes because walkcbfs is not garbage-collected, yet it isn't used. This problem is solved by assembling walkcbfs.S separately, and linking it. Change-Id: Ib3a976db09b9ff270b7677cb4f9db80b0b025e22 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/11785 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-08arch/x86/bootblock: Link in object files selected with bootblock-yAlexandru Gagniuc
As part of preparing for systems with non-memory-mapped media, we want to be able to call into C code. This change allows us to link C code directly into the bootblock. The steps of going from bootblock main() to CAR setup to C code will be implemented in subsequent patches. Note that a few files selected with bootblock-y will now be compiled for the bootblock as well, but since we enabled garbage collection, they will not be included in the final binary. Change-Id: I5ca6dcaf176f5469c6a3bb925859399123493bc6 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/11783 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2015-10-08arch/x86/Makefile.inc: Simplify rule for bootblock.debugAlexandru Gagniuc
The only difference between the ifeq/else/endif guarded rules is the linker flags specific to x86. Add those flags to LDFLAGS_bootblock, and only use one rule for bootblock.debug. Change-Id: I986a93e0418f05fb273512d7efe0573052493332 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/11782 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-10-08lib/gcov-glue.c: Define macro `COVERAGE_MAGIC` and use itPaul Menzel
The macro is defined in `util/cbmem/cbmem.c` too, so do the same here, so that searching for that macro name shows all the usages. Change-Id: I52e9fa414fbbe2012bc6d00312db528efba3e564 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/11803 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2015-10-08fsp1_0: Fix broken logic when searching for FSPWerner Zeh
Commit 47818b4d6017b89e398cfbc86e3c437e0f81cfdf (fsp/cache_as_ram.inc and boards: Fix incorrect usage of POST_IO) breaks the logic which decides whether FSP could be found or not in cache_as_ram.inc. Fix the error by inverting the logic of the test. TEST=Bootet mc_tcu3 board Change-Id: I993d3422ac406d204a53e4dc890210fb9a52469d Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: http://review.coreboot.org/11806 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-10-07cbfs: add struct cbfsfAaron Durbin
Now that cbfs is adding more metadata in the cbfs file header one needs to access that metadata. Therefore, add struct cbfsf which tracks the metadata and data of the file separately. Note that stage and payload metadata specific to itself is still contained within the 'data' portion of a cbfs file. Update the cbfs API to use struct cbfsf. Additionally, remove struct cbfsd as there's nothing else associated with a cbfs region aside from offset and size which tracked by a region_device (thanks, CBFS_ALIGNMENT!). BUG=None BRANCH=None TEST=Built and booted through end of ramstage on qemu armv7. Built and booted glados using Chrome OS. Change-Id: I05486c6cf6cfcafa5c64b36324833b2374f763c2 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11679 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-07x86/bootblock: Use LDFLAGS_bootblock to enable garbage collectionAlexandru Gagniuc
The x86 bootblock linking is a mess. The bootblock is treated in a very special manner, and never received the update to link-time garbage collection. On newer x86 platforms, the boot media is no longer memory-mapped. That means we need to do a lot more setup in the bootblock. ROMCC is unsuitable for this task, and walkcbfs only works on memory-mapped CBFS. We need to revise the x86 bootflow for this new case. The approach this patch series takes is to perform CAR setup in the bootblock, and load the following stage (either romstage or verstage) from the boot media. This approach is not new, but has been done on our ARM ports for years. Since we will be adding .c files to the bootblock, it is prudent to use link-time garbage collection. This is also consistent to how we do things on other architectures. Unification FTW! Change-Id: I16b78456df56e0053984a9aca9367e2542adfdc9 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/11781 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-10-06vboot2: Look up actual CBFS in MULTIPLE_CBFS configurationPatrick Georgi
Up to now, the multi-CBFS code path merely looked up files in the "boot ro" image (ie. the default), disregarding the specified fmap region to use for CBFS. The code still relies on the master header being around, which on the upside allows it to skip an offset at the beginning of the region (eg. for ARM bootblocks). This will change later (both the reliance on the master header and the presence of the bootblock like this). Change-Id: Ib2fc03eac8add59fc90b4e601f6dfa488257b326 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/11805 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-10-06fsp/cache_as_ram.inc and boards: Fix incorrect usage of POST_IOAlexandru Gagniuc
POST_IO is a user-visible config bool. fsp_1_0/cache_as_ram.inc made a mess of it, by forcing a build-time error when CONFIG_POST_IO was not being set. fsp 1.0 boards ended 'select'ing this in their Kconfig. Refactor fsp/cache_as_ram.inc handling of POST codes, and remove the "select POST_IO" from boards that have it. Instead of implementing an ad-hoc changing post code display and a delay based on port 0xed, just encode the FSP failure code in the POST code. Since FSP failure codes are > 16, we can encode the failure code in the lower nibble, and theirfailing function in the upper nibble. Change-Id: Iaa3e6533e8406b16ec0689abd704984d79293952 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/8485 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2015-10-05cpu/Makefile.inc: Only inculde x86 subdir if ARCH_x86 is selectedAlexandru Gagniuc
There is no other guard to prevent this from being picked up when building for other architectures. Change-Id: I2039a289a4dd9970d5dd0f90d43d5d5c2a6d0a0b Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/11795 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-10-05Add EM100 'hyper term' spi console support in ramstage & smmMartin Roth
The EM100Pro allows the debug console to be sent over the SPI bus. This is not yet working in romstage due to the use of static variables in the SPI driver code. It is also not working on chipsets that have SPI write buffers of less than 10 characters due to the 9 byte command/header length specified by the EM100 protocol. While this currently works only with the EM100, it seems like it would be useful on any logic analyzer with SPI debug - just filter on command bytes of 0x11. Change-Id: Icd42ccd96cab0a10a4e70f4b02ecf9de8169564b Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/11743 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-10-05buildgcc: Fix the binutils-no-doc patch with 2.25zbao
The binutils-2.25 has added some new line, making the hunk move downward a little. The utility patch can fix the offset with "fuzz" message. So, recreate the patch to avoid that message. Change-Id: Ie659a8faf923465f6d47f7c0c0bf903c5eb903ab Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/11639 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-05buildgcc: Add patch for building binutils by clang 6.0zbao
Clang is the default compiler on BSD and OS X. With this change, we don't have to install gcc any more. Clang can act as host cc. This is a known issue on GNU mail list. Please refer the link below. https://sourceware.org/bugzilla/show_bug.cgi?id=17473 Change-Id: I0f014b776e86e6d0cbebd560cb17f469f31e1dfb Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/11638 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-05buildgcc: Show the progress when downloadingzbao
Grep the output of wget, showing only the percentage. Leave the final "100%" unerased. Checking return code of wget is removed. Change-Id: I4559e88d541738a594dce92e23589992f234cb9b Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/11520 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-05libpayload: Check for CBFS_DEFAULT_MEDIA in cbfs_get_file_content()Nico Huber
The error-prone interface of cbfs_get_file_content() led to another possible NULL dereferencing. So check for CBFS_DEFAULT_MEDIA here like the other functions do. Change-Id: Ib8732160d389e9ecceb44f28be0e7de9a1d66e04 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/11796 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-10-04northbridge/intel/nehalem: Fix native VGA initNicolas Reinecke
Building an image for the Lenovo X201 with native graphics initialization selected fails due to the changes introduced by commit a3b898aa (edid: Clean-up the edid struct). Same as in 11738 / 11585 / 11491 Change-Id: I4233a4ce2f5423c7ebdad68e8059cd34ac61cfaa Signed-off-by: Nicolas Reinecke <nr@das-labor.org> Reviewed-on: http://review.coreboot.org/11787 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-10-04drivers/uart/Kconfig: Select 8250 mem when 8250 mem32 is enabledAlexandru Gagniuc
Users of DRIVERS_UART_8250MEM_32 would have to also select DRIVERS_UART_8250MEM to avoid missing Kconfig dependencies. Instead, do what the OXPCIE driver dies and select the appropriate options. Change-Id: I40d93df024fcb3a9ad6dc51d6a5966e7b1b6c07f Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/11786 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-10-03Remove FSP Rangeley SOC and mohonpeak board supportAlexandru Gagniuc
mohonpeak is the reference board for Rangeley. I doubt anyone uses it or cares about it. We jokingly refer to it as "Moron Peak". It's code with no known users, so we shouldn't be hauling it around for the eventuality that someone might use it in the future. Change-Id: Id3c9fc39e1b98707d96a95f2a914de6bbb31c615 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/11790 Tested-by: build bot (Jenkins) Reviewed-by: Philipp Deppenwiese <zaolin@das-labor.org>
2015-10-03Remove sandybridge and ivybridge FSP code pathAlexandru Gagniuc
We already have two other code paths for this silicon. Maintaining the FSP path as well doesn't make much sense. There was only one board to use this code, and it's a reference board that I doubt anyone still owns or uses. Change-Id: I4fcfa6c56448416624fd26418df19b354eb72f39 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/11789 Tested-by: build bot (Jenkins) Reviewed-by: Philipp Deppenwiese <zaolin@das-labor.org>
2015-10-03sandybridge ivybridge: Treat native init as first class citizenAlexandru Gagniuc
This is a sad story. We have three different code paths for sandybridge and ivybridge: proper native path, google MRC path, and, everyone's favorite: Intel FSP path. For the purpose of this patch, the FSP path lives in its own little world, and doesn't concern us. Since MRC was first, when native files and variables were added, they were suffixed with "_native" to separate them from the existing code. This can cause confusion, as the suffix might make the native files seem parasitical. This has been bothering me for many months. MRC should be the parasitical path, especially since we fully support native init, and it works more reliably, on a wider range of hardware. There have been a few board ports that never made it to coreboot.org because MRC would hang. gigabyte/ga-b75m-d3h is a prime example: it did not work with MRC, so the effort was abandoned at first. Once the native path became available, the effort was restarted and the board is now supported. In honor of the hackers and pioneers who made the native code possible, rename things so that their effort is the first class citizen. Change-Id: Ic86cee5e00bf7f598716d3d15d1ea81ca673932f Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/11788 Tested-by: build bot (Jenkins) Reviewed-by: Philipp Deppenwiese <zaolin@das-labor.org>
2015-10-02libpayload: Fix possible NULL deref in cbfs_get_file_content()Nico Huber
Change-Id: I2e10ccac3248717d90838ca721cc691de792b507 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/11780 Tested-by: build bot (Jenkins) Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
2015-10-02cbfstool: relocate FSP blobs on cbfstool addAaron Durbin
When adding an FSP blob relocate it to its final destination. This allows FSP to not be hard coded in the cbfs. In order for the include paths to work correctly w/ the edk 2 headers we need to supply a neutered ProcessorBind.h to match up with the tool environment such that one can get the UEFI Platform Initialization type definitions. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built glados and booted. Also added FSP with -b and manually adjusted location in fsp cache-as-ram. Booted as well. Change-Id: I830d93578fdf745a51195109cf18d94a83ee8cd3 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11778 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-02vboot: provide CHIPSET_PROVIDES_VERSTAGE_MAIN_SYMBOL optionAaron Durbin
Certain chipsets provide their own main symbol for verstage. Therefore, it's necessary to know this so that those chipsets can leverage the common verstage flow. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built nyan using this option. Change-Id: If80784aa47b27f0ad286babcf0f42ce198b929e9 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11777 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-02tegra124: use the common verstage flowAaron Durbin
Though the tegra124 SoC makes their faster cpus come up in verstage it can still use the common flow. Therefore, use the common verstage API for performing thenecessary steps to initialize the caches on the faster cores. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built nyan. Change-Id: I93023ec92a9de111db688742b057b5c64143f0b3 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11776 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-02broadcom/cygnus: remove verstage.cAaron Durbin
The file was not referenced or used. Kill it. BUG=chrome-os-partner:44827 BRANCH=None TEST=None Change-Id: I30285d523ef3ca4dd3ce38b53aeb42862d929c90 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11775 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-02cbfstool: provide printk() to cbfstool codeAaron Durbin
For shared compilation units between coreboot proper and cbfstool that means one needs to provide printk logging. Therefore, provide printk() at <console/console.h> to mimic coreboot's environment. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built cbfstool with code that includes and uses <console/console.h>. Change-Id: I8e54d403526a397e4fd117738a367a0a7bb71637 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11774 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-02commonlib/helpers.h: handle interaction with other environmentsAaron Durbin
There are compiler settings and interactions with other header files that should be handled. First use __typeof__ instead of typeof because 'std' modes don't accept typeof. The __typeof__ variant works equally well on clang. The other change is to guard the helper macros so as not to trigger redefinition errors. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built cbfstool including commonlib/helpers.h Change-Id: I58890477cb17df14a9fa8b7af752a7c70769cf36 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11773 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-02fsp1_1: move relocation algorithm to commonlibAaron Durbin
In order to support FSP 1.1 relocation within cbfstool the relocation code needs to be moved into commonlib. To that end, move it. The FSP 1.1 relocation code binds to edk2 UEFI 2.4 types unconditionally which is separate from the FSP's version binding. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built and booted glados. Change-Id: Ib2627d02af99092875ff885f7cb048f70ea73856 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11772 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-02fsp1_1: use commonlib/endian.h routinesAaron Durbin
Now that the commonlib/endian.h routines have landed utilize those in the FSP relocation code. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built and booted glados. Change-Id: If431d64fd2843bea864d971ca1ea06b07c0d6435 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11771 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-02cbfstool: Allow anonymous structs/unions for older gcc versionsWerner Zeh
Older gcc versions throws a warning when a struct or union is declared without a valid name (anonymous). This patch enables the feature for older gcc versions so that no warning will be issued. Change-Id: Idc5481f4d5723c5090a6f7d7dbb0686a737e11fc Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: http://review.coreboot.org/11779 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-02mc_tcu3: Remove dummy blocks from hwinfo.hexWerner Zeh
Remove dummy data from hwinfo.hex as it is not needed anymore in the system. Change-Id: I4f328a4ef61741039eb2c030e23fea33f539c2bb Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: http://review.coreboot.org/11763 Tested-by: build bot (Jenkins) Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2015-10-02mc_tcu3: Enable the usage of blobs.Werner Zeh
Since microcode was moved to 3rdparty/blobs, we need to select USE_BLOBS in Kconfig to get the submodule 3rdparty/blobs automaticaly. Change-Id: I25e574fd90b830448cacccd16d01a5a2dbc8517d Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: http://review.coreboot.org/11764 Tested-by: build bot (Jenkins) Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2015-10-01tegra132/tegra210: remove verstage.cAaron Durbin
I missed these Makefile.inc changes. As verstage.c was removed remove the references within the Makefile.incs. Change-Id: I5d38c0a87d057622a3706bf3bde1142944c3b17c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11759 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-01cbfstool: Add support for hashes as file metadataPatrick Georgi
They allow optimizing a verification of a whole CBFS image by only dealing with the headers (assuming you choose to trust the hash algorithm(s)). The format allows for multiple hashes for a single file, and cbfstool can handle them, but right now it can't generate such headers. Loosely based on Sol's work in http://review.coreboot.org/#/c/10147/, but using the compatible file attribute format. vboot is now a hard dependency of the build process, but we import it into the tree for quite a while now. Change-Id: I9f14f30537d676ce209ad612e7327c6f4810b313 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/11767 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-10-01kconfig: fix build for xconfig, tooPatrick Georgi
Change-Id: I1c5e3424cb56f1f10e75bb07db084c3500f3ba07 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/11768 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-10-01cbfstool: Add bintohex functionPatrick Georgi
We need to emit some hex strings. Change-Id: I9e7e184282f6ad0470f2e269f5dc874e78f8b697 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/11766 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-10-01intel/fsp_baytrail: Remove unused MICROCODE_INCLUDE_PATH from KconfigWerner Zeh
Since fsp_baytrail was refactored to use microcode.bin in 3rdparty/blobs, we do not need MICROCODE_INCLUDE_PATH any more. Change-Id: I4382b0c174877186bd37fbff21f3269136d15e10 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: http://review.coreboot.org/11762 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-01northbridge/intel/gm45: Fix native VGA initAudrey Pearson
Building an image for the Lenovo X200 with native graphics initialization selected fails due to the changes introduced by commit a3b898aa (edid: Clean-up the edid struct). Change-Id: Ifd36571c9c00761b4a2a6deb3c9c4a52d9d13e25 Signed-off-by: Audrey Pearson <apearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11738 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-09-30Makefile.inc: Align paths in CBFS add messagesPaul Menzel
Building coreboot with the SeaBIOS or FILO payload selected, their config and revision are added to CBFS. ``` Creating out/bios.bin.elf CBFS coreboot.rom PAYLOAD payloads/external/SeaBIOS/seabios/out/bios.bin.elf (compression: LZMA) CONFIG .config REVISION build.h CONFIG payloads/external/SeaBIOS/seabios/.config REVISION payloads/external/SeaBIOS/seabios/out/version.c CBFSPRINT coreboot.rom ``` Align the path of the payload config by removing one space. Change-Id: Icbb139c28b9dcb8d31989a48fa4fbe4a9b088972 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/11710 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-09-30chromeos: vboot_common: Avoid code duplication when grabbing the handoff infoPaul Kocialkowski
vboot_handoff_flag was duplicating the logic to grab the handoff info, that is already made available with vboot_get_handoff_info. This uses vboot_get_handoff_info in vboot_handoff_flag instead. Change-Id: I28f1decce98f988f90c446a3a0dbe7409d714527 Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-on: http://review.coreboot.org/11498 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-30pcengines/apu1: Add CMOS/NVRAM supportMaxime de Roucy
Inspired by the Sage source code (itself from coreboot). Change-Id: I4864923166efb200882d895c572d1ee060c71951 Signed-off-by: Maxime de Roucy <maxime.deroucy@gmail.com> Reviewed-on: http://review.coreboot.org/11730 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-09-30kconfig: kconfig_warnings needs to be defined for all frontendsPatrick Georgi
Change-Id: Iecefdd1e827e4eb8b4da573e4291850d6c47767f Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/11754 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2015-09-30amd/family14: Add k10temp thermal zone.Tobias Diedrich
The thermal sensor interface exposed in function 3 of the northbridge is a more convenient and faster way to access the processor-internal thermal sensor than using the SMBus/SB-TSI interface from the FCH, see the Family14 BKDG: "Tctl is a processor temperature control value used for processor thermal management. Tctl is accessible through SB-TSI and D18F3xA4[CurTmp]. Tctl is a temperature on its own scale aligned to the processors cooling requirements" Also on at least some of these boards the existing thermal zone is broken and always returns 40C (the default value if the SMBus read failed) because the SMBus muxing register (SmBus0Sel) is not set up correctly. Case in point: The fallback "smbus read failed" temperature is 40 C and the the logs taken from the board status repository for the Asrock E350M1 board all show: "ACPI: Thermal Zone [TZ00] (40 C)" e.g. http://review.coreboot.org/gitweb?p=board-status.git;a=blob;f=asrock/e350m1/4.0-5054-gf584218/2013-12-20T20:56:20Z/kernel_log.txt#l390 and http://review.coreboot.org/gitweb?p=board-status.git;a=blob;f=asrock/e350m1/4.0-7030-g6d7de4f/2014-10-16T15:34:19Z/kernel_console.txt#l404 and http://review.coreboot.org/gitweb?p=board-status.git;a=blob;f=asrock/e350m1/4.0-9989-gf2dfef0/2015-06-13T00:22:49Z/kernel_log.txt#l425 Example lm-sensors output with this patch on the pcengines APU1, on Linux 4.1.0-rc8+ (wiht both CONFIG_ACPI_THERMAL and CONFIG_SENSORS_K10TEMP enabled): acpitz-virtual-0 Adapter: Virtual device temp1: +54.0 C (crit = +100.0 C) k10temp-pci-00c3 Adapter: PCI adapter temp1: +54.0 C (high = +70.0 C) (crit = +100.0 C, hyst = +97.0 C) Change-Id: Id9c5b783ba424246816677099ec6651814e59f21 Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Reviewed-on: http://review.coreboot.org/10940 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-30AMD Bettong: Fix usb device in devicetree for Carrizozbao
Add some missing devices to device tree and header. Remove the obsolete devices. Change-Id: Ieeca06c68fe8c8eef6be4fab43193b898aebf013 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/11378 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-30kconfig: Allow KCONFIG_STRICT outside of confdata.cStefan Reinauer
To catch dependency errors in symbol.c (such as the ones fixed by I51b4ee326f082c6a656a813ee5772e9c34f5c343) we need to check for global kconfig warnings before saving config files. This patch will produce errors for wrong dependencies and add catching of errors to conf, nconf and mconf. Sorry, gconf users, you will have to wait. Change-Id: Idf7ee406ce3869941af319219aea16fab826df84 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/11291 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-30vboot: provide a unified flow for separate verstageAaron Durbin
The vboot verification in a stage proper is unified replacing duplicate code in the tegra SoC code. The original verstage.c file is renamed to reflect its real purpose. The support for a single verstage flow is added to the vboot2 directory proper. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built glados. Change-Id: I14593e1fc69a1654fa27b512eb4b612395b94ce5 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11744 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-30cpu: microcode: Use microcode stored in binary formatAlexandru Gagniuc
Using a copiler to compile something that's already a binary is pretty stupid. Now that Stefan converted most microcode in blobs to a plain binary, use the binary version. Change-Id: Iecf1f0cdf7bbeb7a61f46a0cd984ba341af787ce Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/11607 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-30intel/fsp1_0: Declare microcode to be size 0 if it doesn't existPatrick Georgi
Change-Id: Id2063fb29226dcb55fe84f680b7b9cb10313ef2b Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/11753 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2015-09-30x86: prepare cache-as-ram to allow multiple stagesAaron Durbin
In order to do a verification of romstage on x86 one needs to run verstage which verifies romstage (and the memory init code). However, x86 doesn't have SRAM like every other modern SoC so managing the cache-as-ram region is especially critical. First move all of the "shared" objects to the beginning of the .car.data section. This change then ensures that each stage using car.ld to link has the same consistent view of the addresses of these fixed-sized objects in cache-as-ram. The CAR_GLOBALs can be unique per stage. However, these variables are expected to have a value of zero at the start of each stage. In order to allow a stage to provide those semantics outside of the initial cache-as-arm setup routine add _car_global_start and _car_global_end symbols. Those symbols can be used to clear the CAR_GLOBALs for that stage. Note that the timestamp region can't be moved out similarly to the pre-ram cbmem console because the object storage of the timestamp cache is used *after* cache-as-ram is torn down to indicate if the cache should be used or not. Therefore, that timestamp needs to migrated to ram. A logic change in src/lib/timestamp.c could alleviate this requirement, but that task wasn't tackled in this patch. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built and booted glados. Change-Id: I15e9f6b0c632ee5a2369da0709535d6cb0d94f61 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11740 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-30x86: provide common macro for linking early stagesAaron Durbin
In order to support verstage on x86 one needs to link verstage like romstage since it needs all the cache-as-ram goodies. Therefore, provide a macro that one can invoke that provides the necessary recipes for linking that particular stage in such an environment. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built and booted glados. Change-Id: I12f4872df09fff6715829de68fc374e230350c2e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11739 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-29chromeos: vboot-related functions move to common vboot codePaul Kocialkowski
This moves a few vboot-prefixed functions that were defined in chromeos.c to vboot_common.c, since those are only relevant to vboot and depend on the vboot handoff data. This allows more separation between CONFIG_CHROMEOS and what CONFIG_CHROMEOS selects, so that each separate option (such as CONFIG_VBOOT_VERIFY_FIRMWARE) can be enabled separately. Thus, the actual definitions of these functions will only be declared when CONFIG_VBOOT_VERIFY_FIRMWARE is set, so the check before calling vboot_skip_display_init in bootmode was also adapted. Change-Id: I52f8a408645566dac0a2100e819c8ed5d3d88ea5 Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-on: http://review.coreboot.org/11497 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-09-29intel/fsp1.0: Get size of microcode during build timeWerner Zeh
Avoid specifying the size of the microcode in microcode_size.h. Instead, the size will be determined during build time and microcode_size.h will be generated. This way, the size does not need to be adjusted by hand. Change-Id: I868f02b0cc03af12464a6a87c59761c200eb2502 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: http://review.coreboot.org/11709 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-09-29skylake: select HAVE_INTEL_FIRMWAREAaron Durbin
Use the common ME and descriptor code. BUG=chrome-os-partner:43462 BRANCH=None TEST=Built glados Change-Id: I7196f587b92fd26129b30e2cd73f4caf5f4ebef8 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11735 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-29intel: auto include intel/common/firmwareAaron Durbin
Instead of selecting the Kconfig option and adding the subdir entry within each chipset auto include the common/firmware directory as it's guarded by HAVE_INTEL_FIRMWARE. BUG=chrome-os-partner:43462 BRANCH=None TEST=Built glados. Change-Id: I166db67c41b16c4d9f0116abce00940514539fa5 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11734 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-293dparty/blobs: Advance to pull in binary microcodeAlexandru Gagniuc
Change-Id: I2071586e1f3b4464464928c11475f9283084dbcd Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/11693 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2015-09-29Makefile: Replace the way to test if a string is emptyzbao
The output of command below, # i386-elf-nm build/cbfs/fallback/romstage_null.offenders | \ grep -q "" ; echo $? has different result on MacOS, OS X Mavericks, which outputs 0. On linux, it outputs 1. I assume it is misleading to search an empty string in a empty string. Change it to testing if the string is empty. Change-Id: Ie4b8fe1fb26df092e2985937251a49feadc61eb0 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/11600 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-28.gitignore: adapt to new buildgcc versionzbao
1. The build folders are capitalized. 2. Add folders for build LLVM and IASL. Change-Id: I6c752f08aa545d8878fddd373e5acbfade317ad5 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/11602 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-28cbfstool: prefer fmap data over cbfs master header if it existsPatrick Georgi
Up to now, if both fmap and a master header existed, the master header was used. Now, use the master header only if no fmap is found. Change-Id: Iafbf2c9dc325597e23a9780b495549b5d912e9ad Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11629 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-28cbfstool: have update-fit always work from CBFSPatrick Georgi
On x86, the bootblock can (and will) become part of the regular file system, so there's no distinct fixed-size region for the bootblock there. Change-Id: Ie139215b73e01027bc0586701361e9a0afa9150e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11691 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-28program.ld: terminate ALIGN statementPatrick Georgi
This fixes building with CONFIG_COVERAGE=y Change-Id: I5128ae0ef0d4f71e3ede7bcb3ee7ed7e265d1bb7 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/11729 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-28arm64: mmu: Prevent CPU prefetch instructions from device memoryJimmy Huang
Set XN bit of block upper attribute to device memory in mmu. CPU may speculatively prefetch instructions from device memory, but the IO subsystem of some implementation may not support this operation. Set this attribute to device memory mmu entries can prevent CPU from prefetching device memory. BRANCH=none BUG=none TEST=build and booted to kernel on oak-rev3 with dcm enabled. Change-Id: I52ac7d7c84220624aaf6a48d64b9110d7afeb293 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 7b01a4157cb046a5e75ea7625060a602e7a63c3c Original-Change-Id: Id535e990a23b6c89123b5a4e64d7ed21eebed607 Original-Signed-off-by: Jimmy Huang <jimmy.huang@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/302301 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/11722 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-28skylake: Work around issue in ACPI interpreterDuncan Laurie
There appears to be an issue that is causing this particular bit of ACPI code to be incorrectly interpreted by the kernel and the IASL disassembler. Ensuring the PCRB() method is defined in the DSDT before any uses of it appears to fix the problem, but that relies on specific ordering of the ASL files included by pch.asl and may break again in the future if the includes were re-ordered. (they are alphabetic now) So in this case to work around the issue unroll the function call so the admittedly messy calculation is reduced to a constant when compiled. Note this issue was observed with both iasl-20130117 and iasl-20150717. ACPICA bug: https://bugs.acpica.org/show_bug.cgi?id=1201 BUG=chrome-os-partner:45760 BRANCH=none TEST=verify disassembled AML is correct Change-Id: I7b6a3b792f79755db0ea7b9f2ef6ee7f5000e018 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ecacc340d6e1068ea649f0859657bb3208695730 Original-Change-Id: I232523f5b6ce290da6e7d99405a53b9437b10e0d Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/302167 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11721 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-09-28glados: Provide nau8825 platform data via _DSDBen Zhang
BUG=chrome-os-partner:41280 BRANCH=none TEST=Audio jack insert/eject detection and headset buttons work on glados with the nau8825 driver in chromeos-3.18 and the staging kernel skl2. Change-Id: I813a985b4a39249a2cdbe45117acbdb7710bfa29 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 7a5b3dafd407fea2376dff5c3dcde50dff4704fb Original-Change-Id: Ic24a0c444761d0f3a35c268078e70d9aacca4c80 Original-Signed-off-by: Ben Zhang <benzh@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/293610 Original-Reviewed-by: Anatol Pomazau <anatol@google.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/11720 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2015-09-28skylake: ACPI: Remove Configurable TDP support codeDuncan Laurie
Remove the CTDP support code that is in ACPI. It has been ported from haswell and while the MCHBAR register interface does seem to still exist the calculations for determining PL2 is no longer straightforward. Additionally nothing is using this interface and the expectation is that DPTF will be used for throttling with PL[1234] and having ACPI interfere with the configuration would not be good. BUG=chrome-os-partner:44622 BRANCH=none TEST=emerge-glados coreboot Change-Id: I81e356ddf564a5253458b82bc3327bfb573ab16d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 884ee9a764bad0b3b4bcaeb5a3f46c5f090a116c Original-Change-Id: I284ab52a305cee25c88df5228b01ff1e9544efe3 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/302166 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11719 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-09-28kunimitsu: Fix typo for WLAN ACPI device nameDuncan Laurie
Fix the typo of _DDR to be _DDN. BUG=chrome-os-partner:40635 BRANCH=none TEST=build kunimitsu with iasl-20150717 Change-Id: I1e7c20d450ea897bfd24506d10a5f466b03610e4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f136581b653bfb63aac24065c8837307e3fc5432 Original-Change-Id: I3358e6d3d05bcfc291199e8ef12ff92c66f5b74f Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/302165 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11718 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2015-09-28glados: Fix typo for WLAN ACPI device nameDuncan Laurie
Fix the typo of _DDR to be _DDN. BUG=chrome-os-partner:40635 BRANCH=none TEST=build glados with iasl-20150717 Change-Id: I8d61a6653c3109890d04e54f0d694703b9c9f2bf Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d4a2b2583bdbf9afd7b306359338d4c49bbb44ad Original-Change-Id: I7b7905a217d34a8a78b8280c898f1074ecbe3cf6 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/302164 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11717 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2015-09-28chromeec: Fix ACPI compile warningsDuncan Laurie
Recent version of iasl are flagging more things as warnings. Remove unused Local0 uses and make _CRS method serialized to fix these warnings. BUG=chrome-os-partner:40635 BRANCH=none TEST=build glados with iasl-20150717 Change-Id: I1d4535205426dd9a6346f53ff159221cf5cd899a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 8b43f8f24bb7cb33ad0411c24616da66663c2e3e Original-Change-Id: I71eafd91d30d5f50e6211368f0bbc517c8085892 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/302163 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11716 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2015-09-28tpm: acpi: Make _CRS method serializedDuncan Laurie
Since the TPM _CRS method creates named objects it needs to be serialized to prevent a warning in recent iasl. BUG=chrome-os-partner:40635 BRANCH=none TEST=build glados with iasl-20150717 Change-Id: I59a52552ab24b7d9c9928331aa8c8d19f54fd1b7 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 2a5c474c94980661573a99eb94d5f661f2d0114b Original-Change-Id: Ie9d164ea8781304dd0bf1833d182d7c601b8e18d Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/302162 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11715 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2015-09-28cbfs: allow cbfs-files to use compressionDaisuke Nojiri
This change allows files added to cbfs-files-y to specify compression algorithm. BUG=none BRANCH=tot TEST=Tested on Samus Change-Id: I29ba0c6f8290b500072a0b17460ee590d6bb6efa Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4284160bdbbc54ed1da8b5477b02ee315061206b Original-Change-Id: Idf81e1cc0a1030449da632f6d89cdc87c624f9f3 Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/302132 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11714 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-28cbfs: fix debug messageDaisuke Nojiri
BUG=none BRANCH=tot TEST=built for Samus with debugging enabled Change-Id: I0b555d018f8c2eb1b51519a6227298c8d5d58a42 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5908e4b8ffc66e6ecc7cae78cf10055fbd727c81 Original-Change-Id: Ifd049111fee540789dabb1d7653568b80405b77d Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/302131 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11713 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-28ec: superio: Report keyboard IRQ as wake capableDuncan Laurie
In order to wake from S0ix the kernel needs to know that the keyboard interrupt is wake capable. Using IRQNoFlags does not allow the wake capability to be reported. For normal S3 this does not matter as the EC is the one handling the keyboard wake event. For S0ix the EC does not need to be involved in this particular wake event. BUG=chrome-os-partner:43079 BRANCH=none TEST=echo freeze > /sys/power/state and wake from keyboard Change-Id: I7175d2ea98f8a671765897de295df7b933151fc4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 645f1cd96c35f42aa7c40ff473b15feb619b0373 Original-Change-Id: Ia89c30c51be9db7b814b81261463d938885325fd Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/301441 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11712 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2015-09-24cbfstool: Proper commonlib include path with no dependency on $(src)Paul Kocialkowski
$(src) is not defined when building directly from the cbfs directory (that is, when building cbfs as standalone, running make in the cbfs directory), so we need to define the path to the commonlib include path relative to $(top). Change-Id: I72e80b030d4a156ec653ded5ab1457b16f612526 Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-on: http://review.coreboot.org/11706 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2015-09-24coreboot: move TS_END_ROMSTAGE to one spotAaron Durbin
While the romstage code flow is not consistent across all mainboards/chipsets there is only one way of running ramstage from romstage -- run_ramstage(). Move the timestamp_add_now(TS_END_ROMSTAGE) to be within run_ramstage(). BUG=chrome-os-partner:44827 BRANCH=None TEST=Built and booted glados. TS_END_ROMSTAGE still present in timestamp table. Change-Id: I4b584e274ce2107e83ca6425491fdc71a138e82c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11700 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-23chromeos: vboot and chromeos dependency removal for sw write protect statePaul Kocialkowski
This removes the dependency on chromeos and vboot for the sw write protect state function: vboot_get_sw_write_protect, renamed to get_sw_write_protect_state to both reflect this change and become consistent with the definition of get_write_protect_state that is already in use. Change-Id: I47ce31530a03f6749e0f370e5d868466318b3bb6 Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-on: http://review.coreboot.org/11496 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-23google: veyron: CBFS_SIZE to match the available size for Coreboot in ChromeOSPaul Kocialkowski
When building for ChromeOS, it is expected that Coreboot will only occupy the first MiB of the SPI flash, according to the veyron fmap description. Otherwise, it makes sense to use the full ROM size. Change-Id: I168386a5011222866654a496d8d054faff7a9406 Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-on: http://review.coreboot.org/11117 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-23RISCV: modify arch_prog_run to handle payloads correctly.Ronald G. Minnich
Unlike the other stages, the payload requires virtual memory to be set up and also a privelege level change. Change-Id: Ibbe2a55f7719d917f121a53a17c6d90e6b2ab3d1 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/11699 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2015-09-22linking: link bootblock.elf with .data and .bss sections againAaron Durbin
Currently coreboot expects the loader to clear the bss section for all stages. i.e. stages don't clear their own bss. On ARM SoCs the BootROM would be responsible for this. To do that one needs to include the bss section data (all zeros) in the bootblock.bin file. This was previously being attempted by keeping the .bss info in the .data section because objcopy happened zero out non-file allocated data section data. Instead go back to linking bootblock with the bss section but mark the bss section as loadable allocatable data. That way it will be included in the binary properly when objcopy -O binary is emplyed. Also do the same for the data section in the case of no non-zero object values are in the data section. Without this change the trick of including .bss in .data was not working when there wasn't a non-zero value object in the data section. BUG=None BRANCH=None TEST=Built emulation/qemu-armv7 and noted bootblock.bin contains the cleared bss. Change-Id: I94bd404c2c4a8b9332393e6224e98940a9cad4a2 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11680 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-22commonlib: add endian related accessor functionsAaron Durbin
This commit adds read/write functions for both big and little endian interpretations. Additionally there are variants that allow an offset to be provided into the source buffer. BUG=None TEST=Wrote test harness for functions. Also booted ARM QEMU through end of payload. Change-Id: If44c4d489f0dab86a73b73580c039e364c7e517d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11677 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-09-22coreboot: introduce commonlibAaron Durbin
Instead of reaching into src/include and re-writing code allow for cleaner code sharing within coreboot and its utilities. The additional thing needed at this point is for the utilities to provide a printk() declaration within a <console/console.h> file. That way code which uses printk() can than be mapped properly to verbosity of utility parameters. Change-Id: I9e46a279569733336bc0a018aed96bc924c07cdd Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11592 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-09-21cbfstool: don't use endian to fix BSD hostsAaron Durbin
endian.h lives in under sys on the BSDs. Replace htole32() with swab32(htonl(..)) as a proxy for little endian operations. Change-Id: I84a88f6882b6c8f14fb089e4b629e916386afe4d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11695 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com> Reviewed-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
2015-09-21cbfstool: make fmap search more strictPatrick Georgi
Since fmap doesn't come with a checksum, we resort to a number of heuristics to determine if a given location hosts an fmap (instead of another data structure that happens to store the fmap magic string at the right location). The version test is particularly effective against strings containing the magic (which either terminate with 0, or have some other ASCII data, but rarely a '\001' byte inside the string). Change-Id: Ic66eb0015c7ffdfe25e0054b7838445b8ba098e9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11690 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-21cbfstool: add new add-master-header commandPatrick Georgi
The command adds a new cbfs file, fills in the CBFS meta data in cbfs master header format, then points the master header pointer (which resides at the last 4 bytes of the CBFS region) to the data area of the new file. This can leak some space in CBFS if an old-style CBFS with native master header gets the treatment, because a new header is created and pointed at. flashmap based images have no such header, and the attempt to create a second file with the (hardcoded) name will fail. Change-Id: I5bc7fbcb5962b35a95261f30f0c93008e760680d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11628 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-21ifdfake: allow "base+size" description of regionsPatrick Georgi
This is more in line with how fmd/fmap specify ranges. Change-Id: Iecf8250e84d6eb267711ded446909b21147f1a9c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11623 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-19cbfstool: introduce new file typesPatrick Georgi
Let's move x86 style bootblocks (and later the others) and the master header into the CBFS structure. Prepare for this by adding file types. Change-Id: I1b4149c7f3b8564ee358a2c18ba91e6a7a6797da Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11627 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-09-17libpayload: provide cbfs_file_find_attr()Patrick Georgi
cbfs_file_find_attr(file, tag) finds the first attribute of file with the given tag. Change-Id: I78ee3b996b4b086605244c5d7d57ef7e3fc1db47 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11678 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2015-09-17cbfstool: Don't use fileno() to get file sizeStefan Reinauer
fileno() is a mess on some operating systems. Don't deliberately convert between FILE * and file handles. Change-Id: I5be62a731f928333ea2e5843d81f541453fdb396 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/11636 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-09-17libpayload: allow compression at file header levelDaisuke Nojiri
Decompression is handled transparently within cbfs_get_file_content: const char *name = "foo.bmp"; void *dst = cbfs_get_file_content(media, name, type, NULL); To keep things consistent, a couple of API changes were necessary: - cbfs_get_file_content always returns a copy of the data, even for uncompressed files. It's the callers responsibility to free the memory. - same for cbfs_load_payload and cbfs_find_file. - cbfs_load_optionrom doesn't take a "dest" argument anymore but always returns a copy of the data, for compressed and uncompressed files. Like with cbfs_get_file_content, the caller is responsible to free it. It also decompresses based on extended file attributes instead of the cbfs_optionrom subheader that libpayload specified but that (AFAIK) nobody ever used, given that there's not even tooling for that. Change-Id: If959e3dff9b93c6ae45ec7358afcc7840bc17218 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10938 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2015-09-17libpayload: rename cbfs variable from name to vardataDaisuke Nojiri
The dynamically sized region after struct cbfs_file doesn't contain only the file name anymore. Change-Id: I3241cb2f0cbec3fcf4d3c27d638e2847e43f4761 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11676 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-17libpayload: bring in file attribute support from cbfstoolPatrick Georgi
This comes from cbfstool (GPL) into libpayload (BSD-l), but I could have just as well written it in libpayload first. Change-Id: I86baefe5c299125a4733fa20523efd5d06de7182 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11675 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-17broadwell: Switch to using common ACPI _SWS codeDuncan Laurie
Use the common ACPI _SWS code and provide a function to fill out the wake source data. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-samus coreboot Change-Id: I3d2ceca8585314122b78317acb7f848efb6e9a14 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d8afaee8e27222639c5e249d53be28cddcb78f72 Original-Change-Id: Ie551ecf3397c304216046cc2046c071f7b766e5f Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/298168 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11647 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-17braswell: Switch to using common ACPI _SWS codeDuncan Laurie
Switch braswell to use the common code for filling out the NVS data used by ACPI _SWS methods. This code was out of date on braswell so also update it to provide the \_GPE.SWS method. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-cyan coreboot Change-Id: I41c2a141c15f78dc0d9482954c157f81bd0759fa Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4c4d1ee76f337addf687ca5a9ae2da5e898c2de0 Original-Change-Id: I44424784d5d3afb06d0d58c651a9339c7b77418c Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/298230 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11649 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-17skylake: Use common ACPI _SWS codeDuncan Laurie
Enable and use the common code for filling out the NVS data used by the _SWS methods. Add a function to provide the wake source data. With Deep S3 enabled skylake does not retain the contents of the PM1_EN register so instead just select the wake related events in PM1_STS. BUG=chrome-os-partner:40635 BRANCH=none TEST=tested on glados by checking for valid _SWS string in /sys/firmware/log after suspend/resume. Wake sources that were tested are RTC, power button, keypress, trackpad, and wifi. Change-Id: I93a4f740f2e2ef1c34e948db1d8e273332296921 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: cb4d4705b87ef7169f1979009c34a58de93c4ef0 Original-Change-Id: Ib6b4df09ea3090894f09290d00dcdc5aebc3eabb Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/298169 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11648 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-17glados/kunimitsu: remove the implementation of mainboard_add_dimm_inforobbie zhang
This is a follow-up patch to https://chromium-review.googlesource.com/#/c/286877, after fsp support is landed in v1.5. BUG=chrome-os-partner:42975 BRANCH=none TEST=execute "mosys memory spd print all" on glados and kunimitsu Change-Id: I949e287372b190affac36a0efde8a30402eecdc8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 71a2e1838ff8bbaa358c167dad905b63d23c43fa Original-Change-Id: I64103af4f8456a053a955845a067062122f47af3 Original-Signed-off-by: Robbie Zhang <robbie.zhang@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/298967 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/11657 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-17kunimitsu: Enable wake-on-wifiDuncan Laurie
- Assign GPE DW0 to GPP_B block - Enable GPP_B16 as ACPI_SCI for wake - Define PCIe WLAN device in ACPI with GPE0_DW0_16 for _PRW Note that current designs cannot wake from Deep S3 via wifi. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-kunimitsu coreboot Change-Id: I1fe15a5a9b3d868a0e4f1bfb102b69f024c3aa48 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: de9dfee840246866a8dcca2e1c42c0292e820529 Original-Change-Id: I926d74b6bcf6d64c3db61ed23d7c17b51a98b052 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/298232 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11651 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-17glados: Enable wake-on-wifiDuncan Laurie
- Assign GPE DW0 to GPP_B block - Enable GPP_B16 as ACPI_SCI for wake - Define PCIe WLAN device in ACPI with GPE0_DW0_16 for _PRW Note that current designs cannot wake from Deep S3 via wifi. BUG=chrome-os-partner:40635 BRANCH=none TEST=tested on glados: 1-disable deep s3 in devicetree.cb 2-enable magic packet with "iw phy phy0 wowlan enable magic-packet" 3-powerd_dbus_suspend to go to S3 4-wake system with magic packet Change-Id: I989768615e9da8ecf6354852d2db7aae8069aa82 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 894354c5bfd499b911b7f89310c48b503dbaadc2 Original-Change-Id: I9a7a317fc2eccc70fdb4862843de1a654fbc2eee Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/298231 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11650 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-17Skylake: update C state latency and power numbersrobbie zhang
The values are taken from latest BWG as well fsp src. BRANCH=none BUG=chrome-os-partner:45208 TEST=Built and boot on kunimitsu Signed-off-by: Robbie Zhang <robbie.zhang@intel.com> Change-Id: Ia6bd336a71b0313801b59990c78822fa0d789e36 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c955ab43245153d76932daa527f1b5ebea859164 Original-Change-Id: I3f7307951753c2bbe6319f627a82a93359c4e61b Original-Reviewed-on: https://chromium-review.googlesource.com/299480 Original-Commit-Ready: Wenkai Du <wenkai.du@intel.com> Original-Tested-by: Wenkai Du <wenkai.du@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11659 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-17drivers/intel/fsp1_1: split relocation code for tool useAaron Durbin
In order for easier consumption in userland tools split the FSP 1.1 relocation logic into a single file w/ an aptly named function name. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built and booted glados. Change-Id: I49998b8621611c638375bc90884e80d0cd3bdf78 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: bc898e1c528df60683575d553d6194a1e8200afa Original-Change-Id: I736c0059d43f6d0be4fdb6e6f47cdb5c189a7ae8 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/298833 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/11665 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>