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2023-09-25mb/google/corsola: Move board-specific selects to board optionsFelix Singer
Instead of selecting board-specific options under the common option and making them conditional, move them to their related board option. Change-Id: If9bea61cb84590e7455add908fa7722c60444503 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78100 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-09-25mb/google/corsola: Fine tune LCM ADC voltagesRuihai Zhou
The tolerance of LCM voltage table is too small which leads to wrong panel ID detection. Fine tune LCM ADC voltages based on hardware calculations. BUG=b:300418909 TEST=FW screen display normally Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Change-Id: Id8dec043584f4c552837f70adb491584bfda7acf Reviewed-on: https://review.coreboot.org/c/coreboot/+/78063 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com>
2023-09-25util: Drop flashrom -p host alias which equals to -p internalHsuan Ting Chen
There is a technical debt in ChromeOS flashrom, `cros_alias.c`, which is to work around ChromeOS calling flashrom with `-p host` instead of `-p internal`. Replace all `-p host` occurrences with `-p internal`. BUG=b:296978620 TEST=none Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org> Change-Id: I81674213b9a21598002f349ced1130f0844841ca Reviewed-on: https://review.coreboot.org/c/coreboot/+/77865 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-09-25treewide: Adopt TCG standard namingJon Murphy
Adopt TCG standard naming and definitions for TPM Return codes. BUG=b:296439237 TEST=Build and boot to OS on skyrim BRANCH=None Change-Id: I60755723262ec205a4c134948b0250aac4974d35 Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77665 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-25Revert "soc/intel/jasperlake: Enable early caching of RAMTOP region"Matt DeVillier
This reverts commit 21e61847c4cf643d79855deba8f58fd45808d571. Reverting as it breaks booting on google/dedede based boards. First boot after flashing is successful, 2nd hangs with the following error: [EMERG] FspMemoryInit returned with error 0x80000003! TEST=build/boot google/dedede (magpie, metaknight) Change-Id: I6a2474617b444414c4248dbeda23ed0915704a17 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78091 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
2023-09-25commonlib: Make CBMEM_ID_CSE_BP_INFO little endian, fix id for stringSubrata Banik
This patch fixes the mistake introduced with 'commit 17cea380d985 ("commonlib: Add CBMEM ID to store CSE Boot Partition Info")' where single CBMEM ID name `CBMEM_ID_CSE_INFO` is associated with two different name description. Additionally, use little endian format for `CBMEM_ID_CSE_INFO` cbmem id. TEST=Build and boot google/rex. Able to fix the issue introduced in commit 17cea380d985 while running cbmem --list and verify that the associated name string is proper. Change-Id: I4235f1f6881ab86ccb252065e922d5d526f7f1f7 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78110 Reviewed-by: Patrick Georgi <patrick@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: sridhar siricilla <siricillasridhar@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
2023-09-24Doc/: Remove an extra spacePatrick Georgi
Change-Id: I462d0bd3e9f3b425631987fa793d29323c3f9d61 Signed-off-by: Patrick Georgi <patrick@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78021 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-09-24Doc/infra: Update my contact informationPatrick Georgi
Change-Id: If7081897d8232e3ac84de0fa76689ad05808996d Signed-off-by: Patrick Georgi <patrick@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78020 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-09-23mb/google/cherry: Move common selects to BOARD_GOOGLE_CHERRY_COMMONFelix Singer
BOARD_SPECIFIC_OPTIONS is duplicate to BOARD_GOOGLE_CHERRY_COMMON. Thus, move all selects to the latter option. Change-Id: I080201761d0a06d3b8a5a29de6085dde58960a60 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75085 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-23mb/google/asurada: Move common selects to BOARD_GOOGLE_ASURADA_COMMONFelix Singer
BOARD_SPECIFIC_OPTIONS is duplicate to BOARD_GOOGLE_ASURADA_COMMON. Thus, move all selects to the latter option. Change-Id: Id80523dce70f13f64a49b71656276c51e80ae5cd Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75084 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-23mb/google/rex: Move selects from Kconfig.name to KconfigFelix Singer
Selects should be done in the Kconfig file instead of Kconfig.name and not mixed over both files. Change-Id: Id69ea99b452e4214fcc81335a5c961b4da3ce48b Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75021 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-09-23mb/google/veyron: Move selects from Kconfig.name to KconfigFelix Singer
Selects should be done in the Kconfig file instead of Kconfig.name and not mixed over both files. Change-Id: Id85503a5ec970ea92c07b99ec7048c521d85c79b Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75026 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-23mb/google/corsola: Move selects from Kconfig.name to KconfigFelix Singer
Selects should be done in the Kconfig file instead of Kconfig.name and not mixed over both files. Change-Id: Id450a4b6e409a548ee4d79b8b2ebf30ef61a3e27 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78083 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-23commonlib: Add CBMEM ID to store CSE Boot Partition InfoKrishna Prasad Bhat
PSR data is created and stored in CSE data partition. In platforms that employ CSE Lite SKU firmware, a firmware downgrade involves clearing of CSE data partition which results in PSR data being lost. In order to backup PSR data before initiating firmware downgrade, CSE Lite firmware supports a command to do this. This command works only after memory has been initialized. So the CSE firmware downgrade can be done only in post-RAM stage. CSE firmware sync actions will be moved to early ramstage to support this. Moving CSE firmware sync actions to ramstage results in cse_get_bp_info command taking additional boot time of ~45-55ms. To avoid this, cse_get_bp_info will be sent in early romstage and the response will be stored in cbmem to avoid sending the command again, and re-use in ramstage. This patch adds a CBMEM ID to store this CSE Boot Partition Info response in cbmem. BUG=b:273207144 Change-Id: I914befadab4ad0ac197435e2a2c4343a796b2b1b Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78052 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: sridhar siricilla <siricillasridhar@gmail.com>
2023-09-23soc/intel/cse: Move cse_store_rw_fw_version from cse_print_boot_partition_infoKrishna P Bhat D
cse_store_rw_fw_version() stores CSE RW firmware version in global variable or cbmem in romstage and ramstage respectively, based on the stage it is called in. The call to this function is from the cse_print_boot_partition_info() in cse_get_bp_info. In the subsequent patches, the idea is to send the cse_get_bp_info early in romstage and store in cbmem once memory is initialized. So when the cse_fw_sync is called in early ramstage, the stored cse_bp_info_rsp is used instead of sending the CSE get boot partition info command again. To de-link the call to cse_store_rw_fw_version from cse_get_bp_info and to ensure the CSE RW FW version is stored in all cases, moving the function to do_cse_fw_sync. BUG=b:273207144 Change-Id: I0add2c167c85cbddef2ecb4c019061a08562bbdf Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78051 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: sridhar siricilla <siricillasridhar@gmail.com>
2023-09-23soc/intel/cse: Make cse_bp_info response globalKrishna Prasad Bhat
PSR data is created and stored in CSE data partition. In platforms that employ CSE Lite SKU firmware, a firmware downgrade involves clearing of CSE data partition which results in PSR data being lost. CSE Lite SKU firmware supports a command to backup PSR data before initiating a firmware downgrade. PSR data backup command works only after memory has been initialized. Moving only the downgrade would add complexity of splitting the cse_fw_sync across pre-RAM and post-RAM stages. So the idea is to move cse_fw_sync into ramstage when PSR is enabled. We are introducing a flow to get CSE boot partition info in early romstage and then same data will be stored in cbmem once DRAM is initialized. The CSE BP info data in cbmem will be utilized in early ramstage to perform cse firmware sync operations. This helps in avoiding re-sending the CSE get boot partition info command in ramstage. Having cse_bp_info_rsp as global helps in de-linking cse_get_bp_info from cse_fw_sync. Many functions take cse_bp_info as input parameter. Since cse_bp_info_rsp is global now, we can make use of global cse_bp_info and remove it as input parameter from those functions. BUG=b:273207144 TEST=Verify cse_bp_info_rsp holds value across the stage. Change-Id: I0ee050b49fcae574882378b94329c36a228e6815 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77070 Reviewed-by: sridhar siricilla <siricillasridhar@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com>
2023-09-23soc/intel/meteorlake: Reduce memory test sizeSubrata Banik
Enable upd to reduce size of the memory test. BUG=b:301441204 TEST=Able to build and boot google/rex. w/o this patch: 951:returning from FspMemoryInit 650,922 (79,560) w/ this patch: 951:returning from FspMemoryInit 618,490 (45,621) Change-Id: I903591ec749d270a98895dafb2d8f8d0b287c26a Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78067 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-09-23soc/intel/meteorlake: Hook up UPD LowerBasicMemTestSizeSubrata Banik
Hook the newly exposed LowerBasicMemTestSize UPD up so that boards can configure it via devicetree. BUG=b:301441204 TEST=Verified by enabling/disabling the UPD on google/rex. Change-Id: Iec466aeaebd72f222d97f720a85bbb8c27e26325 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78066 Reviewed-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-09-23vc/intel/fsp/mtl: Update header files from 3323.84 to MTL.3323.86Subrata Banik
Update header files for FSP for Meteor Lake platform to version 3323.86, previous version being 3323.84. FSPM: 1. Added new UPDs - AcLoadline - DcLoadline - LowerBasicMemTestSize 2. Address offset changes BUG=b:301441204 TEST=Able to build and boot google/rex to ChromeOS. Change-Id: I6c2f7f588874b37c52e3926c02e381ceff14f5af Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78065 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
2023-09-23arch/x86/cpu_common: use cpuid_e[a,c]xFelix Held
Use cpuid_eax and cpuid_ecx instead of sort-of open-coding the same functionality in cpu_check_deterministic_cache_cpuid_supported. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib0dc2be4f602bf63183b9096e38403ae2f45d959 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78058 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-23arch/x86/cpu_common: use cpu_cpuid_extended_levelFelix Held
Use cpu_cpuid_extended_level instead of open-coding the same functionality in cpu_check_deterministic_cache_cpuid_supported. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4ea22c3997769179311f3c8822e6d8cc15a8834c Reviewed-on: https://review.coreboot.org/c/coreboot/+/78057 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-23vboot: Remove the unnecessary PCR digest checkYi Chou
This PCR digest length check is no longer necessary. Signed-off-by: Yi Chou <yich@google.com> Change-Id: I256938c69be7787f5c8fca3e633ac93a69368452 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78084 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-09-22mb/google/skyrim/frostflow: Hide fingerprint reader from Windows OSMatt DeVillier
No Windows driver exists or is needed, so hide to prevent an unknown device from being listed in Windows Device Manager. TEST=build/boot Win11 on frostflow, verify unknown device for the fingerprint reader no longer present. Change-Id: I666e92706f698608f2df92c8296cfb615d5ece67 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77677 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-09-22mb/google/guybrush: Hide I2S machine driver from Windows OSMatt DeVillier
No Windows driver exists or is needed, so hide to prevent an unknown device from being listed in Windows Device Manager. TEST=build/boot Win11 on dewatt, verify unknown device for the ACP machine driver no longer present. Change-Id: I44d25fd2ea75593383cbb14f2324d4376b399de7 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77676 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-09-22mb/google/zork: Hide I2S machine driver from Windows OSMatt DeVillier
No Windows driver exists or is needed, so hide to prevent an unknown device from being listed in Windows Device Manager. TEST=build/boot Win11 on morphius, verify unknown device for the ACP machine driver no longer present. Change-Id: I14347ab6c840066db4ff700eff1aad4cf6faf66b Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78039 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-09-22mb/google/nissa/var/quandiso: Update USB port configRobert Chen
1. Support world facing usb camera on usb2_port7. 2. Update MB/DB fw_config to distinguish LTE and non-LTE devices. BUG=b:296506936 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I0c508475fdc86f0d7357f19684bdaae06e77fc27 Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77398 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-22mb/google/nissa/var/quandiso: Add P-sensor supportRobert Chen
- GPIO changes: GPP_B5 ==> I2C_P_SENSOR_SDA GPP_B6 ==> I2C_P_SENSOR_SCL GPP_H19 ==> P_SENSOR_INT_L - I2C SX9324 support - Disable GPIOs when sub board LTE not used BUG=b:296506936 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I5ed82b125b6c594225efca418017ef42f4f63b9d Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77392 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-09-22mb/google/nissa/var/quandiso: Add SD card supportRobert Chen
GPIO changes - GPP_D8 ==> SD_CLKREQ_ODL - GPP_D17 ==> SD_WAKE_N - GPP_H12 ==> SD_PERST_L - GPP_H13 ==> EN_PP3300_SD_X Genesys Logic GL9750 support BUG=b:296506936 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: Ib7c80f43680481c0d1a18662fa494012390a984d Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77391 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-22mb/google/nissa/var/quandiso: Disable WCAM supportRobert Chen
Quandiso doesn't support mipi WCAM. BUG=b:296506936 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I8a166d0bb1c034f2e3a5af7456500abd078e93f9 Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77389 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-22mb/google/nissa/var/quandiso: Update initial files based on yavillaRobert Chen
Update files copied from yavilla - fw_config setting - GPIO setting - Kconfig setting - overridetree setting - SPD memory parts - variant setting BUG=b:296506936 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage flash bin file in DUT Change-Id: Ibbef42a1f891d0cf0309aa76edd7ec5dd664588e Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77361 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-22security/tpm: Remove unnecessary tss_common.hJon Murphy
Remove the unnecessary tss_common.h header from the repo. tss_errors.h is a more appropriate place for the TPM_SUCCESS value, and the other define is only used by tpm_common.c and can be placed there. BUG=b:296439237 TEST=Builds Change-Id: I99cf90f244a75c1eeab5e9e1500e05c24ae0a8e5 Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78033 Reviewed-by: Tim Van Patten <timvp@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2023-09-22mb/google/dedede: Fix SOF config for unprovisioned audio ampMatt DeVillier
Dedede boards which select AUDIO_AMP_UNPROVISIONED via fw_config use rt1015 for the speaker topology, not max98360a. TEST=build/boot Win11 on google/magpie, verify correct audio profile selected. Change-Id: I5b75bd8fd37d2837de3c5bd25a02411a6982103b Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77741 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2023-09-22drivers/sof: Add support for rt1019 speaker topologyMatt DeVillier
Enables correct identification of boards using rt1019 speaker amplifier by SOF Windows drivers. TEST=tested with rest of patch train Change-Id: I550dc8614e6e21d6d8715c12b7a4af35117497b5 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77739 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-09-22soc/intel/Makefile.inc: Add comment where CONFIG_CSE_*_FILE are usedReka Norman
commit 06cb756f0202d7 ("soc/intel/common/block/cse/Kconfig: Remove unused symbols") removed these Kconfigs since it's not obvious where they're used. Add a comment to make it easier to grep for their uses. Change-Id: I27d94e8a558d6e73004d45cd2aedd94678d29b94 Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78041 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-22Revert "soc/intel/common/block/cse/Kconfig: Remove unused symbols"Reka Norman
This reverts commit 06cb756f0202d78d299b30728b6559f6107c43c3. Reason for revert: These Kconfigs are needed by boards which use the CSE stitching tools (i.e. select STITCH_ME_BIN). They're selected by some boards in the downstream ChromeOS repo. They're used in src/soc/intel/Makefile.inc (see the line with `$(CONFIG_CSE_$(2)_FILE)`). Change-Id: Ide6fc74b457439f06b7ef9b37f11d6c9ff226b80 Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76719 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-22mb/google/puff: Add VBT for Genesis variantMatt DeVillier
Add data.vbt file and Kconfig to use it. Extracted from google firmware genesis_13324.283.0 TEST=build genesis with FSP GOP display init Change-Id: If836b214da1350111d7b7d1f24865199f814c521 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78035 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-09-22mb/google/puff: Add VBT for Ambassador variantMatt DeVillier
Add data.vbt file and Kconfig to use it. Extracted from google firmware ambassador_13324.283.0 TEST=build ambassador with FSP GOP display init. Change-Id: I5c47700c5abe7d96112702d48a2b749f1784a494 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78032 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-09-22mb/google/puff: Set early GPIOs to enable bootblock consoleMatt DeVillier
Without the PCH UART GPIOs set early, there is no serial console output until ramstage. Add them to the early GPIOs for all puff variants. TEST=build/boot google/puff (wyvern) with serial console enabled, verify console output starts in bootblock. Change-Id: Ica0506b2b80e4fac0d3ca11b4cfdd128ce424b36 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78029 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-22soc/mediatek: Move common devapc definitions to common/Nina Wu
Move following definitions to common/ 1) the definition of the bit fields for domain remap 2) the definition of the structure for the permission of all domains Change-Id: Iac84ebc908ae384a6280388af4120f6349a32ed4 Signed-off-by: Nina Wu <nina-cm.wu@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77860 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-22mb/google/brya: Init TPM in bootblock when not using vbootMatt DeVillier
Brya queries the TPM in early ramstage (pre-device init) to determine if the CR50 has support for long-pulse interrupts. If the TPM (and underlying I2C controller) hasn't already been setup in verstage, it will fail to do so in ramstage since the I2C controller has not yet been initialized. To work around this, initialize the TPM in bootblock for the non-vboot case, to ensure the I2C controller is set up when needed in early ramstage. TEST=build/boot google/brya (banshee), verify no I2C errors in cbmem console when initializing TPM in early ramstage. Change-Id: I26f0711a9cc4c2eb9837f258cadf391d337994c9 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78028 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-22mb/google/rex/var/rex0: Add entries for SAR Proximity SensorsSubrata Banik
This patch adds ACPI entries for SAR Proximity Sensors as below SAR1 Sensor: - SAR1_INT_L : GPP_E00 - I2C5 7-bit address 0x28 SAR2 Sensor:   - SAR2_INT_L : GPP_E08 - I2C 7-bit address 0x2c BUG=b:297977526 TEST=Able to build and boot google/rex. w/o this patch: Total 6 devices are listed below: > ls -lt /sys/bus/iio/devices/iio:device* /sys/bus/iio/devices/iio:device5 -> ../../../devices/LNXSYSTM:00/ LNXSYBUS:00/PNP0A08:00/device:07/ /sys/bus/iio/devices/iio:device0 -> ../../../devices/pci0000:00/ 0000:00:1f.0/PNP0C09:00/GOOG0004:0 /sys/bus/iio/devices/iio:device2 -> ../../../devices/pci0000:00/ 0000:00:1f.0/PNP0C09:00/GOOG0004:0 /sys/bus/iio/devices/iio:device4 -> ../../../devices/pci0000:00/ 0000:00:1f.0/PNP0C09:00/GOOG0004:0 /sys/bus/iio/devices/iio:device1 -> ../../../devices/pci0000:00/ 0000:00:1f.0/PNP0C09:00/GOOG0004:0 /sys/bus/iio/devices/iio:device3 -> ../../../devices/pci0000:00/ 0000:00:1f.0/PNP0C09:00/GOOG0004:0 w/ this patch: Total 8 devices are listed below: > ls -lt /sys/bus/iio/devices/iio:device* /sys/bus/iio/devices/iio:device6 -> ../../../devices/pci0000:00/ 0000:00:19.1/i2c_designware.4/i2c- /sys/bus/iio/devices/iio:device5 -> ../../../devices/LNXSYSTM:00/ LNXSYBUS:00/PNP0A08:00/device:07/ /sys/bus/iio/devices/iio:device7 -> ../../../devices/pci0000:00/ 0000:00:19.1/i2c_designware.4/i2c- /sys/bus/iio/devices/iio:device0 -> ../../../devices/pci0000:00/ 0000:00:1f.0/PNP0C09:00/GOOG0004:0 /sys/bus/iio/devices/iio:device2 -> ../../../devices/pci0000:00/ 0000:00:1f.0/PNP0C09:00/GOOG0004:0 /sys/bus/iio/devices/iio:device4 -> ../../../devices/pci0000:00/ 0000:00:1f.0/PNP0C09:00/GOOG0004:0 /sys/bus/iio/devices/iio:device1 -> ../../../devices/pci0000:00/ 0000:00:1f.0/PNP0C09:00/GOOG0004:0 /sys/bus/iio/devices/iio:device3 -> ../../../devices/pci0000:00/ 0000:00:1f.0/PNP0C09:00/GOOG0004:0 Change-Id: I0a518d58915f9f4dbe58a45c4dc5875abbfda135 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78045 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2023-09-22coreboot.org-status: Make URLs branch agnosticPatrick Georgi
The primary branch changed names. To remain robust, just use HEAD, which will point to whatever is authoritative. Change-Id: I809ea748a5e51f4eea6bc227fa1fc5c8b07fe2ef Signed-off-by: Patrick Georgi <patrick@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78015 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-22mb/google/rex: Add new FMD for prod (QS) Meteor Lake siliconSubrata Banik
Intel Meteor Lake QS silicon provides better size optimized pre-x86 reset blobs. This patch creates a new flash layout (FMD) for QS to accommodate those optimizations, and renames the existing FMD for ES (pre-prod) silicon. Comparative analysis between QS and ES flash layout is here: For QS silicon: - SI_ALL reduced from 9MB to 8MB. - SI_BIOS increased by 1MB (from 23MB to 24MB) to fill in the 32MB SPI layout. - ME_RW_A/B reduce from ~4.5MB to 4MB. - Ensure RW-B slot is starting at 16MB boundary. - Unused space increased by 1MB. For ES silicon: - SI_ALL: 9MB - SI_BIOS: 23MB - ME_RWA/B: 4.5MB (for ISH) and 4.4MB (non-ISH). - Unused space 3MB (for release) and 2MB (for debug) layout. Change-Id: I881832a6b11a35710d4e847feadcc544b1f5d048 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77994 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
2023-09-21MAINTAINERS: Remove Elyes as toolchain maintainerElyes Haouas
I didn't have enough time, so it's reasonable to remove myself. Change-Id: I8f7d87f70916f3d0697b6c38ca6d75f3375bd374 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77965 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-09-21mb/google/geralt: Move selects from Kconfig.name to KconfigFelix Singer
Selects should be done in the Kconfig file instead of Kconfig.name and not mixed over both files. Change-Id: I590b7fb5f5f52cbf1a61c65f8fac757e36feac5e Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75028 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-21mb/google/kukui: Move selects from Kconfig.name to KconfigFelix Singer
Selects should be done in the Kconfig file instead of Kconfig.name and not mixed over both files. Change-Id: I866333a234203dc2da3d4dd8c4f87e4cfa332787 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75027 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-09-21mb/google/myst: Move selects from Kconfig.name to KconfigFelix Singer
Selects should be done in the Kconfig file instead of Kconfig.name and not mixed over both files. Change-Id: Ia4ed3491e6a32659b957285ab20ad47c9085083c Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75025 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-21mb/google/skyrim: Move selects from Kconfig.name to KconfigFelix Singer
Selects should be done in the Kconfig file instead of Kconfig.name and not mixed over both files. Change-Id: I097d50a7af7c8ea48369806e8bb73734a8e84470 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75024 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-21mb/google/gru: Move selects from Kconfig.name to KconfigFelix Singer
Selects should be done in the Kconfig file instead of Kconfig.name and not mixed over both files. Change-Id: Id7f9b598cc9df51ddf664b851172cc96a710c580 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75023 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-21mb/google/asurada: Move selects from Kconfig.name to KconfigFelix Singer
Selects should be done in the Kconfig file instead of Kconfig.name and not mixed over both files. Change-Id: I3f4965b8b253983ad1f8db77e1b91860a270c305 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75022 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-09-21Documentation: Remove unused build targetsFelix Singer
The options in conf.py for the following build targets are either commented out or contain example values, which suggests that there was no interest in them recently. Their comments also seem more like generated examples. * LaTeX * man pages * Texinfo In order to clean up our configs and scripts for the documentation, remove the configuration options from conf.py for these build targets. Also, remove the build targets responsible for generating a PDF file from Makefile. Don't touch Makefile.sphinx for now though as we usually wrap around it. We may bring these build targets back if there is real interest in them, but it seems only the HTML target was really used. Change-Id: I7df8ea886f94d9b25e8eeb0ccbc2a7392b96a575 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77439 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-21mb/google/guybrush: Move selects from Kconfig.name to KconfigFelix Singer
Selects should be done in the Kconfig file instead of Kconfig.name and not mixed over both files. Change-Id: If2c9c52f1e2866082df8e534b1a074639bb62db2 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75020 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-21mb/google/oak: Move Selects from Kconfig.name to KconfigFelix Singer
Selects should be done in the Kconfig file instead of Kconfig.name and not mixed over both files. Change-Id: Idf4a566af3853636945709c88c03fb8e777211c2 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75014 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-09-21mb/google/zork: Move selects from Kconfig.name to KconfigFelix Singer
Selects should be done in the Kconfig file instead of Kconfig.name and not mixed over both files. Change-Id: Iaa73bf7f85f840299c467b7d712546d3f72a4e75 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75019 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-09-21mb/google/cherry: Move selects from Kconfig.name to KconfigFelix Singer
Selects should be done in the Kconfig file instead of Kconfig.name and not mixed over both files. Change-Id: Id1b0d375670f9e59047eff737bc17e61bf93175e Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75016 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-21mb/google/mistral: Move selects from Kconfig.name to KconfigFelix Singer
Selects should be done in the Kconfig file instead of Kconfig.name and not mixed over both files. Change-Id: I1033a974a818308b31e1334cad5869d2cd81bd9e Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75017 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-21mb/google/corsola: Move selects from Kconfig.name to KconfigFelix Singer
Selects should be done in the Kconfig file instead of Kconfig.name and not mixed over both files. Change-Id: I207e25059a9fb9e6a951018e954662931b3f8b93 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75018 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-21mb/google/kahlee: Move selects from Kconfig.name to KconfigFelix Singer
Selects should be done in the Kconfig file instead of Kconfig.name and not mixed over both files. Change-Id: Id060f781b87567da2756c89275002b9ea4f4976c Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75015 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-21mb/google/zork/morphius: Hide FPR, PENH from Windows OSMatt DeVillier
No drivers exists or are needed, so use devicetree hidden keyword to set the ACPI status to hidden to prevent unknown devices from showing in Windows Device Manager. TEST=build/boot Win11 on morphius, verify unknown devices for the fingerprint reader and stylus detection are no longer shown. Change-Id: I992c0ec8d97c6041e3a268445613bfa42dd8b279 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78038 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-09-21drivers/generic/gpio_keys: Write device ACPI statusMatt DeVillier
Allows device to be hidden from OS (Windows) via devicetree 'hidden' keyword. TEST=tested with rest of patch train Change-Id: I81482bd19e24627cab80deed2b9057f45b6ac0a0 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78037 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-21soc/amd/*/cpu: factor out common noncar mp_init_cpusFelix Held
Since all non-CAR AMD SoCs have the same mp_init_cpus implementation, factor it out and move it to a common location. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ibf4fa667106769989c916d941addb1cba38b7f13 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78013 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-09-21mainboard/google/skyrim: Enable wake-on-DPRobert Zieba
Enable wake-on-DP by adding USB mux events to the wake mask. The EC wakes the AP with these events for DP connect/disconnect. BUG=b:294307786 TEST=DP connect/disconnect wakes the DUT appropriately. Change-Id: I864b03d08ce3d756bf4987d886db621d937483ce Signed-off-by: Robert Zieba <robertzieba@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78034 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-09-21soc/amd/mendocino: Do not load MP2 Firmware when in ROKarthikeyan Ramasubramanian
Currently MP2 Firmware is not built into RO firmware section but the soft fuse bit to disable MP2 firmware loading is not set. This causes the device to boot loop during recovery mode. Set the bit to disable MP2 firmware loading in RO. BUG=b:259554520 TEST=Build and boot to OS in Skyrim under both normal and recovery modes. Change-Id: I9e4cf4f72e2d36ad3cc33629ddb501ecdbf5eda9 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78023 Reviewed-by: Robert Zieba <robertzieba@google.com> Reviewed-by: Tim Van Patten <timvp@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-09-21mb/google/rex/var/karis: Enable PIXA touchpadTyler Wang
Karis uses PIXA touchpad, update related settings. BUG=b:294155897 TEST=(1) emerge-rex coreboot (2) Test on karis, touchpad function works Change-Id: I26e3257485c4abe050de7a79c6d3b72dbd048710 Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77517 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-09-21mb/x11-lga1151-series: Add x11ssw-fKieran Kunhya
This board is similar to x11ssm-f but has a proprietary form factor with NVMe and a single x16 slot (potentially bifurcated to 2x x8) and a x4 slot. Change-Id: I53a0b6012ae64cf1ba4b625f11aaf771637307f3 Signed-off-by: Kieran Kunhya <kieran@kunhya.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77610 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2023-09-20arch/arm64/Makefile.inc: Replace HAVE_ACPI_SUPPORT with HAVE_ACPI_TABLESMaximilian Brune
CONFIG_HAVE_ACPI_SUPPORT does not exist. Replace it with HAVE_ACPI_TABLES. Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: Icc7c00dc19cae4be13e6c8cc0084a69aed8fb8f5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77977 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-09-20cpu/x86/mtrr/debug: rename variables in display_variable_mtrrFelix Held
Change the name of msr_a and msr_m to the more descriptive msr_base and msr_mask. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6e0010f6d35ccf4288f4e0df8f51ea5f17c98b0f Reviewed-on: https://review.coreboot.org/c/coreboot/+/78007 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-20cpu/x86/mtrr/debug: use MTRR_PHYS_MASKFelix Held
Instead adding 1 to the result of MTRR_PHYS_BASE(index) to get the variable MTRR's mask MSR number, use the MTRR_PHYS_MASK macro. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ieecc57feb25afa83f3a53384e5a286f2e4e82093 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78006 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-09-20cpu/x86/mtrr/debug: use msr_t parameter in display_mtrr_fixed_typesFelix Held
Now that no local union definitions are used any more, pass the msr data to display_mtrr_fixed_types as an msr_t type parameter instead of a uint64_t parameter. Also rename the parameter from msr to msr_data to be more specific that this parameter is the MSR contents and not the MSR number. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iafde64129acc4bf9f01816de21c7793edfc1a799 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78005 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-09-20cpu/x86/mtrr/debug: make local MSR variables constFelix Held
In the functions the local MSR variables are only written once by rdmsr calls at the beginning of the function and then only read, so those can be made const. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1be6a5158c0c06abe128e9394d6001c40a8d4cbb Reviewed-on: https://review.coreboot.org/c/coreboot/+/78004 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-09-20cpu/x86/mtrr/debug: drop unnecessary MSR unionFelix Held
Commit 407e00dca06e ("include/cpu/msr.h: transform into an union") changed the msr_t type to a union that allows accessing the full 64 bit via the raw element, so there's no need to wrap it again in another union for the full 64 bit access. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I750307297283802021fac19e2cdf5faa12ede196 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78003 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-09-20soc/intel/alderlake: Hook up the OC watchdogMichał Żygowski
Hook up the OC watchdog common block and initialize it if requested. TEST=Enable watchdog on MSI PRO Z690-A and see the platform resets after some time. Enable the watchdog in driverless mode and see the platform no longer resets and periodic SMI keeps feeding the watchdog. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I1c2c640d48b7e03ad8cd8d6cdf6aac447e93cd86 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68945 Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-20intelblocks/oc_wdt: Consolidate the APIMichał Żygowski
Reduce the OC WDT integration code footprint by consolidating multiple API calls into a single function to be called by SoC. Change-Id: Iba031cd8e0b72cabc4d0d8a216273d763231c889 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77574 Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-20mb/google/rex/var/karis: Set VPU disable as defaultTyler Wang
BUG=b:299374763 TEST=emerge-rex coreboot Change-Id: I40fc768522e8679337c3b9f5497278e9f4639c3e Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77888 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-20util/superiotool: Tell compiler to use C99 instead of ANSI CNicholas Sudsgaard
Fails to build on musl libc as pci/types.h expects "POSIX types", which are not implemented, instead of stdint.h when using pre-C99 versions. Change-Id: Id1cf5bd72a0b4d76c87dc62c443d02df18ddd3fe Signed-off-by: Nicholas Sudsgaard <devel@nsudsgaard.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77791 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-20mb/google/rex: Select MIPI pre-prod if MTL pre-prod Si setSubrata Banik
This patch ensures that the `DRIVERS_INTEL_MIPI_SUPPORTS_PRE_PRODUCTION_SOC` config is enabled if the underlying platform is built with a pre-production SoC (aka `SOC_INTEL_METEORLAKE_PRE_PRODUCTION_SILICON` config is enabled). BUG=b:300652989 TEST=Ensures `DRIVERS_INTEL_MIPI_SUPPORTS_PRE_PRODUCTION_SOC` is enabled for google/rex4es aka all variants with ES silicon. Change-Id: Ieda39427915fa3973b832376ec20fc414ac2bedd Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77993 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Jakub Czapiga <jacz@semihalf.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
2023-09-20mb/{google,intel}: Choose platforms with pre-prod Meteor Lake SoCSubrata Banik
The tree contains engineering sample boards, that ship with pre-production Meteor Lake SoC. These boards are not sold. BUG=b:300652989 TEST=Ensure mainboards like google/rex4es and screebo4es have `SOC_INTEL_METEORLAKE_PRE_PRODUCTION_SILICON` config enabled. Change-Id: I1a875a0f1d2c38582f35250ebe645e53599f62de Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77992 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
2023-09-20soc/intel/meteorlake: Add configs for pre-production siliconSubrata Banik
Certain Intel Meteor Lake specific features are only enabled in production silicon (not available in early SoC aka pre-production silicon). - SPI usage for production SoC is much optimized compared to pre- production silicon. - MIPI driver requires a way to identify between pre-prod vs prod silicon. This patch adds config options to select the Pre-Production aka Engineering Silicon (ES). The mainboard users can specify which underlying SoC is being used for the target platform. BUG=b:300652989 TEST=No change in the functionality, just added new configs. Change-Id: I60fe11c1151a3a6c290cd0105eb570cb78e81797 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77991 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
2023-09-20soc/intel/meteorlake: Enable crashlogPratikkumar Prajapati
Enable SOC_INTEL_CRASHLOG and SOC_INTEL_IOE_DIE_SUPPORT Kconfig options. BUG=b:262501347 TEST=Able to build google/rex. Able to trigger and decode crashlog. Change-Id: I4beef7393090889fde8d67827035c3b57a3dbb34 Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77583 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-09-19soc/amd/picasso: add eMMC MMIO device to devicetreeFelix Held
Add the eMMC MMIO device to the devicetree and make it use the common AMD eMMC driver. Since there is now a device for this in the devicetree, also use this device to determine if the FSP should be told if the eMMC controller is supposed to be disabled. TEST=On Mandolin the eMMC controller both disappears in the Windows 10 device manager and in dmesg on Ubuntu 2022.04 LTS TEST=Morphius with NVMe SSD still works Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5453b69df776d2ce1f3be11e37cd26c8c64f0cd5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77990 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-09-19soc/amd/cezanne,common: expose eMMC device in ACPI when enabledFelix Held
When the eMMC MMIO device is enabled in the devicetree, it needs to be exposed in ACPI in order for the OS driver to be able to attach to it. The Cezanne eMMC controller isn't used in google/guybrush, so this the code path where the eMMC MMIO device is enabled in the devicetree can't be easily tested. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I69ff79b2d1c6a08cf333a2bb3996931962c2c102 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77989 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-09-19soc/sifive/fu540: Remove space after a castElyes Haouas
Change-Id: I6a64015326c6ec7e14a0465fe081a2cb4606cdc8 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77734 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-19sb/intel/common: Remove space after a castElyes Haouas
Change-Id: Ic3e9570c110d8cded8c00e74fff29cc3a711582e Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77737 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-09-19mb/google/rex/var/screebo: Change GPP_C06 to NCZhongtian Wu
GPP_C06 is the report pin of the touchpanel and has no actual function. Disable this pin to solve the leakage problem. BUG=b:298529441 BRANCH=none TEST=Test success by EE. Change-Id: I13f25788c0258639da4e277e7a15454a08d1599b Signed-off-by: Zhongtian Wu <wuzhongtian@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77716 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-18soc/amd: introduce SOC_AMD_COMMON_BLOCK_DATA_FABRIC_NP_REGIONFelix Held
Add a separate Kconfig option for adding np_region.c to the build. Only the code for Picasso, Cezanne, Mendocino, Phoenix and Glinda call data_fabric_set_mmio_np which is implemented in that file, so only select the new SOC_AMD_COMMON_BLOCK_DATA_FABRIC_NP_REGION Kconfig option for those. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic49ce039462b52e2c593c7d2fef43efc50901905 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77987 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-18drivers/tpm: Make temp test value naming consistentJon Murphy
Make naming convention consistent across all functions return values. BUG=b:296439237 TEST=Boot to OS on Skyrim BRANCH=None Change-Id: If86805b39048800276ab90b7687644ec2a0d4bee Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77536 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-09-18security/vboot: Add tpm return code to vboot fail callJon Murphy
Add the TPM return code to the vboot fail call to provide additional context. BUG=None TEST=builds Change-Id: Ib855c92d460d1e728718b688ff71cdc6e1d9a84a Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77944 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com>
2023-09-18drivers/pc80/tpm: Rename tis_probe to tis_initJon Murphy
tis_init calls into tis_probe and returns an error or success, simplify the call stack by removing the current tis_init implementation and renaming tis_probe to tis_init. BUG=None TEST=builds Change-Id: I8e58eda66a44abf5858123cf9bcf620626f1b880 Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77943 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com>
2023-09-18libpayload/libcbfs: Add VBOOT_CBFS_INTEGRATION supportJakub Czapiga
If LP_VBOOT_CBFS_INTEGRATION is enabled, then libcbfs will reboot with vboot failure in non-recovery mode on CBFS file hash mismatch. BUg=b:197114807 TEST=Build with VBOOT_CBFS_INTEGRATION enabled and boot on google/ovis4es device Change-Id: Ic0f62212b7217b384e8c4cbd9535fe4243301f8c Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77726 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-18libpayload: Add vboot and reboot utility functionsJakub Czapiga
Patch adds: - vboot_fail_and_reboot() for vboot failures handling. - reboot() weak implementation for payloads to implement, used by vboot_fail_and_reboot(). - vboot_recovery_mode_enabled() to check if recovery mode flag is set in vboot context. Implemented for future libcbfs implementation of VBOOT_CBFS_INTEGRATION in libpayload. BUG=b:197114807 TEST=none Change-Id: I53d1955573d54bc56d05f7780c18dcc8ac1fd399 Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77725 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-09-18soc/amd/common/data_fabric_helper: factor out data_fabric_set_mmio_npFelix Held
Factor out data_fabric_set_mmio_np and the helper functions it uses into a separate compilation unit. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I58625c5a038f668f8e30ae29f03402e1e2c4bee3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2023-09-18libpayload/vboot: Add vboot context initialization and management codeJakub Czapiga
To fully and easily implement fallback/recovery in libcbfs with vboot support the codebase requires access to vboot context. Moving context management to libpayload allows to avoid unnecessary overhead and code complication and still allows payloads to access it in a way it was designed. Access to this codebase will also allow implementation of e.g. vboot_fail_and_reboot() and other helpful utilities used by coreboot and depthcharge. BUG=b:197114807 TEST=make unit-tests TEST=Build and boot on google/ovis4es with CL:4839296 and VBOOT_CBFS_INTEGRATION enabled Change-Id: Id719be7c4f07251201424b7dc6c1125c6b5756d8 Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77635 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-09-18soc/amd/common/data_fabric_helper: use data_fabric_get_mmio_base_sizeFelix Held
Use data_fabric_get_mmio_base_size in data_fabric_print_mmio_conf instead of open coding the functionality. This will fix the printing of the MMIO config in the SOC_AMD_COMMON_BLOCK_DATA_FABRIC_EXTENDED_MMIO case which wasn't handled properly before. TEST=Console output from this function doesn't change on Mandolin: === Data Fabric MMIO configuration registers === idx base limit control R W NP F-ID 0 fc000000 febfffff 93 x x 9 1 10000000000 ffffffffffff 93 x x 9 2 d0000000 f7ffffff 93 x x 9 3 0 ffff 90 9 4 fed00000 fed0ffff 93 x x 9 5 0 ffff 90 9 6 0 ffff 90 9 7 0 ffff 90 9 === Data Fabric MMIO configuration registers === idx base limit control R W NP F-ID 0 fc000000 febfffff 93 x x 9 1 10000000000 ffffffffffff 93 x x 9 2 d0000000 f7ffffff 93 x x 9 3 fed00000 fedfffff 1093 x x x 9 4 0 ffff 90 9 5 0 ffff 90 9 6 0 ffff 90 9 7 0 ffff 90 9 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If602922648deca0caef23a9999c82acdd128b182 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77984 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-09-18security/vboot: Fix return type of extend_pcrs()Yu-Ping Wu
Since vboot_extend_pcr() returns vb2_error_t, the return type of extend_pcrs() should be vb2_error_t too. Also fix an assignment for vboot_locate_firmware(), which returns int instead of vb2_error_t. Change-Id: I1a2a2a66f3e594aba64d33cfc532d1bd88fa305e Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77869 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2023-09-18acpi: Add functions to declare ARM GIC V3 hardwareArthur Heymans
For GICD and GICR a SOC needs to implement 2 callbacks to get the base of those interrupt controllers. For all the cpu GIC the code loops over all the DEVICE_PATH_GICC_V3 devices in a similar fashion to how x86 lapics are added. It's up to the SOC to add those devices to the tree. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I5074d0a76316e854b7801e14b3241f88e805b02f Reviewed-on: https://review.coreboot.org/c/coreboot/+/76132 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-18acpi/Makefile.inc: Move code inclusionArthur Heymans
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I63bbac225662377693ad5f29cc8911494c49b422 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76009 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-09-18arch/arm64: Hook up ACPI table generationArthur Heymans
Linux v6.3.5 is able to detect and use ACPI tables on an out of tree target using hacked version of u-boot to pass ACPI through UEFI. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I4f60c546ec262ffb4d447fe6476844cf5a1b756d Reviewed-on: https://review.coreboot.org/c/coreboot/+/76071 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-09-18soc/amd/common/data_fabric_helper: make some helper functions staticFelix Held
data_fabric_disable_mmio_reg and data_fabric_find_unused_mmio_reg are only used by data_fabric_set_mmio_np in the same file, so make them static and drop the prototype from the header file. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6bf7a868aae2fd01b8adecd3e4cba6ff6d5119af Reviewed-on: https://review.coreboot.org/c/coreboot/+/77985 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2023-09-18security/vboot: Update vboot context with slot B absenceMichał Żygowski
coreboot offers two vboot schemes VBOOT_SLOTS_RW_A and VBOOT_SLOTS_RW_AB. When VBOOT_SLOTS_RW_AB is not selected then the resulting image is rather not expected to have the FW_MAIN_B FMAP region. When only RW_A region is used, vboot does additional full_reset cycles to try RW_B, even though it does not exist / the build was not configured for two RW partitions. To avoid it, a new vboot context flag has been introduced, VB2_CONTEXT_SLOT_A_ONLY, which can be set right after context initialization to inform vboot about absence of slot B. This will result in less full_reset cycles when vboot runs out of available slots and cause vboot to switch to recovery mode faster. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Ie123881a2f9f766ae65e4ac7c36bc2a8fce8d100 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75462 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-18cbfs: Remove x86 .data section limitation commentJeremy Compostella
With commit b7832de0260b042c25bf8f53abcb32e20a29ae9c ("x86: Add .data section support for pre-memory stages"), this comment is not correct anymore and should be removed. Change-Id: I61597841cd3f90cebe7323a68738f91d6d64b33d Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77988 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: sridhar siricilla <siricillasridhar@gmail.com> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>