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2022-10-13spd/lp5: Add new memory configuration of H58G66BK7BX067 and H58G56BK7BX068EricKY Cheng
Add Hynix H58G66BK7BX067 and H58G56BK7BX068 in the memory_parts.json and re-generate the SPD. BUG=b:243337816 BRANCH=None TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5 Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com> Change-Id: I8d6aac3ecec36b126e7e41d6c9475695aa7a26b2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68212 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com>
2022-10-13soc/amd/*/psp_verstage/svc: Make svc.h macros commonFred Reitberger
The psp_verstage/svc.h SVC_CALLx macros are virtually identical between picasso/cezanne/mendocino, so move to common. TEST=timeless builds are identical Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I86a8d9b043f68c01ee487f2cdbf7f61934b4a520 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68277 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-13mb/google/brya/var/felwinter: adjust I2C5 times for TPJohn Su
This change updates scl_lcnt, scl_hcnt, sda_hold value for I2C5. BUG=b:249031186 BRANCH=brya TEST=TP function is normal from EE check. Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: I5e756b7d7e14cace24ef2dfbb323c840c867ae1a Reviewed-on: https://review.coreboot.org/c/coreboot/+/68329 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
2022-10-13soc/amd/cezanne: enable LPC decodes if platform uses LPCJeremy Soller
Change-Id: I2473fe61b299d1c6221844cd744791b8012c5c67 Signed-off-by: Jeremy Soller <jeremy@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59103 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-10-13mb/hp/z220_series: Add missing PCI Interrupt Routing TableBill XIE
HP Z220 series has PCI slot(s) but Interrupt Routing Table in ACPI used to be missing, so one is added. Note that the values within the added one are obtained from my own SFF variant. If other variants have different values, please add them in a manner similar to mb/gigabyte/ga-b75m-d3h/acpi/pci.asl. Test result: Log lines like pci 0000:00:1e.0: can't derive routing for PCI INT A ath9k 0000:04:00.0: PCI INT A: no GSI disappeared from dmesg. Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Change-Id: I8522b25ac46db2054302c8f2418927c722b157e0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68334 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-13mb/hp/z220_series: Fix the indentation of dsdt.aslBill XIE
Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Change-Id: I66f99a5afbdd2b847a916a470a5def9a6d3999bc Reviewed-on: https://review.coreboot.org/c/coreboot/+/68335 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-13Doc/releases/4.18: Improve several small thingsAngel Pons
Add a missing period, use "SoC" with lowercase 'o' to refer to a "System on a Chip", fix up the redundant "CRB board" expression (that stands for "Customer Reference Board board"), switch the position of a verb and its adverb ("never was" ---> "was never") to sound more natural, and replace "depreciate" with "deprecate" for semantic correctness. Change-Id: Ic821a9030d4ff32c76765f51f1feb0f5503d4cc0 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68330 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-13Documentation: Get rid of trailing whitespacesElyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I698a9501fd3d47e1e5793df32ae1e4118dfd95f6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68328 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-10-13mb/prodrive/hermes: Use `snprintf()` to handle stringsAngel Pons
Strings in C are highly cursed. Use `snprintf()` to minimize the potential of running into undefined behavior in the future. Change-Id: I3caef25bc7676ac84bb1c40efe6d16f50f8f4d26 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68323 Reviewed-by: Patrick Georgi <patrick@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-10-13mb/prodrive/hermes: Harden `eeprom_read_serial()`Angel Pons
The `eeprom_read_serial()` function could return a non-NULL terminated string if the serial in EEPROM has `HERMES_SN_PN_LENGTH` (32) non-NULL characters. Make this impossible by adding an additional character for a NULL byte in the static buffer, which always gets set to 0 (NULL). Change-Id: I306fe1b6dd3836156afca786e352d2a7dca0d77c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68322 Reviewed-by: Patrick Georgi <patrick@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-10-12device: Drop unused ADL-N UFS PCI Device IDSubrata Banik
This patch drops unused ADL-N UFS PCI Device ID macro `PCI_DID_INTEL_ADP_UFS`. BUG=none TEST=Able to build and boot Google/Kano. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I24e4a1a871763473df4d610b13e8a3a754470233 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68292 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.com> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-10-12soc/intel: Kconfig: Correct UART source clock value in commentWonkyu Kim
Correct UART source clock value in comment from 120 MHz to 100 MHz. BUG=b:249530903 Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: Ifc17357051ae0b3bc663da467b4fc809a46024d4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68286 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-12Revert "soc/qualcomm: Update the wait time for checking PCIe link up"Shelley Chen
This reverts commit 4b5ba9436373d1addab13cd38ee6899e49ea029f. Reason for revert: This optimization is causing the non-serial enabled tot BIOS to not boot. To get tot back into good shape, will revert for now and reevalute this fix and resubmit at a later time. BUG=b:218406702 BRANCH=None TEST=reboot from AP console (on herobrine) after flashing image-herobrine.bin. prior to fix the device would never boot to login prompt. after rever the device would boot to login prompt again. Change-Id: Iaac5f2fb2120f6aa41a0ce9a763d50fd7b9a3ec7 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68339 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Douglas Anderson <dianders@chromium.org>
2022-10-12lib/lzma: Build the source for decompression with flag -OfastZheng Bao
The decompression is critical for speed of boot. So we sacrifice some generated code size to optimize for speed. This change speeds up the LZMA decompression between 3% and 6% at a cost of just over 2k of additional code space. BUG=b:223985641 TEST=Majolica The test is done on Majolica and the result is listed below. Time saved: We tested the boot time with each flag for 10 times. The duration of each decompression process is listed as below. Load FSP-M Load ramstage Load payload Ofast Os Ofast Os Ofast Os ------------------------------------------ 62543 62959 20585 22458 9945 10626 62548 62967 20587 22461 9951 10637 62560 62980 20588 22478 9951 10641 62561 62988 20596 22478 9954 10643 62569 62993 20596 22479 9954 10643 62574 63000 20605 22492 9958 10647 62575 63026 20615 22495 9959 10647 62576 63038 20743 22614 9960 10647 62587 63044 20758 22625 9961 10647 62592 63045 20769 22637 9961 10647 ----------------------------------------- average 62568 63004 20644 22521 9955 10642 (unit: microseconds) Size sacrificed: The size of object file with -Os: ./build/ramstage/lib/lzmadecode.o: file format elf32-i386 4 .text.LzmaDecode 00000d84 00000000 00000000 00000076 2**0 CONTENTS, ALLOC, LOAD, READONLY, CODE The size of object file with -Ofast: ./build/ramstage/lib/lzmadecode.o: file format elf32-i386 4 .text.LzmaDecode 00001719 00000000 00000000 00000080 2**4 CONTENTS, ALLOC, LOAD, READONLY, CODE (Output by running "objdump -h ./build/ramstage/lib/lzmadecode.o") We can see that size is increased from 3460 bytes to 5913 bytes, a change of 2453 bytes or 171%. Change-Id: Ie003164e2e93ba8ed3ccd207f3af31c6acf1c5e2 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66392 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-10-12mb/starlabs/starbook/tgl: Configure PMC muxSean Rhodes
Configure PMC mux in devicetree. Tested on StarBook Mk V with Ubuntu 22.04. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I297d5446e43357d97357f345668cf40dcd28502d Reviewed-on: https://review.coreboot.org/c/coreboot/+/68083 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-10-12mb/starlabs/starbook/tgl: Enable P2SBSean Rhodes
Enable the P2SB so that the SPI is discoverable by the OS. Change-Id: I49802f93a97a18ecc10f48d213619855728e1290 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67029 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-12mb/starlabs/starbook/tgl: Use chipset.cb aliasesSean Rhodes
Change-Id: Ie9655406c7afe7a22f131d35633a697c5bbde4e3 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67027 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-10-12payloads/edk2: Add a recipe to build the ShimLayerSean Rhodes
The ShimLayer is required to start the Universal Payload. It will build the required HOBs and pass them accordingly. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I043271994f40813d9059a89420d4311d9d5802b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64485 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-10-12treewide: Use 'fadt->x_pm1a_cnt_blk.addrl = fadt->pm1a_cnt_blk'Elyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Ic48c5c165732c8397c06a2362191a94ae5805cf1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68276 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-12treewide: Use 'fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk'Elyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I7ddb4ea792b9a2153b7c77d2978d9e1c4544535d Reviewed-on: https://review.coreboot.org/c/coreboot/+/68275 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-12treewide: Use 'pm2_cnt_len' for 'x_pm2_cnt_blk.bit_width'Elyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I040ddab8845cc2191c6ca5af7f132ec8a504bccf Reviewed-on: https://review.coreboot.org/c/coreboot/+/68274 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-12treewide: Use 'gpe0_blk' for 'x_gpe0_blk.addrl'Elyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I05d5097097b925a7bc8058f4c23e7c13a49f03c5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68273 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-12treewide: Use 'gpe0_blk_len' for 'x_gpe0_blk.bit_width'Elyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I581cacb6086d94fe65e6f4800454f447e1ada07b Reviewed-on: https://review.coreboot.org/c/coreboot/+/68272 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-12treewide: Use 'fadt->pm_tmr_len' for 'x_pm_tmr_blk.bit_width'Elyes Haouas
Change-Id: Id4e2939b74ec93f50a4bedd0069090f0775b0556 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68271 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-12treewide: Use 'fadt->pm1_cnt_len' for 'x_pm1a_cnt_blk.bit_width'Elyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I4e468e6bb58adc44bd66149eb79dc885dbf73c67 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68270 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-12treewide: Use 'fadt->pm1_evt_len' for 'x_pm1a_evt_blk.bit_width'Elyes Haouas
Change-Id: I1e51ccad32f1c5e692c76b331eedf4d3bb260d38 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68269 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-12soc/intel/ehl: Fix incorrect access to MAC_MDIO_DATA registerMario Scheithauer
Function 'setbits16' performs an 'OR' operation with the new data and the origin register entry. This can lead to an incorrect value in the register which can then lead to issues. Change-Id: I0212420be770e2ffdabebbfaf5dfbf8d99d25915 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68214 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-10-12soc/intel/ehl: Support maximum memory frequency selectionChristian Gmeiner
Makes it possible to configure the maximum allowed/supported DDR memory frequency on a per mainboard basis. Test - Define maximum memory frequency in mainboard devicetree.cb - Boot into Linux and run 'sudo dmidecode --type 17' to check memory speed - Boot into Linux and run 'phoronix-test-suite benchmark ramspeed' Change-Id: I9e0c7225e2141e675a20b8e3f0dbe8c0b3a29b28 Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68097 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-10-12device/dram/ddr2: Use 'enum cb_err' instead of 'int'Elyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I8ea6e773d858b30d75ff93d4fe07301f3825c1cb Reviewed-on: https://review.coreboot.org/c/coreboot/+/68240 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-10-12nb/intel/i945/raminit: Include `inttypes.h` for PRIxPTRPaul Menzel
Selecting *Output verbose RAM init debug messages* (`CONFIG_DEBUG_RAM_SETUP=y`) the build fails due to the missing header. CC romstage/northbridge/intel/i945/raminit.o src/northbridge/intel/i945/raminit.c: In function 'ram_read32': src/northbridge/intel/i945/raminit.c:77:39: error: expected ')' before 'PRIxPTR' 77 | PRINTK_DEBUG(" RAM read: %" PRIxPTR "\n", offset); | ^~~~~~~ src/northbridge/intel/i945/raminit.c:25:52: note: in definition of macro 'PRINTK_DEBUG' 25 | #define PRINTK_DEBUG(x...) printk(BIOS_DEBUG, x) | ^ src/northbridge/intel/i945/raminit.c:22:1: note: 'PRIxPTR' is defined in header '<inttypes.h>'; did you forget to '#include <inttypes.h>'? 21 | #include "chip.h" +++ |+#include <inttypes.h> 22 | src/northbridge/intel/i945/raminit.c:25:39: note: to match this '(' 25 | #define PRINTK_DEBUG(x...) printk(BIOS_DEBUG, x) | ^ src/northbridge/intel/i945/raminit.c:77:9: note: in expansion of macro 'PRINTK_DEBUG' 77 | PRINTK_DEBUG(" RAM read: %" PRIxPTR "\n", offset); | ^~~~~~~~~~~~ src/northbridge/intel/i945/raminit.c:77:22: error: spurious trailing '%' in format [-Werror=format=] 77 | PRINTK_DEBUG(" RAM read: %" PRIxPTR "\n", offset); | ^~~~~~~~~~~~~~~~ src/northbridge/intel/i945/raminit.c:25:52: note: in definition of macro 'PRINTK_DEBUG' 25 | #define PRINTK_DEBUG(x...) printk(BIOS_DEBUG, x) | ^ src/northbridge/intel/i945/raminit.c:77:36: note: format string is defined here 77 | PRINTK_DEBUG(" RAM read: %" PRIxPTR "\n", offset); | ^ Include `inttypes.h` to fix it. Fixes: e8bb6d2b16ac ("Output verbose RAM init debug messages") Change-Id: If3851ec899d4c7ce5fd64542827f9e0eb546d68b Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68265 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-12cpu/x86/64bit: Fix building with -jxArthur Heymans
config.h is a dependency so add it. Change-Id: Iac87039dd43aa75d49766b9a239fbd841ca6850c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68244 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-12util/superiotool/nuvoton.c: Add NCT6687D-W register definitionsMichał Żygowski
Based on public NCT6686D hardware datasheet revision 0.5 which should be similar to NCT6687D. TEST=Dump NCT6687D, GPIO and EC registers on MSI PRO Z690-A WIFI DDR4 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I38db1de0f3d3b6de14bcb758afc9804c072c1895 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63868 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
2022-10-12docs/releases/4.18: Rephrase deprecation note of Intel Ice LakeFelix Singer
The release of coreboot 4.18 is delayed and thus version 4.19 won't be released in upcoming November. Instead, just mention the version to be more flexible about the date. Change-Id: I33213479b02c2159beca78432aca775a04409e4c Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68261 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-12docs/releases/4.18: Deprecate Intel Quark and Intel GalileoFelix Singer
The SoC Intel Quark is unmaintained and various efforts to revive it failed. Thus, deprecate the following components with the 4.18 release. * Intel Quark SoC * Intel Galileo mainboard The support for these components will be dropped with the release 4.20. Change-Id: I738ad74da043649107473dc0c2e6adf343e4cd35 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68260 Reviewed-by: ron minnich <rminnich@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-11mb/system76: Set gfx registerTim Crawford
Fixes brightness controls on Windows 10. Change-Id: I33ac1b5a17c95dbb1b166c38fcd639cdac439724 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67636 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2022-10-11mb/system76: Set SMBIOS wakeup type to power switchTim Crawford
Windows hardware tests require this field not be "Reserved". The System76 EC firmware does not report the wake type, so it is not possible to know if the system was powered on from the power switch or Wake-on-LAN. In the case WoL is used, this will report the wrong value. Change-Id: I4653c6bce2a5f0a88281fc810df5646e44f90674 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66837 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2022-10-11mb/starlabs/starbook/kbl: Use chipset.cb aliasesSean Rhodes
Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I2da15db3d7fba4396c74800e531476c108cafe17 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67421 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-11mb/starlabs/starbook/cml: Enable SRAMSean Rhodes
Enable SRAM in devicetree so that resources are allocated properly for it. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I1d7ee4f950b31f2be6fb7bd107b5fe54785ed81a Reviewed-on: https://review.coreboot.org/c/coreboot/+/67420 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-11mb/starlabs/starbook/cml: Enable P2SBSean Rhodes
Enable the P2SB so that the SPI is discoverable by the OS. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ied7a6ea706e6da86182c109ab4813fa3fcebb1f8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67419 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-11util/amdfwread: Fix cookie error messageArthur Heymans
Change-Id: I580675fcbf8c5058ade371c6b9edb7b7070a78a3 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68234 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-10-11util/amdfwutil: Order enum and use hex consistentlyArthur Heymans
This makes it easier to match the code to the datasheet (55758, NDA only). This also removes the duplicate lines: "{ .type = AMD_FW_PSP_SMU_FIRMWARE, .subprog = 1, .level = PSP_BOTH | PSP_LVL2_AB }, { .type = AMD_FW_PSP_SMU_FIRMWARE2, .subprog = 1, .level = PSP_BOTH | PSP_LVL2_AB }," TESTED: google/vilboz still boots. Change-Id: I1c959a0fbbf16cc65be34b79f68ec7f92fd4368f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68118 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marvin Drees <marvin.drees@9elements.com> Reviewed-by: ritul guru <ritul.bits@gmail.com>
2022-10-11mb/google/brya/nivviks: Enable ISH driver and firmware nameMeera Ravindranath
BRANCH=none BUG=b:234776154 TEST=build and boot Nirwen UFS, copy ISH firmware to host file system /lib/firmware/intel/adln_ish.bin check "dmesg |grep ish", it should show: ish-loader: ISH firmware intel/adlnrvp_ish.bin loaded Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Change-Id: I89782b0b7dde1fca0130472a38628e72dfd5c26c Reviewed-on: https://review.coreboot.org/c/coreboot/+/68164 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-10-11mb/prodrive/hermes: Make board settings less error-proneAngel Pons
First of all, make sure that `get_board_settings()` never returns NULL. If there's a problem, return predefined values for board settings. If the board settings definition differs between coreboot and the BMC, the CRC will not match. Allow coreboot to use the BMC settings provided by older BMC firmware revisions which have less settings, if the CRC of the first N bytes matches the expected CRC. TEST=Boot coreboot master with BMC FW R04.05, observe board settings being honored even though coreboot's definition has an extra option. Change-Id: I0f009b21ef0850a2af6edef1818c770171358314 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67381 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-11payloads/edk2: Add a recipe to build UniversalPayload.elfSean Rhodes
Add a recipe to build UniversalPayload.elf, which uses a wrapper for the UniversalPayloadBuild.py that is hosted in the edk2 repository. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I2aa318513244f576e07e72713fad3b4f7bd7c22e Reviewed-on: https://review.coreboot.org/c/coreboot/+/68183 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-10-11coreboot: Add support for include-what-you-useMartin Roth
The tool "include-what-you-use" analyzes each file's headers and makes recommendations for header files to add and remove. There are additional scripts as part of the package that will make these changes directly based on the recommendations, but due to the way coreboot compiles code in/out base on Kconfig options, this isn't really safe for the project to use. It is a good starting point though. To use, set the IWYU kconfig option, then build with the command: make -k Because this doesn't actually build any files, the -k option is needed or make will stop after looking at the first file. Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Change-Id: I084813f21a3c26cac1e4e134bf8a83eb8637ff63 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67915 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-10-11configs/config.msi_ms7d25: Enable CBFS serial and UUID as defaultMichał Żygowski
There is no option to calculate or generate the serial number and UUID on this platform. Enable CBFS UUID and serial by default so anybody can easily populate the missing fields. TEST=Add UUID and serial CBFS files, boot the platform and see both UUID and serial number are populated correctly. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Ic8af889f12617d4ab6a27c6f336276c04f26244c Reviewed-on: https://review.coreboot.org/c/coreboot/+/64640 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-11drivers/generic/cbfs-uuid: Add driver to include UUID from CBFSMichał Żygowski
When system_uuid CBFS file is present and contains the UUID in a string format, the driver will parse it and convert to binary format to populate the SMBIOS type 1 UUID field. TEST=Add UUID file and boot MSI PRO Z690-A DDR4 WIFI and check with dmidecode if the UUID is populated correctly. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I22f22f4e8742716283d2fcaba4894c06cef3a4bf Reviewed-on: https://review.coreboot.org/c/coreboot/+/64639 Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-11mb/google/rex: Enable PD SyncSubrata Banik
This patch enables PD Sync for Rex. BUG=b:248775521 TEST=Able to boot Google/Rex with PD sync enabled. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I749b5dea481c7546579e97f923f143dd17f831d3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67819 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-10-10brya: add new zydron variantDavid Wu
Add a new zydron variant, which is a variant of brya's skolas baseboard. currently copy the variant file from kano. BUG=b:250787251 TEST=build pass Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I49a41678568daef80b7cd1e3ed60ce4763034f9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/68130 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: YH Lin <yueherngl@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-10nb/intel/i945/raminit.c: Fix formatted printElyes Haouas
Change-Id: I7122988a1c88175a2e72c11bb95bfa434ce48ff2 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68104 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-10Documentation/flashing_firmware: Add info about SPI flash headerNicholas Chin
Some mainboards have a header connected to the SPI bus, which can be used to connect a second flash chip and override the onboard flash. This allows one to boot coreboot on the system without ever having to flash the onboard flash. HP boards with this header all seem to use the same 2x8 or 2x10 header layout, so document the pinout. Change-Id: Ic2bf1244adfb78872340f212519c6ab33e26646a Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67818 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-10util/amdfwtool: Add Mendocino to usageFred Reitberger
Add missing Mendocino soc to usage print. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I8b995fccc23dcca87d45cc13fbb1ebbc1f0e2add Reviewed-on: https://review.coreboot.org/c/coreboot/+/68226 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-10mb/amd/birman: Add framework for morgana crb birmanMartin Roth
birman is the reference board for the morgana SoC. It needs to be updated to match the actual board design as well. Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Change-Id: I4b16854c954949217a76c3d4f04ddc4001f64337 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68196 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-10soc/amd/common: Remove buildtime error for unknown cpuMartin Roth
This is not critical functionality and doesn't need a build-time error. Having it as a build time error causes a chicken & egg issue where the chipset needs to be added before it can be added to this file, but the header file fails the build because the chipset is unknown. It's not practical to exclude these files from the new platform builds because the PSP functionality is thoroughly embedded into the coreboot structure. Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Change-Id: Ib02bbe1f9ffb343e1ff7c2bfdc45e7edffe7aaed Reviewed-on: https://review.coreboot.org/c/coreboot/+/68245 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-10-10soc/amd/morgana: Add initial commit for new SoCMartin Roth
This is an initial framework for the Morgana SoC. TODOs have been added to the files for both customization and commonization. Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Change-Id: If92e129db10d41595e1dc18a7c1dfe99d57790cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/68195 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-10util/amdfwtool: Add preliminary code for morgana & glinda SOCsMartin Roth
This allows amdfwtool to recognize the names for the upcoming morgana and glinda SoCs. It does not yet do anything for those SoCs, but this allows the morgana SoC to build. Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Change-Id: I766ce4a5863c55cbc4bef074ac5219b498c48c7f Reviewed-on: https://review.coreboot.org/c/coreboot/+/68193 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-10payloads/edk2: Guard the build targetSean Rhodes
Specifying a build target only applies to UefiPayloadPkg, so guard it against the relevant Kconfig option. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ia4597b5ed76616e39cec45f8a69be9f1ccd72d4c Reviewed-on: https://review.coreboot.org/c/coreboot/+/68182 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-10-10payloads/edk2: Guard the silent switchSean Rhodes
The silent switch, `-s`, only works for building UefiPayloadPkg. Guard it against the relevant Kconfig option so that it doesn't cause problems with other targets. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I5a5df636e6484a435c849c6d19c7cb61e8e62ee6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68181 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-10util/lint/lint-stable-003-whitespace: Fix shell variable nameFred Reitberger
Fix shell variable "LINTDIR" so that helper_functions.sh can be found. TEST=`./util/lint/lint lint-stable --junit` no longer prints "cannot open /helper_functions.sh: No such file" Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I68f2e65fa1c9297ad6b58b77576deaeef8bd76e3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68225 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-10-10Docs/architecture: Fix filename for coreboot architecture diagramNicholas Chin
A spelling mistake in the markdown reference to the coreboot vs EDK II bootflow diagram was previously fixed, but the actual filename was not changed resulting in a broken reference. Change-Id: I512646e9af312ba2e1db8f597f6fffa8d54a3515 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67782 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-10-08soc/amd/mendocino/psp_verstage: Remove TODO commentKarthikeyan Ramasubramanian
PSP verstage has been successfully enabled and this makefile looks good. Hence removing a TODO comment. BUG=b:239090306 TEST=Build Skyrim BIOS image. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: Ic3cd55171fd1e4d74fac72f0b0b92dc80e533b5c Reviewed-on: https://review.coreboot.org/c/coreboot/+/68227 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-08mb/google/skyrim: Create frostflow variantChao Gui
Create the frostflow variant of the skyrim reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:240970782 BRANCH=None TEST=util/abuild/abuild -p none -t google/skyrim -x -a make sure the build includes GOOGLE_FROSTFLOW Signed-off-by: Chao Gui <chaogui@google.com> Change-Id: I937e6562094968824e73bfa20390b3ec8b24dfa0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68189 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-10-08mb/prodrive/hermes: Write reset cause regs to EEPROMAngel Pons
Write the value for reset cause registers to the EEPROM for debugging. Change-Id: I827f38731fd868aac72103957e01aac8263f1cd3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67483 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-08mb/prodrive/hermes: Add part numbers to SMBIOSAngel Pons
Adjust the EEPROM layout to account for two new fields: board part number and product part number. In addition, put them in a Type 11 SMBIOS table (OEM Strings). Also, rename a macro to better reflect its purpose. Change-Id: I26c17ab37859c3306fe72c3f0cdc1d3787b48157 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67759 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-08util/inteltool: Add support for (non-ULT) BroadwellAngel Pons
Add support for traditional (non-ULT) Broadwell. Change-Id: Ibe0ed9badd580e28060fe8df14a01352d4c1e11e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68186 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-10-08util/inteltool: Add 9 series PCH supportAngel Pons
Add the PCI device IDs for 9 series PCHs. Change-Id: Id216cd071b09c93ee6a4792944c6fad39254aa3b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68185 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-10-08payloads/edk2: Add note that upstream edk2 does not workSean Rhodes
Upstream edk2 doesn't work, but we still have the option for it for testing. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I6ec9f4746640baa030762650ab7b83d85ab8c1e1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67780 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-10-08payloads/edk2: Add an option for verbose buildsSean Rhodes
Add EDK2_VERBOSE_BUILD which removes the `-q` and `-s` switches so the build log becomes verbose. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Iaf1e96657f43edddfa4de0d3e00f3b24e7eb855b Reviewed-on: https://review.coreboot.org/c/coreboot/+/67677 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-10-08vc/amd/fsp: Add Morgana FSP vendorcodeMartin Roth
Initial commit of the FSP-specific code for the Morgana SoC. This is just an initial framework and still needs to be updated to match the Morgana FSP. Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Change-Id: Ic53c59404f96c73c55eb2648113c5ced26d6e20c Reviewed-on: https://review.coreboot.org/c/coreboot/+/68192 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2022-10-08vc/amd/fsp: Make common directoryMartin Roth
The common directory is for files that shouldn't change, or shouldn't change much between platforms. These will be removed from other directories and used in upcoming commits. Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Change-Id: I37ed98a67b066598fdebcc5b034e64dc639fda7f Reviewed-on: https://review.coreboot.org/c/coreboot/+/68191 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2022-10-08Update amd_blobs submodule to upstream masterMartin Roth
Updating from commit id 43136aa: 2022-09-30 11:01:39 -0700 - (mendocino: Add stripped microcode patch) to commit id 234dc70: 2022-10-06 16:05:45 -0700 - (morgana: add placeholder blobs) This brings in 3 new commits: 234dc70 morgana: add placeholder blobs 84928ce mendocino: Upgrade SMU to 90.35.0 12ca1df mendocino: Add all blobs from PI 1.0.0.2 Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Change-Id: Id55c468721ac42ecd71e8e3d1fa1cb4887a98c99 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68190 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2022-10-08Documentation/releases: Add details about edk2 updatesSean Rhodes
Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I592f0ee971737ef271d1df9142551eb24b775a06 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66440 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-10-08payloads/edk2: Separate the build target and repositorySean Rhodes
Until recently, there were two options to build edk2, UefiPayloadPkg and CorebootPayloadPkg. Now, there is only one, UefiPayloadPkg but soon, there will be Universal Payload. It makes more sense, as the official edk2 repository doesn't work with coreboot, to have the build target and repository separate. That will allow for building either UefiPayloadPkg or Universal Payload from the official repository, MrChromebox' fork or a custom repository. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: If7f12423058ef69838741f384495ca766ccea083 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66080 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-10-08mb/google/brya: Enable DRIVERS_GENESYSLOGIC_GL9750 for lisbonKevin Chiu
Enable DRIVERS_GENESYSLOGIC_GL9750 for lisbon BUG=b:246657849 TEST=FW_NAME=lisbon emerge-brask coreboot Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Change-Id: I74cd634700b2de16ae471e0a738b67a14fd82a50 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68168 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-07ec/starlabs/merlin: Add EC related files for Alder Lake boardsSean Rhodes
Add EC memory layout and Q events for Intel Alder Lake based boards, the "StarBook Mk VI" and "StarFighter Mk I", which both use the ITE 5570E. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I8cea386ba91d076084002738fe7041834deea311 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67398 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-07mb/prodrive/hermes: Factor out serial reading logicAngel Pons
Add the `eeprom_read_serial()` function to read serials from the EEPROM. Note that there's only one buffer now: this means only one serial can be accessed at the same time, and the buffer needs to be cleared so that it does not contain old data from other serials. Given that the serials are copied one at a time into SMBIOS tables, having one shared buffer is not a problem. Change-Id: I5c9781e4e599043be756514cfd6dd86dedcf580c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67275 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-07mb/prodrive/hermes: Prevent SGPIO cross-powering 5V railAngel Pons
The PCH's SGPIO pads are connected to a buffer chip that is powered from the always-on +3V3_AUX rail. For some cursed reason, when the SGPIO pads stay configured as SGPIO when a Poseidon system shuts down, voltage from the +3V3_AUX-powered buffer chip will leak into the +5V rail through the SATA backplane. Just pulling the SGPIO pads low before the system powers off stops the +5V rail from being cross-powered. This issue has only been observed in S5, but it's very likely other sleep states are affected as well. Thus, always pull the SGPIO pins low before entering ACPI S3 or deeper because the power supply will turn off in these states as well. TEST=Obtain a Poseidon system, verify that the +5V rail is cross-powered after going to S5. We measured 0.17V on our system, but voltages as high as 0.6V were measured on other systems. Verify that unplugging the SGPIO cable going to the SATA backplane results in the +5V rail voltage dropping to 0V, which indicates that the voltage leakage is exclusively coming from the SGPIO and SATA backplane. Finally, make sure that the +5V rail voltage drops to 0V after going into ACPI S5 with this patch applied and the SGPIO cable connected. Change-Id: Ic872903d5fcdd1c17e02b4c06d5ba29889fbc27d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66616 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-10-07util/coreboot-configurator: Update the READMESean Rhodes
Update the README with new instructions for Debian 11 and MX Linux. Also add the build dependencies. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I6942b9532e8d82f7fc5d6455c96913bcba6e983e Reviewed-on: https://review.coreboot.org/c/coreboot/+/65350 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-10-07soc/intel/apollolake: Add UFS InterruptSean Rhodes
According to Intel document number 336561, GLK has UFS (0x1d), so add the PCI interrupt. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I68bac590bd1a9a0b8213440e882c8f431f06c95f Reviewed-on: https://review.coreboot.org/c/coreboot/+/67680 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-07soc/intel/apollolake: Remove SD Card interrupt for GLKSean Rhodes
According to Intel document number 336561, G, SD Card (0x1b) does not exist on GLK, so remove it. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I6921fc3db430c76ec54cf832ce51c627a507385c Reviewed-on: https://review.coreboot.org/c/coreboot/+/67679 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-07mb/siemens/mc_ehl2: Use preset driver strength for SD-CardMario Scheithauer
The intention of predefining driver strength is to avoid that the OS SD-Card driver changes this setting. Change-Id: I02fdac94462da1cd77f8dc972faf16f28d94c946 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68166 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-10-07soc/intel/ehl: Set Ethernet controller to D0 power stateMario Scheithauer
To be able to change the MAC addresses, it is necessary that the controllers are in D0 power state. As of FSP MR3, Intel has set the controllers to D3 power state at the end of FSP-S TSN GbE initialization. This patch sets the state back to D0 before the programming of the MAC addresses. Test: - Build coreboot with FSP MR4 for mc_ehl2 mainboard - Boot into Linux and check MAC addr via 'ip a' Change-Id: I4002d58eb4332ba45c35d07820900dfd2c637f21 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67976 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-10-07util/inteltool: Add support for Alderlake P in inteltoolKacper Stojek
TEST=Dump registers on Clevo NS70PU with Intel® Core™ i7-1260P Document number: 626817, 630094, 655258 Change-Id: I2ba4ef7eee33d4dd762a05dd755de5e4d2e566dd Signed-off-by: Kacper Stojek <kacper.stojek@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66825 Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-07mb/google/nissa/pujjo: Change TPM I2C freqeuncy to 1 MHzLeo Chou
Change the TPM I2C freqeuncy to 1 MHz for pujjo. BUG=b:249953707 TEST=On pujjo, all timing requirements in the spec are met. Frequencies: pujjo - 987.80 kHz Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Change-Id: If99b5022a9b67e9c63c440a1e398d56bb2c467e2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68098 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-10-07mb/google/nissa/var/yaviks: Config I2C frequencyWisley Chen
Update parameters for all I2C devices. After applied this patch, the measured the I2C frequency meets spec BUG=b:249953708 TEST=FW_NAME=yaviks emerge-nissa coreboot flash and measure the all I2C devices 1. I2C0 (TPM): 980.6 Khz 2. I2C1 (TouchScreen); 392.6 Khz 3. I2C3 (Audio): 394.9 Khz 4. I2C5 (Touchpad): 391.6 Khz Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: I33c2891f17bc3c572bbfcbf30bbbdef9eb850ce7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68082 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-10-07soc/amd/{CZN,MDN,PCO}: Fix building with only single RW regionMatt DeVillier
apu/amdfw_a was only getting added to CBFS when VBOOT_SLOTS_RW_AB was selected, but needs to be added in the RW_A only case as well (VBOOT_SLOTS_RW_A). Since VBOOT_SLOTS_RW_AB selects VBOOT_SLOTS_RW_A, we can guard amdfw_a and _b separately and both will be added in the RW_AB case. TEST=build google/zork with VBOOT_SLOTS_RW_A or VBOOT_SLOTS_RW_AB selected, ensure amdfw_a and amdfw_b are added to correct CBFS regions as appropriate. Change-Id: Ic8048e869d7449eeb1ac10bfec4a5646b848d6a8 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68126 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-10-07soc/amd/{stoney,picasso}/Kconfig: Fix guarding of amdfwMatt DeVillier
apu/amdfw should be restricted to the RO region only when building with VBOOT + any RW region (RW_A or RW_A + RW_B); it is not tied to ChromeOS in any way. Fix guarding to match newer AMD platforms (eg, CZN/MDN). TEST=build google/zork without CHROMEOS, with VBOOT_SLOTS_RW_A Change-Id: I32d7fa7a4b3d41107cfdba96128a4a75f7066c6f Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68125 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-10-07MAINTAINERS: Update maintainers for several Google projectsTarun Tuli
Signed-off-by: Tarun Tuli <taruntuli@google.com> Change-Id: I973b0abf8a82189df1495e3bcd9bae452a5be827 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67289 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2022-10-07soc/intel/alderlake: Support Raptor Lake VR Fast VMODEJeremy Compostella
RaptorLake introduces the support of the Voltage Regulator Fast Vmode feature. When enabled, it makes the SoC throttle when the current exceeds the I_TRIP threshold. This threshold should be between Iccmax.app and Iccmax and take into account the specification of the Voltage Regulator of the system. This change provides a mean to: 1. Enable the feature via the `vr_config->enable_fast_vmode'. If no I_TRIP value is supplied FSPs picks an adapted I_TRIP value for the current SoC assuming a Voltage Regulator error accuracy of 6.5%. 2. Set the I_TRIP threshold via the `vr_config->fast_vmode_i_trip' field. These new fields are considered independent from the other `vr_config' fields so that the board configuration does not have to unnecessarily supply other VR settings to enable Fast VMode. Information about the Fast VMode Feature can be found in the following Intel documents: - 627270 ADL and RPL Processor Family Core and Uncore BIOS Specification - 724220 RaptorLake Platform Fast V-Mode - 686872 RaptorLake Lake U P H Platform BUG=b:243120082 BRANCH=firmware-brya-14505.B TEST=Read I_TRIP from the Pcode and verify consistency with a few `enable_fast_vmode' and `fast_vmode_i_trip' settings. Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Change-Id: I313acf01c534d0d32620a9dedba7cf3b304ed2ee Reviewed-on: https://review.coreboot.org/c/coreboot/+/66917 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-07mb/google/skyrim: Override SPI flash bus speedKarthikeyan Ramasubramanian
Add configuration to bump up the SPI flash bus speed from 66 MHz to 100 MHz starting the board version where required schematics update is done. BUG=b:245949155 TEST=Build and boot to OS in Skyrim with 100 MHz SPI bus speed. Perform warm and cold reboot cycles for 100 iterations each. Observe that the boot time improved by ~115 ms compared to 66 MHz SPI flash bus speed. At 66 MHz: 508:finished loading body 538,319 (83,806) 11:start of bootblock 1,196,809 (624,777) 14:finished loading romstage 1,236,905 (39,163) 970:loading FSP-M 1,237,056 (37) 15:starting LZMA decompress (ignore for x86) 1,237,073 (17) 16:finished LZMA decompress (ignore for x86) 1,358,937 (121,864) 8:starting to load ramstage 2,010,304 (0) 15:starting LZMA decompress (ignore for x86) 2,010,312 (8) 16:finished LZMA decompress (ignore for x86) 2,067,181 (56,869) 971:loading FSP-S 2,078,232 (7,999) 17:starting LZ4 decompress (ignore for x86) 2,078,253 (21) 18:finished LZ4 decompress (ignore for x86) 2,084,297 (6,044) 90:starting to load payload 2,316,933 (5) 15:starting LZMA decompress (ignore for x86) 2,316,947 (14) 16:finished LZMA decompress (ignore for x86) 2,339,819 (22,872) Total Time: 2,464,338 At 100 MHz: 508:finished loading body 515,118 (59,364) 11:start of bootblock 1,115,043 (566,110) 14:finished loading romstage 1,146,713 (29,697) 970:loading FSP-M 1,146,865 (38) 15:starting LZMA decompress (ignore for x86) 1,146,881 (16) 16:finished LZMA decompress (ignore for x86) 1,249,351 (102,470) 8:starting to load ramstage 1,900,568 (1) 15:starting LZMA decompress (ignore for x86) 1,900,576 (8) 16:finished LZMA decompress (ignore for x86) 1,956,337 (55,761) 971:loading FSP-S 1,967,357 (7,930) 17:starting LZ4 decompress (ignore for x86) 1,967,377 (20) 18:finished LZ4 decompress (ignore for x86) 1,972,925 (5,548) 90:starting to load payload 2,205,300 (6) 15:starting LZMA decompress (ignore for x86) 2,205,313 (13) 16:finished LZMA decompress (ignore for x86) 2,227,087 (21,774) Total Time: 2,349,804 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I5e8db22151fbc2db1f9e81b3644338348160736d Reviewed-on: https://review.coreboot.org/c/coreboot/+/68116 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com>
2022-10-06smbios: Add API to generate SMBIOS type 28 Temperature ProbeErik van den Bogaert
Based on DMTF SMBIOS Specification 3.5.0 Signed-off-by: Erik van den Bogaert <ebogaert@eltan.com> Change-Id: I710124ca88dac9edb68aab98cf5950aa16c695d3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67926 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-06treewide: use predicate to check if pci device is on n-th busFabio Aiuto
use function to check if pci device is on a particular bus number. TEST: compiled and qemu run successfully Signed-off-by: Fabio Aiuto <fabioaiuto83@gmail.com> Change-Id: I4a3e96381c29056de71953ea2c39cd540f3df191 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68103 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-06treewide: use predicates to check for enabled pci devicesFabio Aiuto
use functions to check for pci devices instead of open-coded solution. TEST: compiled and qemu run successfully Signed-off-by: Fabio Aiuto <fabioaiuto83@gmail.com> Change-Id: Idb992904112db611119b2d33c8b1dd912b2c8539 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68102 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-06include/device/device_util.c: add predicates for pci devicesFabio Aiuto
add functions to check whether a device is enabled pci device or a pci device on a specific bus number. TEST: compile and qemu run successfully Signed-off-by: Fabio Aiuto <fabioaiuto83@gmail.com> Change-Id: I3257c8404017372f6cdd9f6cf9453502447343a0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68101 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-06mb/google/brya/var/mithrax: adjust I2C5 times for TPJohn Su
This change updates scl_lcnt, scl_hcnt, sda_hold value for I2C5 to follow I2C specification. I2C_TCHPAD_SCL high period time is from 0.53 us to 0.6952 us. I2C_TCHPAD_SDA hold time is from 0.13 us to 0.4623 us. BUG=b:249031186 BRANCH=brya TEST=EE check OK with test FW and TP function is normal. Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: I5977f0dbba8924cc8a1c72c36358d6ba6f2de940 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67920 Reviewed-by: Ricky Chang <rickytlchang@google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
2022-10-06mb/google/nissa/pujjo: Tuning eMMC DLL value for eMMC initialization errorLeo Chou
Configure eMMC DLL tuning values for Pujjo board. BUG=b:241854926 TEST=Use the value to boot on Pujjo successfully. Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Change-Id: Ic36c817fa546741e394668297ca43db3a45ee105 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68095 Reviewed-by: Reka Norman <rekanorman@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-06mb/lenovo/t440p: Enable PCI 00:01.1 bridge for dGPUNico Huber
An optional dGPU can be connected to the second PEG bridge: -[0000:00]-+-00.0 Intel Corporation Xeon E3-1200 v3/4th Gen Core Processor DRAM Controller +-01.0-[01]-- +-01.1-[02]----00.0 NVIDIA Corporation GK208M [GeForce GT 730M] It's possible that the 01.0 bridge is never populated, but we have to leave it on anyway so 01.1 can be enumerated. Change-Id: Ieab7a7bf3b31b4ee9d9f12b5d827d866c87356e1 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68099 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-06mb/kontron/bsl6: Set board type to mobile for memory configNico Huber
Given the embedded nature, the Halo SKU, SO-DIMMs and 1 DIMM per channel, `mobile` seems to come closest. Change-Id: Ia27f1e4dec0a0d06be3d8c08bfe82becd41a2149 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67399 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-06mb/google/nissa/var/pujjo: Disable stylus GPIO pins based on fw_configLeo Chou
BUG=b:250470706 TEST=Boot to OS on pujjo and check that stylus GPIO are configured based on fw_config. Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Change-Id: I4218748cb06426a918d89f688599c652062ac78c Reviewed-on: https://review.coreboot.org/c/coreboot/+/68075 Reviewed-by: Reka Norman <rekanorman@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-06soc/intel/apollolake/acpi: Add PCIEXBAR to MCHCSean Rhodes
The values in this patch were found in the following datasheets: * 334819 (APL) * 336561 (GLK) Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I14c5933b9022703c8951da7c6a26eb703258ec37 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66230 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>