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2014-05-23vendorcode/intel/fsp/rangeley: remove extra fileMartin Roth
This is an extra file that is included in the Intel GSP release. It's got a coreboot header on it, isn't used, and looks very platform specific. I'm not sure where it belongs, but it doesn't belong in vendorcode. I've sent the contacts at Intel an email letting them know that this file should probably be removed from their FSP release and is getting removed here. Change-Id: I5ac6649235846ce5716bb180af29a5e422f4cce3 Signed-off-by: Martin Roth <gaumless@gmail.com> Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/5809 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-05-23drivers/pc80/Kconfig: Revert PS/2 initialization defaultsPatrick Georgi
Remove the inconsistent behaviour based on unrelated configuration: PS/2 init is now always enabled. This can change once we find a better approach. Change-Id: Ia8d55032f0e5eca0bf82d77df7dab95bcb2b353a Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/5634 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Peter Stuge <peter@stuge.se>
2014-05-23mainboard/google/peppy Fix usage of GNU field designator extensionEdward O'Callaghan
Following the reasoning in, 8089f17 mainboard/lenovo/x230 Fix usage of GNU field designator extension In C99 we defined a syntax for this. GCC's old syntax was deprecated. Change-Id: Idd7305cb34be77894ca4b6062bc0a2dc61126347 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5822 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-23mainboard/google/parrot Fix usage of GNU field designator extensionEdward O'Callaghan
Following the reasoning in: 8089f17 mainboard/lenovo/x230 Fix usage of GNU field designator extension In C99 we defined a syntax for this. GCC's old syntax was deprecated. Change-Id: I5be77fe6670601e103260077fae07a5b9fd41f1d Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5821 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-23payloads/coreinfo/multiboot_module.c: Trivial fix indentsEdward O'Callaghan
Stylistic fix-up's. Change-Id: I0cad7c860280d0d8dcb16d052846c72f690e2b65 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5731 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-05-23abuild: make build directory configurable with a variablePatrick Georgi
Allow overriding the build directly (default: coreboot-builds) using the COREBOOT_BUILD_DIR variable, in addition to setting it through the -o parameter. This helps with build nodes where jenkins wants to run the same command everywhere but allows different environment variables. Change-Id: If907897cf6ac01caa7d1e4b51aad4c005356bc5b Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/4543 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-05-23abuild: update version and copyrightPatrick Georgi
Enough changed to warrant a new version, date, and copyright. Change-Id: Ia099cd4fec3b05efc3f8bac09d38baede1c719e0 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/5806 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-05-23abuild: allow build results outside the source treePatrick Georgi
A reasonable configuration that minimizes disk traffic could be $ abuild -o /tmp/abuild-$$ -z Change-Id: Ic91798af7e799a40a77025e09a6078ea6758cdac Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/5805 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-05-23abuild: allow deleting the work directories immediatelyPatrick Georgi
This is useful on pure build nodes that don't care for object files, just for a build log and success flag. Change-Id: Ida65d4e41652af0f1b7255309aec2eeb6ef5c9ef Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/5804 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-05-23build: allow obj=/absolute/pathPatrick Georgi
This allows moving the build tree outside the source tree. Change-Id: I97882c4820d2c962c27bf8d50378e64016ce5790 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/5803 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-05-23northbridge/amd/amdmct: Incorrect usage of logical over bitwise andEdward O'Callaghan
Small mix up of logical/bitwise logical and operation. Spotted by Clang. Change-Id: I2c2256b9b2f2b6ca627914118c745f579555acc9 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5820 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-05-23northbridge/amd/amdmct: Superfluous parenthesis in if-statementsEdward O'Callaghan
Remove superfluous parenthesis found in some if-statements, spotted by Clang. Change-Id: I98d2bf6b408caf320c5bcc8adb23d621b182976b Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5817 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-05-22southbridge/amd/cimx/sb700: Unused func smbus_delay()Edward O'Callaghan
Spotted by Clang. Change-Id: Ie4bed914ab694f4e96155140b8b54b6eb96d70d7 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5819 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-05-22vendorcode/amd/agesa/f*: Fix typo in header guardsEdward O'Callaghan
_CPU_L3_FEATIRES_H -> _CPU_L3_FEATURES_H Spotted by Clang Change-Id: I1eabebffc7fd5e4f37b28dabcd28984bed64acd8 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5818 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-05-22northbridge/amd/amdmct/mct: Initialize variables at the eolEdward O'Callaghan
Spotted by Clang Change-Id: Idada98b7863ef986021943cf3ddb92d2f035e3e1 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5816 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-05-22southbridge/amd/sb700/smbus.c: Unused func smbus_delay()Edward O'Callaghan
Spotted by Clang Change-Id: I0f04c380b5ada28fb900710facc293edd65ac177 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5815 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-05-22device/pci_ids.h: defines for new Intel LPC devicesMartin Roth
Add defines for the Cave Creek and Rangeley LPC devices. These chipsets will be added shortly. This file is outside of any of the directories that will be touched by those additions, so it's getting changed in its own commit. Change-Id: Ia829282b2ad67eef09689858500bc7f93a1cd05b Signed-off-by: Martin Roth <gaumless@gmail.com> Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/5810 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-22x86/include/arch/acpi.h: remove incorrect semicolonMartin Roth
The semicolon really shouldn't be in the include... Change-Id: I90a0f516857365fddd21311cd703132af8d51007 Signed-off-by: Martin Roth <gaumless@gmail.com> Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/5808 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-21device_romstage: Add a way to move to the next deviceMartin Roth
When trying to loop through all the devices in romstage, there was no function to just go from one to the next. This allows an easy way to go all the way down the chain of devices. Change-Id: Id205b24610d75de060b0d48fa283a2ab92d1df0a Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/5732 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-05-21amd/agesa/*/gcc-intrin.h: Invaild inline asmEdward O'Callaghan
The 'm' (a memory reference) constraint makes little sense here since we are talking about a fs relative read, rather 'ir' (immediate or register) constraint is more sensible. N.B. The 'p' constraint allows anything which fits the form of an address calculation where the 'ir' constraint is just a register /xor/ immediate. Hence would produce better code here however, unfortunately, clang does not currently support it properly. The %b and %w constraints are also redundant and only hide errors. The functions writefsword() and writefsdword() should use ir instead of iq. iq is unnecessarily restrictive (it is only required for writing bytes). The cld in stosb is redundant (and the constraints are unnecessarily complicated). Note that The ABI guarantees that the direction flag is cleared. i.e. eax, ecx, edx are caller-saved, returned value in eax, eax+edx, st0, yaddayadda, direction flag cleared. In fact bad things can happen if you set it in some asm and do not clear it until the end of the asm. Line wrap these extraneously long lines found with these particular functions. Many thanks to Christoph Mallon <christoph.mallon@gmx.de> from #llvm for helping me with this. Change-Id: Iaf3ad65791640e1060a2029e7ebb043f57b338a9 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5758 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-05-21amd/agesa/f1?/Lib/amdlib.c: Integer overflow in loop constructEdward O'Callaghan
The semantics of this loop relies on an integer overflow in Index >=0 that implies a return value of (UINT8)-1 which around wraps to 0xFF, or VOLT_UNSUPPORTED. Change-Id: I44d68973d0a80093350b2a8a4d3b46bfbb57917a Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5801 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-05-21mainboard/ibase/mb899: Sanitize headersEdward O'Callaghan
These are not local headers. Change-Id: Ie0b0a682565a08dbfa089986dc7860fdb0846949 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5796 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-05-21vendorcode/amd/agesa: unsigned enum is strictly positiveEdward O'Callaghan
The typedef'ed BIT_FIELD_NAME enum is type unsigned. The parameter 'FieldName' is decleared with type BIT_FIELD_NAME and thus the redudant comparison of unsigned enum expression >= 0 is always true. BIT_FIELD_NAME is declared in vendorcode/amd/agesa/f14/Proc/Mem/mm.h Change-Id: Id2f03596c44b68e861e939f3528256d4b08c45ce Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5757 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-05-21amd/cimx/sb?00/SATA.c: Integer overflow in loop conditionEdward O'Callaghan
The conditional comparison in the for-loop construct with the constant 300000 has an index incrementor of type 'UINT16' (aka 'unsigned short') which is always true. Change-Id: I932c168742163be4038728fb40833231a447fa78 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5799 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-05-21baytrail: Fix some minor errors in FSPDavid Hendricks
- Duplicate declaration of GetFspReservedMemoryFromGuid - Corrupt line that was only compiled for a southbridge that no board in coreboot currently uses. (thanks for Mike Hibbett <mhibbett@ircona.com> for pointing this out) Change-Id: I847e807272acbaa93c87a89c0d2f94829c9121e6 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/5798 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-05-20mainboard/ibase/mb899: Indent devicetree.cbEdward O'Callaghan
Change-Id: I29037c322dac5ed9ebc36b95bc1981acf21e5bd0 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5778 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-05-20drivers: Drop GbE stub driversEdward O'Callaghan
These NIC stub drivers were to initialize the Gigabit Ethernet adapters just enough to keep coreboot from trying to execute an option ROM. However this is no longer required as non-VGA option roms are not ran; See: b32816e Remove PCI_ROM_RUN option Change-Id: Idc44619767c631c5fcf550a5948c8947bde5e218 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5777 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-05-19vendorcode/amd/agesa: Logic typo in GfxPowerPlayLocateTdpEdward O'Callaghan
The function GfxPowerPlayLocateTdp() sets MinDeltaSclk to a maximum sentinel value and checks DeltaSclk in a loop to minimize MinDeltaSclk. However, MinDeltaSclk incorrectly self-assigns. Change-Id: Id01c792057681516bba411adec268769a3549aa8 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5752 Tested-by: build bot (Jenkins) Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
2014-05-19amd/agesa: Implicit assigment between enum without castEdward O'Callaghan
Change-Id: I31632948ce69b2d1ff63b6c920016ed6fdf9e2f8 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5760 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-05-19amd/agesa/f*: Strip tailing white-spaces from gcc-intrin.hEdward O'Callaghan
Change-Id: I1d801b9d8387e267feeb95563e55910b30ebbc34 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5790 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-05-19via/vx900: Remove GFXUMA and use of related global variablesKyösti Mälkki
Remove global variables uma_memory_base and uma_memory_size from builds with via/vx900 northbridge, as these variables can be kept within the chipset. Change-Id: I9f8aea4836d81e704eae6a0f2cefc7fd4586b8b8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5721 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-19intel: Remove GFXUMA and related global variablesKyösti Mälkki
Remove use of global variables uma_memory_base and uma_memory_size from builds with Intel northbridges, as these variables can be kept within the chipset or even as stack locals. Intel platforms have no functional implemenation for option GFXUMA. If we did implement some choice between external and integrated graphics, it needs to be named in less obscure fashion. Change-Id: I12f18c4ee6bc89e65a561db6c2b514956f3e2d03 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5720 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-19Add guard for UMA globalsKyösti Mälkki
We no longer need these globally. Guard them so we get to declare static replacements at few locations until complete removal. Change-Id: Ie33e2a680fc9bbb7e28c8fbe17e5181e626736a5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5718 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-19build: use CFLAGS_* in more places where they're neededPatrick Georgi
After moving out -m32 from CC_*, 64bit compilers need CFLAGS_* in more places to handle everything in 32bit as appropriate. Change-Id: I692a46836fc0ba29a3a9eb47b123e3712691b45d Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/5789 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-19vendorcode/amd: kill some intermediate variables in build systemPatrick Georgi
They don't exactly add clarity, but increase the risk they're used at some obscure place. Change-Id: Ic74f72dae3f9b7eb2343cb5c51bc44c888e1276c Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/5787 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-19build: move include paths where they belongPatrick Georgi
They're _not_ part of the compiler binary, so they have no place in $(CC_*) Change-Id: I1e1c3c0be6f75629450a824ea834e1614d48ed9b Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/5785 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-19agesa: drop non-existing search pathsPatrick Georgi
With the upcoming CC/CFLAGS/CPPFLAGS split, romcc gets more CPPFLAGS, and it's picky about directories actually existing. Change-Id: Ib9c525296e5be0c8ace935ab8096bc98206cbcc1 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/5784 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-19fix printk typesPatrick Georgi
Some size_ts were considered long int and some compilers are picky about that. Change-Id: I671daa18eb3bfa2a7defc120e77bbb1ef72bd417 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/5788 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-19Add aliases for Chromebooks in board_infoKyösti Mälkki
This defines new board_info entry 'Vendor name' to be displayed in place of, or in addition to, the CONFIG_VENDOR string 'Google'. Also flag these as flashrom accessible SPI without socket. Instructions to disable flash write-protection can be found at Chromium developer documentation. Change-Id: I69791a091417a80d01e0ba2c6462417730a07be0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5750 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-19Board-status: Add second vendor lineKyösti Mälkki
Change-Id: I8a962f323cbc6347f266a188a07f870ce174d339 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5751 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-19LiPPERT: Add aliases for board_status wikiKyösti Mälkki
While at it, fix frontrunner-af board URL. Change-Id: I3b631830d679abc20f8a72411f2402689d9f9aac Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5706 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
2014-05-19abuild: Only build boards with KconfigPatrick Georgi
We have dupes in the tree for aliases, board variants and the like, for board-status reporting purposes. But we don't need to build all of them. Change-Id: Ic1c6415568800350bdc0db97471e3875d9eac98c Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/5776 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-18device/oprom/yabel/vbe.c: Avoid unused func warnEdward O'Callaghan
Change-Id: Idd74893c1fc3d0818d00c1f727c9fdc27168af0c Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5782 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-05-18drivers/spi/sst.c: Remove unused func to_sst_spi_flash()Edward O'Callaghan
Trips up clang builds with a warn treated as error. Change-Id: I9c0e2930ba8a60c7ad6063e9826b1b8638185505 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5779 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-05-17lenovo/t60: Enable dock serial port when undocked and redockedDamien Zammit
When the system is started with dock, the serial port works. As soon as the laptop is undocked and redocked, the serial port no longer works. See below superiotool dump snippet: Upon bootup: SIO @ 0x2e LDN 0x03 (COM1) idx 30 60 61 70 71 74 75 f0 val 01 03 f8 04 03 04 04 02 Redocked: SIO @ 0x2e LDN 0x03 (COM1) idx 30 60 61 70 71 74 75 f0 val 00 03 f8 04 03 04 04 02 Since the function dock_connect is executed every time the dock is reconnected, starting without a dock and then attaching it to a dock is now also fixed. Change-Id: Ibd97589a8c743673a55e382a5db2ba62656c595e Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: http://review.coreboot.org/5761 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-17build: re-enable ccache supportPatrick Georgi
The ccache support was mostly disabled because it didn't hook onto most compilers anymore. Caveat: ccache and scan-build don't work together since scan-build doesn't like arguments in its compiler command line (eg. "ccache gcc"). Change-Id: I7c1c6e22cb662f2b08e774ea484ac1c412fdd2db Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/5775 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-17build: make scan-build work againPatrick Georgi
This drops the scan-build related Kconfig options since it's now possible to simply run scan-build [-o outdir] make and get coreboot built with its report. There's also no inner make process anymore, and the way things work should be clearer now. Also adapt abuild to this new reality. Change-Id: I03e03334761ec83f718b3235ebf811834cd2e3e3 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/5774 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-17build: allow romcc to be wrappedPatrick Georgi
Allow ccache and scan-build to wrap romcc. This works a bit different from the other compilers because we only define it later. Change-Id: I3adce91d3dde9dd50aa6a2baad5b457744f35575 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/5773 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-17abuild: replace hardcoded values by their variablesPatrick Georgi
Some coreboot-builds/ and makes made their way into abuild. Stop them. Change-Id: I5784e1fd623ada30e2fadcc74a7da3ee75c5ee96 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/5772 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-17build: remove call to missing functionPatrick Georgi
set_stage_libgcc never existed in our tree. Change-Id: I864fc683dd7b89a030daf05eafb9624ce828cb72 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/5770 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-17build: break compiler flags out of $(CC)Patrick Georgi
Having more than the executable in $(CC) only leads to trouble in a number of situations. Change-Id: I7642ca4068b3a3bd5798219d74de9e0eb85bb4e5 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/5769 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-17build: don't call $(CC) -print-libgcc-file-name twicePatrick Georgi
Change-Id: Iaeeb8fc58e06c98273520e79999737da9ff3f872 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/5768 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-17build: kill one indirectionPatrick Georgi
No need to first define X86_32 and then replace every single use of it with its lower cased equivalent. Just start out with the lower case versions in the first place. Change-Id: I1e771ef443db1b8d34018d19a64a9ee489cd8133 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/5767 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-17build: get rid of a special casePatrick Georgi
Don't call things in xcompile i386 and in the buildsystem x86_32 and then bridge things so they match. just call it the same everywhere. Change-Id: Ieef5f03f7aafb0b0a606fbe5a2386e310d2b0e94 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/5766 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-17build: separate CPPFLAGS from CFLAGSPatrick Georgi
There are a couple of places where CPPFLAGS are pasted into CFLAGS, eliminate them. Change-Id: Ic7f568cf87a7d9c5c52e2942032a867161036bd7 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/5765 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-17build: CPPFLAGS is more common than INCLUDESPatrick Georgi
Rename INCLUDES to CPPFLAGS since the latter is more commonly used for preprocessor options. Change-Id: I522bb01c44856d0eccf221fa43d2d644bdf01d69 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/5764 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-17build: reduce duplication in payload adding rulesPatrick Georgi
They're all the same, so treat them that way. Change-Id: I8e3976df1e3a0f9dbcf1d5373611f6197bc9701b Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/5763 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-17libpayload: Fix to properly disable serial consoleKyösti Mälkki
With coreboot builds with serial console disabled, there is no CB_TAG_SERIAL entry in coreboot tables. We ended up with lib_sysinfo.serial == NULL and serial_hardware_is_present == 1. Change-Id: I9a2fc0b55bf77769f2f2bfbb2b5476bee8083f7d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5723 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-05-15xcompile: ABIs are really architecture specificPatrick Georgi
no need to test for i386-eabi or armv7a-elf Change-Id: Icbef5a64f5b793092ca0f94ee8f54bc896bf39ad Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/5746 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-05-15drivers/pc80/Kconfig: simplify PS/2 selection rulesPatrick Georgi
There's no need to state the dependency twice. Change-Id: Ia241d441211c6f476d0a6ed7589b038f7a220265 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/5633 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-05-15xcompile: break out big loop content into functionPatrick Georgi
Change-Id: Id98afa956a2af7113a6ef848b436d661a1fa39f2 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/5745 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-05-15xcompile: move tempfile cleanup closer togetherPatrick Georgi
Change-Id: I4fb3041d505402de3cbcd7ec079dde5e168a90cf Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/5744 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-05-15xcompile: actually use "special compile flags" ideaPatrick Georgi
xcompile used to test for special ARM flags - that were empty. Meanwhile, -Wa,--divide, which is only useful on i386-elf was tested for on arm and aarch64, too Change-Id: I1a5a1bc40fa1040d0939038b073aef31c72d0c6f Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/5743 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-05-15xcompile: fail earlier on missing host toolsPatrick Georgi
No need to test all the cross compiler things if there's no host compiler or iasl. Also test that the alternatives work, instead of assuming iasl or cc are in the path. Change-Id: I1d2293873f4bf1bb525d794851ec20adddb05ac6 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/5742 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-05-15xcompile: slightly refactor variable expansion magicPatrick Georgi
Change-Id: Iebe071c863c6c7139128a2ec59acfb9da0f83512 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/5741 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-05-15xcompile: use bashPatrick Georgi
I don't think all /bin/sh implement all features used in xcompile. Change-Id: Ida2a166242201ed0221316b123888127c83bf3c1 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/5740 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-05-15abuild: add -L|--clang to enable clang buildsPatrick Georgi
Change-Id: I11053456fd90cda07143b76de49c2804e38f06e0 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/5739 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-05-15baytrail: Add SOC thermal settingsDuncan Laurie
Apply the SOC thermal settings from DPTF reference code for SdpProfile=4 and adjust graphics PUNIT setting to match. BUG=chrome-os-partner:17279 BRANCH=baytrail TEST=boot on rambi and check for valid GPU power values from DPTF Change-Id: I59fc4b75b52084ebcc4c0556563afca0585ea6b8 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/182786 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5052 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-15baytrail: Enable PCIe common clock and ASPMDuncan Laurie
Enable the config options to have the device enumeration layer configure common clock and ASPM for endpoints. BUG=chrome-os-partner:23629 BRANCH=baytrail TEST=build and boot on rambi, check PCIe for ASPM and common clock: lspci -vv -s 0:1c.0 | grep LnkCtl: LnkCtl: ASPM L0s L1 Enabled; RCB 64 bytes Disabled- Retrain- CommClk+ lspci -vv -s 1:00.0 | grep LnkCtl: LnkCtl: ASPM L0s L1 Enabled; RCB 64 bytes Disabled- Retrain- CommClk+ Change-Id: I2477e3cada0732dc71db0d6692ff5b6159ed269f Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/182860 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5051 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-15baytrail: enable graphics turboAaron Durbin
Though the limited documentation indicates the default is 0 for the gfx_turbo_disable bit, in practice that isn't true. Knock down the gfs_turbo_disable bit to enable graphics turbo mode. BUG=chrome-os-partner:25044 BRANCH=baytrail TEST=Built and booted. Added debug code to output SB_BIOS_CONFIG. Noted that bit 7 was set to 0. Change-Id: I11210c6a0b29765cb709a54d6ebd94211538807b Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/182640 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/5050 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-15rambi: Add ACPI devices and interrupts for codec and ALSDuncan Laurie
The Codec and ALS both have interrupt sources that can be configured. The ALS kernel driver currently does not try to use it but the codec driver does for things like jack detect. ACPI Devices are added, but as with other ACPI devices the HID may need to be updated once more official strings are decided. BUG=chrome-os-partner:24380 BRANCH=baytrail TEST=manual: build and boot on rambi and check for functional lightsensor Change-Id: Ib51a2aaf32d5597926fcbe9183947e9ac53e1468 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/182366 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5049 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-15baytrail: use CPU_INTEL_TURBO_NOT_PACKAGE_SCOPEDAaron Durbin
On baytrail, it appears that the turbo disable setting is actually building-block scoped. One can see this on quad core parts where if enable_turbo() is called only on the BSP then only cpus 0 and 1 have turbo enabled. Fix this by calling enable_turbo() on all non-bsp cpus. BUG=chrome-os-partner:25014 BRANCH=baytrail TEST=Built and booted rambi. All cpus have bit 38 set to 0 in msr 0x1a0. Change-Id: Id493e070c4a70bb236cdbd540d2321731a99aec2 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/182406 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/5048 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-15baytrail: Add ACPI Device for XHCIDuncan Laurie
This will allow USB devices to wake the system (if 5V is not turned off) and the controller to enter D3 at runtime. (if autosuspend is enabled) BUG=chrome-os-partner:23629 BRANCH=baytrail TEST=build and boot on baytrail 1) with modified EC to leave 5V on in S3 ensure that waking from suspend with USB keyboard works. 2) with laptop-mode-tools usb autosuepend config updated see that device enters D3 at runtime when no external devices attached. Change-Id: Ia396d42494e30105f06eb3bd65b4ba8b1372cf35 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/182536 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5046 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-15rambi: Add ACPI table support for I2C devicesDuncan Laurie
In order to support probing I2C devices when the controller is in ACPI mode the mainboard needs to decalre them in the proper scope with the address/interrupt information. The touchpad devices are ATML0000/ELAN0000 and the touchscreen is ATML0001 so they can be distinguished in userland scripts based on ID. There is also a special "ISTP" node that indicates whether the devices is a touchpad (=1) or touchscreen (=0) in case this is useful to drivers. These names may not be final but they are a starting point and can be easily changed. Atmel devices also have a bootloader mode which needs to be declared as a separate device. Unfortunately it does not work as expected to have multiple I2cSerialBus() resources declared in a single device and have it select properly, even with the use of StartDependentFn(), so bootloader devices are declared separately. The original devices are left in \_SB scope and are only enabled if the I2C controllers are in PCI mode. The new devices are only enabled if the I2C controllers are in ACPI mode. BUG=chrome-os-partner:24380 BRANCH=baytrail TEST=manual 1) Ensure there is no change in functionality by default and that the devices are still probed by chromeos_laptop in the kernel. 2) Enable lpss_acpi_mode=1 in devicetree.cb and kernel changes to add _HID entries for devices in appropriate drivers. Ensure that the devices are probed successfully. Further changes are needed to the chromeos-touch-firmware scripts to load config and update firmware based on the new ACPI _HID entries. 3) Put touchpad in bootloader mode (by flashing bad firmware) and ensure that it is detected at address 0x25 and the firmware is able to be updated. Change-Id: I5b9b47ddc94474a677497271e963f62cb09438e0 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/182259 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5045 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-15baytrail: nvm: use proper types for checking eraseAaron Durbin
The current byte value was being converted to an int when checking against literal 0xff. As the type of the current pointer was char (signed) it was sign extending the value leading to 0xffffffff != 0xff. Fix this by using an unsigned type and using a constant type for expected erase value. BUG=chrome-os-partner:24916 BRANCH=baytrail TEST=Booted after chromeos-firmwareupdate. Noted that MRC cache doesn't think the erased region isn't erased. Change-Id: If95425fe26da050acb25f52bea060e288ad3633c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/182154 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/5044 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-15baytrail: mrc_cache: check region erased before erasingAaron Durbin
On a firmware update the MRC cache is destroyed. On the subsequent boot the MRC region was attempted to be erased even if it was already erased. This led to spi part taking longer than it should have for an unnecessary erase operation. Therefore, check that the region is erased before issuing the erease command. BUG=chrome-os-partner:24916 BRANCH=baytrail TEST=Booted after chromeos-firmeareupdate. Noted no error messages in this path. Change-Id: I6fadeb6bc5fc178abb0a7e3f0898855e481add2e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/182153 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/5043 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-15rambi: disable SERIRQ native functionalityAaron Durbin
Nothing can actually use this as the EC cannot speak using baytrail's SERIRQ protocol. Also, the voltage bridge is going away so nothing will be hooked up to it. Therefore disable this it. BUG=chrome-os-partner:24693 BRANCH=rambi TEST=Built and booted. Change-Id: I406bb9c227578ec0a75eaf67143b3b27cb7880ae Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/182082 Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/5042 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-14southbridge/amd/cimx/sb800: Unused func smbus_delay()Edward O'Callaghan
Change-Id: Icc12aafc1462c08bca77a1798d4fae86b8250708 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5748 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
2014-05-14mainboard/lenovo/t520: too many arguments to pc_keyboard_initEdward O'Callaghan
Fix build regression introduced in: a823f9b mainboard/lenovo: Add Lenovo Thinkpad T520 support Change-Id: I60d92f8cceda6427f43e6be9d78c2af82af4b061 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5738 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-14intel: Drop obsolete comments on MTRR usageKyösti Mälkki
Problem with UMA region allocation was fixed when MTRRs changed to use memrange implementation. Change-Id: I420dac30de2836a91596d81f88bb45b46f248532 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5719 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-05-13mainboard/lenovo: Add Lenovo Thinkpad T520 supportZaolin
Short list of known issues for this patchset: * Suspend/Resume - does not work * Combi pci card for SD/MMC card reader with IEEE1394 - not found * Shutdown - sometimes does not work as expected * At least mysterious harddrive i/o Change-Id: Iaba8d1f5e471cfeca20d82f4e1b416641e1f2ae9 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: http://review.coreboot.org/5672 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-05-13cpu/intel: Add CPU socket rPGA988BZaolin
Used by the Lenovo ThinkPad T520 Change-Id: I1009616cc4c18ebd0e3be7ceb50398617b49e3a3 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: http://review.coreboot.org/5671 Reviewed-by: Idwer Vollering <vidwer@gmail.com> Tested-by: build bot (Jenkins)
2014-05-13baytrail: add C0 microcode updateAaron Durbin
Include C0 microcode drop. BUG=None BRANCH=rambi,squawks TEST=Built. Booted B3 part. Change-Id: If454658235cd5a7b8640de0b3fa12dccddb0e9f6 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/182080 Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/5041 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-13baytrail: reboot with EC in S0 with no MRC cache and EC in RWAaron Durbin
This improves boot time in 2 ways for a firmware upgrade: 1. Normally MRC would detect the S0 state without an MRC cache even though it's told to the S5 path. When it observes this state a cold reset occurs. The cold reset stays in S5 for at least 4 seconds which is time observed by the end user. 2. As the EC was running RW code before the reset after firmware upgrade it will still be running the older RW code. Vboot will then reboot the EC and the whole system to put the EC into RO mode so it can handle the RW update. The issues are mitigated by detecting the system is in S0 with no MRC cache and the EC isn't in RO mode. Therefore we can do the reboot without waiting the 4 secs and the EC is running RO so the 2nd reboot is not necessary. BUG=chrome-os-partner:24133 BRANCH=rambi,squawks TEST=Booted. Updated firmware while in OS. Rebooted. Noted the EC reboot before MRC execution. Change-Id: I1c53d334a5e18c237a74ffbe96f263a7540cd8fe Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/182061 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/5040 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-13chromeec: add function to reboot on unexpected imageAaron Durbin
It's helpful to have a generic function that will tell the EC to reboot if the EC isn't running a specified image. Add that and implement google_chromeec_early_init() to utilize the new function still maintaing its semantics of if recvoery mode is enabled the EC should be running its RO image. There is a slight change in that no communication is done with the EC if not in recovery mode. BUG=chrome-os-partner:24133 BRANCH=rambi,squawks TEST=Built and boot with recovery request. Noted EC reboot. Change-Id: I22240f6a11231e39c33fd79796a52ec76b119397 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/182060 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/5039 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-13baytrail: dptf: Add disable trip point methodsDuncan Laurie
Added a method in each temp sensor to disable the aux trip points and then a wrapper function to call this method for each enabled temperature sensor. The event handler function is changed to not use a switch statement so it does not need to be serialized. This was causing issues with nested locking between the global lock and the EC PATM mutex. Some unused code in temp sensors that was added earlier is removed and instead a critical threshold is specified in _CRT. The top level DPTF device _OSC method is expanded to check for the passive policy UUID and initialize thermal devices. This is done for both enable and disable steps to ensure that the EC thermal thresholds are reset in both cases. Additionally the priority based _TRT is specified with TRTR=1. BUG=chrome-os-partner:17279 BRANCH=rambi TEST=build and boot on rambi, load esif_lf kernel drivers and start esif_uf application. Observe that temperature thresholds are set properly when running 'appstart Dptf' and that they are disabled after running 'appstop Dptf' Change-Id: Ia15824ca42164dadae2011d4e364b70905e36f85 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/182024 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5037 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-13rambi: dptf: Set critical thresholdsDuncan Laurie
Set critical temperature thresdholds to 70C. This will cause DPTF framework to shut down the system so it may need to be higher or lower but will need some testing. BUG=chrome-os-partner:17279 BRANCH=rambi TEST=build and boot on rambi, start DPTF framework and observe it using specified critical thresholds. Change-Id: Ibbf6d814295eb5ff006cb879676b7613f5eb56a3 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/182025 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5038 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-13chrome ec: Fix temperature calcualtion in PATx methodsDuncan Laurie
The PATx methods will be passed a temperature in deci-kelvin, so it needs to be converted back to kelvin before being sent to the EC. The PAT disable method is changed to take the temperature ID as an argument so individual sensors can be disabled. BUG=chrome-os-partner:17279 BRANCH=rambi TEST=build and boot on rambi, load esif_lf kernel drivers and esif_uf userspace application. Start and stop DPTF and see that temperature thresholds are set to sane values. Change-Id: Ieeff5a5d2d833042923c059caf3e5abaf392da95 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/182023 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5036 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-13chrome ec: call DPTF thermal threshold event handlerAaron Durbin
When an EC thermal event occurs call the DPTF thermal threshold event handler to handle notifications. Change-Id: Ica928790bb478fccf8a46afef4eb7800589518b2 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5726 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-13baytrail: Updates for DPTF ACPI frameworkDuncan Laurie
- Remove some unused functions from CPU participant that were confusing the userland component since the CPU does not have an ACPI managed sensor. - Guard the charger participant with an ifdef so it can be left out if not supported. - Use the EC methods for setting auxiliary trip points and for handling the event when those trip points are crossed. - Add _NTT _DTI _SCP methods for thermal sensors. I'm not clear if these are required or not but they seem to be expected by the other DPTF framework components. BUG=chrome-os-partner:17279 BRANCH=rambi TEST=build and boot on rambi and load ESIF framework Change-Id: I3c9d92d5c52e5a7ec890a377e65ebf118cdd7087 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/181662 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5028 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-13chrome ec: Update header and add functions to support DPTFDuncan Laurie
The EC now supports two auxiliary programmable trip points for thermal monitoring. These are expected to be used by DPTF and need to be exported. In order to support these the header was updated from the latest chrome ec source. BUG=chrome-os-partner:17279 BRANCH=rambi TEST=build and boot on rambi Change-Id: I257d910daac4e36280c0cecf4129381a32ffcb9a Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/181661 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5027 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-13rambi: Update the DPTF configurationDuncan Laurie
- Add passive thresholds for thermal participants - Disable the charger participant and remove from _TRT BUG=chrome-os-partner:17279 BRANCH=rambi TEST=build and boot on rambi and start ESIF framework Change-Id: Ie5917413aceadee6e39594257aaafb0bcb399d09 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/181663 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5029 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-13baytrail: don't SMI on tco timer firingAaron Durbin
The SMI on TCO timer timeout policy was copied from other chipsets. However, it's not very advantageous to have the TCO timer timeout trigger an SMI unless the firmware was the one responsible for setting up the timer. BUG=chromium:321832 BRANCH=rambi,squawks TEST=Manually enabled TCO timer. TCO fires and logged in eventlog. Change-Id: I420b14d6aa778335a925784a64160fa885cba20f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/181985 Reviewed-on: http://review.coreboot.org/5035 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-13baytrail: clear the pmc wake status registersAaron Durbin
The PMC in baytrail maintains an additional set wake status in memory-mapped registers. If these bits aren't cleared the device won't be able to go to S5 or S3 without being immediately woken up. Therefore clear these registers. BUG=chrome-os-partner:24913 BRANCH=rambi,squawks TEST=Ensured PRSTS bit 4 is cleared after a reboot and S3 and S5 work correctly. Change-Id: I356e00ece851961135b4760cebcdd34e8b9da027 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/181984 Reviewed-on: http://review.coreboot.org/5034 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-13baytrail: log reset, power, and wake events in elogAaron Durbin
When CONFIG_ELOG is selected the reset, power, and wake events are logged in the eventlog. BUG=chrome-os-partner:24907 BRANCH=rambi,squawks TEST=Various resets and wake sources. Interrogated eventlog to ensure results are expected. Change-Id: Ia68548562917be6c2a0d8d405a5b519102b8c563 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/181983 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/5033 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-13baytrail: snapshot power state in romstageAaron Durbin
The memory reference code doesn't maintain some of the registers which contain valuable information in order to log correct reset and wake events in the eventlog. Therefore snapshot the registers which matter in this area so that they can be consumed by ramstage. BUG=chrome-os-partner:24907 BRANCH=rambi,squawks TEST=Did various resets/wakes with logging patch which consumes this structure. Eventlog can pick up reset events and power failures. Change-Id: Id8d2d782dd4e1133113f5308c4ccfe79bc6d3e03 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/181982 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/5032 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-13baytrail: add cpuid for C0Aaron Durbin
The C0 part uses a new cpuid. BUG=None BRANCH=squawks,rambi TEST=None. Change-Id: Iddf1bc4d6f7bbec3ca92bff8edf613e00a4b4286 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/181980 Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/5031 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-13rambi: Move KBD_IRQ pin for Rambi 2.0 boardShawn Nematbakhsh
KBD_IRQ# is moved to GPIO SC101, with SC50 going back to its original SERIRQ function. Note that this change breaks Rambi 1.5 keyboard functionality. BUG=chrome-os-partner:24424 TEST=Manual on Rambi 2.0. Verify KB functions in OS with SC50 / SERIRQ KB interrupt toggling removed from EC code. BRANCH=Rambi, Glimmer, Clapper Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I3fa40441741ea9d52a6e2ff15925570510b5b82b Reviewed-on: https://chromium-review.googlesource.com/181757 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5030 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-13src/*: Remove the last remnants of struct keyboardEdward O'Callaghan
Change-Id: I7d0e8d2119a470428cfc01c0738b8988ab75ba2d Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5624 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-13superio/*: Remove redundant chip.h headerEdward O'Callaghan
Change-Id: If7141112ea67071ee05c52f455c3b2496aa7e17e Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5622 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>