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2024-06-18cpu/x86: Rename paging structure variables for claritySubrata Banik
The following variables have been renamed: * PDPE_table -> PDPT (Page Directory Pointer Table) * PDE_tables -> PDT (Page Directory Table) This change improves the consistency and clarity of the code as per AMD Architecture Programmer's Manual document. PML4 -> PDPT -> PDT -> 2MB Physical Page TEST=Able to build and boot google/rex64. Change-Id: Ib57d1d54c2c1f4fcce2315b508ed7643251a20c5 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83101 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
2024-06-18cpu/x86: Rename `PDE_table` to `PDPT` for 1 GiB page mappingsSubrata Banik
This commit fixes an incorrect variable name in the page table setup for 1 GiB pages. The label PDE_table was used when it should have been PDPT, as it represents a "Page Directory Pointer Table (PDPT)", not a "Page Directory Table (PDT) or PDE_Table". This change ensures correct nomenclature and consistency in the code. PML4 -> PDPT --------> 1GB Physical Page As per x86-64 specification, 1GB pages bypass the Page Directory Table (PDT) level of the page table hierarchy, mapping directly from the Page Directory Pointer (PDPT) Table to the physical page. Change-Id: I1e1064653a265215054f31f0e4e46bf8200ca471 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83100 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
2024-06-17Revert "mb/google/brox/var/lotso: enable CNVi bluetooth"Matt DeVillier
This reverts commit 0e0bc618e3ed1888ac140010057dc7485443c3c2. Reason for revert: Merged out of order, breaks tree Change-Id: I22bd85a2008db471177257a8b779c06898b1010c Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83105 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-06-17util/intelp2m: Add support for Emmitsburg macro generationFabian Meyer
Test: Generated GPIO for ASRock Rack SPC741D8-2L2T/BCM. Change-Id: Ib7ded47fb1c0b87ebb3cecaf3e41319ac552b797 Signed-off-by: Fabian Meyer <fabian.meyer@student.kit.edu> Co-authored-by: Yussuf Khalil <yussuf.khalil@kit.edu> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82204 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim <max.senia.poliak@gmail.com>
2024-06-17mb/google/nissa/var/riven: Disable storage devices based on fw_configDavid Wu
Disable devices in variant.c instead of adding probe statements to devicetree because storage devices need to be enabled when fw_config is unprovisioned, and devicetree does not currently support this (it disables all probed devices when fw_config is unprovisioned). BUG=b:337169542 TEST=Local build successfully. Change-Id: I3d71a35e9c0a33b72720b093b5a05eb69d5bb9f8 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83060 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-06-17mb/google/nissa/var/riven: Add initial override devicetreeDavid Wu
Add initial override devicetree for riven based on the latest schematic (Riven(ZDK)_MB_Proto_0601.pdf). 1. Add eMMC DLL tuning value (copy from craask) 2. Configure I2C frequency (copy from craask) 3. Add audio codec and speaker amp settings 4. Add Elan touchscreen settings (copy from craask) 5. Add WFC and usb settings (copy from craask) 6 Add Elan and Synaptics touchpad settings (copy from craask) 7. Add WIFI6(CNVI) and WIFI7(PCIE) configuration 8. Add LTE settings (copy from craask) BUG=b:337169542 TEST=Local build successfully. Change-Id: I1dda3557edb44dda9c3a1efaf98437352978561c Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83059 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-17util/autoport: Factor out yes/no prompt handlingAngel Pons
In preparation for introducing other yes/no prompts, factor out the logic into a common function. Change-Id: Iff1f0c6c665a5352013122fb791121a116c434f3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82402 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-06-17vc/amd/opensil/*/opensil.h: add missing device/device.h includeFelix Held
device/device.h provides the definition of struct device. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id1c3c09665e3eedec6055f4a0586016c5a5537bc Reviewed-on: https://review.coreboot.org/c/coreboot/+/83083 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-17mb/google/drallion: Set touchpad IRQs as wake sourceAngela Czubak
Elan touchpad driver in newer linux kernels (>= 5.15) no longer explicitly configures the touchpad as a wakeup source for devices not using device tree. It is now assumed this information should be extracted from ACPI, therefore we need to update drallion's devicetree so that the device regains its lost capability. TEST=update drallion FW and verify touchpad can cause wake up from suspend Change-Id: Iff21afda144cc11a013cb72816064df1c9eb21ae Signed-off-by: Angela Czubak <aczubak@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83070 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-17ec/google/chromeec/acpi/cros_ec: Ensure GpioInt and _PRW are mutually exclusiveCoolStar
Under Windows ACPI, GpioInt and _PRW must be mututally exclusive within the scope of a device, otherwise a BSOD occurs with an ACPI_BIOS_ERROR. To enforce this, only use _PRW when EC_ENABLE_SYNC_IRQ_GPIO is not set. If both EC_ENABLE_WAKE_PIN and EC_ENABLE_SYNC_IRQ_GPIO are set, then ensure that the GpioInt is flagged as ExclusiveAndWake (vs just Exclusive) so that the CREC device is still able to wake the device as needed. TEST=Build/boot google/{nocturne,frostflow} to Win11 w/ sync_irq_gpio and wake_pin both enabled. Change-Id: Ia59cce2ee12bfc8d3ac0173a7a4ec88d7079a958 Signed-off-by: CoolStar <coolstarorganization@gmail.com> Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82233 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-17mb/google/brya/base/nissa: Add default GMA panelMatt DeVillier
Enables ACPI brightness controls to be generated, and display brightness controls to be functional under Windows. TEST=build/boot Win11 on google/brya (craaskin), verify display brightness controls present and functional. Change-Id: I821b912cf52b5b89c5c9d831a5a15566b1b31639 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83071 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-06-17mb/google/brya: Add default ACPI brightness levelsMatt DeVillier
Boards using the brya baseboard already generate ACPI brightness controls via their use of the gfx/generic driver, but need the default brightness steps in order for display brightness control to be functional under Windows. TEST= build/boot Windows 11 on banshee, verify brightness controls functional. Change-Id: I03bb7a7309476839c49d2e862a036d9e89800605 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70372 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-17mb/google/brox/var/lotso: enable CNVi bluetoothJian Tong
Lotso's WIFI_BT is same design as brox, copy from brox. BUG=b:339612353 TEST=emerge-brox coreboot chromeos-bootimage and boot on Change-Id: I3946297db7f10a31570f773bdc5665f9f472c9fe Signed-off-by: Jian Tong <tongjian@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83053 Reviewed-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-06-17mb/google/trulo/var/orisa: Configure GPIO settingsAmanda Huang
Configure GPIOs according to schematic_20240607. BUG=b:333486830 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: I760a7a234df43db3a557b3be9e20ff7aa5f80b72 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82661 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-06-17mb/google/nissa/var/riven: Use unified AP FW for UFS/Non-UFS SKUsDavid Wu
This patch selects USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS which intends to achieve a unified AP firmware image across UFS and non-UFS skus. BUG=b:328580882 TEST=Local build successfully. Change-Id: Ifcee68a3492ab4606819de0be41701f803151f66 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83061 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-06-17mb/hp/snb_ivb_laptops/8560w: Move genx_dec settings into LPC scopeFelix Singer
Change-Id: I3cb0a39c83d6c92d604f1190538db88d97a81693 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83091 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
2024-06-16mb/hp/snb_ivb_laptops/8560w: Make use of device alias names in dtFelix Singer
Also, remove superfluous comments from devices which repeat their name. Change-Id: I26f7d5155f73bcf3cb3872f206c946da5029bda8 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83090 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
2024-06-16console: Only add non-stub code to romstage if SEPARATE_ROMSTAGE=yNicholas Chin
If both CONFIG_SEPARATE_ROMSTAGE and CONFIG_BOOTBLOCK_CONSOLE are not set, compilation will fail with errors indicating redefinitions of various console methods. When BOOTBLOCK_CONSOLE is not set, the __CONSOLE_ENABLE__ macro in include/console/console.h evaluates to zero when compiling the bootblock, resulting in various console methods being defined as stubs in the header. In a typical build with a separate bootblock and romstage, this will not cause a conflict as the non-stub definitions found in the console/*.c files are added conditionally to the bootblock depending on CONFIG_BOOTBLOCK_CONSOLE. When SEPARATE_ROMSTAGE is not set, the list of romstage objects gets added to the bootblock. Since the console sources were unconditionally added to romstage, the non-stub definitions were able to slip into the bootblock, causing a redefinition of the stubs. Avoid this by conditionally adding these sources to romstage depending on CONFIG_SEPARATE_ROMSTAGE. If SEPARATE_ROMSTAGE is set, the non-stub definitions are handled in the same way as they were before. If it is not set, the union of bootblock and romstage objects will only include the non-stub definitions based on CONFIG_BOOTBLOCK_CONSOLE, which uses existing console/Makefile.mk rules for the bootblock. TEST=qemu-i440fx builds successfully with all possible settings of CONFIG_SEPARATE_ROMSTAGE and CONFIG_BOOTBLOCK_CONSOLE. Change-Id: I59b3f0c52a4338b1573e0a647bc16cec4943fd7f Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83088 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-06-16soc/intel/alderlake: Use the RPL-P IoT FSP if desiredBenjamin Doron
This change also drops a duplicated config default line, which might be why this was omitted. Change-Id: I2b4c8b316adaadec3e49d5162b37b37629331b06 Signed-off-by: Benjamin Doron <benjamin.doron@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83086 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-16mb/gigabyte/ga-b75m-d3h: Make use of device alias names in dtFelix Singer
Also, remove superfluous comments from devices which repeat their name. Change-Id: Ia4a9a5c5897fe78a1243e4c42a7d8753cfe039c0 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83095 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-06-16mb/gigabyte/ga-b75m-d3h: Remove superfluous comments from dtFelix Singer
Change-Id: I20aca1a63306b0f39f97fd0b85d61cd957cb2150 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83094 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-16mb/gigabyte/ga-h61m-series: Make use of device alias names in dtFelix Singer
Also, remove superfluous comments from devices which repeat their name. Change-Id: I00473e44fce9197f818f5a8d131e9be31e8b0f69 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83093 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-16mb/gigabyte/ga-h61m-series: Remove superfluous comments from dtFelix Singer
Change-Id: I6026498c2853f5951227ace57b7198579f342647 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83092 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-16mb/dell/snb_ivb_latitude: Move E6430 USB config to devicetreeNicholas Chin
As of commit ee12634872 (nb/sandybridge,sb/bd82x6x: Configure USB from southbridge devicetree) and earlier commits, the USB port configuration should be located in the devicetree instead of the mainboard_usb_ports array, typically located in the boards early_init.c. TEST=USB ports still function; and the USBIRx, USBPDO, USBOCM1, and USBOCM2 RCBA registers in the inteltool dump did not change between an E6430 build before and after the sb/intel/bd82x6x that moved the usb config to the devicetree. Change-Id: Ia5aa03a5894a8ef29e863470925a223f52e0ab70 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83006 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-15.gitmodules: Use https to fetch modulesMartin Roth
Instead of using a relative path for the submodules, specify the sub- module URLs as pointing at coreboot.org, using https. While the relative path works well for coreboot itself, when the repo is forked and fetched from from anywhere other than review.coreboot.org, this file either needs to be modified, or all the submodules need to be checked out as well. Change-Id: Ie4f95c70a7f194d1073dc561c9f33dcc108060cc Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80552 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2024-06-15mb/hp: Add Elitebook 8560w as an HP Sandy/Ivy Bridge laptop variantIru Cai
The components listed in the documentation work in this port. The MXM structure of the vendor firmware is added, which is used by the VGA option ROM with int15h functions. Change-Id: I15181792b1efa45a2a94d78e43c6257da1acf950 Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39398 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-06-14util/inteltool: Add more Westmere/Ironlake device IDsAngel Pons
The host bridge PCI device ID can be changed by the firmware. There is no documentation about it, though. There's 'official' IDs, which appear in spec updates and Windows drivers, and 'mysterious' IDs, which Intel doesn't want OSes to know about and thus are not listed. For the sake of completeness, add the PCI device IDs for Clarkdale. Though coreboot only supports Arrandale, both of them are Ironlake. It is possible that the Management Engine handles changing the PCI device ID, which would not happen when using a broken ME firmware. Change-Id: I85a48fcf0e0e62f42fe147a5d4e2d557b2143e5b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60215 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-06-14util/smmstoretool: add uint64 data typeSergii Dmytruk
It's in particular useful for working with variables that contain 64-bit pointers, like CapsuleUpdateData* global variables defined by UEFI specification. Change-Id: I4b46b41cdc5f69d4ca189659bef1e44f64c0d554 Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82611 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
2024-06-14util/smmstoretool: fix uint{16,32} not being listed by helpSergii Dmytruk
These data types were added during review of CB:79080 but they weren't added to the help message. Change-Id: I6e79d65c80c292c3f5d2a2611e602db5cc6cf374 Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82610 Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maciej Pijanowski <maciej.pijanowski@3mdeb.com>
2024-06-14soc/intel/common/block: Move VTd basic definitions into header fileJincheng Li
TEST=Build and boot on intel/archercity CRB Change-Id: I4f9e606cf9ec01ec157ef4dd7c26f6b5eb88c7b7 Signed-off-by: Jincheng Li <jincheng.li@intel.com> Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82941 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-14mb/google/brya/var/xol: Turn off camera power during s0ixSeunghwan Kim
Turn off camera power during s0ix to improve power consumption. BUG=None BRANCH=brya TEST=built and verified GPP_A17 went to low during s0ix with a scope. [Measurement of s0ix power consumption - 1 hour avg] Before this: 301.4 mW After this: 299.8 mW Change-Id: Iae02d06e9f5a5988563b2b7ae36d153aecedb9d7 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83029 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: YH Lin <yueherngl@google.com>
2024-06-14mainboard/qemu-riscv: Get top of memory from device-tree blobAlper Nebi Yasak
Trying to probe RAM space to figure out top of memory causes an exception on RISC-V virtual machines with recent versions of QEMU, but we temporarily enable exception handlers for that and use it to help detect if a RAM address is usable or not. However, QEMU docs recommend reading device information from the device-tree blob it provides us at the start of RAM. A previous commit adds a library function to parse device-tree blob that QEMU provides us. Use it to determine top of memory in RISC-V QEMU virtual machines, but still fall back to the RAM probing approach as a last-ditch effort. Change-Id: I9e4a95f49ad373675939329eef40d7423a4132ab Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80363 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
2024-06-14tpm: Add Ti50 OpenTitan DID_VIDJett Rink
The OpenTitan HW implements the same firmware interface as the Ti50 H1D3C hardware variant; it just has a different DID_VID. Allow this new DID_VID to be recognized correctly. BUG=b:324940153 Change-Id: Iaacf6d88bc6067948756c465aac1cd8b24ecae1f Signed-off-by: Jett Rink <jettrink@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83033 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2024-06-14Documentation/index.md: Add coreboot's blob policyWerner Zeh
Every now and then we have discussions about blobs and how and if they should be introduced or handled. This patch adds a clear statement on the project's view on this topic to avoid unclear situations in the future. Change-Id: I20bc0b345c129ecd59aa1190647d89f6d4e07d46 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82086 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-06-13soc/intel/adl: Skip RW CBFS ucode update if RO is lockedSubrata Banik
This patch eliminates coreboot from loading microcode from RW CBFS (when the RO descriptor is locked, which indicates a fixed RO image) because the kernel can already patch the microcode on BSPs and APs while booting to OS. This may be a chance to lower the burden on the AP FW side because patching microcode on in-field devices is subject to firmware updates, which are rarely published and, if required, must go through the firmware qualification testing procedure (which is costly, unlike kernel updates for ucode updates). 1. The FIT loads the necessary microcode from the RO during reset. 2. Reloading microcode from RW CBFS impacts boot time (~60ms, core-dependent). 3. The kernel can still load microcode updates. ChromeOS devices leverage RO+RW-A/RW-B booting. The RO's microcode is sufficient for initial boot, and the kernel can apply updates later. BUG=none TEST=Verified boot optimization; in-field devices skip RW-CBFS microcode loading when RO is locked. Change-Id: I68953d45d3624aba0a3be28bc7b266b7621ddcc4 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82999 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-13soc/intel/apollolake: Add SoC-specific microcode update check for GLKMatt DeVillier
While both APL and GLK load the CPU microcode from FIT, only GLK supports the PRMRR/SGX feature. When this feature is supported, the FIT microcode load will set the msr (0x08b) with the patch id/revision one less than the revision in the microcode binary. This results in coreboot attempting (and failing) to reload the microcode again in ramstage. Avoid the microcode reload attempt for GLK by using a SoC- specific microcode update check which accounts for the off-by-1 when comparing versions. Implementation is based on the one used for SKL and CNL, but modified based on feedback in comments on Gerrit. TEST=build/boot google/reef (electro) and google/octopus (ampton), verify in cbmem console log that CPU microcode update in ramstage is skipped due to already being up to date, and that GLK uses the SoC-specific check and APL uses the non-specific/general one. Change-Id: Iab97f23d4388d5057797bb13f585db821c735bd0 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83037 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-13mb/dell/optiplex_9020: Fix integrated video port listMate Kukri
- Physical DP ports are DP2/DP3 (HDMI2/HDMI3 for DP++) - VGA port is Analog - DP1 is not connected Signed-off-by: Mate Kukri <kukri.mate@gmail.com> Change-Id: I8ed79167d5445d607acbee491c3382ff2585583f Reviewed-on: https://review.coreboot.org/c/coreboot/+/83049 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-06-13drivers/gfx/generic: Don't set DOD constraints when generating device addressMatt DeVillier
When dynamically generating the DOD (Display Output Device) device address (_ADR), don't set the DOD constraint flags; only set them when using the address value to generate the DOD package. This fixes ACPI brightness control functionality under Windows 11. Before: Name (_ADR, 0x80010400) After: Name (_ADR, 0x00000400) TEST=build/boot Win11 on google brya (banshee), ensure display brightness controls present and functional. Ref: ACPI Spec 6.5 Appendix B.6.1 - _ADR Change-Id: I1d710c6e55e6cb1d20d580bd784221ee1482b871 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83025 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-12libpayload/arch/x86: Fix register alignment in exception state dumpSubrata Banik
Removed an extra space character from the `printf` format string in `dump_exception_state` to ensure proper alignment of register values when printed during exception handling. BUG=b:336265399 TEST=Built and booted google/rex64 successfully. Verified correct alignment in exception state dumps. Change-Id: I8ff92775e32ee754967b1b0a43cd68971b4aadfc Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83047 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-12soc/sifive/fu540/chip.c: Add RAM resourcesMaximilian Brune
Add RAM region so that the payload can be placed in there without coreboot complaining that the payload doesn't target a RAM region. Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: Id07eae3560ce69cd8a6a695702fa0b4463c50855 Reviewed-on: https://review.coreboot.org/c/coreboot/+/81909 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-06-12configs: Add Hifive Unleashed config with OpenSBIMaximilian Brune
OpenSBI often breaks if you update it. This should ensure that jenkins keeps an eye on it. Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I2101b194bf0d74f4f444fba507e0294bddc746d3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/81859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-06-12soc/sifive/fu540/memlayout.ld: Enlarge OpenSBI regionMaximilian Brune
OpenSBI got bigger and doesn't fit anymore in 128K which causes coreboot to not compiler anymore because the region overlaps with ramstage This patch simply increases the size and uses the OpenSBI linker macro instead. Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: If1ccaafbf91dae986c470020faf9c0b4fba448e5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/83046 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-06-12mb/google/volteer/var/drobit: Update boot resolution in VBTMatt DeVillier
Enable the fixed boot mode option in the VBT and set it to 1920x1080, so that drobit boards equipped with 4K screens are legible at boot. TEST=build/boot drobit w/4K screen using edk2 payload, verify boot resolution set to 1080p and UEFI menus readable without a magnifying glass. Change-Id: If1f9e36d9bbdc2955ba890e2832aa64af9ba8f73 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83024 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-06-12mb/google/brox: Generate RAM IDsKun Liu
Generate RAM IDs for K3KL6L60GM-MGCT H9JCNNNBK3MLYR-N6E K3KL8L80DM-MGCU MT62F1G32D2DS-023 WT:C H58G56BK8BX068 BUG=b:333494257 BRANCH=None TEST=Run part_id_gen tool without any errors Change-Id: I7a240a263816193b9f3d418385c1673e9d3f89db Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83040 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Jian Tong <tongjian@huaqin.corp-partner.google.com>
2024-06-12mb/google/brox/var/lotso: Update gpio settingJian Tong
Based on lotso EVT schematics update gpio settings. GSPI0_CS0_L -> NF7 GSPI0_MISO -> NF7 GSPI0_MISO -> NF7 GPP_F18 -> EDGE_SINGLE BUG=b:333494257 TEST=emerge-brox coreboot chromeos-bootimage and boot on Change-Id: I12d84538566c4d51fe346eb5609e55d91ddafbea Signed-off-by: Jian Tong <tongjian@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83039 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
2024-06-12util/autoport: Update for recent USB developmentsKeith Hui
Update autoport for: 1. Commit ee126348726b ("nb/sandybridge,sb/bd82x6x: Configure USB from southbridge devicetree") 2. Commit 94625d2aae76 ("sb/intel/bd82x6x: Allow actual USBIRx values for native USB config") As a side effect of #2 above, no more (broken anyway) FIXME comment will be written for usb_port_config. Change-Id: I3b8f44d9de19a7446e2fbcbce1aab6ec6583ebe3 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82656 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-06-12mb/google/nissa/var/pujjoga: Add WWAN power off sequenceLeo Chou
Pujjoga support EM060 WWAN, use wwan_power.asl to handle the power off sequence. BUG=b:346479638 TEST=Build and boot on pujjoga Change-Id: I1273d09385c661835d741691b3c4af26e72a9f86 Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83042 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-12mb/google/nissa/var/pujjoga: Tune SX9324 registers settingLeo Chou
Currently, the P sensor does not work. So add SX9324 registers settings based on tuning value from SEMTECH. BUG=b:340749850 TEST=Check i2c register settings on Pujjoga and confirm P sensor function can work by kernel 6.6 driver. Change-Id: I205c1f5228d792afc763a06f74a8744918e2da75 Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82689 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-06-12mb/google/nissa/var/sundance: Add wifi sar tableLeo Chou
Add AX211 wifi sar table for sundance wifi sar config. Use fw_config to separate different wifi card settings. WIFI_SAR_TABLE_AX211: 0 BUG=b:332978681 Test=emerge-nissa coreboot Change-Id: Ide84996da567e4f866a2a1309a6976ed8df635a6 Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83044 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-06-12mb/google/nissa/var/sundance: Add FW_CONFIG probe for WWAN devicesLeo Chou
Add FW_CONFIG probe based on sundance boxster of below devices: WWAN Schematic version: NEC_SHIKIBU_ADL_N_MB_EVT_20240330 BUG=b:332978681 TEST=Boot to OS and verify the WWAN devices is set based on fw_config. Change-Id: I14339201d8ee21c85fefa96a49323e0c25cb8eca Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83041 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-12mb/google/trulo/var/orisa: Disable storage devices based on fw_configAmanda Huang
Disable devices in variant.c instead of adding probe statements to devicetree because storage devices need to be enabled when fw_config is unprovisioned. BUG=b:345112878 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I1e5e49c1baa8d2b00134c26cc3b69aa15712b512 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82907 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-06-12mb/google/trulo/var/orisa: Enable HDA Codec ALC256Amanda Huang
We use ALC256 as HDA codec on orisa. Add verb table and the related device tree changes for HDA related registers. BUG=b:338523452 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: I92051886341bd317cce6061ece83439d156b0f90 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82719 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-06-12mb/google/trulo/var/orisa: Add overridetreeAmanda Huang
Add override devicetree based on schematic_20240607. BUG=b:333486830 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: Id3ceff41fdb8e4a57bd6dab6247b622a5d13587d Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82714 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-06-11treewide: Move skip_atoi function to commonlibKapil Porwal
BUG=none TEST=Build and verify on Screebo TEST=make unit-tests ``` $ make tests/commonlib/bsd/string-test [==========] tests_commonlib_bsd_string-test(tests): Running 1 test(s). [ RUN ] test_skip_atoi [ OK ] test_skip_atoi [==========] tests_commonlib_bsd_string-test(tests): 1 test(s) run. [ PASSED ] 1 test(s). ``` Change-Id: Ifaaa80d0c696a625592ce301f9e3eefb2b4dcd98 Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82910 Reviewed-by: Jakub Czapiga <czapiga@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-06-11mb/razer/blade_stealth_kbl/h3q: add VBIOS tableReagan Bohan
This commit adds the VBIOS table, extracted from Linux sysfs running on the stock firmware version 8.02, to the coreboot tree, required for some graphics backends. Change-Id: I0d1c9795741e112154bfe6885eea744538373d5a Signed-off-by: Reagan Bohan <xbjfk.github@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82460 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-06-11mb/razer/blade_stealth_kbl: add panel_cfgReagan Bohan
This commit defines the panel_cfg register for the Razer Blade Stealth (Kaby Lake). This enables libgfxinit support. These values are derived from the stock firmware. First, VBIOSes were extracted from the stock firmware. Then, intelvbtool was used to extract the VBT from each of the VBIOS tables. Finally, intel_vbt_decode from igt-gpu-tools was used to extract the register values. Although there were multiple VBIOSes present in the firmware, all VBIOSes across both firmwares (on version 1.50 for the H2U and 8.02 for the H3Q) had the same register values. Change-Id: I4c8b26ffb7a70d08655986084a714206d9d0c96a Signed-off-by: Reagan Bohan <xbjfk.github@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82458 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-11sb/intel/lynxpoint/fadt: Fill extended FADT after populating lengthsMatt DeVillier
Commit 88decca14f84 ("ACPI: Add helper fill_fadt_extended_pm_io()") moved the population of the extended FADT to a separate function, but incorrectly placed that function call before various length fields were populated, leading to spurious validation errors in the cbmem boot log. Correct this by moving the call to fill_fadt_extended_pm_io() after the required fields are populated. TEST=build/boot google/slippy (wolf), verify no FADT errors in cbmem console log. Change-Id: I1f8522e4813e6071692206f2b7ad2a2f5086071e Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83035 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-06-11soc/amd/genoa_poc: Prefer include <soc/gpio.h> via <gpio.h>Elyes Haouas
Change-Id: I0e5fba7db7d97835001934cb140f4c76bdc46d3e Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82889 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-06-11tree: Drop non-existent directories from subdirs-yElyes Haouas
Change-Id: Icb9e72edf3a982a095dceee4da19f90c53fcddd0 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83021 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-06-11mb/google/trulo/var/orisa: Add memory configAmanda Huang
Fill in memory config based on the the schematic_20240607. BUG=b:333486830 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: I1456f7385e092b606fc0a35b25f3454600af8b23 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82662 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-10MAINTAINERS: Add Nicholas Chin for all Dell LatitudesNicholas Chin
All of the Dell Latitudes from GM45 and until at least Haswell use a derivative of the MEC5035 EC, and I have been actively working on coreboot support for this EC and boards that use it. Rename the "E6400 MAINBOARD" section to "DELL LATITUDE" and add mb/dell/snb_ivb_latitude and mb/dell/e7240 as additional paths. Change-Id: I7ba46980bfc8569a85593e415f01cc83fe7d67d7 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83008 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-10util/autoport: Assign SPD addresses in devicetreeAngel Pons
Commit 45e4ab4a660c (mb/*: Update SPD mapping for sandybridge boards) changed the way in which SPD addresses are set up for SNB/IVB boards, but autoport was not updated to reflect these changes. Result is: register "spd_addresses" = "{0x50, 0x51, 0x52, 0x53}" # FIXME: Put proper SPD map here" The stray quote at the end is irritating, but is hard to get rid of without substantial refactoring of autoport's guts. But, given that this is a FIXME comment, anyone using autoport should just drop the comment after verifying the SPD map, so it's not a big deal. In addition, update the corresponding section of the README, which was horrendously out-of-date. Change-Id: I6ad38f53afc4fafb45be7f086723cc0782a965ed Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82405 Reviewed-by: Keith Hui <buurin@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-10mb/google/nissa/var/riven: Add GPIO tableDavid Wu
Refer to the reference board of nivviks, and update GPIO settings based on latest schematic (Riven(ZDK)_MB_Proto_0601.pdf). BUG=b:337169542 TEST=Local build successfully. Change-Id: Ic43c743fcc2ec89b5a9e2fbe1a87b833d59f1e74 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82973 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-10arch/x86: Clarify help text for 64-bit supportSubrata Banik
The word "experimental" has been removed from the help text for HAVE_X86_64_SUPPORT Kconfig. This is because the x86_64 architecture has now been officially tested and enabled for several x86 SoC platforms. This work will provide us with the foundation we need to begin working with Intel's next-generation SoC platform (which requires to support 64-bit mode of booting by default). Therefore, we can now remove the word "experimental" from the "HAVE_X86_64_SUPPORT" Kconfig help text. TEST=Able to build and boot google/rex64 in 64-bit mode to ChromeOS. Change-Id: Ibd629f4e2722f3cbabbe297d4481790c9fa9226a Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83009 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-09sb/intel/lynxpoint/pcie.c: Add 9-series PCH-H device IDsAngel Pons
Looks like PCIe root port device IDs for 9-series PCH-H are missing from commit 434d7d45829e (sb/intel/lynxpoint: Add PCI DIDs for 9 series PCHs) for some reason. Add them, so that coreboot performs PCIe initialisation for 9-series PCH-H. Change-Id: I1589418e5e25daabbf09c66c637e9c4f86aa02a6 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82947 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-09mb/asrock/h110m/Makefile.mk: Remove superfluous spd from subdirs-yNicholas Chin
The H110M does not use memory down, and the spd directory doesn't exist in the board's directory in the first place. This was probably just copy and paste leftover from some existing Skylake board in the initial port. TEST=Timeless build does not change. Change-Id: I35744310b2bf8a14165dae9808c982e6dc274a74 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83010 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-09cpu/x86/Kconfig: Add SMM Kconfig helpMaximilian Brune
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: Ia0a5c48c6314f53c4ed72958f5d6f839f0a5c2ca Reviewed-on: https://review.coreboot.org/c/coreboot/+/77973 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-09superio/ite/it8659e: Add driver for ITE IT8659EMichał Żygowski
Based on the non-public "ITE IT8659E-I Preliminary Specification V0.7.2 (For H Version)". TEST=Initialize IT8659E on the new Protectli platform Change-Id: I11657ec6e1c880f0cee247071486a904a92bb7a1 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80497 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-06-09util/superiotool: Add support for dumping ITE IT8659E configurationMichał Żygowski
Based on the non-public "ITE IT8659E-I Preliminary Specification V0.7.2 (For H Version)". TEST=Dump IT8659E configuration on the new Protectli platform Change-Id: Ic036f8b99d5bd0107be7850fc4509da1bf020fe5 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80495 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-06-08mainboard/emulation/qemu-sbsa: Add qemu-sbsa boardDavid Milosevic
Add coreboot support for qemu's sbsa-ref (Server Base System Architecture) machine (-m sbsa-ref). The qemu-sbsa coreboot port runs on EL2 and is the payload of the EL3 firmware (Arm Trusted Firmware). Note that, coreboot expects a pointer to the FDT in x0. Make sure to configure TF-A to handoff the FDT pointer. Example qemu commandline: qemu-system-aarch64 -nographic -m 2048 -M sbsa-ref \ -pflash <path/to/TFA.fd> \ -pflash <path/to/coreboot.rom> The Documentation can be found here: Documentation/mainboard/emulation/qemu-sbsa.md Change-Id: Iacc9aaf065e0d153336cbef9a9b5b46a9eb24a53 Signed-off-by: David Milosevic <David.Milosevic@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79086 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-06-08mainboard: add Dell Latitude E7240Iru Cai
Based on autoport output. It boots to Arch Linux (Linux 6.6.3) from USB and mSATA with SeaBIOS. Change-Id: I6933bdbcc8d0bbb85d62657624740266284ac71c Signed-off-by: Iru Cai <mytbk920423@gmail.com> Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79746 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-06-08soc/alderlake/romstage: Set UsbTcPortEnPreMem UPD based on devicetreeMichał Żygowski
The UsbTcPortEn UPD for FSP-S is being set in ramstage, however the equivalent FSP-M UPD, the UsbTcPortEnPreMem, was not being set. Following the Meteor Lake example, set the UsbTcPortEnPreMem UPD as well for Alder Lake. Setting this FSP-M UPD will cause FSP to properly program sideband use BSSB_LSx pins for the enabled Type-C ports. Required for proper DCI debug and TCSS initialization flow. Change-Id: If3b79167ec1769ddfb7d28a6c78a3e80bd10afe7 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80500 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-06-08mb/dell: Add Latitude E6430 (Ivy Bridge)Nicholas Chin
Mainboard is QAL80/LA-7781P (UMA). The version with an Nvidia dGPU was not tested. This is based on the autoport output with some manual fixes. The VBT was obtained using `intelvbttool --inlegacy --outvbt data.vbt` while running version A24 (latest version) of the vendor firmware. The flash is 8MiB + 4MiB, and can be easily accessed by removing the keyboard. It can also be internally flashed by sending a command to the EC, which causes the EC to pull the FDO pin low and the firmware to skip setting up any chipset based write protections [1]. The EC is the SMSC MEC5055, which seems to be compatible with the existing MEC5035 code. Working: - Libgfxinit - USB EHCI debug (left side usb port is HCD index 2, middle port on the right side is HCD index 1) with the CH347 - Keyboard - Touchpad/trackpoint - ExpressCard (tested with USB 3.0 card) - Audio - Ethernet - SD card reader - mPCIe WiFi - SeaBIOS 1.16.3 - edk2 (MrChromebox's fork, uefipayload_202309) - Internal flashing using dell-flash-unlock Not working: - S3 suspend: Possibly EC related, DRAM power is getting cut when entering S3 - Physical wireless switch: this triggers an SMI handler in the vendor firmware which sends commands to the EC to enable/disable wireless devices, and has not been reimplemented - Battery reporting: needs ACPI code for the EC - Brightness hotkeys: probably EC related - The system reports that the power button was pressed and shuts down when the CPU hits around 86 degrees Celsius, before the CPU can thermal throttle. Likely EC and possibly PECI related. - Integrated keyboard with upstream GRUB 2.12 payload: Upstream GRUB initializes the 8042 PS/2 controller in a way that is incompatible with how the EC firmware emulates it. GRUB tries to initialize the controller with scan code set 2 without translation, but the EC only ever returns set 1 scan codes to the system and thus is only works as an untranslated set 1 keyboard or a translated set 2 keyboard, regardless of commands to set the scan code. A USB keyboard works fine. Unknown/untested: - Dock - eSATA - TPM - dGPU on non-UMA model - Bluetooth module (not included on my system) [1] https://gitlab.com/nic3-14159/dell-flash-unlock Change-Id: I93c6622fc5da1d0d61a5b2c197ac7227d9525908 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77444 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-08tree: Remove unused <option.h>Elyes Haouas
Change-Id: Ia3df14ebd365c00902b5d2ba300d8ade4c2d6c26 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82690 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2024-06-08sio/nuvoton: Add Kconfig for shared PS/2 portKeith Hui
Introduce HAVE_SHARED_PS2_PORT Kconfig for this Super I/O to have mainboards indicate if they have one shared PS/2 port on the rear panel. On these boards (where a Y-cable cannot allow both keyboard and mouse to work off the same port), if a PS/2 keyboard is not present, SIO should be configured to swap its role to mouse, to allow the OS to find and initialize any mouse connected. Supporting code will come in a separate patch. Idea is to condition them on this Kconfig. Change-Id: I156b15c6ba233cbe8b9ba4d2cfbca6836ad7483a Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82631 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-08mb/*: Remove old USB configurations from SNB/bd82x6x boardsKeith Hui
Remove USB configurations and data structures from northbridge devicetree (SNB+MRC boards) and bootblock/romstage C code (native-only SNB boards). All USB configurations are drawn from southbridge devicetree going forward. Change-Id: Ie1cd21077136998a6e90050c95263f2efed68a67 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81882 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-08nb/sandybridge,sb/bd82x6x: Configure USB from southbridge devicetreeKeith Hui
Transfer all USB responsibilities to southbridge/intel/bd82x6x, using one set of USB port configuration supplied by mainboards in the southbridge section of their devicetree. For MRC raminit, export southbridge_fill_pei_data() as a hook for southbridge code to implement. With new code via this hook, bd82x6x fills pei_data based on this one set of USB port config. For native raminit, early_usb_init() now goes directly to the devicetree and no longer get passed an address to it. TEST=abuild passes for all affected boards. All USB ports still work on asus/p8x7x-series/v/p8z77-m. Change-Id: I38378c7ee0701abc434b030dd97873f2af63e6b0 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81881 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-08mb/asus/p8z77-m: Update USB current map to match vendorKeith Hui
This board has used the USB current map from asus/p8z77-m_pro since it first landed in coreboot, which actually doesn't match vendor firmware. Apply values obtained from hardware while running vendor firmware to both native and MRC config. Change-Id: I7ce13493c3ecac8154460c1fedf05e2d70a8e394 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82756 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-08mb/*: Add consolidated USB port config for SNB+MRC boardsKeith Hui
For each sandybridge boards with option to use MRC or native platform init code, add a copy of the board's USB port config, consolidated between both code paths, into the southbridge devicetree, using special values allocated for this consolidation. These get hooked up in a separate patch. Change-Id: I53efca3d29b3c5d4d5b7e3d6dc3e6ce6c34201e6 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81880 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-08mb/asus/p8z77-v: Apply updated USB current map to sb devicetreeKeith Hui
This map is found stored in plain text in vendor firmware image. They will take effect when USB config is transitioned to southbridge devicetree. Change-Id: Iab0a225560856771407bb815ff4d8bc95d0f884f Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82755 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-06-07mb/*: Copy bd82x6x boards' USB port config into devicetreeKeith Hui
For mainboards using southbridge/intel/bd82x6x, copy the contents of mainboard_usb_ports array into southbridge devicetree. In-line comments are maintained. Boards also capable of using MRC raminit are done in a separate patch. Change-Id: Ia8a967eb3466106f3a34e024260e13d02f449a25 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81879 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-07sb/intel/bd82x6x/early_usb.c: Align native current map with MRCKeith Hui
Replace 3 unused values in the map with those found during a Ghidra examination of MRC binary, and on hardwares running vendor firmware (asus/p8z77-m and HP Z210 CMT Workstation). The outgoing values were introduced in commit 216ad2170ca8 ("sb/intel/bd82x6x: Add new USB currents") in anticipation for Gigabyte GA-Z77-DS3H mainboard, but effort to land it was eventually abandoned. Since commit xxxxxxxxxxxx, such values can be placed directly in the port config, so there should be no hurdle should that effort be resurrected. Add a few #defines in pch.h to place some inline documentation on MRC values, but more will be documented in the future when this mapping is introduced MRC-side. Finally, update autoport to match. Change-Id: I195c7f627994e48f7a6e6698589504dc96248cff Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82754 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-06-07sb/intel/bd82x6x: Make space for USB port config in devicetreeKeith Hui
This is the first step to: - Move USB port configs, which are static, from C code to devicetree; - Unify USB port configs between MRC and native code path. Change-Id: I59af466d41790e2163342cac8676457ac19371ea Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81878 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-07nb/intel/sandybridge: Refactor pei_data building codeKeith Hui
Incorporate fixed constants and simple data members into struct pei_data as it gets initialized and make more use of existing helpers. Compiler zeroes structs set up this way so the memset() is no longer needed. Drop northbridge_fill_pei_data() as it gets replaced entirely. Gut southbridge_fill_pei_data() in preparation for having southbridge code fill in USB-related members. This is to make the code easier to maintain, and realizes small savings in compiled code size too. Change-Id: I3140cb99b0106669aa27788641c2895ced048e95 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82480 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-07sb/intel/bd82x6x: Allow actual USBIRx values for native USB configKeith Hui
For USB to work under native code path, the USB port config needs to include a current setting for each port, which gets mapped to an initialization value that gets programmed into the USBIRx register for the respective port. This map resides in early_usb.c. The need to update it, whenever we see a previously unaccounted for initialization value, is getting out of hand. Instead this patch will allow specifying those values, presumably taken from an inteltool dump while running vendor firmware, directly in the USB port map. Because all USBIRx values are always in the 0x20000yyy form, we only need the lowest 12 bits. We have more than enough space in the USB port config structure for this. As the lowest yyy value we saw so far is 0x53, a note is included to limit the map to not more than 80 entries. Any value that is too big to be an index into the map is programmed directly, + 0x20000000, into the registers. This opens the future possibility to use the map for a simpler mapping for boards also using MRC, and remove the need for any mapping at all for the rest. Change-Id: I3d79b33bac742faa9bd4fc9852aff73fe326de4e Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82655 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-06-07soc/intel/cmn/cse: Support CSE sync from payloadKapil Porwal
Skip CSE sync in coreboot when payload is doing it. BUG=b:305898363 TEST=Verify CSE sync from depthcharge on Screebo Change-Id: Ifa942576c803b8ec9e1e59c61917a14154fb94b2 Signed-off-by: Kapil Porwal <kapilporwal@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82660 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com>
2024-06-07util/smmstoretool: explain what happens when no store is foundMaciej Pijanowski
We are going to expose ths tool to end users, and want to take care that the presented information can be consumed by them. The current code simply prints below warnings if we use release binary available for end-user to download: No firmware volume header present No valid firmware volume was found It will be concerning and not clear to end users, they might not understant why it happens, what are the implications, and whether it is something that they should worry about. This commit tries to explain what actually happens here. Change-Id: Iaa2678f5ae7c243811484c0567ced97ae0b3fc0a Signed-off-by: Maciej Pijanowski <maciej.pijanowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82692 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
2024-06-07soc/mediatek/mt8173/i2c.c: Remove unused macroElyes Haouas
Change-Id: I90fbd7ce0e1c6cd15d73cb73dc774df2de56b346 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82932 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2024-06-07ec/starlabs/merlin/battery: Calculate unknown valuesSean Rhodes
If the EC doesn't know a value, it will report it as 0xffff. In these cases, calculate a value to used based on others. For example, if the EC doesn't know the last full charge capacity, report the design capacity to the OS. Change-Id: I310555ff913c2e492bbaec4d77281ac32c0de7a3 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81408 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-07ec/starlabs/merlin/battery: Check values are valid before using themSean Rhodes
Change-Id: I559aca98044b7f0e6b08c475b5383c014bb4cd3f Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81407 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-07ec/starlabs/merlin: Rename BRPR to B1RPSean Rhodes
Rename the BRPR (Battery Remaining Percentage) to B1RP to match the format of the other variables. Change-Id: I64a744d78180156e16dbd483a35c7f97ac84bcba Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81406 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-07ec/starlabs/merlin: Report the battery cycle count to ACPISean Rhodes
Change-Id: Iccb60d3530227fb71a3ce5a3ab1421627cc86611 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81405 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-07ec/starlabs/merlin/*: Remove temperature and control variablesSean Rhodes
The BT1T (temperature) and BT1C (control) are not used so remove them. Change-Id: Ie6e85042ec59851bcfb4c88a2e04181c3c39f89c Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81404 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-07ec/starlabs/merlin/*: Fix the size of the battery socSean Rhodes
The battery remaining percentage is a uint16_t, so correct this in the EC memory. This change is non-function, as the EC is little endian. Change-Id: I56a0ae8199a95c9722e9bcb4c0739f4ef1d6ab05 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81403 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-07ec/starlabs/merlin/battery: Add extended battery informationSean Rhodes
Add BIX Method to report extended battery information. Change-Id: Ie5baecb20c7d4600e0cf1d19ff5f67ce2003fa1d Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81402 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-06-07mb/google/brya/var/xol: add support for wifi sar tableYH Lin
Add wifi sar table support for xol. Bit 31 in CBI/FW_CONFIG is used to select different sar table (index 0 or 1) but only 0 is in used at the moment. BUG=b:344274789 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot chromeos-bootimage Change-Id: Id4dc74c4f2a807d2e531b419ecb7b590d4c32ac2 Signed-off-by: YH Lin <yueherngl@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82945 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-06-07mb/google/brox/var/brox: update thermal settings to start fan earlySumeet Pawnikar
Current existing temperature thresholds of TSR1 sensor are set at 60C to start fan. Due to this CPU gets hot and temperature goes over 80C. In this situation, fan does not even start to lower down CPU temperature. With updated new settings based on tuning from thermal team, start fan early at 40C for TSR0 and TSR1 so the CPU temperature stays below 80C. BUG=b:339493551 TEST=Built and tested on google/brox board Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Change-Id: I4765c13c10e436733d8c9d017085968daa561ccc Reviewed-on: https://review.coreboot.org/c/coreboot/+/82784 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-06-07mb/siemens/mc_apl1: Prefer include <soc/gpio.h> via <gpio.h>Elyes Haouas
Change-Id: If43089560a391d6a844ef1716b277e3146c66945 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82861 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2024-06-07mb/google/rex0: Restore SSD power sequencing GPIOs in ramstageSubrata Banik
This change restores the EN_PP3300_SSD GPIO configuration in the ramstage for the Rex0 variant. This is necessary to enable testing of RO lockdown scenarios on FSI'ed Screbo devices, where bootblock changes are not applicable. Additionally, ensures locking the GPIO PAD from getting misconfigured after booting to OS. BUG=b/337971452 BRANCH=firmware-rex-15709.B TEST=Able to boot google/rex with RO locked to an older version without SSD GPIO refactored, and RW is with the latest revision. Change-Id: Ia7564b14a20d00e9bb2c9466b7a737dd97f01351 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82909 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-06-07mb/google/nissa/var/pujjoga: Add wifi sar tableLeo Chou
Add AX211 and AX203 wifi sar table for pujjoga wifi sar config. Use fw_config to separate different wifi card settings. WIFI_SAR_TABLE_AX211: 0 WIFI_SAR_TABLE_AX203: 1 BUG=b:336167281 Test=emerge-nissa coreboot Change-Id: If0f542cb13e93e99960bf65d616b26cee7617a43 Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82702 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>