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2015-07-09smaug: Update PMIC settingsFurquan Shaikh
Update PMIC settings as per table provided by hardware eng team. Change-Id: I17a8a1a44fa8c9093e13e8d7e4a2f5b07a3b1f1f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3c49afd0d1a17b73f2192206ff7389e2f7930fec Original-Change-Id: I027febb6849f1c4d15bf56d8bcd29c431655c7b6 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/283543 Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/10843 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-09arm64: Print sp value when dumping registers for exceptionFurquan Shaikh
BUG=None BRANCH=None TEST=Compiles successfully, sp verified during exception Change-Id: Idbeb93b1dbf163e2d86cd42369941ff98a3d2d9e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ca73b40f0248497143b6ab42bd0f5cc6cddf7713 Original-Change-Id: I38ee403200acb0e3d9015231c274568930b58987 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/283542 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/10842 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-09t210: set CAR2PMC_CPU_ACK_WIDTH to 0Yen Lin
HW team has suggested to set CAR2PMC_CPU_ACK_WIDTH to 0. BUG=None BRANCH=None TEST=Tested on Smaug; still boot to kernel Change-Id: I4d13a4048b73455b16da7a40c408c912fa97e4e7 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 8891a79e72af26d986af9e415149d4ca0aa6fedd Original-Change-Id: I850a6756d7743993802fb85aad403e4cbef7a661 Original-Signed-off-by: Yen Lin <yelin@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/282416 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/10841 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-09t210: i2c6: enable SOR_SAFE and DPAUX1 clocks for i2c6 to workYen Lin
I2C6 controller needs SOR_SAFE and DPAUX1 clocks to work. These 2 clocks are mistakenly enabled by MBIST. MBIST fix will be submitted next, which will disable these 2 clocks as initial states. Enable these 2 clocks now so I2C6 will continue to work after MBIST fix. BUG=None BRANCH=None TEST=Tested on Smaug, make sure that panel shows display (I2C6 is used to turn on backlight) Change-Id: Id47453e784d53fd6831e8d19a8d57c04c4e1f82f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 83e935f100be85e1e831a3f9f16962304f7cd7d6 Original-Signed-off-by: Yen Lin <yelin@nvidia.com> Original-Change-Id: If312881c94570066bdc54f0f5c48226e862bddc6 Original-Reviewed-on: https://chromium-review.googlesource.com/282415 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/10840 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-09veyron_danger: Enable developer mode switchDavid Hendricks
Danger has a physical developer mode switch, it was just never set up. This patch defines it, sets it up in fill_lb_gpios(), and disables VIRTUAL_DEV_SWITCH. Note: For now at least, dev mode is a bit wonky on Danger. It's connected to both a DIP switch and a button. The button is normally open, pulling dev mode high (defaulting to ON). The switch's "ON" position will pull the value low, so we invert the value in coreboot to see the expected behavior. Dev mode is enabled by holding the button down during boot or by setting switch 2 in the DIP bank to the ON position. BUG=none BRANCH=none TEST=toggled dev switch on Danger and saw dev screen show up (or not) as expected Change-Id: I9369b96b6c9b54553d969b919ed663abdc704dd2 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: dce53f1a31919f15f6e46c4a7d1c5ce541c2b318 Original-Change-Id: I737f165d7704e2f73375099367f012b365e3e77d Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/280852 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/10839 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-08vboot: Don't count boot attempts if lid is closedPatrick Georgi
This can be a problem with freshly updated devices that are periodically powered on while closed (as explained in the bug report). In this case, just don't count down. In case of actual errors (where we want the system to fall back to the old code), this now means that the retries have to happen with the lid open. Bump vboot's submodule revision for the vboot-side support of this. BUG=chromium:446945 TEST=to test the OS update side, follow the test protocol in https://code.google.com/p/chromium/issues/detail?id=446945#c43 With a servo, it can be sped up using the EC console interface to start the closed system - no need to wait 60min and plugging in power to get to that state. Change-Id: I0e39aadc52195fe53ee4a29a828ed9a40d28f5e6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10851 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-07-08build system / amd64: Avoid GCC taking the ABI spec too literallyPatrick Georgi
-mno-red-zone is an option that pretty much every barebone software package (eg. kernel, bootloader, ...) needs to use. We weren't hurt by it yet, but make sure we won't in the future. Change-Id: Ide5b63424ec1be5bf7bcade10540190b9871593b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10852 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-07-08vendorcode/intel/edk2: Fix EFI_PEI_GRAPHICS_INFO_HOB structureLee Leahy
Change the FrameBufferSize field from UINT64 to UINT32 to match the Platform Initialization 2.4 specification. BRANCH=none BUG=None TEST=Build and run on cyan Change-Id: I28dc0608675ed5840863ecd15bd2f57e6b2f4c1d Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10834 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-07-08Braswell: Fix error in the warranty statementLee Leahy
Fix a cut and paste error in the warranty statement. BRANCH=none BUG=None TEST=Build and run on cyan Change-Id: If64b02f2c0fc2970932f23b99ad64beab5ab754e Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10835 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
2015-07-08libpayload: update defconfigsPatrick Georgi
That way they don't need an initial 'make oldconfig' pass to be useful again. Change-Id: I3724fffab24b69478b8077f34e9d787555fd157b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10805 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-08toolchain.inc: Don't overwrite architecture specific CFLAGSStefan Reinauer
For almost all platforms the CFLAGS_<arch> specified in .xcompile were overwritten by toolchain.inc, effectively breaking the build in different places and in subtle ways. Change-Id: I8e1db0eee7ca417ec56ed2156ae1b0b318e57e81 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10831 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-08memlayout: Add timestamp regions for t210 and cygnusStefan Reinauer
This is needed to make those SOCs compile with timestamps enabled. Change-Id: Iac20cb9911e1c76a18c8530385c9d7b8b46399e5 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10833 Reviewed-by: Marc Jones <marc.jones@se-eng.com> Tested-by: build bot (Jenkins)
2015-07-07stddef.h: Disable check_member() macro when compiling with CLANGStefan Reinauer
CLANG assumes that _Static_assert() is a C++11 only feature and errs out when encountering the check_member macro complaining about a reinterpret_cast. Change-Id: Id8c6b47b4f5716e6184aec9e0bc4b0e1c7aaf17c Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10827 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2015-07-07payloads: Reorganize Makefile.incs for external payloadsStefan Reinauer
This is not going as far as I would like it to go, but some of the external payloads have to be fixed up first. Long term, I would like to directly add payloads/external/* to subdirs-y and remove one layer of indirection from the build process. For now, moving the payload Makefile targets into payloads/ is already a small improvement. Change-Id: Ie4eb492eb804e0aaaf1a4d90af2f876f27a32a75 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10829 Reviewed-by: Martin Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-07payloads: Reorganize Kconfig for external payloadsStefan Reinauer
The integration of external payloads in coreboot is a bit messy. You have to change the to level Kconfig file for every payload (something that we recently fixed for mainboards and chipsets). This means that updating e.g. the SeaBIOS version requires a change outside of the SeaBIOS directory. With this patch you can create a new directory under payloads/external and place a Kconfig and Kconfig.name file in there, and the payload will automatically show up when you do "make menuconfig". Change-Id: I293abcb8eae581d4b3934e64897c0d339a27e7c1 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10828 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-07timestamp: remove conditional #if CONFIG_COLLECT_TIMESTAMPSAaron Durbin
Empty functions are provided when !CONFIG_COLLECT_TIMESTAMPS so stop guarding the compilation. BUG=None BRANCH=None TEST=Built Original-Change-Id: Ib0f23e1204e048a9b928568da02e9661f6aa0a35 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/228190 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> (cherry picked from commit 9aa69fd43d77f5f7acdc9f361016c595dd16104e) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I14418c8ef3ccb57ac6fce05b422e1c21b1d38392 Reviewed-on: http://review.coreboot.org/10742 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-07-07marvel/bg4cd: move timestamp init to SoC codePatrick Georgi
No need to repeat this in the mainboard code (even if there's only one right now). Change-Id: Iaa3508c27f8c38cfa343ab1d8a094ce922dec157 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/10825 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2015-07-07timestamp: add generic cache regionAaron Durbin
In order to accommodate tracking timestamps in all the __PRE_RAM__ stages (bootblock, verstage, romstage, etc) of a platform one needs to provide a way to specify a persistent region of SRAM or cache-as-ram to store the timestamps until cbmem comes online. Provide that infrastructure. Based on original patches from chromium.org: Original-Change-Id: I4d78653c0595523eeeb02115423e7fecceea5e1e Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/223348 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Change-Id: Ie5ffda3112d626068bd1904afcc5a09bc4916d16 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/224024 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Change-Id: I8779526136e89ae61a6f177ce5c74a6530469ae1 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10790 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-07-07rk3288: Use timestamp region for pre-cbmem timestampsFurquan Shaikh
BUG=None BRANCH=None TEST=Compiles successfully for veyron_pinky Original-Change-Id: I3862e9bf2c32085c921adae4c1dcdf88ff0f3ff3 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/227243 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 0fabdbb05826160beb8ee8f89339b18a49e87ab8) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I4504d29a43084d4bd406626899b25903200fa6d7 Reviewed-on: http://review.coreboot.org/10740 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2015-07-07t132: Add timestamp collection support in t132Furquan Shaikh
Add a region TIMESTAMP to store all the timestamps starting from bootblock to end of romstage. At the end of romstage take all the timestamps in TIMESTAMP region and put it into cbmem BUG=chrome-os-partner:32973 BRANCH=None TEST=Compiles successfully and cbmem -t prints all timestamps Original-Change-Id: I856564de80589bede660ca6bc1275193f8a2fa4b Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/223110 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit b8ccf5731df9ca149a2a0661362e7745515bfe5e) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I266e46ed691ebe5f0a20ed28b89e6e74399487a1 Reviewed-on: http://review.coreboot.org/10736 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2015-07-07x86 makefile: Use preprocessed linker filesMarc Jones
The top level Makefile runs the $stage-src .ld scripts through the preprocessor and puts them in $(obj). Use the preprocessed .ld files and cat them together into x86 romstage_null.ld. Change-Id: If71240fbf7231df2b1333a1f8e5160cb8694f6ce Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/10743 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-07smbios: fix copy&paste errorPatrick Georgi
While extending the SMBIOS code to write a proper maximum structure size, the call to elog_smbios_write_type15() was botched. Fix the name and arguments. Change-Id: I4c93490b09ddf4da240ff8f2bd8f8cc3f2abd96e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10823 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-07x86: Drop -Wa,--divideStefan Reinauer
Fix up all the code that is using / to use >> for divisions instead. Change-Id: I8a6deb0aa090e0df71d90a5509c911b295833cea Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10819 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-07-07cbfstool: Make sure CBFS data structures are packed gcc styleStefan Reinauer
On Windows systems, structs can be packed gcc style or ms style. Make sure we use the same one (gcc style) in our user space tools that we use in coreboot. Change-Id: I7a9ea7368f77fba53206e953b4d5ca219ed4c12e Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Signed-off-by: Scott Duplichan <scott@notabs.org> Reviewed-on: http://review.coreboot.org/10794 Tested-by: build bot (Jenkins)
2015-07-07cbfstool: Fix kv_pair on WindowsStefan Reinauer
On Windows systems the archetype printf defaults to ms_printf instead of gnu_printf. Keep the archetype print for all non- Windows compiles to not break compatibility with other systems out there. Change-Id: Iad8441f4dc814366176646f6a7a5df653fda4c15 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Signed-off-by: Scott Duplichan <scott@notabs.org> Reviewed-on: http://review.coreboot.org/10793 Tested-by: build bot (Jenkins)
2015-07-07blobs: move markerStefan Reinauer
Makes the following changes available: 61d663e blobs: Fix assembler code to allow dropping -Wa,--divide a6c34a6 AMD Steppe Eagle: add PlatformMemoryConfiguration.h 95b8050 AMD FT3b binary PI: Fix Windows 7 graphics driver hang c7c816e AMD Kern: remove PspSecureOs_prod_CZ.sbin Change-Id: Ie8ce8278f72c998b91717658a6fc1d0948c7c50a Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10824 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-07Unconditionally compile romstage with -Wa,--divideStefan Reinauer
The option --divide is required by our assembler to ensure that '/' is not parsed as a comment sign but as a division, because some of the cache as ram code is using divisions. The --divide parameter has been part of the GNU as since binutils 2.17. Hence, compile romstage (which contains cache as ram init) with -Wa,--divide unconditionally instead of probing for it and adding it to all compiler invocations (because that is causing random trouble with clang when compiling the SMM code and calling gcc with --divide instead of -Wa,--divide) Change-Id: Ideefb2a243dc1d657ba415a99c1f8ab1d93800e0 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10817 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-07T210: UTMIP: Correct UTMIP PLL programming as per Mark KuoTom Warren
BUG=chrome-os-partner:39603 BRANCH=none TEST=Built OK for Smaug. Change-Id: Iba170d8ad6f1dff111421fd61f71da19de57efaa Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 1bf1c1442dacf45bac5d55b05ada99a2c96f2e45 Original-Change-Id: Iecf04691a637b56e2f2287ab7d4d0cdda0382421 Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/282720 Original-Reviewed-by: Andrew Bresticker <abrestic@chromium.org> Original-Reviewed-by: Mark Kuo <mkuo@nvidia.com> Reviewed-on: http://review.coreboot.org/10814 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-07amd/lamar: drop unused value from mainboard_intr_data[]Stefan Reinauer
This value is overwritten in the next line. Change-Id: I622c35b8d78f6b01f2532dd8b40db15b2e888f58 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10822 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-07buildgcc: update IASL to version 20150619Stefan Reinauer
Change-Id: Ic0cb6826bb624e905b9c715f17a7629bc7b751c5 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10818 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-07xcompile: Fix compiler invocation in testccStefan Reinauer
While for GCC targets the compiler is just defined as a single binary, for clang it is defined as a binary and some options, e.g.: clang -target i386-elf -ccc-gcc-name i386-elf-gcc When executing the compiler with "$1", the shell will look for a binary with the above name (instead of just clang) and always fail detection of any CFLAGS. By adding -c we prevent the compiler from failing because it can't link a user space program (when what we're looking for, is whether a specific compiler flag can be used to compile a coreboot object file) Change-Id: I1e9ff32fe40efbe3224c69785f31bc277f21d21b Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10816 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-07buildgcc: work around bug in --print-librt-file-nameStefan Reinauer
Running "clang -target i386-elf --print-librt-file-name" prints [..]/bin/../lib/clang/3.6.1/lib/libclang_rt.builtins-i386.a However, the correct path is [..]/lib/linux/libclang_rt.builtins-i386.a on a Linux host. Hence, create symbolic links to make sure that our build system finds the file where it expects it. Change-Id: I21ef5c4a690d83c326717ca55c5ace558257a0ec Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10815 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-07mainboard/msi/ms7135: remove bogus MADT IRQ override for timerJonathan A. Kollasch
Stops Linux from complaining: [0.097286] ..TIMER: vector=0x30 apic1=0 pin1=2 apic2=0 pin2=0 [0.100005] ..MP-BIOS bug: 8254 timer not connected to IO-APIC [0.100005] ...trying to set up timer (IRQ0) through the 8259A ... [0.100005] ..... (found apic 0 pin 0) ... [0.143507] ....... works. Change-Id: Ic09a6940f80e3da2c1f3c0ef04fb50a4096b7943 Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: http://review.coreboot.org/10642 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-07smbios: Calculate SMBIOS Max Struct sizeBen Frisch
The SMBIOS Specification 2.3 and up defines Maximum Structure Size as the "Size of the largest SMBIOS structure, in bytes, and encompasses the structure’s formatted area and text strings." The hardcoded size is too small to accurately represent the maximum SMBIOS structure sizes. While the field is not used by Linux it is used by some RTOS implementations, eg. VxWorks. TEST=Booted Linux and ran github.com/bfrisch/dmidecode which verified the maximum structure size on Minnowboard Max. Change-Id: I98087975c53a02857742dea283f4e303485b2ffe Signed-off-by: Ben Frisch <bfrisch@gmail.com> Reviewed-on: http://review.coreboot.org/10163 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-07ec/lenovo/h8: silence sound on bootAlexander Couzens
Fix a bug when a sound was generated while going into suspend. E.g. When a low battery sound is played while going into suspend a sample is stuck in this register. The user will hear a sample forever. Change-Id: I103a5f462c8044ef5875a9adf812234b5e6960ac Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: http://review.coreboot.org/10297 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
2015-07-07sandybridge: provide monotonic timer functionPatrick Georgi
This fixes building the ELOG_GSMI feature by using the TSC as time source for the flash drivers. It's not the most precise clock, but should be good enough for the purpose. Change-Id: I2d416c34268236228300a9e868628c35e22bf40c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10813 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-07gitconfig: Improve robustness when blobs aren't presentPatrick Georgi
With no blobs present the 'make gitconfig' target failed when trying to add a file to a directory which doesn't exist. Only try to deal with blobs if they're around. Change-Id: I27ed33e2e22bb1571bc73fe55cf45aa1e2310bf1 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10806 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-07-07util/cbfstool: use _XOPEN_SOURCE=700 to find strdup(3)Jonathan A. Kollasch
Change-Id: I974c6c8733356cc8ea4e0505136a34b6055abf0c Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: http://review.coreboot.org/10809 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2015-07-07cpu/amd/model_10xxx: Determine single-link status of each CPU in _PSD generatorTimothy Pearson
The prior ACPI _PSD generator committed in ef33db01 incorrectly assumed the active link count of each processor was identical. Detect the link count on each node when generating the _PSD objects. Change-Id: Ic8aaa0728a43936cd4c6e1ed590e01ba8f0fbf9b Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/10158 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-07-07cpu/amd/car: Move AP stacks below the BSP stack to free up spaceTimothy Pearson
Caching SPD data during startup requires additional CAR space. There was a large chunk of free space between the AP stack top and the BSP stack bottom; moving the AP stacks below the BSP stack allows this space to be utilized. TEST: Booted ASUS KGPE-D16 with dual Opteron 6129 processors (16 cores) and 120k of CAR. Change-Id: I370ff368affde7061d6547527bda058b9016e977 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/10404 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2015-07-07cpu/amd/car: Increase Family 10h CAR size limit to 128kTimothy Pearson
This resolves issues with 4-node (32-core) systems not having sufficient CAR memory available to boot. TEST: Booted ASUS KGPE-D16 with dual Opteron 6129 processors (16 cores) and 120k of CAR. Change-Id: Ie884556edc5c85c2c908a8c6640eeec11594ba3a Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/10402 Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-07-07cpu/amd: Detect any conflicts between sysinfo and the stack regionTimothy Pearson
When increasing the number of supported CPUs on AMD Family 10h/15h systems there is a relatively high chance of causing a collision between the CAR global variable region and the AP stack space. Such collision was noted when increasing the number of supported CPUs to 32 on the ASUS KGPE-D16. Detect collision at runtime and print a warning if collision is present. Change-Id: Ib5c32f868b1dfffb3b840bb1b1df5f55b5a25f8d Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/10401 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2015-07-07northbridge/amd/amdfam10: Remove array to null comparisonTimothy Pearson
The address of array 'sysinfo->DCTstatA' will always evaluate to 'true'. Remove checking the base pointer of an array for validity. Found-by: Coverity (CID 1293135: Incorrect expression) Found-by: Clang (Wpointer-bool-conversion) Change-Id: I99c9c9f1564dfb997c60b2a895d664e3b06c117b Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/9596 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-07-06util/ectool: don't dump the whole ram when writing to itAlexander Couzens
Change-Id: Ib2f417ff91862c71de32b3f8929d2017a725ea47 Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: http://review.coreboot.org/10767 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-06Revert "sandy/ivybridge: use LAPIC timer in SMM"Patrick Georgi
This reverts commit a3aa8da2acec28670b724b7897ae054592746674. Chrome OS builds require the monotonic timer API in SMM for ELOG_GSMI, but sandy/ivy doesn't provide it. The commit tried to work around that by using generic LAPIC code instead, but this leads to multiple definition errors in other configurations (and it may be unreliable once the OS reconfigured the APIC timers anyhow). This fixes the situation for the non-ELOG_GSMI case (which is more or less everybody but Chrome OS). ELOG_GSMI requires a separate fix. Change-Id: If4d69a122b020e5b2d2316b8da225435f6b2bef0 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10811 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-07-06util/cbfstool: don't override ntohl(3) and htonl(3) on NetBSDJonathan A. Kollasch
Change-Id: I9bfc017dee86fe6cbc51de99f46429d53efe7d11 Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: http://review.coreboot.org/10810 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-07-06util/xcompile/xcompile: use env(1) to find bashJonathan A. Kollasch
Not all systems put bash at /bin/bash. Change-Id: Ib58cd2f6cf330b5b2678d55bb929696872fba9c9 Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: http://review.coreboot.org/10808 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-07-06Braswell: Update to end of June.Lee Leahy
Remove some CamelCase in acpi.c Add FSP PcdDvfsEnable configuration parameter. Add lpc_init and lpc_set_low_power routines. Remove Braswell reference to make code easier to port to another SOC. BRANCH=none BUG=None TEST=Build and run on cyan Change-Id: I5063215fc5d19b4a07f3161f76bf3d58e30f6f02 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10768 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-06Braswell: Update the ACPI tablesLee Leahy
Build the GNVS pointer and add it to the DSDT. Add the opregion for GOP support. Build the SSDT entry and add it to the RSDP. The arch/x86/boot/acpi.c module adds the HPET entry, remove the acpi_create_intel_hpet routine. BRANCH=none BUG=None TEST=Build and run on cyan Change-Id: I8c7ae36b24da583928ad2532f611a855268b51f9 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10748 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-06libpayload: don't overwrite CFLAGSPatrick Georgi
Makefile already sets it to contain the architecture specific flags, don't drop them, but add to that instead. Change-Id: I147e6480ab2b3c1ee4f4ace511197b4ba94280b8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10804 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-06libpayload: architecture mapping is now done in xcompilePatrick Georgi
This helps the build system find i386 and mips compilers. Change-Id: I17d18019b556190f860d288e66f368f8d29ca24d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10803 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-06libpayload: drop LIBGCC_FILE_NAME variablePatrick Georgi
It's unused. If we need something like that, .xcompile provides it, and in a cross-platform and clang-aware way. Change-Id: Ic1bdc2e3e252d612a5b99ad4e8caebc5158a485f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10802 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-06libpayload: defer including .xcompilePatrick Georgi
It needs to come after DOTCONFIG so that the compiler decision can be made. Change-Id: I5c6730ac58ab8731f07bb7c5161b2d0a59588e28 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10801 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-06libpayload: Add compiler switchPatrick Georgi
clang is totally untested, but it mirrors coreboot now. Change-Id: I0e13ff8bba2007159a4a795ca07d187504b606b2 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10800 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-06libpayload: mark util/xcompile/xcompile executablePatrick Georgi
Change-Id: I97088df1550f580d4648c7cccbd81c696fcfe2dc Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10799 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-06veyron*: Kill SKIP_DISPLAY_INIT_HACKDavid Hendricks
Now that we have functioning display code for all platforms, we can just get rid of this ugly hack used on non-Chromebook veyrons. BUG=none BRANCH=none TEST=built for Brain, Rialto, Mickey, Romy Change-Id: Ibe248c7cc74940811345c249d66992d74fe85fe5 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 9c627b087ba9fc07b4ec4a6d55d2e0203bdd4ff5 Original-Change-Id: I946eddb4e8ce1dbaa20212a2bb417e71a31b2ba3 Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/282049 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/10785 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-07-06veyron_rialto: Use VOP_MODE_NONE for display init.David Hendricks
This uses VOP_MODE_NONE for display init on veyron_rialto and adds a mainboard_power_on_backlight() stub so that we can finally get rid of SKIP_DISPLAY_INIT_HACK. BUG=none BRANCH=none TEST=built for veyron_rialto Change-Id: Ia6b420a962fe266e773c804b8e5c68da35848753 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a290c938c163759a3672c07d8ec7c0a38057b13d Original-Change-Id: Iec2d7f03857198a4d6f7490db1e3e19c74f18c43 Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/282048 Reviewed-on: http://review.coreboot.org/10784 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-06cbfs: define libpayload_init_default_cbfs_media weaklyDaisuke Nojiri
To allow a payload to define its own libpayload_init_default_cbfs_media, default implementation needs to be defined weakly. BUG=none BRANCH=tot TEST=dumped a cbfs file from depthcharge cli on jerry Change-Id: Ice73ae5a63dfd49e79c0eeb92d4eade016d61c39 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 1f308177fffb0d525fdb50f8d024568bb9025352 Original-Change-Id: I4721139aea3169c62c10a2a26582bd9277e4cb83 Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/283061 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10783 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-06sysinfo: remove unused tag for struct spi_flashDaisuke Nojiri
This will conflict with struct spi_flash defined in spi_flash.h BUG=none BRANCH=tot TEST=built libpayload for veyron jerry Change-Id: I7e1be28cf430021944fc96890082a0704d093e9f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0f0b8a7ec114046335fb1a51b6a92e10e5a16520 Original-Change-Id: I6d4f8a8e93aeb055f7dd6e5e8fd5e6c6153ab837 Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/282588 Original-Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: http://review.coreboot.org/10782 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-06update common base header filesDaisuke Nojiri
IS_ENABLED is defined in kconfig.h, thus, should be included in libpayload.h. BUG=none BRANCH=tot TEST=built coreboot/libpayload for veyron_jerry Change-Id: I9c5879b6125ac66a75a507ab07a6816ab54ed0ba Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 51dcd58a841009081fdefcadf9aa74286152dde6 Original-Change-Id: I30e6d87c9de827a214a6100449cd716e773c2ba3 Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/282587 Original-Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: http://review.coreboot.org/10781 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-06t210: MTC cleanupFurquan Shaikh
1. Correct MTC weak function definitions. 2. Correct MTC message in case no training data is present. BUG=None BRANCH=None TEST=Compiles successfully and boots to kernel prompt on smaug. Change-Id: Iba3c994982da947af3fbd2d7e9a06dff7947f2b9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ce9a4cd7d824acd0da5615b33319869f6cf1cd56 Original-Change-Id: I037439246709c8ec0ec7f12ea109cbe0ae1073ae Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/278027 Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/10780 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2015-07-06rk3288: Add VOP_MODE_NONE for headless devicesDavid Hendricks
BUG=none BRANCH=none TEST=built w/ follow-up rialto patch Change-Id: I166c75673c199e8c6860f601db6759cdc3cb9c96 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ba0e0b639f12654ec54216d4366c688baa5b3253 Original-Change-Id: Id21c87ace2f4d381a1e374e1d5fe15cf1cd96da0 Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/282047 Reviewed-on: http://review.coreboot.org/10779 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-06veyron_brain: Add basic HDMI supportDavid Hendricks
This adds a configure_hdmi() function that drives the HDMI enable output high and configures the iomux. Calls to PMIC functions to enable HDMI power are moved here as well. BUG=none BRANCH=none TEST=with follow-up patches, we now get a dev screen on Brain. Change-Id: Ifd2648376c789fb29c9e2e4ab6bdb10ca439e4a2 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 91ec6a96edaf2042236aee0383e18715014f1013 Original-Change-Id: I0c6e9f8fc5e06f53a1a160d8ab2e32447168139e Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/282046 Reviewed-on: http://review.coreboot.org/10778 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-07-06lzma: Return correct amount of decompressed bytesJulius Werner
The LZMA functions are supposed to return the decompressed size, but what they actually return is just an unaltered field from the LZMA header that is *supposed* to contain the decompressed size. Apparently some encoders just overshoot that for no good reason. This patch changes the code such that the actual amount of decompressed bytes is returned. BRANCH=smaug BUG=None TEST=Printed output bytes when decompressing kernels with LZMA in depthcharge, noted that amounts now make sense. Change-Id: Icdd8f782aa87841f770eff4c14a08973530c7446 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 24b2fa8c9a342ca4288dad1430c8965395f00263 Original-Change-Id: Ib4cf8673846aedd34656e594ce7b8ea875b56099 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/282742 Original-Reviewed-by: Stefan Reinauer <reinauer@google.com> Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10777 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-06veyron_*: Set vop_mode in devicetree.cb filesDavid Hendricks
This avoids any ambiguity or breakage in case the vop_modes get shuffled around or changed in some future patch or copy+paste job. Brain and Rialto need some more work done so their devicetree.cb files will be updated in follow-up patches. BUG=none BRANCH=none TEST=compiled only (for danger, jerry, mickey, romy, speedy) Change-Id: I4fd549c82c8a5c31525c4e485fa8df73f33f2049 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: bd88973b53949058331613c7582650fbd4ea48db Original-Change-Id: I47da45c5fd9648544392de8d76f86af812de9093 Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/282610 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/10776 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-06rk3288: Auto-detect display.David Hendricks
We currently select either HDMI or EDP (default). This patch allows us to use HDMI as a fallback for devices that may have a display connected on either interface. It also renames the enums to sound a little more sensible in other contexts (more on that in the follow-up patches). VOP_MODE_AUTO is added to the mode enum which will make it explicit that a board can support either. In AUTO_MODE we will try EDP first and then fallback to HDMI. Other modes can be set to force a certain behavior such as HDMI-only on Mickey where it doesn't make sense to try EDP. A follow-up patch will add logic for when we explicitly don't want to probe for any display (headless devices). BUG=none BRANCH=none TEST=On veyron_danger, connected EDP and HDMI displays and saw dev mode screen appear on EDP display. Unplugged EDP and then dev mode screen showed up on HDMI. Change-Id: I22b38031c4ab3d79fbb182f7a906da1197f35543 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3f57ed3758c4e516d9fd226ad9499b102b81b423 Original-Change-Id: I352dcde16f7f3ebbf5796852b685685e541eb794 Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/281076 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/10775 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-06libpayload: usb: dwc2: support interrupt transferYunzhi Li
dwc2 host core do not have a periodic schedule list, so try to send an interrupt packet in poll_intr_queue() function and use frame number read from usb core register to calculate time and schedule transfers. BUG=None TEST=Tested on RK3288 with two USB keyboards(connect to SoC without USB hub), both work correctly. BRANCH=None Change-Id: I16f7977c45a84b37c32b7c495ca78ad76be9f0ce Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3d0206b86634bcfdbe03da3e2c8adf186470e157 Original-Change-Id: Ie54699162ef799f4d3d2a0abf850dbeb62417777 Original-Signed-off-by: Yunzhi Li <lyz@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/280750 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Commit-Queue: Lin Huang <hl@rock-chips.com> Original-Tested-by: Lin Huang <hl@rock-chips.com> Reviewed-on: http://review.coreboot.org/10774 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-06libpayload: arm(64): add read8/16/32 and write8/16/32Daisuke Nojiri
This applys the same change made by https://chromium-review.googlesource.com/261692 to libpayload. BUG=none BRANCH=tot TEST=built for veyron_jerry, rush_ryu, samus Change-Id: I26dd66d79cd1559a7852b3c9d252420f2fed5fa0 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d0d6f70aa805e18966e80618fbf9e9605274b030 Original-Change-Id: Ib0c199238f8fa58643d51782b17550dbd0d9ebd7 Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/282541 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10773 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-06rockchip: rk3288: correct ddr 300MHz clock settinghuang lin
CRU request (24MHz * nf) / nr > 440MHz, but now ddr 300MHz setting can't meet this request, so modify it BRANCH=None BUG=None TEST=Set ddr frequency to 300MHz and boot from mickey Change-Id: I00324f5864f5ce8c1a3768268e402e0beca214c6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3d292b67245e714cb03ed35ee28c9b838d514da5 Original-Change-Id: I885704542293ed55e429a0b4b30135af7978990f Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/282445 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/10772 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-06veyron_danger: EDP changes for v2David Hendricks
EDP-related hardware modifications for v2: - BL_EN moved from GPIO7_A3 to GPIO7_A2 - EDP_HPD added to GPIO7_B3 BUG=none BRANCH=none TEST=built and booted Danger v2 with EDP panel attached, saw dev mode screen come up Change-Id: I47383610082b371a612aced656e56f1bd1cfa098 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: fb939ff17cca7bbd24aabfdb3cbd444696a5a845 Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: Id271cdcfcde6fa84c1bb707b9842bddd77a7121b Original-Reviewed-on: https://chromium-review.googlesource.com/280855 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/10771 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-06libpayload: udc: dwc2: support force_shutdown() routineYunzhi Li
Add force_shutdown() routine for dwc2 udc driver to support disconnect and reconnect case when fastboot receiving data. BUG=chrome-os-partner:41687 BRANCH=None TEST=None Change-Id: I9ec204d8b7088cfafd3164c9779a6fd85d379dba Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 9238f87c065ba8a57bfb4a7e65fd1821ff2922f9 Original-Change-Id: I1e584aaf19efa14409bdfa26039c27fa7034b5f0 Original-Signed-off-by: Yunzhi Li <lyz@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/281130 Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> Original-Tested-by: Lin Huang <hl@rock-chips.com> Original-Commit-Queue: Jeffy Chen <jeffy.chen@rock-chips.com> Reviewed-on: http://review.coreboot.org/10770 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-05nvidia/l1_2pvv: whitespace: remove spaces that are followed by tabJonathan A. Kollasch
Change-Id: Ia84df2f4467e102fd5f675dba6432996584d78c1 Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: http://review.coreboot.org/10796 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2015-07-04Kconfig: Fix references to obsolete symbolsMartin Roth
These are all Kconfig symbols that have been removed or renamed. USE_PRINTK_IN_CAR was removed in commit 8c4f31b3 Drop the USE_PRINTK_IN_CAR option. It's a bogus decision... DYNAMIC_CBMEM was removed in commit e2b0affd Remove Kconfig variable that has no effect MAINBOARD_HAS_BOOTBLOCK_INIT was removed in commit 342535cc Remove Kconfig variable that has no effect CACHE_ROM was removed in commit 4337020b Remove CACHE_ROM. SMM_MODULES was removed in commit 44cbe10f smm: Merge configs SMM_MODULES and SMM_TSEG INCLUDE_MICROCODE_IN_BUILD was removed in commit eb73a218 soc/fsp_baytrail: Fix use of microcode-related Kconfig variables CAR_MIGRATION was removed in commit cbf5bdfe CBMEM: Always select CAR_MIGRATION REQUIRES_BLOB was removed in commit 70c85eab build system: Retire REQUIRES_BLOB CPU_MICROCODE_IN_CBFS was renamed to SUPPORT_CPU_UCODE_IN_CBFS in commit 66e0c4c8 - cpu: Rename CPU_MICROCODE_IN_CBFS to SUPPORT_CPU_UCODE_IN_CBFS CONSOLE_SERIAL_UART was renamed to CONSOLE_SERIAL in commit afa7b13b uart: Redefine Kconfig options CONSOLE_SERIAL8250MEM was renamed to DRIVERS_UART_8250MEM in commit afa7b13b - uart: Redefine Kconfig options Change-Id: I8952ca8c53ac2e6cec5f9c77d2f413f086bfab9d Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/10766 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-07-04intel raminit: rename registerPatrick Rudolph
Found while doing code review. Rename reg_4004_b30 to cmd_stretch. Found in 4th-gen-core-family-desktop-vol-2-datasheet.pdf chapter 4.2.1. Change-Id: Ib07059625ed458332708562e836803f2b587d5d8 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: http://review.coreboot.org/10789 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
2015-07-04buildgcc: Deal with gmp on 32bit Linux on 64bit CPUsPatrick Georgi
GMP is overeager to detect 64bit ABIs even if the entire running codebase is 32bit (but on a 64bit CPU). Enforce a 32bit build in that situation. Change-Id: I23e9e57f3c8b0e3ad2e4e1e3eb106f7830aa76a1 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/10792 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-04xcompile: ask for compiler runtime using appropriate CFLAGSPatrick Georgi
xcompile keeps two CFLAGS around now, for GCC and CLANG. Normally they're not required to request the libgcc/compiler-rt path, but with the multilib capable x86_64-elf target it's required to make it pick the right libgcc when used as i386-elf builder. Change-Id: I700e7aa5783dc36698dd2ab8a38642a144e80fe9 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/10795 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-07-04crossgcc: Fix binutils for aarch64Patrick Georgi
The gold linker didn't build. Change-Id: I93c26a7715e781b001a71978d8fadbf65fdfe427 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/10791 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-07-03hp/pavilion_m6_1035dx: Remove 'select USBDEBUG_IN_ROMSTAGE'Kimarie Hoot
Since USBDEBUG is not selected by this platform, there is no benefit to selecting USBDEBUG_IN_ROMSTAGE in the mainboard Kconfig. Further, using a 'select' for USBDEBUG_IN_ROMSTAGE prevents the value from being modified by a user in menuconfig. Change-Id: I67b71a724a8614882cff4bb43b042f0c092d11d2 Signed-off-by: Kimarie Hoot <kimarie.hoot@se-eng.com> Reviewed-on: http://review.coreboot.org/10671 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-07-03Kconfig whitespace cleanup: Change leading spaces to tabsMartin Roth
Change-Id: Icab6bd9f55f086da7b51ae463f34e29366d50e1a Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/10764 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-03SeaBIOS: Change clean to just 'rm -rf seabios/out'Martin Roth
When running 'make clean' if the seabios directory is present, we get warnings about not having IASL installed or that the C compiler can't be executed. It fails to actually run the clean because we're not correctly passing in the toolchain. Just do what the SeaBIOS clean does directly and delete the 'out' directory without actually calling the SeaBIOS clean. Here were the previous warnings: % make clean Unable to execute the C compiler (). Please install a working compiler and retry. Makefile:104: *** "Please upgrade the build environment". Stop. or % make clean The SeaBIOS project requires the 'iasl' package be installed. Many Linux distributions have this package. Try: sudo yum install iasl Or: sudo apt-get install iasl Please install iasl and retry. Makefile:106: *** "Please upgrade the build environment". Stop. Change-Id: Ice41376bc242f1f622d849e7628f8a9b6ef47404 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/10655 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-03storm: Enable DRIVER_UART since we use CONSOLE_CBMEM_DUMP_TO_UARTStefan Reinauer
This fixes the build with CONSOLE_CBMEM_DUMP_TO_UART. Change-Id: Ibe79239c5799a5c4a08ed195fce4d0c63d629ca4 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10769 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-03libpayload: update xcompile scriptPatrick Georgi
Copy from coreboot. at some point it probably should just reuse coreboot's version. Change-Id: Iee905a9060983ff85e2e70bde69a221c64a07cbc Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10756 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-02tegra124: verified boot fixupsStefan Reinauer
This patch fixes up verified boot (vboot2) configuration of all tegra 124 bases boards in the tree. Change-Id: I81f2e83821cbfdbe2a55095543e7447efdde494e Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10761 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-07-02sandy/ivybridge: use LAPIC timer in SMMStefan Reinauer
This fixes an issue with using the flash driver in SMM for writing the event log through an SMM call. Change-Id: If18c77634cca4563f770f09b0f0797ece24308ce Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10762 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-02purin: chromeos.c also needed in romstageStefan Reinauer
Otherwise the Chrome OS build won't succeed. Change-Id: Idf93a09f53d08b6c201f1de140f0fff35f928dcc Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10760 Reviewed-by: Marc Jones <marc.jones@se-eng.com> Tested-by: build bot (Jenkins)
2015-07-02ME/IFD binaries: Implement sane defaults for file pathsStefan Reinauer
Change-Id: I81298aca07c18359e8e4bf5b2d8926d6b45a30c5 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10763 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <gaumless@gmail.com>
2015-07-02ifdfake: Add prompts and help for the regions in KconfigMartin Roth
Update the ifdfake region questions in Kconfig with help descriptions and prompts to allow values to be entered and not just use pre-defined default values. Change-Id: Ifdffadc3d74ec49492c2ded66623a1be6945425f Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/10649 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-02Intel Firmware Descriptor: Add Lock ME Kconfig questionMartin Roth
Add the Kconfig question to allow the user to lock the ME section using ifdtool. Change-Id: I46018c3bc9df3e309aa3083d693cbebf00e18062 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/10648 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-02Move baytrail & fsp_baytrail to the common IFD interface.Martin Roth
- Add the common/firmware subdir to the baytrail & fsp_baytrail makefiles and remove the code it replaces. - Update baytrail & fsp_baytrail Kconfigs to use the common code. - Update the IFD Kconfig help and prompts for the TXE vs ME. - Whittle away at the CBFS_SIZE defaults. All the fsp_baytrail platforms have their own defaults. Change-Id: I96a9d4acd6578225698dba28d132d203b8fb71a0 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/10647 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-02Intel Firmware Descriptor Kconfig: remove USES_INTEL_MEMartin Roth
When I added the common IFD Kconfig and Makefile, My thinking was that I could use this symbol to differentiate between the ME and the TXE, and to exclude the ME questions from platforms that use the IFD, but don't use an ME, like Rangeley. In practice this made things a lot more complicated and isn't worth it. Change-Id: I4428744e53c6bb7fc00a4fa4f0aa782c25fc9013 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/10678 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-01coreinfo: use coreboot's kconfigStefan Reinauer
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Change-Id: I99e612dca3c2e5678d43b3e85eaf2f51d8f693e7 Reviewed-on: http://review.coreboot.org/10715 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-01tegra132: adjust vboot2 memlayout to make coreboot compileStefan Reinauer
romstage didn't fit in it's region anymore. Change-Id: I5a2f41cb0e0a87339dbf61906ee2060e132cc394 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10759 Reviewed-by: Marc Jones <marc.jones@se-eng.com> Tested-by: build bot (Jenkins)
2015-07-01google/veyron_minnie: Add new boardPatrick Georgi
Copied from speedy, with changes to mainboard.c (and speedy -> minnie renames across the directory) Change-Id: Ib38f0b15da8306984869e7ee7b4ddf366b0df82c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10757 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-07-01libpayload: always compile with -ffunction-sectionsStefan Reinauer
Always compile with -ffunction-sections and -fdata-sections This does not hurt, and it allows the linker to produce much smaller binaries in some circumstances. Change-Id: Ibf9f24c210d6d2ed40451b4cf0d68ce88220bc5f Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10750 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-01nvidia/tegra210: Drop unused Kconfig symbolPatrick Georgi
The deleted symbols aren't used anywhere in the coreboot tree and come from the downstream chromeos-2013.04 branch. Change-Id: I0ebc2936dff400cf8fe68794c86ac583aba2a14b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10752 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-01linker scripts: Fix symbol handling for pre-RAM cbmem consolePatrick Georgi
Some ld versions (eg. the one used in the chromium build system) mis-handled the redefined symbol in romstage.ld, so use the feature that exists for precisely that purpose. Change-Id: I184310ab20a02f6b3d569798448eac78b13e88a3 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10754 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-01rockchip/rk3288: Initialize CPU in bootblockPatrick Georgi
Some basic MMU setup is required to allow unaligned memory accesses that happen across our entire codebase. Change-Id: If5a84e19a7a3e47d6009fd073b1323dfb25e6a06 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Found-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/10753 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner@chromium.org>
2015-07-01libpayload: Fix compilation on ARM with GDB enabledStefan Reinauer
Without this, gdb_enter() is not defined. Change-Id: I067dce371ee817d6ac77387fcbe42a9a7deb6438 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10755 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2015-07-01libpayload: Keep stack boundary small on x86Stefan Reinauer
There is no measurable performance impact, but this positively impacts the memory used by payloads. Change-Id: Ib2bdba4a7bf2a4c2391a20b3225bbb44422d3194 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10751 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-01tegra210: Include correct include filesStefan Reinauer
Some include files were unnecessary, and program_loading.h was missing. Change-Id: Ief3d970af5fbbb6b79da06ba3ea1d8613bfc314f Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10749 Reviewed-by: Marc Jones <marc.jones@se-eng.com> Tested-by: build bot (Jenkins)
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-25 14:26:37 +0000