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2023-05-13drivers/net/r8168: add ACPI _STA field entryMatt DeVillier
Add _STA field entry for r8168 ACPI device and set to ACPI_STATUS_DEVICE_HIDDEN_ON in order to hide device from OS (Windows) as there is no driver needed (or available). Windows correctly attaches drivers to the PCIe device, the separate ACPI device is unused and unneeded. Linux is unaffected as it does not use the ACPI device status. Change-Id: Ib7ae99fffcb00e71421b93c2794119841aa239d3 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75177 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-13mb/samsung/lumpy: Adjust touchpad ACPI for Windows driversReddestDream
Adjust the touchpad HID/CID/HRV to allow coolstar's crostouchpad Windows drivers to properly attach. Change the interrupt type from EDGE to LEVEL. TEST=build/boot samsung/lumpy, verify touchpad functional under both Windows 10/11 and Linux, verify Windows overlay driver correctly remaps top row keys. Change-Id: Ie4268b4de5779ee148699c7bef8c700a99816f1e Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75181 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-05-13mb/google/parrot: Adjust touchpad ACPI for Windows driversReddestDream
Adjust the touchpad HID/CID/HRV to allow coolstar's crostouchpad Windows drivers to properly attach. TEST=build/boot google/parrot, verify touchpad functional under both Windows 10/11 and Linux, verify Windows overlay driver correctly remaps top row keys. Change-Id: Ic164244eceb52221653bd60f7217f9a09e38c1b6 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75180 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-13mb/google/butterfly: Adjust touchpad ACPI for Windows driversMatt DeVillier
Adjust the touchpad HID/CID/HRV to allow coolstar's crostouchpad Windows drivers to properly attach. Change the interrupt type from EDGE to LEVEL. TEST=build/boot google/butterfly, verify touchpad functional under both Windows 10/11 and Linux, verify Windows overlay driver correctly remaps top row keys. Change-Id: I971795becfb05fb42921ff6f40a20892f4f5654a Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75179 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-05-13mb/google/stout: Use board-specific PS2M HID/CID to enable multitouchMatt DeVillier
Use board-specific ASL for PS2-attached trackpad rather than the EC/SIO default, so that Windows installs a multitouch-capable driver rather than the standard PS2 mouse driver. TEST=build/boot Win11 on google/stout, verify trackpad is multitouch capable. Change-Id: Id93bbe53f35b1e2c35e36d8175889786b9f5de8b Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75176 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-13sio/smsc/mec1308: fix SIO/PS2 keyboard ACPI for WindowsMatt DeVillier
Add _HID to parent SIO device so Windows can find the PS2K, and remove _ADR since HID and ADR are mutually exclusive. TEST=build/boot Win11 on samsung/lumpy, verify keyboard functional. Change-Id: I7b6b09da1a3fdc34ef43789c699f7fd22b4b655b Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75175 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-05-13ec/quanta/ene_kb3940q/acpi: Fix PS2K under WindowsMatt DeVillier
Add _HID to parent SIO device so Windows can find the PS2K, and remove _ADR since HID and ADR are mutually exclusive. TEST=build/boot Win11 on google/butterfly, verify keyboard functional. Change-Id: I772ceef1b439cfd4e2740e53362bee9d494fb36d Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75174 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-05-13acpi/Kconfig: move \_SB scope out of ACPI_CPU_STRINGFelix Held
In ACPI 1.0 the processor objects were inside the \_PR scope, but since ACPI 2.0 the \_SB scope can be used for that. Outside of coreboot some firmwares still used the \_PR scope for a while for legacy ACPI 1.0 OS compatibility, but apart from that the \_PR scope is deprecated. coreboot already uses the \_SB scope for the processor devices everywhere, so move the \_SB scope out of the ACPI_CPU_STRING to the format string inside the 3 snprintf statements that use the ACPI_CPU_STRING. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Change-Id: I76f18594a3a623b437a163c270547d3e9618c31a Reviewed-on: https://review.coreboot.org/c/coreboot/+/75167 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-05-13soc/amd/*/acpi/mmio.asl,sb_fch.asl: hide MISC deviceFelix Held
Don't set bit 2 of the return value of the _STA method in order for Windows not to show a warning about an unknown device in the device manager for this device. TEST=The unknown device with device instance path ACPI\AMD0040\3 disappeared from the device manager in Windows 10 build 19045 on a Mandolin board with a Picasso APU. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If005f06843956004c281fd70cf364171148cb9ff Reviewed-on: https://review.coreboot.org/c/coreboot/+/68962 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-13soc/amd/*/acpi/mmio.asl,sb_fch.asl: change AAHB's _STA back to methodFelix Held
Commit 396fb3db74db ("soc/amd/*/acpi/mmio.asl,sb_fch.asl: hide AAHB device") didn't only change the visibility of the device, but also changed the _STA method to a name. While this worked, the specification says that _STA is supposed to be a method, so change it back to being a method. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id0932b2875aaf563a4dbd860bdd11a04272e3780 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75169 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-13soc/cavium/cn81xx: Use correct size for MPIDR_EL1 registerArthur Heymans
Clang complains about this. Change-Id: I2d761d2fa946f171033220ab7b2e399cf359782a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74538 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-05-13vendorcode/mediatek/mt8195: Fix set but unused variablesArthur Heymans
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I5738e73f2121e2558831fbaa9c92a2fd0926ad88 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75038 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-05-13vendorcode/mediatek/mt8195: More sure ucDoneFlg is initializedArthur Heymans
One some codepaths ucDoneFlg is not initialized. This fixes a clang warning. Change-Id: I78aa2c711626b24f003f5c95b1c9598eaff7cb1b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74552 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-05-13vendorcode/mediatek/mt8195: Make order of operators more explicitArthur Heymans
Clang warns about this. Change-Id: I9a19f33df64a63e51e3dadac4aae28a8bb12121d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74551 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-05-13vendorcode/mediatek/mt8195: Fix superfluous bracketsArthur Heymans
Clang warns about this. Change-Id: I4310737bd63728d3c592d0f4d1030bc352afa575 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74550 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-05-13vendorcode/mediatek/mt8195: Fix casting enum of different typesArthur Heymans
Clang warns about this. Change-Id: I18ff23c3c18b7cd74f0d6fe0b308b9096ce269ae Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74549 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-05-13vendorcode/mediatek/mt8195: Fix set but unused variablesArthur Heymans
The clang compiler warns about this. Change-Id: I1584258aa24d6a0bf558b3c622bc53c156a37b09 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74548 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-05-13soc/cavium: Guard gcc specific compiler flagArthur Heymans
TEST: BUILD_TIMELESS=1 remains the same. Change-Id: I740b59574303145fc673a97556367daefe8d1540 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74540 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-13vendorcode/cavium: Fix additions to stringArthur Heymans
The clang compiler is confused about adding integers to strings. Adding brackets around the macros fixes this. TEST: BUILD_TIMELESS=1 remains the same. Change-Id: I2ea17322352d977bf0ec3ee71b14463fa218d07c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74541 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-13soc/mediatek/mt8195/apusys_devapc.c: Fix unsigned comparisonArthur Heymans
Clang warns about unsigned comparison below 0. Use the enum value itself to fix this warning. Change-Id: I12fccff2fb7d43fd4582afd518a7eab632908a5f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74553 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-05-13vendorcode/mediatek/mt8192: Fix set but unused variablesArthur Heymans
TEST: BUILD_TIMELESS=1 binary remains the same. Change-Id: Ic05a9819764c03184b54c4fc58dbe325fddeae10 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74543 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-05-13vendorcode/mediatek/mt8192: Fix set but unused variablesArthur Heymans
The binary does change on these with BUILD_TIMELESS. Change-Id: I45d51d53f991556cedd1cc45997d76fc828bceb5 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74544 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-05-13mb/prodrive/hermes: Ensure VMX setting is appliedAngel Pons
VMX is enabled through a bit in the IA32_FEATURE_CONTROL MSR, which can be locked. The MSR remains locked after a non-power cycle reset, though. If the MSR is locked, coreboot bails out and leaves VMX in the state it was found. Because of this, changes to the VMX enable option in the BMC only take effect after the system is power cycled. This behaviour is highly undesirable because users are likely not aware that a power cycle is required for changes to VMX state to take effect. So, if VMX is supported, the IA32_FEATURE_CONTROL MSR is locked and the current VMX state does not match the requested state, then issue a full reset. This will power cycle the system and unlock the MSR, so that the desired VMX state can be programmed into the MSR. This is checked early to avoid needlessly doing time-consuming operations (running FSP) twice if we know we will need to power cycle the system anyway. Note that a user may change the VMX setting after the newly-added check but before the setting is read in ramstage to program the MSR, but this is a non-issue as firmware settings need a reset to take effect anyway. TEST: Toggle VMX setting in BMC and reboot without power cycle, observe coreboot automatically issues a power cycle reset because the MSR is locked and the VMX state differs. Verify that the system boots properly with VMX in the correct state after having power cycled. Change-Id: Id9061ba896a7062da45a86fb26eeb58927184dcb Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75141 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-05-13cpu,nb/amd/pi/00730F01: dynamically generate CPU devicesFelix Held
Instead of having the maximum number of possible CPU objects defined in the DSDT, dynamically generate the number of needed CPU devices in the SSDT like it's done on all other x86 platforms in coreboot. TEST=APU2 still boots and Linux doesn't show any ACPI errors with this patch applied and it prints "ACPI: \_SB_.P000: Found 2 idle states". Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id6f057ad130a27b371722fa66ce0a982afc43c6c Reviewed-on: https://review.coreboot.org/c/coreboot/+/73073 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-05-13nb/amd/pi/00730F01: request binaryPI to use \_SB_ scope in PSTATE SSDTFelix Held
Instead of having binaryPI generate a PSTATE SSDT that uses \_PR_ as the scope for the CPU objects and patching this SSDT in coreboot to use the \_SB_ scope in patch_ssdt_processor_scope, request binaryPI to use the \_SB_ scope instead by setting the late platform configuration option ProcessorScopeInSb to true. TEST=APU2 still boots and Linux doesn't show any ACPI errors with this patch applied and it prints "ACPI: \_SB_.P000: Found 2 idle states". Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I411201b55cfee30ae41da4e6814679bdb49e9bf7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73386 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-05-12MAINTAINERS: Add Felix Singer to util/dockerFelix Singer
Change-Id: Ic2efbb1d2a13212921ad110314a6394a4dca6a8a Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72918 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-05-12soc/intel/apl: Remove set but unused variableArthur Heymans
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I62b7390c2de244cce169550e9b1fa41af738525d Reviewed-on: https://review.coreboot.org/c/coreboot/+/75037 Reviewed-by: Jan Samek <jan.samek@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-05-12soc/mediatek/mt8183: Fix set but unused variablesArthur Heymans
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I1c995d942fa25a9268fbf716034335937df57714 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75036 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-05-12soc/qualcomm/sc7180: Fix set but unused variablesArthur Heymans
This fixes clang warnings. Change-Id: I407da6ec05ef646f61bd81e314fee1b5ea659192 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74557 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-05-12vendorcode/cavium: Fix set but unused variablesArthur Heymans
TEST: BUILD_TIMELESS=1 remains the same. Change-Id: Id2cb37dbe4d450fe7f91a527b5cd73ac55863548 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74542 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-05-12mb/prodrive/hermes: Simplify handling board cfgAngel Pons
The `get_board_settings()` function always returns non-NULL, so there is no need for NULL checks. When only one member is accessed, also drop the local variable and directly dereference the function's return value. Change-Id: I4fc62ca2454f4da7c8ade506064a7b0e6ba48749 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75140 Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-05-12drivers/ocp/ewl: Add EWL driver for EWL type 3 error handlingJohnny Lin
1. Restore the reverted 'commit 059902882ce5 ("drivers/ocp/ewl: Add EWL driver for EWL type 3 error handling")'. 2. Print more EWL type 3 error information when it occurs. Change-Id: Ib83b7653a839d18a065b929127549acd10bce7a7 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69280 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jon.zhixiong.zhang@gmail.com>
2023-05-12mb/siemens/mc_ehl5: Add PTN3460 eDP-to-LVDS bridgeMario Scheithauer
This mainboard contains in addition to its base variant, mc_ehl2, an LCD panel driven through the PTN3460 eDP-to-LVDS bridge. This patch enables the PTN3460 support by adding the device to devicetree.cb and board-specific configuration parameters in lcd_panel.c. BUG=none TEST=Boot with the LCD panel attached and observe whether the picture is stable and free of artifacts coming from wrong resolution and timing. Change-Id: I196d7ceeb7ac241c9b95db2ef791a5f3ff7890a7 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74936 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jan Samek <jan.samek@siemens.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2023-05-12mb/siemens/mc_ehl5: Add new board variant based on mc_ehl2Mario Scheithauer
This mainboard is based on mc_ehl2. In a first step, it contains a copy of mc_ehl2 directory with minimum changes. Special adaptations for mc_ehl5 mainboard will follow in separate commits. Change-Id: Id80f8eb49dd2fed0ed1ffc479d47d8669eca84c9 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74935 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2023-05-12mb/google/nissa/var/uldren: Fix Touch screen power sequenceIan Feng
Based on touchscreen product spec. For uldren variants with a touchscreen, drive the enable GPIO high starting in romstage while holding in reset, then disable the reset GPIO in ramstage (done in the baseboard). BUG=b:279989974 TEST=Build and boot to OS in uldren. Touch screen is workable. Change-Id: Ib1b1ce80aa1dd8c312e3663fc50c9e9f53cc07fe Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74835 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-05-12mb/prodrive/atlas: Shorten FSP-M UPD statementsAngel Pons
Replace `memupd->FspmConfig.` with `mcfg->` for the sake of brevity. Change-Id: If2e7cccca955b0c1e07c1ecf100d29a923107856 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75136 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com>
2023-05-12mb/google/rex: Set WWAN_RF_DISABLE_ODL to NCTarun Tuli
This signal isn't functionally being used and is causing leakage during suspend. Set it to NC. BUG=b:279762779 TEST=builds. WWAN functional. Change-Id: I93f2b0a781e250678280b57e4ab1d80ef27ff460 Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75053 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-05-12soc/intel/common: Define enum types for MKHI group IDs and ME SKUsSridhar Siricilla
The patch defines enum type for MKHI group IDs and ME SKU types instead of macros. TEST=Build code for Rex Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I102e802938a6a664a43a362d90a26755cff8f316 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74996 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Harsha B R <harsha.b.r@intel.com> Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
2023-05-12soc/intel/common: Remove superfluous cmos_offset from ramtopSean Rhodes
Having `_cmos_offset` in a CMOS offset is superfluous; remove it so the CMOS entry is just `ramtop`. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ibc1e7d78d2e3ae04330d19e64c3437ff07060ea8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74516 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-05-12mb/prodrive/atlas: Make default SN/PN not emptyAngel Pons
If reading the serial/part number fails, returning an empty string is very confusing. Instead, return "INVALID" to make problems obvious. Change-Id: I3c174ca76d51b44456c7b68f4fcffb4c8f9379be Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75132 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com>
2023-05-12mb/asus/p8z77-m: Make onboard NIC a child device below PCIe port 5Fabian Groffen
The Realtek RTL8111F NIC is currently not defined at all, nor as a child device, resulting in the on_board flag not being set to 1. This means that Linux / udev will call the device enp3s0 rather than eno0, as it's appropriate for on-board ethernet devices. Signed-off-by: Fabian Groffen <grobian@gentoo.org> Change-Id: I95f01a466a59234d1cbe2420f208bf58ae28fcc6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75106 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-05-12mb/asus/p8z77-m: Add TPM configFabian Groffen
This board has a TPM connector, enable support for it. Signed-off-by: Fabian Groffen <grobian@gentoo.org> Change-Id: I1861df95eef15bc2bd29412240d61456eaaad8c9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75105 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-05-12mb/google/brya: Fix typo in gma-mainboards filenameTarun Tuli
Small typo in brask/gma-mainboards-ads Should be brask/gma-mainboards.ads BUG=b:277861633 BRANCH=firmware-brya-14505.B TEST=Builds Change-Id: I9800870dcef13a3e16f6235137e79234a5e6bf83 Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75052 Reviewed-by: Eran Mitrani <mitrani@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-05-11acpi/acpigen: add acpigen_resource_io to generate I/O resourceFelix Held
Add the acpigen_resource_io helper function to generate an I/O range resource. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I177f59b52d4dbbff0a3ceeef5fc8c7455cef9ff8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75044 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
2023-05-11acpi/acpigen: add acpigen_resource_bus_number to generate bus numberFelix Held
Add the acpigen_resource_bus_number helper function to generate a bus number range resource. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Ib1f1da3dbe823c6bc4fc30c0622653410cfbf301 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75043 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
2023-05-11drivers/pcie/generic: Add DmaProperty to configMark Hasemeyer
Adds the option to set the 'DmaProperty' in the device's _DSD. This can be done by setting "add_acpi_dma_property"="true". If not set (or set to false), the device descriptor generation behavior will remain unchanged. The naming convention for the config option was chosen to match that of other drivers. This partially reverts commit 5609f7a684c6 ("drivers/pcie/generic: Clean up driver") as the driver is now used on a couple mainboards which need the DmaProperty. Change-Id: I996fe4923948d13a20bf8b6b1a93dab0866d0fd4 Signed-off-by: Mark Hasemeyer <markhas@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75094 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jan Samek <jan.samek@siemens.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-05-11soc/intel/apollolake: Only use 8 bits for afterg3Sean Rhodes
In GEN_PMCON1 (Offset 1020h), Bit 0 is the "After G3 Enable" (ag3e) (source Intel document #569262). Only use 8 bits, in the same way as most other Intel SOCs do, for pmc_soc_set_afterg3_en. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Idb290d1480b03cb3425edc6ff29b9c78a6545df1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74955 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-11util/scripts/show_platforms.sh: Fix reStructuredText table outputNicholas Chin
reStructuredText grid tables require row separators otherwise the rows get concatenated into a single cell for each column. Representative output of previous behavior: ```eval_rst +-------------------------+-------------------+------------+----------+ | Vendor/Board | Processor | Date added | Brd type | +=========================+===================+============+==========+ | 51nb/x210 | INTEL_KABYLAKE | 2020-03-16 | laptop | | acer/aspire_vn7_572g | INTEL_SKYLAKE | 2022-01-28 | laptop | | acer/g43t-am3 | INTEL_X4X | 2020-09-28 | desktop | +-------------------------+-------------------+------------+----------+ ``` Representative output of corrected behavior: ```eval_rst +-------------------------+-------------------+------------+----------+ | Vendor/Board | Processor | Date added | Brd type | +=========================+===================+============+==========+ | 51nb/x210 | INTEL_KABYLAKE | 2020-03-16 | laptop | +-------------------------+-------------------+------------+----------+ | acer/aspire_vn7_572g | INTEL_SKYLAKE | 2022-01-28 | laptop | +-------------------------+-------------------+------------+----------+ | acer/g43t-am3 | INTEL_X4X | 2020-09-28 | desktop | +-------------------------+-------------------+------------+----------+ ``` Change-Id: I83be58dd2c34c65ae2c65cf2bd98330936fb6f6a Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72624 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-05-11mb/google/brya: Create gothrax variantYunlong Jia
Create the gothrax variant of the nissa reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0.). BUG=279614675 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_GOTHRAX Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com> Change-Id: I129e4a55e4b87091e425a45392024d04f3977c79 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74748 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-05-11mb/google/dedede/var/boxy: Disable EXT_VRKevin Yang
The boxy removed the APW8738BQBI-TRG and "disable_external_bypass_vr" should be set to "1" to disable BUG=b:271407334 TEST=emerge-dedede coreboot Signed-off-by: Kevin Yang <kevin3.yang@lcfc.corp-partner.google.com> Change-Id: Ic6667e93de41e84f67363ab7554fe755fe50684a Reviewed-on: https://review.coreboot.org/c/coreboot/+/74889 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-11mb/google/dedede/var/boxy: Update devicetree and GPIO tableKevin Yang
Create overridetree and GPIO config based on latest schematic: 1. Update PCIe ports 2. Update USB ports 3. Remove unused I2Cs 4. Remove unused peripherals (SD card, eDP, speakers) 5. Add LAN 6. Thermal policy for updated temp sensors BUG=b:277529068 BRANCH=dedede TEST=build Signed-off-by: Kevin Yang <kevin3.yang@lcfc.corp-partner.google.com> Change-Id: I5a155ebca50dbd5bdb046713ebabbee395361273 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74626 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-05-11soc/intel/cmn/blk.cse: Fix check condition in store_cse_rw_fw_version()Dinesh Gehlot
The return value of cse_get_bp_info() is an enum integer, where zero means success and non-zero means failure. The function store_cse_rw_fw_version() calls the function cse_get_bp_info() and validates the return value as a boolean causing prematurely returns of the parent API even if cse_get_bp_info() is successful. This patch corrects this logical error by returning only if cse_get_bp_info() fails. TEST=Build and boot google/nivviks and verify that the ISH version info command is only being sent during cold boot. Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: Ice278e5ac69ff2f2c9f1936b76d71ae9deb6f855 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74998 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2023-05-11acpi/acpi.c: Assign coreboot_rsdp for QEMUBin Meng
At present coreboot_rsdp remains unset for QEMU, which results in an incomplete LB_TAG_ACPI_RSDP coreboot table generated. Fix this by assigning coreboot_rsdp properly. TEST=Build coreboot for QEMU x86 i440fx (default) with U-Boot x86 as the payload, boot coreboot.rom with QEMU, and run 'acpi list' from U-Boot shell to show the ACPI tables. Signed-off-by: Bin Meng <bmeng@tinylab.org> Change-Id: I5bc3f0528d4431fd388ca52b8865f9be0e1faf92 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75088 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
2023-05-11mb/google/brya/variant/hades: Reduce PEXVDD shutoff delay for HadesTarun Tuli
For the sequenced controlled shutdown path, there's a 10ms delay after the PEXVDD rail is disabled to permit discharge needed on Agah/Proxima. This can be dropped to 3ms for Hades designs Proto0 and forward. Once Agah board is dropped, "if CONFIG" can be cleaned up/removed. BUG=b:271167335 TEST=builds Signed-off-by: Tarun Tuli <taruntuli@google.com> Change-Id: I8a0d62ec76caff861adce2d6c0ba2d4e4064affa Reviewed-on: https://review.coreboot.org/c/coreboot/+/75051 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-11mb/siemens/mc_apl5: Set Full Reset Bit into Reset Control RegisterMario Scheithauer
With the introduction of a new Linux version a problem has appeared after a software initiated reset via CF9h register. The problem manifests itself in the fact that the Linux kernel does not start after the reboot. The problem is solved by setting bit 3 to 1 in Reset Control Register (I/O port CF9h). This leads to the fact that the PCH will drive SLP_S3 active low in the reset sequence. It leads to the same behavior as in commit 04ea73ee78bc ("siemens/mc_apl3: Set Full Reset Bit into Reset Control Register") explained. Change-Id: Ia8b7f997ca6234add569da751e1070144790e258 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75041 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jan Samek <jan.samek@siemens.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2023-05-11mb/siemens/mc_apl: Correct multi-line comment style for all Siemens APL BoardsMario Scheithauer
Change-Id: I6578aee52e6900b25441dc119383856acc480231 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75042 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jan Samek <jan.samek@siemens.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2023-05-11mb/siemens/mc_ehl: Remove '_' from mainboard model option in Kconfig.nameMario Scheithauer
An underscore has crept into the mainboard model option for mc_ehl3 and mc_ehl4 by mistake. This patch fixes the incorrect entry. Change-Id: Ie59619877fb6341a5bbfe91c13e7692943480ad0 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75040 Reviewed-by: Jan Samek <jan.samek@siemens.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-11mb/siemens/mc_ehl1: Use SSD type for SATA portsMario Scheithauer
There are only SSD connected to SATA ports on this mainboard. To prevent misbehavior, set the correct hard drive type for enabled SATA ports. BUG=none TEST=Boot into OS and check the stability of the SSD Change-Id: I116b1e36f0582956604c3c2508961ffb3de0898a Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74947 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jan Samek <jan.samek@siemens.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2023-05-11Documentation: Fix broken URLsNicholas Chin
- VBT information: The link from 01.org is dead, but appears to have been identical to the i915 page in the Linux kernel docs based on snapshots on archive.org. - Cgit: coreboot no longer has cgit running for the repos it hosts, and these links redirect to the Gitiles list of repos hosted on review.coreboot.org. Based on snapshots on archive.org, these used to link to the individual repo or tree. Replace these with an equivalent Gitiles link. Change-Id: Id0bfee7b806c851fbe1dcf357e14d9b593e8569a Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74188 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Patrick Georgi <patrick@coreboot.org>
2023-05-11soc/intel/common: Fix long delay when ME is disabledSean Rhodes
If the ME is disabled with the `me_state` CMOS setting, boot times are approximately 5 seconds longer: 942:before sending EOP to ME 1,240,773 (5,599) 943:after sending EOP to ME 6,263,951 (5,023,177) Total Time: 6,167,443 This is because the current code only checks if the ME is disabled for CSE LITE SKUs. With this patch, boot times are approximately 5 seconds quicker: Total Time: 1,143,932 Tested on `starbook/adl` and `starbook/tgl`. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I182f30d4fbf43955747c6a7a0b284a43f9c5e4ef Reviewed-on: https://review.coreboot.org/c/coreboot/+/74435 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-05-11util/inteltool: Add ADL-S device identificationsMaximilian Brune
R680E, Q670E, H610E are the ADL-S IoT variants see also: commit a0bc90e4abfe ("Add missing ADL-S device identification") Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I1dbfa0464bc22f9bcf91d9e9fa9eb79132600175 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74360 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-05-11vc/intel/fsp/mtl: Update header files from 3084_85 to 3165_81Kilari Raasi
Update header files for FSP for Meteor Lake platform to version 3165_81, previous version being 3084_85. FSPM: 1. Change UPD name from 'GtExtraTurboVoltage' to 'GtAdaptiveVoltage' 2. Change UPD name from 'CoreVoltageAdaptive' to 'CoreAdaptiveVoltage' 3. Change UPD name from 'RingVoltageAdaptive' to 'RingAdaptiveVoltage' 4. Address offset changes FSPS: 1. Remove deprecated UPD 'PcieDpc' 2. Address offset changes BUG=b:280005256 TEST=Able to build and boot google/rex to ChromeOS. Signed-off-by: Kilari Raasi <kilari.raasi@intel.com> Change-Id: I67939ecf71166fca4f3d2d6cd4622215bebc5718 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74803 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-05-11soc/intel/meteorlake: Increase pcie snoop/non-snoop latencyRavi Sarawadi
This fixes an issue where pcie was not power gating and blocked S0ix entry. Overwrite pcie max non-snoop and snoop latency tolerance values to 15.73ms as stated in doc #729123 - MTL External Design Specification. BUG=none TEST=Boot google/rex, print/check values. Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.corp-partner.google.com> Change-Id: I9dfb9edbac95d28d50653777466ea172be64f612 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68308 Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-11Documentation/tutorial: Improve clarity of Part 1Nicholas Chin
Based on feedback and experiences from new coreboot users, it isn't clear that Tutorial 1 is mainly intended to set up the toolchain and will not produce a bootable ROM for their board. Thus, add a note explicitly mentioning this with a short explanation. The process of manually building and adding the payload is also unusual, since payloads are usually handled automatically by the build system. This adds a note in the summary to provide an explanation of this. The savedefconfig output is also outdated, as Kconfig now outputs additional lines (even though many of those are the same as the defaults). This has caused confusion, leading users to think that they may have configured coreboot incorrectly. Update this to the current defconfig contents and add a note that this may change depending on the coreboot version. Change-Id: I13206aa05a425ddfe33ee35feff0db490585a59f Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73816 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-10soc/intel: Clean up some includesKyösti Mälkki
Change-Id: Ibb680bb8f94fb8a2812f420ac38f15684b5c0b4f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74978 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-05-10sb,soc/amd,intel: Sync FADT entries visuallyKyösti Mälkki
Change-Id: I20a66dce1612ab4394c26f9b0943dac14bcdcfc4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74912 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-05-10Documentation/contributing: Update sign-off procedureNicholas Chin
The Linux kernel recently updated the wording of their sign-off procedure, changing the ambiguous "real name" requirement to "a known identity" and dropping "no pseudonyms". Anonymous contributions remain uncommittable [1]. As discussed in the April 19, 2023 leadership meeting, update our policy to go along with Linux and flashrom (who also updated their policy). [1] Linux kernel commit d4563201f3 (Documentation: simplify and clarify DCO contribution example language) Change-Id: Ie676334f7c1509524adcb8dbb78495fb4da35ede Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74851 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <patrick@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-05-10Documentation/contributing: Add sign-off procedureNicholas Chin
Currently, this only exists on the old wiki and the developers.html page on coreboot.org, but it really ought to be somewhere in the new docs alongside the other contribution guidelines. This was largely copied from the text from the developers.html page. Change-Id: If50b3827ab36234719f9a90239caec4612eb6762 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74825 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-05-10soc/intel/cmn/pcie: Allow SoC to overwrite snoop/non-snoop latencyBora Guvendik
The Intel SoC Meteor Lake requires a higher pcie max non-snoop and snoop latency tolerance. Add config to let SoC overwrite the common code settings if needed. BUG=none TEST=Boot google/rex and print/check if able to overwrite values. Change-Id: Ic2b9a158d219e6c6e7f6e7f0ae0f093c1183b402 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74141 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-05-10soc/intel/elkhartlake: Make hard drive type for SATA ports configurableMario Scheithauer
Intel's EHL FSP offers the possibility to select the connected hard drive type to SATA ports. One has the option to choose between HDD ('0' - default) and SSD ('1'). This patch provides a chip config so that this FSP parameter can be set as needed in the devicetree on mainboard level. Change-Id: Idb03aff5b6c5df592b47e2f4abe4fe58ac7151ba Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74946 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-05-10mb/amd/mayan: Enable MXM PCIe slotAnand Vaikar
Follow the EC GPIO programming sequence to enable the MXM PCIe slot. Change-Id: I75d7ac488bb005751e6f674ab9a2fd99baad571b Signed-off-by: Anand Vaikar <a.vaikar2021@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74308 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-05-09mb/google/link: Apply symmetry for EC events definesKyösti Mälkki
All other boards use MAINBOARD_ prefix instead of board name. Change-Id: I97d9d28963c97e780156d75b39deac069028866a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74602 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-05-09arch/x86/car.ld: Fix undefined macroArthur Heymans
Processing LD flags is done without most warnings enabled, which is why this never caused problems. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Ic9d82c1426a1c1d2f21c8e7560685cf9d7106a88 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75033 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-09mb/google,intel: Use common ChromeEC code for lid shutdownKyösti Mälkki
Change-Id: I4d34e5c094440dad4a6ab9adc67d3da6b71ac2bf Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74514 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-05-09mb/google,intel: Use common ChromeEC code for SMI APMCKyösti Mälkki
Change-Id: If4b7c2b94e0fec84831740336ccdbea0922ffbfe Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74513 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-05-09mb/purism: Move selects from Kconfig.name to KconfigFelix Singer
Selects should be done in the Kconfig file instead of Kconfig.name. Change-Id: I2ae03a3ac548674b8c5e7dfaff47d6c536b452f1 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75013 Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-09sb,soc/amd,intel: Apply minor FADT fixesKyösti Mälkki
Change-Id: I27a610255e5680be1b507d45c6695cf9419ee052 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74911 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-05-09mb/google,intel,samsung: Use common poweroff()Kyösti Mälkki
Change-Id: I3881c152663a038833d8126d7f24f2a6688426d1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74515 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-09soc/intel/xeon_sp/spr: Drop spurious FADT fieldsKyösti Mälkki
Assigning duty_offset while duty_width==0 has no purpose. Under intel/common/block, previous assignment for fadt->gpe0_blk resolves GPE0_STS(0) from xeon_sp/ebg/.../soc_pm.h and also assigns value matching pmbase + 0x60. Change-Id: Iaf688d9471ac527ac20307cf16216abdab731a06 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74827 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-09mb/google/corsola: Enable HIMAX83102_J02 and ILI9882T panel for StarmieRuihai Zhou
The STA_HIMAX83102_J02 and STA_ILI9882T panel will be used for Starmie, enable these two panels config for it. BUG=b:272425116 BRANCH=corsola TEST=build starmie and check the cbfs include the panels Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Change-Id: I1dd696dd6a84d9606e4b9a2d4884dd70a6df9161 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74200 Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-09drivers/mipi: Add support for STA_ILI9882T panelRuihai Zhou
Add STA_ILI9882T panel serializable data to CBFS. The panel datasheet: ILI9882T_Datasheet_20220428.pdf BUG=b:275470328 BRANCH=corsola TEST=build and check the CBFS include the panel Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Change-Id: Ia7a37c0659f0959fe7be01aba0f08d63119d139f Reviewed-on: https://review.coreboot.org/c/coreboot/+/74871 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com>
2023-05-08Revert "soc/amd/cezanne/romstage: Preload fspm.bin"Raul Rangel
This reverts commit d6e0a90aa0bd574b28b6c9b4b46289bf46a208db. Reason for revert: Not ready to land, blocked by ancestor CL Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ic14e17db4aed2f998878920c66cdc16362920dcb Reviewed-on: https://review.coreboot.org/c/coreboot/+/75050 Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-08drivers/pc80/rtc/mc146818rtc.c: Add Kconfig for RTC CMOS base addressesJonathon Hall
Configure the CMOS bank I/O base addresses with PC_CMOS_BASE_PORT_BANK* rather than hard-coding as 0x70, 0x72. The defaults remain the same. Change-Id: Ie44e5f5191c66f44e2df8ea0ff58a860be88bfcf Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74903 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-08drivers/pc80/rtc/option.c: Allow CMOS defaults to extend to bank 1Jonathon Hall
CMOS defaults greater than 128 bytes long will extend to bank 1. Change-Id: I9ee8364d01dd8520be101de3f83d2302d50c7283 Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74902 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-05-08soc/amd/cezanne/romstage: Preload fspm.binRaul E Rangel
FSP-M is normally memmapped and then decompressed. The SPI DMA controller can actually read faster than mmap. So by reading the contents into a buffer and then decompressing we reduce boot time. It is interesting that FSP-M takes an additional 8ms to execute. I suspect since we call it 50ms earlier it's having to wait for one of its dependencies. BUG=b:179699789 TEST=Boot guybrush and see 30ms reduction in boot time | 970 - loading FSP-M | 0.316 | 0.997 Δ( 0.68, 0.05%) | | 17 - starting LZ4 decompress (ignore for x86) | 0.026 | 13.874 Δ( 13.85, 0.96%) | | 18 - finished LZ4 decompress (ignore for x86) | 64.361 | 0.337 Δ(-64.02, -4.43%) | | 2 - before RAM initialization | 0.534 | 0.529 Δ( -0.01, -0.00%) | | 950 - calling FspMemoryInit | 1.455 | 1.132 Δ( -0.32, -0.02%) | | 951 - returning from FspMemoryInit | 207.695 | 216.537 Δ( 8.84, 0.61%) | Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I850b1576501753a355e7b23745e04802a0560387 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58988 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-05-08mb/purism/librem_cnl: Use EC BRAM bank 1 as CMOS memory bank 1Jonathon Hall
Librem Mini v1/v2 has an automatic power-on setting provided by the EC in BRAM bank 1. Use this bank as the high bank of CMOS memory so that setting can be described in cmos.layout. Change-Id: Icb87bc521f71aa4350c8f5a64fc2cbe7a7a8c808 Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74904 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-05-08soc/amd/phoenix/include/xhci: add USB4 XHCI device pointersFelix Held
Beware that there's no XHCI2 controller and the USB4 controller device pointers were added right after the xhci_0 and xhci_1 controller device pointers. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I14725d4b546ffcca42e21bbe7756babaaff8fea3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74658 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-05-08acpi/acpigen: add acpigen_write_BBN to generate base bus number methodFelix Held
Introduce acpigen_write_BBN to generate the ACPI method object that returns the base bus number for a PCI(e) host bridge. When called, the base_bus_number argument must be the first PCI bus number that got assigned to the corresponding host bridge. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib67bf42b9c77c262d8a02d8f28ac5cb8482136b9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74991 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
2023-05-08drivers/mipi: Add support for STA_HIMAX83102_J02 panelRuihai Zhou
Add STA_HIMAX83102_J02 panel serializable data to CBFS. The panel datasheet: HX83102-J02_Datasheet_v03.pdf. BUG=b:272425116 BRANCH=corsola TEST=build and check the CBFS include the panel Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Change-Id: I382bdc89e5a217fd1c28e677938f454dc09725cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/74084 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com> Reviewed-by: Yidi Lin <yidilin@google.com>
2023-05-08util/amdfwtool: Consolidate entry line regex patternKarthikeyan Ramasubramanian
There are 2 regex patterns defined to process the lines from *fw.cfg: 1) for lines with mandatory entries 2) for lines with mandatory + optional entries Consolidate the regex pattern. Add enums for matching regex caller groups so that the human readable group IDs can be used instead of magic numbers. BUG=None TEST=Build Skyrim BIOS which only have mandatory entries. Build Guybrush BIOS image which have both mandatory and optional entries. Confirm that the amdfw.rom built before and after this change have matching SHA in both Skyrim and Guybrush images. This ensures that the optional level entries in Guybrush are handled as expected. Boot to OS in Skyrim. Change-Id: I7289ddbbec4d5daefe64f59b687ba3a4af46d052 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74950 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2023-05-08mb/google/myst: Add selective FP initJon Murphy
Add FW_CONFIG item for FP sensor init and conditionally init the GPIOs based on whether we're using a SPI or UART FP sensor. BUG=b:276939271 TEST=builds Change-Id: I9815bd17df1d15f73529beb15d08cde1ef90efad Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74958 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-05-08mb/google/myst: Add eMMC/NVMe config supportJon Murphy
Add FW_CONFIG item for eMMC/NVMe support and address the init of the lanes based on said config. BUG=b:278877257 TEST=builds Change-Id: Id6452f497cf78549b7d6126f1b55cd6d45b403c3 Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74957 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Mark Hasemeyer <markhas@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-05-08soc/intel/early_graphics: support to allow early graphics GPIO configTarun Tuli
For early Sign of Life to work, we may need certain pin configurations very early in boot (e.g. HDMI). This may happen before romstage GPIOs are configured, and bootblock is not suitable for field upgrading existing devices. Add a separate GPIO table that can be configured when early graphics is invoked. BUG=b:277861633 BRANCH=firmware-brya-14505.B TEST=Builds and SoL functions on HDMI enabled variants Change-Id: I7b3ce96a4166451e72aa70b3086eff3fb8b082b7 Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74697 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
2023-05-08mb/google/brya: Split gma-mainboards for different baseboardsTarun Tuli
Allow different gma-mainboards configs for different baseboards as they support varying display interfaces. Set Brya to eDP only and Brask to HDMI only. BUG=b:277861633 BRANCH=firmware-brya-14505.B TEST=Builds and SoL functions on both brya and brask varaints Change-Id: Iaf3f35b009d53e50723e4aa82c0f4932783f9bb9 Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74696 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
2023-05-08mb/google/rex/var/rex0: Correct _PLD values for USB C0Won Chung
Denote the correct value of ACPI _PLD for USB ports. The horizontal position of port C0 is incorrectly labelled. +----------------+ | | | Screen | | | +----------------+ C0 | | A0 | | C1 | | +----------------+ BUG=b:216490477 TEST=emerg-rex coreboot Signed-off-by: Won Chung <wonchung@google.com> Change-Id: Id9ed435ca0af131e3bb4538701fc97d78146899f Reviewed-on: https://review.coreboot.org/c/coreboot/+/74366 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-08drivers/gfx/generic: Add _PLD support to GFX deviceWon Chung
Add _PLD support to GFX device so that each display output can store its physical location of connection point. This is to be used primarily for describing DP on USB-C ports in the future patches. The upstream Linux kernel now has a feature to compare _PLD of Type C connectors and DP connectors to link them together. https://cgit.freedesktop.org/drm/drm-misc/commit/?id=c5c51b2420625faa1f0e363f21dba1de53806ff7 This feature allows us to tell which display output is used by which USB-C port. So, for the future boards, we want to add _PLD for each DP connector matching with the corresponding USB-C port. BUG=b:277629750 TEST=emerge-${BOARD} coreboot Signed-off-by: Won Chung <wonchung@google.com> Change-Id: I393207746a9e82c1fd7622ab3661d7b1232cb62f Reviewed-on: https://review.coreboot.org/c/coreboot/+/74365 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-05-08drivers/i2c: Add PI7C9X2G608GP PCIe switch driver (pi608gp)Jan Samek
This patch adds some of the variety of configuration options exported by the Pericom Inc. PI7C9X2G608GP PCIe switch over its SMBus interface. Currently implemented options are only used to adjust the switch upstream port amplitude and de-emphasis levels in millivolts. Only values specified in the switch datasheet (in tables 6-6 and 6-8) are allowed. Example of a devicetree.cb entry: chip drivers/i2c/pi608gp register "gen2_3p5_enable" = "true" register "gen2_3p5_amp" = "AMP_LVL_MV(425)" register "gen2_3p5_deemph" = \ "DEEMPH_LVL_MV(37, 5)" device i2c 0x6f on ops pi608gp_ops end end Link to the datasheet: https://web.archive.org/web/20210225074853/https://www.diodes.com/assets/Datasheets/PI7C9X2G608GP.pdf BUG=none TEST=Create devicetree.cb and Kconfig entries for this driver in a mainboard containing the switch and verify, that the values read out from the switch config space match the values programmed over the SMBus. Change-Id: Id191c4e97b99da58efd3ba38bf8cca3603ece4d5 Signed-off-by: Jan Samek <jan.samek@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74433 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2023-05-08mb/google/nissa/var/uldren: Update eMMC DLL settingsDtrain Hsu
Update eMMC DLL settings based on Uldren board. BUG=b:280120229 TEST=executed 10 cycles of cold boot successfully Change-Id: I46e2f9df0e82e66fa3ae32aa87b4bcf30d5737ab Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74925 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-05-08mb/google/nissa/var/yavilla: Add G2touch touchscreen supportTony Huang
Update devicetree to support G7500 touchscreen. BUG=b:273791621 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot and check touchscreen function Change-Id: I3b63b1bb45275ad7eef8799dcff27f264739c258 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74942 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-05-08mb/google/volteer/Kconfig: Add variant model namesMatt DeVillier
Change-Id: Id5b0fa96ca8d86ddf20d808f5107a43ad2d0a1e0 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74854 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>