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2023-05-18cpu/qemu-x86/cache_as_ram_bootblock: drop duplicated post codeAlexander Goncharov
Before the bootblock stage starts setting up the CAR mode, it sends `POST_BOOTBLOCK_CAR` POST code. However, before the definition for `POST_BOOTBLOCK_CAR` was introduced in the commit 0d34a50a360228138ade623e799b03eaba83b0a5 , the value `0x20` was used. At that point, `0x20` means "entry into CAR mode" and `0x21` means "the cache memory region is cleared". Right now we are sending the same POST code twice, which makes no sense. So we can do the following (todo: drop me after we decided which one is more appropriate): 1) Drop it (current patchset does exactly that) 2) Introduce POST code similar to POST_SOC_CLEARING_CAR and use it before the cache memory region is cleared. Change-Id: I5d9014c788abdf5a4338c9e199138d1e514450b3 Signed-off-by: Alexander Goncharov <chat@joursoir.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73744 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-05-18mb/amd/birman: Don't select the console UART, default to yMartin Roth
Things with prompts should not use selects, but should instead default to y. If there's a reason they need to be selected, they should be able to be hidden when they're selected. This isn't one of those cases where a select is needed, so set the default to y instead. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: If6de339c3a1ceb3cd71008402bba49b5efc4af3f Reviewed-on: https://review.coreboot.org/c/coreboot/+/75131 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-05-18Myst: Update Makefile to remove SPD injectionMartin Roth
The SPD format in the APCB has changed for Phoenix, and the injection tool 'apcbtool' needs to be updated to match. Until this happens, the APCB will be built containing the correct SPD. BUG=b:281983434 TEST=Build Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: If575f98511c796e93c5a12cd450a3a7985e39806 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75143 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com>
2023-05-17util/docker: Add Dockerfile for Arch LinuxFelix Singer
Add a minimal Dockerfile that pre-installs necessary software which is needed to work with coreboot. Change-Id: I85f3dc7b28b77989f0f1400d1282ed4b17082f65 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74481 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2023-05-17nb/intel/i440bx: Clear memory errors before ending raminitKeith Hui
i440BX datasheet says all memory errors reported during RAM init should be ignored. Do as it says. Change-Id: Iaf85fde813aa083ae62218a2df5aec303e3c9f8c Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73952 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-17nb/intel/i440bx, mb/asus/p3b-f: Abolish disable_spd()Keith Hui
This hook is specifically for asus/p3b-f so its mainboard code has a chance to put SPD away after RAM init completes. What it intends to do is done when GPO gets programmed in ramstage (and it's safe to do so), and no other board needs this hook, so drop it. Change-Id: Ib7874b4d2b69fdaa5f3c5a3421a62a629c4154a4 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73951 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-05-17acpi: Warn on timeout in write_delay_until()Cliff Huang
Make ACPI code print a debug warning message when a timeout is detected in a loop waiting for a condition. This timeout message won't be displayed when this function is used as delay loop (ie. without checking variable condition). The following is required to get this log in kernel log buffer: echo 1 > /sys/module/acpi/parameters/aml_debug_output Here is an example of generated code when waiting for variable L23E to be 0. Local7 = 0x08 While ((Local7 > Zero)) { If ((L23E == Zero)) { Break } Sleep (0x10) Local7-- If ((Local7 == Zero)) { Debug = "WARN: Wait loop timeout for variable L23E" } } BRANCH=firmware-brya-14505.B TEST=Boot to OS and check that the Debug print is added to the function. Change-Id: I3843e51988527e99822017d1b5f653ff2eaa7958 Signed-off-by: Cliff Huang <cliff.huang@intel.com> Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73348 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-05-17mb/google/nissa/var/pujjo: Add GPIO setting for WWAN_5GLeo Chou
Pujjoteen5 support WWAN 5G device, add GPIO setting for WWAN 5G device BUG=b:281943398 TEST=Build and check serial log Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Change-Id: Ie2e0ea34c54a453645d626f892f50654ef5064ce Reviewed-on: https://review.coreboot.org/c/coreboot/+/75195 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-17mb/google/nissa/var/pujjo: Enable PCIe port 3 for WWAN_5GLeo Chou
Pujjoteen5 support WWAN 5G device, enable PCIe port 3 for WWAN 5G device BUG=b:281943398 TEST=Build and boot on pujjo Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Change-Id: I6d2e8eaecae968ed51095d9497beab492ba7e0c8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75153 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-05-17mb/google/brya/variants/hades: Set up internal pull-up for GPIOsEran Mitrani
BUG=b:280843816 TEST=builds Signed-off-by: Eran Mitrani <mitrani@google.com> Change-Id: I55a85335a34eee227abb6ff355719f7ca2cbf04a Reviewed-on: https://review.coreboot.org/c/coreboot/+/75035 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-05-17console: Add format-checking __printf() to die()Nico Huber
Code changes are necessary because `-Wformat` warns about empty format strings by default. Change-Id: Ic8021b70f4cd4875b06f196f88b84940c9a79fe0 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75147 Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-05-17soc/intel/xeon_sp/spr: Fix format specifier for __LINE__ (%d)Nico Huber
Change-Id: I1384a02fa2931002ddd629acef0a4368435cfeb5 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75233 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-05-17ec/google/chromeec/ACPI: Set TBMC status based on motion sensor presenceMatt DeVillier
Use ECRAM field MTNS to determine if motion sensor present, and set TBMC device status accordingly. TEST=build/boot google/{jinlon,drobit}, verify ACPI status for TMBC correct for both devices with and without tablet mode. Change-Id: Ic06ab6d721f0a3435e6dfd7b5e130f378096afec Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75172 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: CoolStar <coolstarorganization@gmail.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-05-17mb/google/volteer: Use FW_CONFIG to determine correct SOF audio profileMatt DeVillier
Use AUDIO PROBE to determine speaker amp config, set SOF driver profile accordingly. TEST=build/boot Win11 on Delbin and Drobit, verify correct audio profile selected, drivers loaded and functional. Change-Id: I13d787cb5ccb74d2774151ccd5deeb45b3364319 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75232 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-05-17drivers/sof: Add support for max98373a using port SSP2Matt DeVillier
Some devices using the MAX98373a smart amp have the speakers connected to port SSP2 vs the default SSP1, so add a configuration item to be able to specify that. TEST=tested with rest of patch train Change-Id: I11d8011c54946aa72a83c73fa88456b4bb5d7d95 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75231 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-17drivers/sof: Use topology enums where appropriateMatt DeVillier
Also correct switch intendation, remove excess empty lines. Change-Id: I86026e7f6c0c1c7f3dc6a473bb3afe2f6d32a247 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75230 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-05-17soc/intel/common: Don't hardcode ramtop offsetSean Rhodes
The `ramtop` can be obtained from the `option.h`, so remove the hardcoded value. Keep the check for the value being byte aligned. Change-Id: I5327b5d4e78b715a85072e5d9a62cf8fd2ae92c0 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74511 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-05-17soc/intel/alderlake: Handle FSP logo paramsSubrata Banik
This patch overrides FSP-S UPD `LogoPtr/LogoSize` with a valid logo.bmp file if `BMP_LOGO` config is enabled. TEST=Able to see splash screen while booting google/marasov with BMP_LOGO config enable. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I421da2b4dadb892f17a859ce0ec586a2880469eb Reviewed-on: https://review.coreboot.org/c/coreboot/+/75294 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-17soc/intel/meteorlake: Handle FSP logo paramsSubrata Banik
This patch overrides FSP-S UPD `LogoPtr/LogoSize` with a valid logo.bmp file if `BMP_LOGO` config is enabled. TEST=Able to see splash screen while booting Intel Meteor Lake RVP with BMP_LOGO config enable. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Iaba187456dd4dfb2f69d3532e83a3850f31783ed Reviewed-on: https://review.coreboot.org/c/coreboot/+/75198 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-05-16cpu/amd/pi/00730f01/Kconfig: use hexadecimal CPU number in ACPIFelix Held
To match the rest of coreboot, also change this ACPI_CPU_STRING Kconfig setting to use hexadecimal CPU numbers for the ACPI CPU objects. Since this SoC has a maximum of 4 cores, this change will make no difference in the runtime behavior. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I58f9c4672f34de0defafc300d2d291f4ad6196ff Reviewed-on: https://review.coreboot.org/c/coreboot/+/75251 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-16soc/amd/*/Kconfig: change ACPI_CPU_STRING to use hexadecimal CPU numbersFelix Held
Both the AMD AGESA reference code and the default coreboot ACPI_CPU_STRING use hexadecimal numbers in the ACPI CPU object names, so change the ACPI_CPU_STRING format string in the both the Stoneyridge Kconfig and the common non-CAR AMD SoC config Kconfig which covers all other AMD SoCs in soc/amd. All platforms where the P state and C state SSDT from binaryPI (Stoneyridge) or FSP (Picasso) was used in coreboot before it got replaced by native code, had at most 8 cores/threads, so the mismatch never became apparent. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I9d6822c5df01786ee541ce90734b75ed1a761fca Reviewed-on: https://review.coreboot.org/c/coreboot/+/75250 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-16ec/google/chromeec: Use host command APICaveh Jalali
Update the chromeec driver to use the EC host command API. Large blocks of repetitive code to set up EC calls are replaced with single function calls to perform the same operation. BUG=b:258126464 BRANCH=none TEST=booted on rex Change-Id: I0317405b1ed0c58568078133c17c8cfbc7c21d80 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73325 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-16ec/google/chromeec: Add ec_cmd_api.h, update ec_commands.hCaveh Jalali
The new util/chromeos/update_ec_headers.sh utility is used to update ec_commands.h and introduce ec_cmd_api.h from the chrome EC repo. ec_cmd_api.h is a new file from the chrome EC repo which defines the API for communicating with the EC. It is a companion to the existing ec_commands.h by defining functions corresponding to EC host command opcodes and request/response struct definitions. See $EC/docs/ec-host-command-api.md for details. Generated using update_ec_headers.sh [EC-DIR]. The original include/ec_commands.h version in the EC repo is: 3e35858003 ec: Add another #line directive The original include/ec_cmd_api.h version in the EC repo is: 59de61f2db zephyr: Add support for RNG devices BUG=b:258126464 BRANCH=none TEST=none Change-Id: I30f20e34d31b7e19cf03f65fefd58ae64eef1d41 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73324 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-16util/chromeos: Add EC header update utilityCaveh Jalali
This adds a new utility for copying ec_commands.h and ec_cmd_api.h from the chrome EC repo with the appropriate copyright header adjustment. It is invoked as: util/chromeos/update_ec_headers.sh [EC-repo] where EC-repo is the top of the EC repo from which header files are to be obtained. The corresponding files in src/ec/google/chromeec are updated but not committed. Also, a commit message is suggested with the original git versions for reference. BUG=b:258126464 Change-Id: Ib43c75d807dd925b2c4bff425c07a36b4b4582c4 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74879 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Boris Mittelberg <bmbm@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-05-16lib: Perform display init in normal boot mode if BMP_LOGO is setSubrata Banik
Traditionally, display init during vboot "verified/secure/normal boot mode" relies on the VB2_CONTEXT_DISPLAY_INIT. This is the default behavior for vboot, meaning skip display init during verified boot mode. However, if the intention is to show the OEM splash screen (using BMP_LOGO config) during boot, then the policy enforced by vboot needs to be overridden. This can be done by setting the BMP_LOGO config flag. If BMP_LOGO is not enabled, then the vboot policy will be followed and display init will be skipped. This change was made to allow OEMs to show their splash screen during boot, even if the system is in verified/secure/normal mode. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ice1f02ad5c02a6a7e74a97ed23c5f11c7ecfb594 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75197 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-05-16acpigen: Add printf-like function for debug stringCliff Huang
Generate formatted string and ACPI code to print debug string. For example (with pcie_rp = 1): acpigen_write_debug_sprintf("calling _ON for RP: %u", pcie_rp); generates the following ACPI code: Debug = "calling _ON for RP: 1" With this new function, the following functions are not needed anymore and therefore are removed by this patch. - acpigen_concatenate_string_string() - acpigen_concatenate_string_int() - acpigen_write_debug_concatenate_string_string() - acpigen_write_debug_concatenate_string_int() BRANCH=firmware-brya-14505.B TEST=Add above functions in the acpigen code and check the generated SSDT table after OS boot. Check the debug messages is in the kernel log when /sys/modules/acpi/parameters/aml_debug_output is set to '1'. Change-Id: Id4a42e5854516a22b7bc4559c2ed08680722c5ba Signed-off-by: Cliff Huang <cliff.huang@intel.com> Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73113 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Zhixing Ma <zhixing.ma@intel.com> Reviewed-by: Musse Abdullahi <musse.abdullahi@intel.corp-partner.google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-05-16x86: pci_io_cfg: Make constant unsigned to fix out of bounds shiftPaul Menzel
Fix the error below when running a coreboot image built with `CONFIG_UBSAN=y`. PCI: pci_scan_bus for bus 00 shift out of bounds src/arch/x86/include/arch/pci_io_cfg.h:13:20 ubsan: unrecoverable error. GCC with `-fsanitize=shift` also flags this: runtime error: left shift of 1 by 31 places cannot be represented in type 'int' So, make the constant unsigned. TEST=emulation/qemu-i440fx with `CONFIG_UBSAN=y` stops later with [ERROR] unaligned access src/lib/rmodule.c:152:27 [EMERG] ubsan: unrecoverable error. Change-Id: Ib05d225ab9f22078d765009b4ee6ef0c63231eed Found-by: UBSAN Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51292 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-05-16soc/intel/xeon_sp: Drop dummy FADT entryKyösti Mälkki
Specifying types without addresses for PM1B events is not useful. Change-Id: I839208eaecf689a32484b9154647fc66633e5eef Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75186 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-05-15device/allocator: Fix format string for resource flags (%lu)Nico Huber
Change-Id: I56ffb82ec417530527ea1ea7e97a593e5bf6b756 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75148 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-05-15mb/google/brya/var/taniks: Update SOF speaker topologyMatt DeVillier
Taniks uses a 4-channel output config, rather than 2-channel. Update the SOF speaker topology accordingly. TEST=build/boot Win11 on taniks, verify speaker output functional. Change-Id: I3c08b12b11464dcada014289174e0cc468d1c39d Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75211 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: CoolStar <coolstarorganization@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-05-15drivers/sof: Add support for max98357a with 4-ch outputMatt DeVillier
Will allow boards using this speaker configuration to correctly specify their output type. TEST=tested with rest of patch train Change-Id: Iefcfc928e2611f533af1a2962ec2761ec1b7bf3a Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75210 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: CoolStar <coolstarorganization@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-05-15commonlib: compiler.h: Add __printf macroJeremy Compostella
This patch adds the `__printf' macro to comply with checkpatch following warning: Prefer __printf(1, 2) over __attribute__((format(printf, 1, 2))) BRANCH=firmware-brya-14505.B TEST=Successful compilation with `__printf(1, 2)' instead of `__attribute__((format(printf, 1, 2)))' Change-Id: Ic2d90478ab0955c2ad0955e8cff5be76bfb2e741 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75159 Reviewed-by: Cliff Huang <cliff.huang@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-05-153rdparty/blobs: Advance submodule pointerSean Rhodes
This contains the following commits: * 9df5910: mb/starlabs/starbook/adl: Update EC binary to 1.13 * 65c8e9a: soc/mediatek/mt8188: Add scramble switch and fix 1RK register bit * 1a4c51c: soc/mediatek/mt8188: Add scramble switch for dpm version 0.2 * 076cdd1: soc/mediatek/mt8188: Update MCUPM firmware from v1.01.03 to v1.01.04 * 2be5f15: soc/mediatek/mt8186: Update SSPM firmware from v2.0.0 to v2.0.1 * 01ba156: mb/google/skyrim: Add RO SPL table * ce5566f: soc/mediatek/mt8186: Update SSPM firmware from v1.0.0 to v2.0.0 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Iee7b479f305b77f4e6ab5e53a0b74cebdc653599 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75103 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-05-15mb/google/myst: Re-organize the FMAP layoutKarthikeyan Ramasubramanian
By moving certain FW UI assets from RO to RW sections, 4 MiB is sufficient for RO section. Split the resultant available 4 MiB equally between 2 RW sections. This will help in getting to 16 MiB SPI flash for the mainboard. BUG=b:281567816 TEST=Build Myst BIOS image with the updated layout. Cq-Depend: chromium:4519688 Change-Id: I09948ceac0a6a1cb109322fc4856b8b486318664 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75184 Reviewed-by: Jon Murphy <jpmurphy@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com>
2023-05-15mb/msi/ms7d25: Update USB port macrosMichał Żygowski
Update USB port macros: - change onboard ports to SHORT: MYSTIC LIGHT, LAN_USB1, PS2_USB1, HUB to USB 2.0 headers, HUB to rear USB 2.0 - change USB type C header to LONG which caused hard lockups on the port making it unable to enumerate in UEFI Payload and Linux - add empty definitions for USBr ports Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I91198aa713e9084ff3906c267ee1b37b10c71843 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69820 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-05-15mb/google/dedede/var/taranza: Copy devicetree and GPIO from var/dibbiSheng-Liang Pan
copy from dibbi since taranza base on dibbi,this is only for first initial configuration, will update the more setting afterward. BUG=b:277664211 BRANCH=dedede TEST=build Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: Ia319f65897c0fea2f0558c20a5bc36bb6fbaea96 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74934 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
2023-05-15mb/google/dedede/var/taranza: Generate SPD ID for supported partsSheng-Liang Pan
Add supported memory parts in the mem_parts_used.txt and generate the SPD ID for the parts. BUG=b:277664211 BRANCH=dedede TEST=build Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: I6bbb67ccdd8ebc21719921d00320907f8dbb285f Reviewed-on: https://review.coreboot.org/c/coreboot/+/74933 Reviewed-by: Zhuohao Lee <zhuohao@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-15docs/releases/4.20: Update release notesFelix Singer
Change-Id: If5627cef5293c160e91ff85297abe695064f1bd1 Signed-off-by: Felix Singer <felixsinger@posteo.net> Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74981 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-14docs/releases: Add 4.21 release notes templateFelix Singer
Change-Id: Ibb4eaba6be088e20c76a8329847148c1d4ff8c04 Signed-off-by: Felix Singer <felixsinger@posteo.net> Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75187 Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-14docs/vboot: Update list of boards supported by vbootFelix Singer
Change-Id: Ib797c17183ca48131713288c618c4c20496583fb Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75215 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
2023-05-14acpi/acpigen: add comment about byte 0 in acpigen_resource_*wordFelix Held
Since it's not obvious, add comments to acpigen_resource_word, acpigen_resource_dword and acpigen_resource_qword to clarify out what the magic number in byte 0 means. The most significant bit of byte 0 indicates if it is a small or large resource data type. In the case of the MSB being 0, it's a small resource data type (aka type 0), and the other bits encode bit the type and size of the item; if the MSB is 1, it's a large resource data type (aka type 1), and the other bits just encode the type and there are two separate bytes to encode the size. Beware that the large resource's data type values in the ACPI specification don't include the MSB that's set, but only the 7 lower bits. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia6a6c9fb1bcde232122bb5899b9a0983ef48e12b Reviewed-on: https://review.coreboot.org/c/coreboot/+/75158 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-05-14arch/x86/ioapic.c: Increase the number of bits for ioapic IDArthur Heymans
In practice hardware can use larger numbers. Change-Id: I6e9ddd1ebd396c37e25eb3019f981d45d9c5e062 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70499 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Naresh Solanki <naresh.solanki.2011@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-05-14mb/google/rex: Add variant specific SOC chip config update functionAnil Kumar
This patch adds support for variant specific chip config update similar to commit 061a93f93d2 ("mb/google/brya: Add variant specific soc chip config update"). Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Change-Id: I60a4042cba608fd527527af9340ec0215f3086ca Reviewed-on: https://review.coreboot.org/c/coreboot/+/75046 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-05-14mb/google/rex/var/screebo: Add initial devicetree configKun Liu
add initial devicetree config for screebo BUG=b:276814951 TEST=emerge-rex coreboot Change-Id: Ie64d0e50ec22b3e363597af64eb723ef1f86dfa8 Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74972 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-05-14mb/google/corsola: Add support for MIPI panelRuihai Zhou
The detachable Starmie will use MIPI panels, which require reading serializable data from the CBFS. So we add MIPI panel support to the display configuration and align the configuration sequence with the panels that use MIPI bridges. The PMIC Datasheet: TPS65132-Single-Inductor-Dual-Output-Power-Supply.pdf BUG=b:275470328 BRANCH=corsola TEST=emerge-corsola coreboot chromeos-bootimage and display normally Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Change-Id: I6f079e54f0317ff2f685f0e3834ebd1ceb8e9fcb Reviewed-on: https://review.coreboot.org/c/coreboot/+/74051 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-05-14mb/facebook/fbg1701/board_mboot.h: Remove config from mb_log_listFrans Hendriks
Error message ´Cannot map compressed file config without cbfs_cache' is reported. Compressed parts of CBFS can not be used during bootblock stage. Remove config from mb_log_list. Will be added to verified items by CB:74752. BUG=NA TEST=booting and verify log on facebook FBG1701 Change-Id: Iacf023bc8b9c2ebc66137c4ea683589751a30d2f Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74750 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-05-14mb/google/nissa/var/uldren: Add wifi sar tableDtrain Hsu
Add wifi sar table for uldren BUG=b:279679700 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I9e3d7a06beb673b204f2dfe8e7beb919730aa885 Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75010 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-05-14screebo: fix the lp5ccc config from 0x55 to 0xaaSimon Zhou
BUG=b:278022971 TEST=verified on screebo Change-Id: I16f1d66ca7f885120358eb2a2d3c6fb111319f11 Signed-off-by: Simon Zhou <zhouguohui@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75173 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-14soc/amd/phoenix/Kconfig: Update default soft fuse bitsFred Reitberger
Set the default soft fuse bits to the recommended values Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I2354aefe90a08eaef95a68926806d11a9118c3de Reviewed-on: https://review.coreboot.org/c/coreboot/+/75183 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-05-14mb/google/myst/Kconfig: Select SPI_FLASH_EXIT_4_BYTE_ADDR_MODEFred Reitberger
When using a 32-MiB ROM chip, the ABL leaves the SPI flash in 4-byte addressing mode, so ensure the driver exits that mode for regular operation. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I9a846be743a65ffe5b3ef94e20e0b5fc5e273961 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75182 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-05-14sb/intel/bd82x6x,ibexpeak: Move UPRWC definitionKyösti Mälkki
Locate it with all the other PM IO registers. Change-Id: I779b2e313c9d8370c66c4adb4f6f4d4cf5b4e7dd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74980 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-05-14sb/intel/lynxpoint: Remove GPE0_{EN,STS}_2 definesKyösti Mälkki
By ACPI specification, those follow GPE0_EN bits in the register space. Use sizeof() to replace the 2/4 offset previously used. Change-Id: I27ada0b19b2cf5e8eca71f48bf103dcab1b3cc11 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74979 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-05-14Makefile.inc: Warn about set but unused variables with GCCArthur Heymans
Clang was already warning about this. Synchronize the behaviour between both compilers. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I3331a7437b17ab5ac97cef94511bb29c020bdff0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75032 Reviewed-by: Jan Samek <jan.samek@siemens.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-05-14mb/google/hades: update TPM IRQ in early gpio tableEric Lai
TPM IRQ should be A20 not A13. RAM table is correct. BUG=b:282164589 TEST=able to boot up Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I82a709cc280288d612c65697b8da3c4274d4cd3b Reviewed-on: https://review.coreboot.org/c/coreboot/+/75191 Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-14mb/google/hades: Correct TPM I2C bus to 3Eric Lai
Follow schematic to correct I2C bus. BUG=b:282164589 TEST=able to boot up Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I277e5190302c98dbce809d09c1a32fac758aa8e9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75190 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-05-13payloads/external/edk2: Verbose builds with coreboot build-systemBenjamin Doron
Rather than requiring another Kconfig symbol to be set, reuse the same `make V=1` command argument. This simplifies rebuilds with a single point of reference. Also, this means that coreboot doesn't have to be rebuilt due to Kconfig changes. Change-Id: I9eba86b234768641a215095b8657e9d07832b1b5 Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75185 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-05-13drivers/net/r8168: add ACPI _STA field entryMatt DeVillier
Add _STA field entry for r8168 ACPI device and set to ACPI_STATUS_DEVICE_HIDDEN_ON in order to hide device from OS (Windows) as there is no driver needed (or available). Windows correctly attaches drivers to the PCIe device, the separate ACPI device is unused and unneeded. Linux is unaffected as it does not use the ACPI device status. Change-Id: Ib7ae99fffcb00e71421b93c2794119841aa239d3 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75177 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-13mb/samsung/lumpy: Adjust touchpad ACPI for Windows driversReddestDream
Adjust the touchpad HID/CID/HRV to allow coolstar's crostouchpad Windows drivers to properly attach. Change the interrupt type from EDGE to LEVEL. TEST=build/boot samsung/lumpy, verify touchpad functional under both Windows 10/11 and Linux, verify Windows overlay driver correctly remaps top row keys. Change-Id: Ie4268b4de5779ee148699c7bef8c700a99816f1e Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75181 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-05-13mb/google/parrot: Adjust touchpad ACPI for Windows driversReddestDream
Adjust the touchpad HID/CID/HRV to allow coolstar's crostouchpad Windows drivers to properly attach. TEST=build/boot google/parrot, verify touchpad functional under both Windows 10/11 and Linux, verify Windows overlay driver correctly remaps top row keys. Change-Id: Ic164244eceb52221653bd60f7217f9a09e38c1b6 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75180 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-13mb/google/butterfly: Adjust touchpad ACPI for Windows driversMatt DeVillier
Adjust the touchpad HID/CID/HRV to allow coolstar's crostouchpad Windows drivers to properly attach. Change the interrupt type from EDGE to LEVEL. TEST=build/boot google/butterfly, verify touchpad functional under both Windows 10/11 and Linux, verify Windows overlay driver correctly remaps top row keys. Change-Id: I971795becfb05fb42921ff6f40a20892f4f5654a Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75179 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-05-13mb/google/stout: Use board-specific PS2M HID/CID to enable multitouchMatt DeVillier
Use board-specific ASL for PS2-attached trackpad rather than the EC/SIO default, so that Windows installs a multitouch-capable driver rather than the standard PS2 mouse driver. TEST=build/boot Win11 on google/stout, verify trackpad is multitouch capable. Change-Id: Id93bbe53f35b1e2c35e36d8175889786b9f5de8b Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75176 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-13sio/smsc/mec1308: fix SIO/PS2 keyboard ACPI for WindowsMatt DeVillier
Add _HID to parent SIO device so Windows can find the PS2K, and remove _ADR since HID and ADR are mutually exclusive. TEST=build/boot Win11 on samsung/lumpy, verify keyboard functional. Change-Id: I7b6b09da1a3fdc34ef43789c699f7fd22b4b655b Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75175 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-05-13ec/quanta/ene_kb3940q/acpi: Fix PS2K under WindowsMatt DeVillier
Add _HID to parent SIO device so Windows can find the PS2K, and remove _ADR since HID and ADR are mutually exclusive. TEST=build/boot Win11 on google/butterfly, verify keyboard functional. Change-Id: I772ceef1b439cfd4e2740e53362bee9d494fb36d Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75174 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-05-13acpi/Kconfig: move \_SB scope out of ACPI_CPU_STRINGFelix Held
In ACPI 1.0 the processor objects were inside the \_PR scope, but since ACPI 2.0 the \_SB scope can be used for that. Outside of coreboot some firmwares still used the \_PR scope for a while for legacy ACPI 1.0 OS compatibility, but apart from that the \_PR scope is deprecated. coreboot already uses the \_SB scope for the processor devices everywhere, so move the \_SB scope out of the ACPI_CPU_STRING to the format string inside the 3 snprintf statements that use the ACPI_CPU_STRING. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Change-Id: I76f18594a3a623b437a163c270547d3e9618c31a Reviewed-on: https://review.coreboot.org/c/coreboot/+/75167 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-05-13soc/amd/*/acpi/mmio.asl,sb_fch.asl: hide MISC deviceFelix Held
Don't set bit 2 of the return value of the _STA method in order for Windows not to show a warning about an unknown device in the device manager for this device. TEST=The unknown device with device instance path ACPI\AMD0040\3 disappeared from the device manager in Windows 10 build 19045 on a Mandolin board with a Picasso APU. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If005f06843956004c281fd70cf364171148cb9ff Reviewed-on: https://review.coreboot.org/c/coreboot/+/68962 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-13soc/amd/*/acpi/mmio.asl,sb_fch.asl: change AAHB's _STA back to methodFelix Held
Commit 396fb3db74db ("soc/amd/*/acpi/mmio.asl,sb_fch.asl: hide AAHB device") didn't only change the visibility of the device, but also changed the _STA method to a name. While this worked, the specification says that _STA is supposed to be a method, so change it back to being a method. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id0932b2875aaf563a4dbd860bdd11a04272e3780 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75169 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-13soc/cavium/cn81xx: Use correct size for MPIDR_EL1 registerArthur Heymans
Clang complains about this. Change-Id: I2d761d2fa946f171033220ab7b2e399cf359782a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74538 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-05-13vendorcode/mediatek/mt8195: Fix set but unused variablesArthur Heymans
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I5738e73f2121e2558831fbaa9c92a2fd0926ad88 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75038 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-05-13vendorcode/mediatek/mt8195: More sure ucDoneFlg is initializedArthur Heymans
One some codepaths ucDoneFlg is not initialized. This fixes a clang warning. Change-Id: I78aa2c711626b24f003f5c95b1c9598eaff7cb1b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74552 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-05-13vendorcode/mediatek/mt8195: Make order of operators more explicitArthur Heymans
Clang warns about this. Change-Id: I9a19f33df64a63e51e3dadac4aae28a8bb12121d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74551 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-05-13vendorcode/mediatek/mt8195: Fix superfluous bracketsArthur Heymans
Clang warns about this. Change-Id: I4310737bd63728d3c592d0f4d1030bc352afa575 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74550 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-05-13vendorcode/mediatek/mt8195: Fix casting enum of different typesArthur Heymans
Clang warns about this. Change-Id: I18ff23c3c18b7cd74f0d6fe0b308b9096ce269ae Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74549 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-05-13vendorcode/mediatek/mt8195: Fix set but unused variablesArthur Heymans
The clang compiler warns about this. Change-Id: I1584258aa24d6a0bf558b3c622bc53c156a37b09 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74548 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-05-13soc/cavium: Guard gcc specific compiler flagArthur Heymans
TEST: BUILD_TIMELESS=1 remains the same. Change-Id: I740b59574303145fc673a97556367daefe8d1540 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74540 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-13vendorcode/cavium: Fix additions to stringArthur Heymans
The clang compiler is confused about adding integers to strings. Adding brackets around the macros fixes this. TEST: BUILD_TIMELESS=1 remains the same. Change-Id: I2ea17322352d977bf0ec3ee71b14463fa218d07c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74541 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-13soc/mediatek/mt8195/apusys_devapc.c: Fix unsigned comparisonArthur Heymans
Clang warns about unsigned comparison below 0. Use the enum value itself to fix this warning. Change-Id: I12fccff2fb7d43fd4582afd518a7eab632908a5f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74553 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-05-13vendorcode/mediatek/mt8192: Fix set but unused variablesArthur Heymans
TEST: BUILD_TIMELESS=1 binary remains the same. Change-Id: Ic05a9819764c03184b54c4fc58dbe325fddeae10 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74543 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-05-13vendorcode/mediatek/mt8192: Fix set but unused variablesArthur Heymans
The binary does change on these with BUILD_TIMELESS. Change-Id: I45d51d53f991556cedd1cc45997d76fc828bceb5 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74544 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-05-13mb/prodrive/hermes: Ensure VMX setting is appliedAngel Pons
VMX is enabled through a bit in the IA32_FEATURE_CONTROL MSR, which can be locked. The MSR remains locked after a non-power cycle reset, though. If the MSR is locked, coreboot bails out and leaves VMX in the state it was found. Because of this, changes to the VMX enable option in the BMC only take effect after the system is power cycled. This behaviour is highly undesirable because users are likely not aware that a power cycle is required for changes to VMX state to take effect. So, if VMX is supported, the IA32_FEATURE_CONTROL MSR is locked and the current VMX state does not match the requested state, then issue a full reset. This will power cycle the system and unlock the MSR, so that the desired VMX state can be programmed into the MSR. This is checked early to avoid needlessly doing time-consuming operations (running FSP) twice if we know we will need to power cycle the system anyway. Note that a user may change the VMX setting after the newly-added check but before the setting is read in ramstage to program the MSR, but this is a non-issue as firmware settings need a reset to take effect anyway. TEST: Toggle VMX setting in BMC and reboot without power cycle, observe coreboot automatically issues a power cycle reset because the MSR is locked and the VMX state differs. Verify that the system boots properly with VMX in the correct state after having power cycled. Change-Id: Id9061ba896a7062da45a86fb26eeb58927184dcb Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75141 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-05-13cpu,nb/amd/pi/00730F01: dynamically generate CPU devicesFelix Held
Instead of having the maximum number of possible CPU objects defined in the DSDT, dynamically generate the number of needed CPU devices in the SSDT like it's done on all other x86 platforms in coreboot. TEST=APU2 still boots and Linux doesn't show any ACPI errors with this patch applied and it prints "ACPI: \_SB_.P000: Found 2 idle states". Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id6f057ad130a27b371722fa66ce0a982afc43c6c Reviewed-on: https://review.coreboot.org/c/coreboot/+/73073 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-05-13nb/amd/pi/00730F01: request binaryPI to use \_SB_ scope in PSTATE SSDTFelix Held
Instead of having binaryPI generate a PSTATE SSDT that uses \_PR_ as the scope for the CPU objects and patching this SSDT in coreboot to use the \_SB_ scope in patch_ssdt_processor_scope, request binaryPI to use the \_SB_ scope instead by setting the late platform configuration option ProcessorScopeInSb to true. TEST=APU2 still boots and Linux doesn't show any ACPI errors with this patch applied and it prints "ACPI: \_SB_.P000: Found 2 idle states". Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I411201b55cfee30ae41da4e6814679bdb49e9bf7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73386 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-05-12MAINTAINERS: Add Felix Singer to util/dockerFelix Singer
Change-Id: Ic2efbb1d2a13212921ad110314a6394a4dca6a8a Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72918 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-05-12soc/intel/apl: Remove set but unused variableArthur Heymans
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I62b7390c2de244cce169550e9b1fa41af738525d Reviewed-on: https://review.coreboot.org/c/coreboot/+/75037 Reviewed-by: Jan Samek <jan.samek@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-05-12soc/mediatek/mt8183: Fix set but unused variablesArthur Heymans
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I1c995d942fa25a9268fbf716034335937df57714 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75036 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-05-12soc/qualcomm/sc7180: Fix set but unused variablesArthur Heymans
This fixes clang warnings. Change-Id: I407da6ec05ef646f61bd81e314fee1b5ea659192 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74557 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-05-12vendorcode/cavium: Fix set but unused variablesArthur Heymans
TEST: BUILD_TIMELESS=1 remains the same. Change-Id: Id2cb37dbe4d450fe7f91a527b5cd73ac55863548 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74542 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-05-12mb/prodrive/hermes: Simplify handling board cfgAngel Pons
The `get_board_settings()` function always returns non-NULL, so there is no need for NULL checks. When only one member is accessed, also drop the local variable and directly dereference the function's return value. Change-Id: I4fc62ca2454f4da7c8ade506064a7b0e6ba48749 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75140 Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-05-12drivers/ocp/ewl: Add EWL driver for EWL type 3 error handlingJohnny Lin
1. Restore the reverted 'commit 059902882ce5 ("drivers/ocp/ewl: Add EWL driver for EWL type 3 error handling")'. 2. Print more EWL type 3 error information when it occurs. Change-Id: Ib83b7653a839d18a065b929127549acd10bce7a7 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69280 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jon.zhixiong.zhang@gmail.com>
2023-05-12mb/siemens/mc_ehl5: Add PTN3460 eDP-to-LVDS bridgeMario Scheithauer
This mainboard contains in addition to its base variant, mc_ehl2, an LCD panel driven through the PTN3460 eDP-to-LVDS bridge. This patch enables the PTN3460 support by adding the device to devicetree.cb and board-specific configuration parameters in lcd_panel.c. BUG=none TEST=Boot with the LCD panel attached and observe whether the picture is stable and free of artifacts coming from wrong resolution and timing. Change-Id: I196d7ceeb7ac241c9b95db2ef791a5f3ff7890a7 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74936 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jan Samek <jan.samek@siemens.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2023-05-12mb/siemens/mc_ehl5: Add new board variant based on mc_ehl2Mario Scheithauer
This mainboard is based on mc_ehl2. In a first step, it contains a copy of mc_ehl2 directory with minimum changes. Special adaptations for mc_ehl5 mainboard will follow in separate commits. Change-Id: Id80f8eb49dd2fed0ed1ffc479d47d8669eca84c9 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74935 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2023-05-12mb/google/nissa/var/uldren: Fix Touch screen power sequenceIan Feng
Based on touchscreen product spec. For uldren variants with a touchscreen, drive the enable GPIO high starting in romstage while holding in reset, then disable the reset GPIO in ramstage (done in the baseboard). BUG=b:279989974 TEST=Build and boot to OS in uldren. Touch screen is workable. Change-Id: Ib1b1ce80aa1dd8c312e3663fc50c9e9f53cc07fe Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74835 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-05-12mb/prodrive/atlas: Shorten FSP-M UPD statementsAngel Pons
Replace `memupd->FspmConfig.` with `mcfg->` for the sake of brevity. Change-Id: If2e7cccca955b0c1e07c1ecf100d29a923107856 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75136 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com>
2023-05-12mb/google/rex: Set WWAN_RF_DISABLE_ODL to NCTarun Tuli
This signal isn't functionally being used and is causing leakage during suspend. Set it to NC. BUG=b:279762779 TEST=builds. WWAN functional. Change-Id: I93f2b0a781e250678280b57e4ab1d80ef27ff460 Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75053 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-05-12soc/intel/common: Define enum types for MKHI group IDs and ME SKUsSridhar Siricilla
The patch defines enum type for MKHI group IDs and ME SKU types instead of macros. TEST=Build code for Rex Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I102e802938a6a664a43a362d90a26755cff8f316 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74996 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Harsha B R <harsha.b.r@intel.com> Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
2023-05-12soc/intel/common: Remove superfluous cmos_offset from ramtopSean Rhodes
Having `_cmos_offset` in a CMOS offset is superfluous; remove it so the CMOS entry is just `ramtop`. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ibc1e7d78d2e3ae04330d19e64c3437ff07060ea8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74516 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-05-12mb/prodrive/atlas: Make default SN/PN not emptyAngel Pons
If reading the serial/part number fails, returning an empty string is very confusing. Instead, return "INVALID" to make problems obvious. Change-Id: I3c174ca76d51b44456c7b68f4fcffb4c8f9379be Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75132 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com>
2023-05-12mb/asus/p8z77-m: Make onboard NIC a child device below PCIe port 5Fabian Groffen
The Realtek RTL8111F NIC is currently not defined at all, nor as a child device, resulting in the on_board flag not being set to 1. This means that Linux / udev will call the device enp3s0 rather than eno0, as it's appropriate for on-board ethernet devices. Signed-off-by: Fabian Groffen <grobian@gentoo.org> Change-Id: I95f01a466a59234d1cbe2420f208bf58ae28fcc6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75106 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-05-12mb/asus/p8z77-m: Add TPM configFabian Groffen
This board has a TPM connector, enable support for it. Signed-off-by: Fabian Groffen <grobian@gentoo.org> Change-Id: I1861df95eef15bc2bd29412240d61456eaaad8c9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75105 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-05-12mb/google/brya: Fix typo in gma-mainboards filenameTarun Tuli
Small typo in brask/gma-mainboards-ads Should be brask/gma-mainboards.ads BUG=b:277861633 BRANCH=firmware-brya-14505.B TEST=Builds Change-Id: I9800870dcef13a3e16f6235137e79234a5e6bf83 Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75052 Reviewed-by: Eran Mitrani <mitrani@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-05-11acpi/acpigen: add acpigen_resource_io to generate I/O resourceFelix Held
Add the acpigen_resource_io helper function to generate an I/O range resource. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I177f59b52d4dbbff0a3ceeef5fc8c7455cef9ff8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75044 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>