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2015-03-23libpayload: EHCI: Support root-hub TT featureJim Lin
If EHCI controller has TT (Transaction Translator) support in root-hub, then we need to keep control over this controller when USB keyboard (low-speed device) is connected to root-hub port. Need to add "CONFIG_LP_USB_EHCI_HOSTPC_ROOT_HUB_TT=y" to config file (e.g. payloads/libpayload/configs/config.nyan_big) to support this feature. BUG=chrome-os-partner:32355 TEST=Tested on nyan_big platform. Press ESC+REFRESH+POWER keys on internal keyboard to power up. Press Left Arrow or Right Arrow on USB keyboard to switch between "English" and "Default Locale" in coreboot UI. Or unplug and plug in device and try again. Root hub <- low-speed USB keyboard Root hub <- full-speed hub <- low-speed USB keyboard Root hub <- high-speed hub <- low-speed USB keyboard Change-Id: Iaa2823f64c8769fc808ee7a316c378f18f004e63 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4ad57fd673d6dc8814fe99a4ac420566bb17e77b Original-Change-Id: Id86a289bc587653b85227c1d50f7a4f476f37983 Original-Signed-off-by: Jim Lin <jilin@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/220125 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/8737 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-23Enable publishing of board ID where supportedVadim Bendebury
These boards are supposed to be able to determine the board ID at run time based on GPIO settings. BUG=chrome-os-partner:30489 TEST=verified that all boards build. Checked that storm proto0 reports board ID of 0 on the console Original-Change-Id: Iadd758a799d69e1e34579d7d495378856b64c45b Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/210119 (cherry picked from commit f4d41ddf906c1bf0d10da38011998fa0a630c332) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I0d5f94d3428157a70f0a9d711b57432e3f796733 Reviewed-on: http://review.coreboot.org/8722 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-23storm: Add board ID calculation functionVadim Bendebury
storm uses three GPIOs in tertiary mode, such that proto0 returns value of 8 when the GPIOs are interpreted as a single tertiary number. Adjust the calculated value to return board ID of 0 on proto0, and monotonously incrementing values on newer boards. BUG=chrome-os-partner:30489 TEST=when enabled, the board ID value of zero is reported on the console. Original-Change-Id: I2ff8fd5cbc8d568877b6f8bf220e146893f1e4be Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/210118 (cherry picked from commit 6ba24f31583933f02be111c8767ae9df56537011) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I35ee218df35a0924d4bb8fcbc6c875450a609f24 Reviewed-on: http://review.coreboot.org/8721 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-23Include board ID calculations only when necessaryVadim Bendebury
For the majority of Chrome OS boards there is no need to include board ID calculation in any stage but ramstage, where the ID should be available for inclusion into the coreboot table. BUG=chrome-os-partner:30489 TEST=build only, no other tests yet Change-Id: I1451d52382bc48cc126d40267e0f61712f4a6d4b Original-Change-Id: Ib9c06698a399d31e79a9b14143343ba2ad46d0fb Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/210117 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> (cherry picked from commit 27dd40e85bfcd0a38f388bad4d79f5fbb77a7566) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/8720 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-23Publish the board ID value in coreboot table, when configuredVadim Bendebury
Board ID value is usually of interest to bootloaders. Instead of duplicating the board ID discovery code in different bootloaders let's determine it in coreboot and publish it through coreboot table, when configured. BUG=chrome-os-partner:30489 TEST=none yet Change-Id: Ia1e36b907ac15b0aafce0711f827cb83622e27bb Original-Change-Id: Iee247c44a1c91dbcedcc9058e8742c75ff951f43 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/210116 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit b2057a02db9391e2085b138eea843e6bb09d3ea2) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/8719 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-23ipq806x: implement GPIO APIVadim Bendebury
Add implementation of the GPIO API defined in src/include/gpiolib.h. Also, clean up the GPIO driver, make it use pointers instead of integers for register address. This requires a touch in the SPI driver, where the CS GPIO is toggled and in the board function where it enables USB interface. BUG=chrome-os-partner:30489 TEST=tested with the following patches, observed proto0 properly read the board ID. Original-Change-Id: I0962947c6bb32a854ca300752d259a48e9e7b4eb Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/210115 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit e951f735001509d135cc61530ed0eecb5fc31a85) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I8a612dce000931835054086c1b02ebfc43dc57d2 Reviewed-on: http://review.coreboot.org/8718 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-23Generalize revision number calculation functionVadim Bendebury
Some platforms use tertiary interpretation of GPIO input state to increase number of distinct values represented by a limited number of GPIOs. The three states are - external pull down (interpreted as 0) - external pull up (1) - not connected (2) This has been required by Nvidia devices so far, but Exynos and Ipq8086 platforms need this too. This patch moves the function reading the tertiary state into the library and exposes the necessary GPIO API functions in a new include file. The functions are still supposed to be provided by platform specific modules. The function interpreting the GPIO states has been modified to allow to interpret the state either as a true tertiary number or as a set two bit fields. Since linker garbage collection is not happening when building x86 targets, a new configuration option is being added to include the new module only when needed. BUG=chrome-os-partner:30489 TEST=verified that nyan_big still reports proper revision ID. Change-Id: Ib55122c359629b58288c1022da83e6c63dc2264d Original-Change-Id: I243c9f43c82bd4a41de2154bbdbd07df0a241046 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/209673 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit c79ef1c545d073eaad69e6c8c629f9656b8c2f3e) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/8717 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-23build: mips: add default compilation optionsVadim Bendebury
MIPS targets should be compiled with no position independent code allowed, as the generated image often does not support short range components reference. BUG=chrome-os-partner:31438 TEST=with the rest of the patches included MIPS board urara builds successfully Change-Id: I8ac2a2f6979d3b468159c9e29d07e022f48ab18a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e932b203db3e7cb510a7bf862d4538d55b6c7271 Original-Change-Id: I637dd44eb565447c18b2c3cdb022d0933c52fd20 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/215677 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8822 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-23console: Allow bootblock console on MIPSPaul Burton
In addition to ARM based systems, allow MIPS based systems to select bootblock console support. BUG=chrome-os-partner:31438 TEST=none yet Change-Id: I40e5d8b651102709118878a317f7e983a617f433 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 1a41853273ef9ae716d5645379fcef79c5771b87 Original-Change-Id: I41f03ea8c8104ba2dd9f532b084696385d29636c Original-Signed-off-by: Paul Burton <paul.burton@imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/207973 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Original-Commit-Queue: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/8769 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-23mips: fix bootblock stack definitionsVadim Bendebury
Bootblock stack on Danube should be SRAM and defined separately from the rest of the coreboot stack. The actual coreboot stack will be defined later. The top of the stack should be above the bottom, as the stack grows towards lower addresses. BUG=chrome-os-partner:31438 TEST=ran bootblock on simulator under codescape, observed stack properly initialized. Change-Id: I43d2bae5f85a09a95ca0103b253399bd92555aef Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e02724cb4b30990ebaa631dabb45917af29d6437 Original-Change-Id: I3c37c8b5a1c0e7fd19411558a8f6d899fc283191 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/218732 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8767 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-23imgvp-danube: Support for the ImgTec Danube Virtual PlatformPaul Burton
Add basic board support for the ImgTec Danube Virtual Platform, which emulates a system built around the Danube SoC. Run this by loading coreboot.bimg into a flash device connected to SPFI1 chip select 0 & then executing the Danube boot ROM. BUG=chrome-os-partner:31438 TEST=none yet Change-Id: Ia62af62804bab261f3cabf7c2e62f5bb08a4a1a4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 6cb1017f5e2fec85f7f5c60cd2cfec63cc886b49 Original-Change-Id: I7a2b52f304bcb4b614440ec38975e05f38b0e590 Original-Signed-off-by: Paul Burton <paul.burton@imgtec.com> Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/207976 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8766 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-23danube: Use the generic timer interfaceVadim Bendebury
Actual timer support is not yet available for Danube, it will be added soon. For now, just to make the target build, modify it to use GENERIC_UDELAY and HAVE_MONOTONIC_TIMER configuration option. BUG=none TEST=the target builds again Change-Id: Iad1ceb966d5dbc8687b966be4d2506c8f92eba5a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 261837539fb5a31f96e682edbcbbbc0e588f2750 Original-Change-Id: Ie3289eace9d2baadd01bd641b5dffc635ac80c0f Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/220395 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8765 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-23danube: use SOC specific rom stage codeVadim Bendebury
Romstage initialization code does not need to be board specific, keep it in the SOC directory. Should there be a need for the board specific code, it can be added later. BUG=chrome-os-partner:31438 TEST=with upcoming patches, the urara board coreboot builds fine Change-Id: Ib619fa9313d463ded13e9259e50bb5aeaab4fb05 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 2c08977aaa5e9b5da29359d1920d7d8b61ce86d3 Original-Change-Id: I27e2d225bd36c42ccd29128d0ea9a970566c02af Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/215992 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8764 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-23t132: Change romstage base addressFurquan Shaikh
Romstage was overflowing. So move the base address lower BUG=chrome-os-partner:31032 BRANCH=None TEST=Compiles successfully Original-Change-Id: Ia05034477b51b149c87347ed1880f8e85ecbfbf8 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/210434 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 14af527a5d7cbb250e2358340196a9d749ec1683) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ib261fdd8b4c7eb4a1660c5d02fbcd3e0e3f34b22 Reviewed-on: http://review.coreboot.org/8723 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2015-03-23rush: Add MMC supportFurquan Shaikh
BUG=None BRANCH=None TEST=Compiles successfully. Depthcharge is able to see mmc. Original-Change-Id: Ia0c9b432fa447c64fa13e5fae5a66a26bbc86360 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/210002 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 4cb05ffa95a2a36c5b4606d2f0efe9e574b84e1d) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I7f9a27a4c0f0553e78fc1a289bffebbebd37c099 Reviewed-on: http://review.coreboot.org/8716 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2015-03-23t132: Add support for tpm i2cFurquan Shaikh
Iniitialize I2C bus required for TPM operation. Problem observed was that if frequency is raised above 20KHz, TPM starts responding with NAKs either for address or for data. Need to look into that. BUG=None BRANCH=None TEST=Compiles successfully and TPM success messages seen while booting. Original-Change-Id: I9e1b4958d2ec010e31179df12a099277e6ce09e0 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/210001 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 01e87ae35431147f442e3f3e531537b8f0de1c9d) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I7dddc39d77f9a726fa51dd58ea9b7712c9a6fae2 Reviewed-on: http://review.coreboot.org/8715 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2015-03-23libpayload arm64: Allow board to define upper address limit on DMAFurquan Shaikh
Instead of forcing boards to have DMA region below 4GiB, provide Kconfig option DMA_LIM_EXCL that a board can use to set the upper limit in MiB units on the address range reserved by DMA. By default, this value is 0x1000 i.e. 4GiB limit on the DMA upper address. BUG=None BRANCH=None TEST=Compiles successfully for rush. Default value is seen as 0x1000. Change-Id: Ie35d3844a0989486ae022f8922fdd4c9d7d57fb4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 6716cf312a103bc0440a558fc43c8c77869816e3 Original-Change-Id: I3ecbb4ec90995ab1568cb0924d5ce9467492697d Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/245250 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8800 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2015-03-23PCIe: Revise L1 Sub-State supportKenji Chen
BRANCH=None BUG=None TEST=Confirmed build pass only Signed-off-by: Kenji Chen <kenji.chen@intel.com> Change-Id: Ic0e845436614e63ad5ace7fb74400f7ea295571c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d3670b92e40d8757a48add6116a0edcec18074d8 Original-Change-Id: I5e029b0f82a771149d4c6127e30b9062e8eaba89 Original-Reviewed-on: https://chromium-review.googlesource.com/244514 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Commit-Queue: Kenji Chen <kenji.chen@intel.com> Original-Tested-by: Kenji Chen <kenji.chen@intel.com> Reviewed-on: http://review.coreboot.org/8833 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-23PCIe: Add L1 Sub-State support.Kenji Chen
Enable L1 Sub-State when both root port and endpoint support it. [pg: keyed the feature to MMCONF_SUPPORT, otherwise boards without that capability fail to build.] Change-Id: Id11fc7c73eb865411747eef63f5f901e00a17f84 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 6ac04ad7e2261846e40da297f7fa317ccebda092 Original-BUG=chrome-os-partner:31424 Original-TEST=Build a image and run on Samus proto boards to check if the settings are applied correctly. I just only have proto boards and need someone having EVT boards to confirm the settings. Original-Signed-off-by: Kenji Chen <kenji.chen@intel.com> Original-Change-Id: Id1b5a52ff0b896f4531c4a6e68e70a2cea8c736a Original-Reviewed-on: https://chromium-review.googlesource.com/221436 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/8832 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21libpayload: whitespace cleanupPatrick Georgi
Align struct members with tabs. Change-Id: Ie8bdbd718c7217a3f3768dd037fa7c10badbc05e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/8854 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21tegra132: convert to stopwatch APIAaron Durbin
Simplify the timed operations by using the stopwatch API. BUG=None BRANCH=None TEST=Built and booted to kernel. Analyzed logs. Output as expected. Change-Id: Ia49bccccc412f23bb620ed386b9174468a434116 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a877020c6d8ba12422c9c2c487122b7eb4a1967b Original-Change-Id: Iffc32fcb9b8bfdcfbef67f563ac3014912f82e7f Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/219494 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8831 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21exynos: convert to stopwatch APIAaron Durbin
Instead of open coding monotonic timer usage, use the stopwatch API. BUG=None BRANCH=None TEST=None Change-Id: I1c541c1c9f3fde0dec9163ad6cc94322538ac7f7 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 46ede0897687da6bcf730a8904f25e5a4485d6cd Original-Change-Id: Ia63a05850a1b6afdc42c2422332f77af516d27e3 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/219716 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8825 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21tegra132: fill out udelay() implementationAaron Durbin
There was an empty udelay() implementation result in 0 waits. Provide an actual implementation. BUG=None BRANCH=None TEST=Built and ran through to depthcharge on rush. Change-Id: Ia7060566a71c36bb7e4543c2fe4ee49d168518c7 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c8832e73de238358ea801ccd7c2330de35a7b40e Original-Change-Id: I201f2fdc4e4f5c88d48e4002839b03e808a5a1bc Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/210827 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8830 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21tegra124: switch to stopwatch APIAaron Durbin
Instead of using rela_time use the stopwatch API as the semantics fit perfectly with the expiration usage. BUG=None BRANCH=None TEST=Built, but similar usage tested on tegra132. Change-Id: I1147f2bed84b93d1b776205df9ae04d1db9c98a5 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c38e054dd166d5eb53f692833b5ce88a230816e3 Original-Change-Id: I6d3f3da4e035e872890d8b67947b17a981673dba Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/219712 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8819 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21device: convert to stopwatch APIAaron Durbin
Instead of open coding the monotonic timers use the stopwatch abstraction. BUG=None BRANCH=None TEST=Booted and noted timings work as expected. Built with software_i2c and no compilation failures. Change-Id: Ie5ecdd5bc764c1ab8ba4a923e65a1666aacd22f7 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c7bffb5aeb41e9b88cd2c99edd6abc38f1dc90af Original-Change-Id: I0170fe4b93d9976957a2dcb00a6ea41ddc0320ce Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/219495 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/8817 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21ramstage: remove rela_time useAaron Durbin
mono_time_diff_microseconds() is sufficient for determining the microsecond duration between 2 monotonic counts. BUG=None BRANCH=None TEST=Built and booted. Bootstate timings still work. Change-Id: I53df0adb26ae5205e2626b2995c2e1f4a97b012e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: deab836febea72ac6715cccab4040da6f18a8149 Original-Change-Id: I7b9eb16ce10fc91bf515c5fc5a6f7c80fdb664eb Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/219711 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8818 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21chromeec: use stopwatch APIAaron Durbin
Simplify the SPI timeout by using the stopwatch. BUG=None BRANCH=None TEST=Built nyan. Confirmed stopwatch works independently. Change-Id: Ida26a0748d4b5a6a28aa8f6e2b92fe2ee4cbe17f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 900d7ac826b76d49290033c87849bf776684f2c1 Original-Change-Id: I84b7949060326b7c6cc1872420b93bd44604c4d3 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/219493 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/8816 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21timer: add stopwatch constructAaron Durbin
There's a lot of places where expiration and running time are open coded. Allow for those places to be simplified by adding a stopwatch construct. The stopwatch can have an expiration or just be used to accumulate time. BUG=None TEST=Built and verified API works as expected by using implementation. Change-Id: Ibd636542b16d8554f1ff4512319a53dce81c97e5 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: bc623a1b36eb08c5877591c4509cd61131c62617 Original-Change-Id: I53604900fea7d46beeccc17f1dc7900d5f28518b Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/219492 Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/8815 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21Allow for different BFD elf formats per architectureVadim Bendebury
The upcoming MIPS toolchain inside chroot generates elf images of elf32-tradlittlemips format, whereas readily available tools outside of chroot generate images of elf32-littlemips format. Both of these formats are perfectly fine, but xcompile accepts only one format per CPU architecture. This patch allows to specify multiple formats per architecture, any matching format will suffice. BUG=chrome-os-partner:31438 TEST=emerged arm, x86 and mips targets inside chroot Change-Id: I2c6b8e46b9299059b8e099b93c8c3dcf0a569899 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 7f2f1d51643f33b72ac5e4091669f38662e5b9ce Original-Change-Id: I22405e71ac72b985fad51e2f5d7cc014107b8a9e Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/214599 Original-Reviewed-by: Stefan Reinauer <reinauer@google.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8823 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21imgtec/danube: Build BIMG boot imagesPaul Burton
Add a new utility named bimgtool, a simple tool which generates boot images in the BIMG format. This is the format the Danube boot ROM expects the user supplied code to be wrapped in, it is described by struct bimg_header in the code. This utility will be used to wrap the coreboot bootblock when building Danube targets. BUG=chrome-os-partner:31438 TEST=none yet Change-Id: I08ddb1b70d0b1feb1ffb3d62c4e5e6f07f4acdb7 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 7fe6a9f383b79120f9ae231453d4b3a0f85b4fa7 Original-Change-Id: I63b9f5e09cd1f12765317b38e2a0dd033cdd6d39 Original-Signed-off-by: Paul Burton <paul.burton@imgtec.com> Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/207975 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8768 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21danube: prepare SOC directory for uraraVadim Bendebury
These modules are necessary to resolve external names when building the board image. These are just skeletons for now which will be filled later. BUG=chrome-os-partner:31438 TEST=when config is enabled, emerge-urara coreboot succeeds. more extensive testing to come later Change-Id: I0fcb5d33187172ecac77041425402b33e89e8944 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 94ec79b0ab872f5c5fe7db5bef5fdabf77d6b3b6 Original-Change-Id: I69cc178976a910ebf8031ed9ac9ad67b4cc0878a Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/215678 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8763 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21imgtec/danube: Add support for ImgTec Danube SoCPaul Burton
Add build infrastructure and basic support code for the ImgTec Danube SoC. This support is sufficient to run on a simulator. BUG=chrome-os-partner:31438 TEST=none yet Change-Id: I59e36589765bf06b075fd4850215a0ef71246bb1 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 881278d7fbb8e6803bc8f6f9e84c64640b097401 Original-Change-Id: Ia7ed7288b13085db7ff37b5ad75d978b6137f958 Original-Signed-off-by: Paul Burton <paul.burton@imgtec.com> Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/207974 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8762 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-21mips: no need in architecture specific implementation of do_printkVadim Bendebury
With the proper configuration flags enabled, do_printk is available from src/console, no need to define it elsewhere. BUG=chrome-os-partner:31438 TEST=with upcoming patches, the urara board coreboot builds fine Change-Id: I82071b4ca1686639c0bd39c63a06b61cb5bf5571 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 69c655537c50274a61cf123b7fc387ec60dd29c7 Original-Change-Id: Ib1e3e5750cdc1adc509b4580a4f24d3ff3b105ee Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/215862 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8761 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21arch/mips: Add base MIPS architecture supportPaul Burton
Add the build infrastructure and basic architectural support required to build for targets using the MIPS architecture. This is sufficient to run on a simulator, but will require the addition of some cache maintenance and timer setup in order to run on real hardware. BUG=chrome-os-partner:31438, chromium:409082 TEST=none yet Change-Id: I027902d8408e419b626d0aab7768bc564bd49047 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: fcc0d934d7223922c878b1f87021cb5c2d7e6f21 Original-Change-Id: If4f99554463bd3760fc142477440326fd16c67cc Original-Signed-off-by: Paul Burton <paul.burton@imgtec.com> Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/207972 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8760 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-21mips: Add mips/ashldi3.c from LinuxVadim Bendebury
As MIPS toolchain does not provide adequate support for 64 bit division and shift operations, the missing functions are required to be provided by the user. This patch brings in the Linux implementation of the 64 bit arithmetic shift borrowed from arch/mips/lib/ashldi3.c (eg. Linux v3.14). BUG=chromium:406038 TEST=With the upcoming patches coreboot successfully builds for MIPS targets in chroot (coming later). Change-Id: I2168f69352a9b9e3c5d197489f701a442e65703c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 8ec616161be8ad3aeb6494e7121615e3329b414d Original-Change-Id: Ia1ccb29d4c9f3c95e04e06f6af7ce8a00e2e7455 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/214156 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8759 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-21libpayload arm64: fix mmu_disable() cache problemHC Yen
The raw_write_sctlr_current() cannot be used in mmu_disable() because it pushes some registers to cached stack, and then just after cache disabled, the value was gone. BRANCH=none BUG=none TEST=build and boot on mt8173-evb Change-Id: I512405b7917f27d16bdd3c51d9459827ad714e67 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: aafe64922cc4cd01ecb099db106d04538e3e57ff Original-Change-Id: I0dda8518d14c46fae1fe76e3629bd4ee81c1e0ee Original-Signed-off-by: HC Yen <hc.yen@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/240323 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8799 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21libpayload arm64: Add helper functions with el argumentHC Yen
Allow read/write to registers at a given el. Also, make read/write registers at current el call this newly added function. BRANCH=none BUG=none TEST=build and boot on mt8173-evb Change-Id: Id69f0fdc07193c5c7e997712f0cd99de6f41510b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c091917babc39d9ab997f51f81b486c9aa900c24 Original-Change-Id: I0944946642066b88331e497a92388e74e86902d0 Original-Signed-off-by: HC Yen <hc.yen@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/240322 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8798 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21libpayload arm64: don't modify cbtable entriesAaron Durbin
The framebuffer structure lives in the coreboot tables. Those tables have a checksum calculation applied over all the entries. Therefore, one shouldnot be modifying fields within the coreboot table entries because the calculated checksum would be wrong. BRANCH=none BUG=chrome-os-partner:31936 TEST=On ryu, confirmed dev screen still works as well as cbmem utility once booted. Change-Id: I93830a8efe98aa848f2b0f8388688de0e93b2f82 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 6026ca5ad0254c14c30412882dc63550656c7d16 Original-Change-Id: Ic9c164ded03d10d6f6f3ce15e9b38b1f6ce61a91 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/230471 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8797 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21libpayload arm64: Allocate framebuffer rangeJimmy Zhang
Allocate noncacheable memory for frame buffer and save base address to sys_libinfo. BRANCH=none BUG=chrome-os-partner:31936 TEST=build and test on ryu Change-Id: I19a8079616376dc7c1a8ecdbd7499c2553b8c6c3 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: cebb5650167264902548339bb1a2b428f3b7f4ed Original-Change-Id: I7bfbfefb92001632ce3d572a50e46188795c4ab8 Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/226404 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8796 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21libpayload arm64: Move console_init after post_sysinfo_mmu_setup callFurquan Shaikh
This is important since mmu is disabled during the post_sysinfo_mmu_setup call and calling printf can cause unaligned access. BUG=None BRANCH=None TEST=Compiles successfully and boots to kernel prompt with console_init Change-Id: I5ef72ee449fdcf30186f97485cc532d6c56b2c5d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 688ef3856d0502d057c9543ee7763601156e6385 Original-Change-Id: Ie376e394d084edd6c999fc9edde79f15a0264e7b Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/222664 Original-Reviewed-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8795 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21libpayload arm64: Add function to get new range from available memrangesFurquan Shaikh
Provide a function to obtain a new memrange with requested properties (type, size, alignment, max_addr and other restrictions) from the set of available memranges passed in coreboot table. One user of this function would be getting memrange for dma, another one would be framebuffer. BUG=chrome-os-partner:31634 BRANCH=None TEST=Compiles successfully and boots to kernel prompt Change-Id: Ic5a63ca2dca6c71f4ca2d77e2e2c8180d32a38e0 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3cd75756e1405e044c029f2878bfcc9c8c962bdf Original-Change-Id: I187d73a4d55d3c6f49afbe9852901672d25de8dc Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/222110 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8794 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21libpayload arm64: fix mmu bugsAaron Durbin
1. keep functions and objects used entirely within mmu.c as static. 2. DMA region finding needs to terminate. Therefore, the next address to be attempted needs to be less then the current end address. 3. Ensure mmu_ranges passed to mmu_init_ranges_from_sysinfo() has 0 entries marked as used. BUG=chrome-os-partner:31634 BRANCH=None TEST=Booted ryu with RAM hole above cbmem tables below 4GiB. Change-Id: I71a9cb89466978aa63fca5d8bee97b8af75ea206 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 66518fd86e676bbddf52e9d9afdd76d72c8e2222 Original-Change-Id: I5cb4e5009359cb04c4e1b5fe60845f80fbdff02c Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/221725 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8793 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21libpayload arm64: Initialize and enable MMUFurquan Shaikh
What this change does: 1) Initialize limited page tables as soon as we jump into libpayload. Basically two ranges are initialized. One is for the BASE_ADDRESS and other is for the coreboot_tables. With page tables initialized and MMU enabled, we jump into code to parse coreboot tables. 2) Once coreboot tables are parsed and we have complete picture of the memory, we perform a complete page table initialzation and enable MMU and then jump to payload. Additionally, we also: 1) Initialize DMA memory on our own depending upon the memory map. It ensures that the DMA buffer is placed in 32-bit memory. CQ-DEPEND=CL:216826 BUG=chrome-os-partner:31634 BRANCH=None TEST=Compiles successfully and we are able to start execution of libpayload in EL2 and reach kernel login prompt Change-Id: I8a6203e465868bc2a3e5cc377e108f36cc58e2fa Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 7695bb7afe34ea460282125a0be440e8994b01e4 Original-Change-Id: Ie0f47b7759d4ac65a6920f7f2f7502b889afda6d Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/216824 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8792 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21libpayload arm64: Add support for read and write registers at current EL in ↵Furquan Shaikh
assembly In order to ease the process of reading and writing any register at current EL, provide read_current and write_current assembly macros. These are included in arch/lib_helpers.h under the __ASSEMBLY__ macro condition. This is done to allow the same header file to be included by .c and .S files. BUG=chrome-os-partner:31634 BRANCH=None TEST=Compiles successfully for ryu Change-Id: I79241a944b68ebb24865e745a9835f54ab6d1a8f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 2b55fbde466126c4de7f5f7bb2d1427196be842f Original-Change-Id: I678ab89c4aa1b08898166e135b5ab2d6453bb5e8 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/214576 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8801 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21libpayload arm64: Add support for mmuFurquan Shaikh
Adds support for initializing mmu, setting up dma areas and enabling mmu based on the memranges passed on in the coreboot tables. CQ-DEPEND=CL:216826 BUG=chrome-os-partner:31634 BRANCH=None TEST=Compiles successfully Change-Id: Id41a4255f1cd45a9455840f1eaa53503bd6fef3f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f2c6676bf51fcd85b61e9e08a261634a78137c4c Original-Change-Id: I217bc5a5aff6a1fc0809c769822d820316d5c434 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/216823 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8791 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21libpayload arm64: Remove dependency on coreboot tables for dma areasFurquan Shaikh
Libpayload should be able to setup its own dma areas and not depend on coreboot tables for passing this information. This patch and next allow libpayload to setup dma areas while performing mmu_init BUG=chrome-os-partner:31634 BRANCH=None TEST=Compiles successfully and dma areas are setup properly with the mmu init patch Change-Id: I5f6fd19a957c7626a2bbe6b826c8987e64ed248f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4f3552b8d3439a8b12d1e0b15ef67dcb14b8c96a Original-Change-Id: I44d9f394fa349abd7182c4ba10f1eaefd6e4fdaa Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/216822 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8789 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21libpayload arm64: Add functions for reading memrangesFurquan Shaikh
BUG=chrome-os-partner:31634 BRANCH=None TEST=Compiles successfully Change-Id: I12e7cdaf07c1bc4802a04dadd85384939b5a67e0 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c454a3d60b0e087df79de4fd9cff09596ae12ca5 Original-Change-Id: Iec82d56ae4a5f1ac6243afef1f453de3905d869c Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/216821 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8788 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21libpayload arm64: Remove the DONT_USE_DC macroFurquan Shaikh
By default we dont want to use the special DC instruction. Thus getting rid of the DONT_USE_DC macro and enabling code appropriately in memset.S BUG=chrome-os-partner:31634 BRANCH=None TEST=Compiles successfully and memset works fine for mmu init Change-Id: Icb3193f4f0d122726dcdacbdcacbf53eba30e235 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 54f639ef2348acab54e32b18f6826a67bf52bc14 Original-Change-Id: Id89ec2c1731d21496eca617a3c03abaf48062908 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/216820 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8787 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21libpayload arm64: Add functions for {read/write}_tcr_currentFurquan Shaikh
BUG=chrome-os-partner:31634 BRANCH=None TEST=Compiles successfully Change-Id: I7a3dc9420fa85fa8f7ab70f0f55b200f432d3240 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 20c89d5df653ad65ad6d8ecc4c26de4c5e447564 Original-Change-Id: Ibd801ef1d777d306f35dde3c2b120af41d8f27e4 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/216819 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8786 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21libpayload arm64: Remove tight-coupling with any particular ELFurquan Shaikh
Allow more flexibility by reading and writing to system registers at current EL. Instead of specifying what _ELx register to write to, code can specify _current. BUG=chrome-os-partner:31634 BRANCH=None TEST=Compiles and boots to kernel on ryu Change-Id: Id38b675bfe67ca1e25f8c268192114e3f0bee800 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 6d4d07e26fc964dc3aaebfe03db59596d90093e9 Original-Change-Id: Ic1d9e18e6fc016a04f17621a148e62d6cbd04ce7 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/214577 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8785 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21libpayload arm64: Add library helpersFurquan Shaikh
Add library helpers to access standard arm64 registers. This library also provides functions to directly read/write register based on current el. So, rest of the code doesnt need to keep checking the el and call appropriate function based on that. BUG=chrome-os-partner:31634 BRANCH=None TEST=Libpayload and depthcharge compile successfully for ryu Change-Id: Ibc0ca49f158362d4b7ab2045bf0fbd58ada79360 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 2ca6da580cb51b4c23abdaf04fee2785e5780510 Original-Change-Id: I9b63e04aa26a98bbeb34fdef634776d49454ca8d Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/214575 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8784 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21libpayload arm64: Make exceptions workFurquan Shaikh
BUG=chrome-os-partner:31634 BRANCH=None TEST=test_exc generates and handles exceptions properly Change-Id: If3ecab93be6d02942b52960ec97edc687bedf64b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: bba2caae0bd436ba9e5215f5d8606ce8c4987c98 Original-Change-Id: I4abe8a0e426eab2532852179dbb32505353cd0a1 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/214609 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8783 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21libpayload arm64: Initialize exception stackFurquan Shaikh
Initialize exception stack to be able to handle exceptions properly BUG=chrome-os-partner:31634 BRANCH=None TEST=test_exc successfully generates and handles exceptions on ryu Change-Id: I19163fae080b9ac3297a7ffe404446e427bf9a1c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 99157687c5178c3b3eb79f5589343db1b2b4cc86 Original-Change-Id: I4dc83ff32c1665e22127bf0b1e6d4c6b45c07a4a Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/214608 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8782 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21libpayload arm64: Add console_init to enable console logsFurquan Shaikh
BUG=None BRANCH=None TEST=Compiles sucessfully and hello libpayload seen on screen Change-Id: If312e005e306f7f70138aa27d2ef5b39620ec91e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 6d6aa84d7255d33e085f12c609f32309521ff58e Original-Change-Id: I73f888a7b8aa0065c1ca0bf7857c445cc5678cdc Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/214073 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8781 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21libpayload: arch/mips: add virt/bus/phy_to_bus/phy/virt operationsIonela Voinescu
BUG=chrome-os-partner:31438 TEST=tested on Pistachio FPGA and bring up board; works as expected BRANCH=none Change-Id: I368494f388b82969dda0ce73a38824791efce616 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e4c2bbcbdbcf706062724cffe2d5f15953468ace Original-Change-Id: Id5c9b1d65c6ec87f2aba06995dc940c50afb041f Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/245386 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/8746 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-21libpayload: mips: add SOC CPU frequencyIonela Voinescu
Add CPU frequency corresponding to SOC. BUG=chrome-os-partner:31438 TEST=tested on Pistachio bring up board; behaves as expected. BRANCH=none Change-Id: I05458070a15c6cf1ef0fc2104715a63902a38887 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4afe332bcc41afeb7e31e918e345c3336f7dc604 Original-Change-Id: I55b788faf7984bafc2509cac69867a772c7cb863 Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/241427 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/8853 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-21libpayload: mips: correct platform IDIonela Voinescu
BUG=chrome-os-partner:31438 TEST=tested on Pistachio bring up board; behaves as expected. BRANCH=none Change-Id: I8e5ac80e95b5169102eaa075bc22045c0789d486 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4afe332bcc41afeb7e31e918e345c3336f7dc604 Original-Change-Id: I55b788faf7984bafc2509cac69867a772c7cb863 Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/241427 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/8745 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-21libpayload: pistachio: fix timer implementationIonela Voinescu
timer_raw_value must return the number of CPU ticks, and not the time obtained by dividing the ticks by the CPU frequency. The CPU counter is increased at every 2 CPU clocks and therfore the number of ticks will be the counter value multiplied by 2. BUG=chrome-os-partner:31438 TEST=tested on Pistachio FPGA; it works properly. BRANCH=none Change-Id: Iae62cb328e882f84822250bdf72146321ca9bbe0 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 7ab25ce7dcaffb453ee774d870963a56444d46af Original-Change-Id: I74408950900463a2c054d5aebd3edb005a325adb Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/242393 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/8744 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21libpayload: mips: add memcmp to the MIPS string functionsIonela Voinescu
The default string functions work with multiple of 4 bytes (sizeof(unsinged long)); MIPS will use LW/SW instructions for these operations and if the source and destination addresses are not aligned it will trigger an exception. Therefore, this implementation does all data access operations per byte, because there is no guarantee that the provided strings are properly aligned. BUG=chrome-os-partner:31438 TEST=tested on Pistachio bring up board; behaves as expected BRANCH=none Change-Id: I05b43673deb954f022d12cb9c3d7baac26be2a34 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 8e13b3d31726404abd8c8e5c8780d3d3e16e032d Original-Change-Id: I456e312eb6b7fee2eff10e461af7f578aed07648 Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/241885 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/8743 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-21libpayload: arch/mips: Add basic MIPS architecture supportIonela Voinescu
Add the basic build infrastructure and architectural support required to build for targets using the MIPS architecture. This will require the addition of cache maintenance. BUG=chrome-os-partner:31438 TEST=tested on Pistachio FPGA with Depthcharge as payload; successfully executed payload. BRANCH=none Change-Id: I75cfd0536860b6d84b53a567940fe6668d9b2cbb Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 758c8cb9a6846e6ca32be409ec5f7a888ac9c888 Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Change-Id: I0b9af983bf5032335a519ce2510a0b3aca082edf Original-Reviewed-on: https://chromium-review.googlesource.com/219740 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8741 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-21libpayload: cbfs: Fix ram_media map() error return valueJulius Werner
The correct return value for errors on a cbfs_media->map() call is CBFS_MEDIA_INVALID_MAP_ADDRESS, not NULL. Not sure if that's the best choice (since 0xffffffff is probably a more likely valid address than 0 there), but that's what the upper layers expect right now. BRANCH=veyron BUG=None TEST=Press CTRL+L with an RW_LEGACY section filled with 0xff. Observe how cbfs_get_header() returns failure without doing a bunch of NULL pointer accesses first (not that those have any visible effect on Veyron, but that's another problem...) Change-Id: I3d012fc9af9da6e01159990a6bdd62c38fc22329 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3a609e17bb9b0ef4d3a833f72fa4fbfd8e8cb0ab Original-Change-Id: I0793434116a8c568e19fe0dee24f13942fc50f25 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/238991 Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/8758 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-21libpayload: Add RAM code to sysinfo_tDavid Hendricks
This adds CB_TAG_RAM_CODE and an entry to sysinfo_t. BUG=chrome-os-partner:31728 BRANCH=none TEST=Built and booted on pinky w/ depthcharge patch and saw that /proc/device-tree/firmware/coreboot/ram-code contains correct value Change-Id: I35ee1bcdc77bc6d4d24c1e804aefdbbfaa3875a4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ca6d044f2e719ded1d78a5ab3d923e06c3b88d6b Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: I69ee1fc7bc09c9d1c387efe2d171c57e62cfaf3f Original-Reviewed-on: https://chromium-review.googlesource.com/231132 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/8755 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-21libpayload: Add support for parsing RAMOOPS range from corebootFurquan Shaikh
CQ-DEPEND=CL:228856 BUG=chrome-os-partner:33676 BRANCH=None TEST=Compiles and boots to kernel prompt. ramoops console log verified after causing kernel to fault. Change-Id: I5af9b995113ee30ac60347acba8fa945fb5cd17a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 80c843fc78b137eb5540f8fefc4a69545b896fb6 Original-Change-Id: I8886015977e1fd999ef74fe73d08cff935cbce5c Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/228742 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8754 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21libpayload: make wifi calibration table available through sysinfoVadim Bendebury
The WiFi calibration blob saved in the CBMEM by coreboot needs to be visible by depthcharge to supply it to the kernel. BRANCH=storm BUG=chrome-os-partner:32611 TEST=none yet Change-Id: I43a857f073a47ca315d400df4c53d5eb38e91601 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 46a649608e6740e07c562c722fadd8c64e264b5f Original-Change-Id: Iecd8739c9269b58064b3c3275f5376cebcd6804b Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/225506 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8753 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-21chromeec: provide proto v3 over i2c supportAaron Durbin
Certain boards need to speak proto v3 over i2c. Leverage the transport agnostic API to share the logic with other proto v3 impelementations. BUG=chrome-os-partner:31148 BRANCH=None TEST=Built and ran on ryu. Can talk to the EC successfully. Change-Id: I1d0cd6907057af4ded3c4460193bbe1d897a1db7 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: cb9ac965ad04c9491f40fd9aa595176a28a467b3 Original-Change-Id: Ib699120fd232392e8caa0889c2bf40f4587a8a35 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/211139 Original-Reviewed-by: Stefan Reinauer <reinauer@google.com> Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8828 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21chromeec: allow transport implementation to provide buffers for proto v3Aaron Durbin
Depending on the transport mechanism for proto v3 different bytes need to be send and/or read before the request and response. Depending on the software and/or controller interface that requirement leads to needing to copy data into temporary buffers. Avoid this by allowing the transport mechanism to provide the request and response buffers. BUG=chrome-os-partner:31148 BRANCH=None TEST=Built for rush and ryu. Ran on ryu with i2c implementation. Also built for rambi to check x86 systems. Change-Id: I35d4d69bd1fa900fc0cfe3822496f381405bdcb1 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c7224426e1d0bcf06ed010131a2462a6ca201d8b Original-Change-Id: Iad6cce566a253ca72e6f5009a97235ece0a6c1b5 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/211138 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8827 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21chromeec: correct response length for VBNV writeAaron Durbin
The EC doesn't return any data when one performs a write to VBNV context. Therefore there is a mismatch of expectations. Correct this by properly setting the expected response length. BUG=chrome-os-partner:31148 BRANCH=None TEST=No longer hanging while writing to VBNV on ryu. Change-Id: I7077a507c3280358dac1f88ece62cacee9b71bea Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c1735c3377163aeb9e90155cb9f081a1eea919c9 Original-Change-Id: I455724f20f5442bd62a792f09273227417475f07 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/211137 Original-Reviewed-by: Stefan Reinauer <reinauer@google.com> Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8826 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21libpayload arm64: Add function to get coreboot table ptrFurquan Shaikh
BUG=chrome-os-partner:31634 BRANCH=None TEST=Compiles successfully Change-Id: If89e7a537e6f0321ef43641c924a8ef057f51147 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 1f39cdbf68b674ef9b65441038ec79548145a88d Original-Change-Id: Ie9904bf8abfa5ce1d87a586e5b08eb320793942f Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/217821 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8790 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21cbmem: stop assuming 1MiB of memory can be mappedAaron Durbin
The default mapping size is 1MiB of ram. However, not all systems allow 1MiB of memory to mapped depending on the kernel's memory map. Therefore, be explicit about the sizes to mmap(). The only path that wasn't cleaned up was the coverage path as that needs to handle dynamic cbmem. The correct way to fix that is to add a global like the timestamps that is set while parsing cbtable. BUG=chrome-os-partner:31355 BRANCH=None TEST=Can cbmem -ltc on ryu. Change-Id: I548afa5ddbe0a859f52bc2ab2d0931186ee378a5 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: df4991ce1da7f0c25e99d84222cbc8d3189d0d66 Original-Change-Id: I27b70ae8a8fba168d1c1829bbef0135c7b651eac Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/221971 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8829 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21arm: add _end symbol to bootblock.ldAaron Durbin
It's helpful to view program size by inspecting the symbols. _start and _end exist on romstage and ramstage. In order to be consistent add _end for bootblock too. BUG=None BRANCH=None TEST=Built and noted bootblock has _end symbol. Change-Id: I06634b317e957e8271bf32530a56b5541c79b9ee Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b4ac926b30749d22e90a6f12ebac52107e241526 Original-Change-Id: I7f0b4dd4078c7d23c70949563b4c3f4df9e66142 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/210832 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8824 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21cbfs: change 1 message level to WARNING if cbfs can't find specific dataKane Chen
In some cases, we need to use 1 common VGA device ID to share among different VGA devices. But it will show error when it can't find a specific pci rom by PCI DID. in fact, it will find the pci rom with common vga ID. Without this commit, you may need to skip error check during suspend_stress_test BUG=none BRANCH=none TEST=build OK, and check no error on Auron and Samus Change-Id: I2b18347e46c831038f048cfd0b065430c72c6f30 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4c32ee21b4c942182e5ffb21b58b93fa7c082223 Original-Change-Id: Ib743e960f772b7e2e73a1feb80790a13bd8c06c7 Original-Signed-off-by: Kane Chen <kane.chen@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/217415 Original-Reviewed-by: Bernie Thompson <bhthompson@chromium.org> Reviewed-on: http://review.coreboot.org/8821 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21superio: ite8772f: Exit extemp busy stateRyan Lin
It causes fan top speed due to this bug + our board-specific workaround, and causes invalid temperature sensor readings. Therefore, re-configure the register "External Temperature Sensor Host Control Register" to terminate processes when this issue happens. BUG=chromium:402204 TEST=ran suspend_stress_test 500 times Change-Id: I439d5de798fbe999e4eec5497e6969b7b453121b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b82f2922c7fce3ca6b2797a8d9775e9db2817fe9 Original-Change-Id: I6e71b6a46a31b00e541c304f1ed58c1678c1d42e Original-Signed-off-by: Ryan Lin <ryan.lin@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/219445 Original-Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/8820 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21ARM64 rmodule: Add new reloc type R_AARCH64_LDST8_ABS_LO12_NCFurquan Shaikh
BUG=chrome-os-partner:33962 BRANCH=None TEST=Compiles and boots to kernel prompt. Change-Id: Id7b0dfb5a51c2f29bdb031b98606940c118959ec Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 7a1c4d2f35c135d542708c4dabcca5e8c1d453c0 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Change-Id: If132323885f23d75e1fcde064398e85c2c17f257 Original-Reviewed-on: https://chromium-review.googlesource.com/231560 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8809 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21cbfstool: Remove empty line that looks out of placeJulius Werner
BRANCH=None BUG=None TEST=Manual Change-Id: I8b31a0b194d353ea3e7863513f2e36f3e032fad8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 7ccba49a7c2372cdfff6e2947e417d4d4f5436c2 Original-Change-Id: I9beebdf29e4fc4aa645581146fdc61c659de72df Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/229973 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org> Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: http://review.coreboot.org/8808 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21rmodtool: add another aarch64 relocationAaron Durbin
BUG=chrome-os-partner:32112 BRANCH=None TEST=Built secmon which had this type of relocation. Change-Id: Ie367c348fbf59465e238e5fa60f217f5373501b3 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a754bc1fe39c19ab8b2f7be9648cccb06156b0ef Original-Change-Id: If170d9e270daf3153e92d16c06516915c727e930 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/218843 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8807 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21rmodtool: Add support for aarch64Furquan Shaikh
BUG=chrome-os-partner:31615 BRANCH=None TEST=Compiles succesfully, rmodule created and loaded for ryu Change-Id: Icc80b845fe43a012665d77c3ef55bd30784fd3fc Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 24ad4383a9ea75ba6beb084451b74e8a8735085b Original-Change-Id: I4f3a5dbb8fc8150aa670d2e6fed56a6774feb4a6 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/214329 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8806 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21mainboards/amd/fam10: Add romstage timestampsTimothy Pearson
Example output: 1:start of rom stage 542 2:before ram initialization 193,989 (193,447) 3:after ram initialization 3,319,114 (3,125,124) 4:end of romstage 3,320,004 (889) Change-Id: Idcde7dc4c7a1d6c3118c82b67e8c2fcd4a07553b Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8776 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-03-21x86: fix romstage_null.debug link w/o --gc-sectionsAaron Durbin
When adding gargabe collection to x86 the --gc-sections flags was inadvertently missed when linking romstage_null.debug. Fix this omission. Change-Id: I7d2700755afa78459c6f8707303a0e64936a1a9f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8850 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2015-03-21libpayload ehci: Use 64-byte aligned data structures for periodic transfersJim Lin
Chapter 3.1 "Periodic Frame List" of EHCI 1.0 specification says "Frame List Link pointers always reference memory objects that are 32-byte aligned." jwerner@chromium.org suggests setting it to be 64-byte aligned for consistency with other EHCI queue structures. BUG=chrome-os-partner:31993 TEST=Tested on nyan platform. Before adding patch, USB keyboard behind an external hub is not working to switch between "Default Locale" and "English" (after pressing ESC+REFRESH+POWER on embedded keyboard and later Left/Right-Arrow key on USB keyboard). Change-Id: Ie6259f2df20ae2618c2074e831fad087f227091d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 23fc02e6ba3b17be4eaf18810ec6fc0d9c0e0b9a Original-Change-Id: If52ddc43ebd5d509c19f104928dced5bd09b1706 Original-Signed-off-by: Jim Lin <jilin@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/218403 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/8738 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21libpayload: EHCI: Fix transaction error for interrupt transferJim Lin
Data toggle should be running like 0, 1, 0, 1, ... In the failed case (where a low-speed USB keyboard or km232 device is installed), data toggle will be running as 0, 1, 0, 1, ..., 1, 1. Therefore causing Halted or Transaction Error bit to be set in qTD Status field. BUG=None BRANCH=None TEST=Tested on nyan_kitty platform, firmware-kitty-5771.61.B branch. Attached USB keyboard or km232 device to root-hub port (same side as SD card slot). Made sure no transaction error after doing interrupt transfer. Change-Id: I576f3c583dae4c279a6e0e8ffdfce5abe463277d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 64b0428aaab869e20f6720669e953acf82ecb846 Original-Change-Id: Ic2c0f95cff2ae6e314967b0b82231a962255f1a7 Original-Signed-off-by: Jim Lin <jilin@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/233857 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/8747 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21libpayload: provide basic 64bit division implementationVadim Bendebury
These functions are usually provided by gcc lib, which is not supposed to be included on embedded platforms. This patch adds a no thrills C implementation. Other than MIPS platforms are happy using the gcc library provided implementation, but in case of Chrome OS MIPS toolchain the libraries are compiled with the small GOT, such that the entire data segment does not fit. With this implementation mips, arm and x86 targets build fine. BRANCH=none BUG=chrome-os-partner:31438 TEST=checked the logic by incorporating this code into a C file and running a loop continuously comparing random inputs' division and left and right shift results. The test ran for extended periods of time without failure. Change-Id: I468acd2fdbcdd493a76758a394e79cad35f9535a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 2cc5f8668dd2609408af8da5a74c5a3d063fc0d3 Original-Change-Id: Ib46616d7eb0b2b497199270057514f730bb1cb0b Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/232232 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8742 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-20Kconfig: Add MAX_REBOOT_CNT descriptionTimothy Pearson
Change-Id: Ie28812a84bd063d097e23294b8588f974a3a19e9 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8725 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-20bootblocks: use run_romstage()Aaron Durbin
Instead of sprinkling the cbfs calls around (as well as getting return values incorrect) use the common run_romstage() to perform the necessary work to load and run romstage. Change-Id: Id59f47febf5122cb3ee60f9741cfb58cb60ccab5 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8711 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-20romstages: use common run_ramstage()Aaron Durbin
Instead of sprinkling the cbfs calls around (as well as getting return values incorrect) use the common run_ramstage() to perform the necessary work to load and run ramstage. Change-Id: I37b1e94be36ef7a43efe65b2db110742fa105169 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8710 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-20loaders: add run_romstage() function to bootblockAaron Durbin
Provide a common run_romstage() function to be used by bootblocks to load and run romstage. This is similar to run_ramstage() in that it provides a single entry point for doing the necessary work of loading and running romstage. Change-Id: Ia9643cc091f97a836cf5caefdff8df4a3443df4c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8709 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-20qemu-riscv: add preram_cbmem_consoleAaron Durbin
Miraculously a console is being compiled in for romstage. However, as no calls were potentially printing to the preram console this was being ignored. Instead provide the symbol required so as not to fail the build. Change-Id: Id8f0b6e6d15b41fa7fe1b63bf2d91f15baa0edda Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8712 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-20loaders: add program_loading.h header fileAaron Durbin
Instead of two headers for payload and ramstage loading combine the 2 files into one. This also allows for easier refactoring by keeping header files consistent. Change-Id: I4a6dffb78ad84c78e6e96c886d361413f9b4a17d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8708 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-20verstage should include the CBFS SPI wrapper, when configuredVadim Bendebury
Vboot2 targets so far did not have COMMON_CBFS_SPI_WRAPPER configuration option enabled, so the verstage is missing the relevant files in some Makefiles. This patch fixes the problem. BRANCH=none BUG=none TEST=with the rest of the patches applied cosmos target builds fine with COMMON_CBFS_SPI_WRAPPER enabled Change-Id: I3ce78c8afc5f7d8ce822bbf8dd789c0c2ba4b99c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b72693c96f7d8ce94ce6fe12b316d5b88fded579 Original-Change-Id: Iab813b9f5b0156c45b007fe175500ef0de50e65c Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/223751 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8772 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2015-03-20spi: Add GigaDevice GD25LQ64C/GD25LB64C SPI ROM supportMarc Jones
GD25LQ64C and GD25LB64C have the same ID and settings. BUG=chrome-os-partner:25907 BRANCH=baytrail TEST=Boot with GD25LQ64 and check MRC data save/restore works. Change-Id: I8a4aa7cabd9a7657c2f0bae255a87341db3f1061 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 20b5896adbbbdedcb1b7de435466dcc6bfa703cb Original-Change-Id: I86d1e69552b6000faa9e0523356e27d7e2a6a6db Original-Signed-off-by: Marc Jones <marc.jones@se-eng.com> Original-Reviewed-on: https://chromium-review.googlesource.com/193238 Original-Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/8770 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2015-03-20spi: do not use malloc in Gigadevice driverDavid Hendricks
This allows us to use the driver before ramstage. BRANCH=none BUG=none TEST=built and booted on Pinky Change-Id: I0700388b0e4e0562e3c0a52863c8357097bfd8d6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: cd57587dab74de509d5c50cfc1ad337d765af6c8 Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: I0ce901331e401274254b8889484ffb41359119fa Original-Reviewed-on: https://chromium-review.googlesource.com/235864 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/8774 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-20spi: do not use malloc in Winbond driverVadim Bendebury
When the driver is included in bootblock, malloc() is not available. Come to think of it, it is perfectly fine to use a statically allocated structure for the SPI device descriptor - coreboot is unlikely to require concurrent support of multiple SPI devices of the same kind. BRANCH=none BUG=chrome-os-partner:31438 TEST=bootblock on the FPGA board recognizes the installed Winbond device: coreboot-4.0 bootblock Tue Nov 11 07:27:24 PST 2014 starting... SF: Detected W25Q16 with page size 1000, total 200000 Change-Id: Iea1936a219d38848580a10f75eb8bbcab17e6507 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0b4082442aa526d387a80cb5872d78670e6b468b Original-Change-Id: Iaa69d610ef18e69b1ae5ade2d958f9fe1595a723 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/228959 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8771 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2015-03-20spi_flash: add support for S25FL116KDaisuke Nojiri
S25FL116K family uses the first 3 bytes in response to a legacy identification command (9f) while previously supported models use the last 4 bytes. This change defines identify functions to allow both types to be handled correctly. BUG=none BRANCH=tot TEST=verified romstage is loaded on cosmos development board. Change-Id: I1970a9af17e81299fada5029724d405de4022156 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 65ff436db2355cb68a766a3dedbcd7e2f765e6db Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Change-Id: Icdd2645e356652672c4482e7b805da1bc0f21e71 Original-Reviewed-on: https://chromium-review.googlesource.com/234431 Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/8773 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-20libpayload: move MRC processing to x86 path and remove ACPI_GNVS duplicationVadim Bendebury
It turns out that CB_TAG_ACPI_GNVS is handled in both x86 specific and common coreboot table parsing code. The MRC cache case used only by x86 is handled in the common code. This patch restores sanity and moves processing to where it belongs. BRANCH=none BUG=none TEST=verified that arm and x86 targets build. Change-Id: Iaddaa3380725be6d08a51a96c68b70522531bafe Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0afae893d5027026cb666cd46e054aeae4e71f83 Original-Change-Id: I2c114a8469455002c51593cb8be80585925969a7 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/225457 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8752 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-20libpayload: cros: include mac addresses in coreboot tableVadim Bendebury
Pass MAC addresses found in coreboot table into lib_sysinfo. BUG=chrome-os-partner:32152 TEST=with all changes in place MAC addresses are properly inserted into the kernel device tree. Change-Id: I6b13c1c2c246362256abce3efa4a97b355647ef8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e2fe74f86b4ed43eb8a3c9d99055afc5d6fb7b78 Original-Change-Id: I1d0bd437fb27fabd14b9ba1fb5415586cd8847bb Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/219444 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8751 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-20libpayload: Consolidate coreboot table parsingVadim Bendebury
There are three instances of coreboot.c in libpayload. for x86, arm and arm64 architectures. The arm and arm64 instances are exactly the same. The differences with the x86 instance are as follows: - a very slightly different set of coreboot table tags is parsed (one tag added and two removed) - instead of checking a fixed address if it contains the coreboot table, the x86 version iterates over two address ranges. This patch refactors the module, leaving architecture specific processing in arch subdirectories and moving the common code into libc. BUG=none TEST=none yet Change-Id: I1c7ad6f74e3498e93df78086ba0ff708c08e0a5c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3df209d58ebd5c5b1cf0168f6466e065d1ef3598 Original-Change-Id: I6dfed73f6ba5939f692d0f98d2774c0e0312a25f Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/210770 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8750 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-20libpayload: Add board id parsingVadim Bendebury
Make board ID value supplied in the coreboot table available to the bootloader on all three architectures. BUG=chrome-os-partner:30489 TEST=none yet Change-Id: I6c2d39e94212b55650929d7d99896581d23f789d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 723e4a600a5d3a03e960169b04f8322f6dd2486b Original-Change-Id: I7847bd9fe2d000a29c7ae95144f4868d926fb198 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/210430 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/8730 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-20libpayload: Do not include gcclib for mips targetsVadim Bendebury
As opposed to other architectures, on MIPS gcc toolchain provided gcclib is not always adequate, for instance when the library does not account for the case when data segment is too large to fit into the 64K GOT. Let's make sure the library is not included when building for MIPS targets. BRANCH=none BUG=chrome-os-partner:31438 TEST=with the rest of patches applied the FPGA board boots all the way to verifying and loading the kernel from the USB stick. Change-Id: I710d3c49bdc57877152cf28d5bd8cb4fa4d0b9ad Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f8d7d84c81af7e3eee1c8f3304c15069e8701cde Original-Change-Id: I1a26b9e575a20101329359b80dffc236ef7f9e9f Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/232231 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8740 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-20stdlib: Add IS_ALIGNED macroAndrew Bresticker
Add a macro to check if a value is aligned. BUG=chrome-os-partner:36258 BRANCH=none TEST=Build and boot on Pistachio. Change-Id: I0680954eb1b1964a631527f96aa0570a32944fa1 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4f1717648e0a4b54217d71f8d0a15d496737d156 Original-Change-Id: Ie0bc1374918a7ffaaec5fea62c1193a42edd416c Original-Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/246692 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/8757 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-20libpayload console: Add check for already existing driverFurquan Shaikh
Add support to check if the driver for console_out or console_in is already present in the list. If console_init is called twice, then the driver might get added twice leading to a loop. BUG=None BRANCH=None TEST=With console_init in libpayload and depthcharge both, there are no console loops seen anymore Change-Id: I9103230dfe88added28c51bff33ea4fa1ab034c1 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 6931236ba2cfa71849973fe41cc340b7d70656ad Original-Change-Id: If9a927318b850ec59619d92b1da4dddd0aa09cd1 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/214072 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8739 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-20libpayload: UTF-16LE to ASCII conversionDan Ehrenberg
This patch adds a simple function to convert a string in UTF-16LE to ASCII. TEST=Ran against a string found in a GPT with the intended outcome BRANCH=none BUG=none Change-Id: I94ec0a32f5712259d3d0caec2233c992330228e3 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 1104db8328a197c7ccf6959a238277f416a2113a Original-Signed-off-by: Dan Ehrenberg <dehrenberg@chromium.org> Original-Change-Id: I50ca5bfdfbef9e084321b2beb1b8d4194ca5af9c Original-Reviewed-on: https://chromium-review.googlesource.com/231456 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/8733 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>