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2015-04-10x86: Support reset routines in bootblockLee Leahy
Expand the boot block include file to allow for a file containing reset routines to be added. Prevent breaking existing platforms by using a Kconfig value to specify the path to this file, and have the code include this file only if the Kconfig value is set. BRANCH=none BUG=None TEST=Build and run on Glados Change-Id: I604f701057d7018f2ed9c3ba49a643c4bca13f00 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: c109481d9503916e19ed300c1a3f085e0d2b5c51 Original-Change-Id: I3214399f8156b5ea2ef709ce77e3915cea1523a3 Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/248300 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Leroy P Leahy <leroy.p.leahy@intel.com> Original-Tested-by: Leroy P Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/9504 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10broadwell: Correct XHCI offset for USB 3.0 portsJulius Werner
Looks like Intel has added two more USB 2.0 ports from LynxPoint to Broadwell, which shifted the port offsets of the USB 3.0 ports behind them. The USB 2.0 ports are now 0x480 to 0x520 and the 3.0 ones 0x530 to 0x560 (at least according to what my kernel seems to think). The offset of the first USB 3.0 port is hardcoded and seems to have been copied over without accounting for this, meaning when we try to operate on all USB 3.0 ports we actually operate on the last two 2.0 and the first two 3.0 ports instead. This patch should fix the bug for now. In the future, we might want to consider dynamically detecting port locations through the Protocol Capability structures at the end of the XHCI register set instead. BRANCH=samus BUG=chrome-os-partner:35320 TEST=TODO Change-Id: Ifab6e484980fd4cd0daf80ceb292ddced2ab1aea Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 525f359c0b6b95b260add2b4617fd86119d69397 Original-Change-Id: Ic2becf2b043612270909ceef66e7d58efc8fcbe1 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/247351 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-by: Todd Broch <tbroch@chromium.org> Reviewed-on: http://review.coreboot.org/9502 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10broadwell: Set PCIe replay timeout to 0xDDuncan Laurie
This changes the PCIe replay timeout value in the root ports to be 0xD to fix correctable AER replay timer timeout errors. BUG=chrome-os-partner:31551 BRANCH=broadwell TEST=build and boot on samus Change-Id: I3084cc633da6e9f9a783d923a3fe2c1097e711fd Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: a64897efc26731fa3896e6d9a413941807296a28 Original-Change-Id: I53d87ad38856fd7de7f3f06a805c9342373bc968 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/245359 Original-Reviewed-by: Shawn N <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/9501 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10samus: Use codec internal 1.8V as DACREF sourceBen Zhang
This is needed for audio playback after we disconnect PP1800_CODEC from DACREF to avoid noise coupled on PP1800_CODEC, which makes recording noisy. For recording, DACREF comes from mic vref pump voltage. For playback, DACREF comes from internal 1.8V. BUG=chrome-os-partner:32953 BRANCH=samus TEST=Set MICBIAS to 2.970V on Samus, playback/recording is clean Change-Id: I65fb6dbfab54c7c4de6496fd4a0d666baead28ec Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 3e62a61f6cf6042f6d653a827698b55ac86e2d2b Original-Change-Id: I27430691e469dd7f4056d99438ce080062b58b9a Original-Signed-off-by: Ben Zhang <benzh@chromium.org> Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/241179 Reviewed-on: http://review.coreboot.org/9500 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10samus: Set MICBIAS1 to 2.970VBen Zhang
The default micbias1 voltage is 1.476V (1.8V * 0.82) which does not match what's specified on the schematic. This patch sets the voltage to 2.970V (3.3V * 0.90) according to the schematic. BUG=chrome-os-partner:32953 BRANCH=samus TEST=Set MICBIAS to 2.970V on Samus and verified with a scope Change-Id: I1ced834a5afe2de3fccf4bcff8ec9c8e5718f60a Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 176f9272801a3de5ed6fc05ade06042e2a2c0a5c Original-Change-Id: Icdbc1b5f65fe28591d54544372bdc2dacb50e9c1 Original-Signed-off-by: Ben Zhang <benzh@chromium.org> Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/241178 Reviewed-on: http://review.coreboot.org/9499 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10baytrail: add code for supporting 2x ddr refresh rateKane Chen
this code change provides a way to enable 2x refresh rate in RW image In baytrail, it enables 2x refresh rate by default BUG=chrome-os-partner:35210 BRANCH=none TEST=check the register is set properly on rambi Change-Id: I2a935b570c564986898b6c2064fc7ad43506dcba Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: c740d403708862514be9fa24f56b2764328979eb Original-Change-Id: I84f33d75ea7ebfea180b304e8ff683884f0dbe8a Original-Signed-off-by: Kane Chen <kane.chen@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/241754 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9498 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10broadwell: Add configuration for tuning VR for C-state operationsDuncan Laurie
Add some configuration options that allow tuning the VR for C-state settings that may be able to reduce noise. - Add option to enable slow VR ramp rate for C-state exit - Add variable to configure the minimum C6/C7 voltage BUG=chrome-os-partner:34771 BRANCH=broadwell TEST=build and boot on samus Change-Id: I01445d62fbfcf200b787b924d8d72685819a4715 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: ed8f355e60292c82791817ae31bff58ac2390a72 Original-Change-Id: I8af75b69c8b55d3e210170ee96f8e22c2fd76374 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/241950 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9497 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10samus: Adjust SATA Gen3 TX voltage amplitudeDuncan Laurie
Reduce the SATA Gen3 TX voltage amplitude by 210mV based on the provided test results to help with SATA validation. BUG=chrome-os-partner:34121 BRANCH=samus TEST=build and boot on samus and ensure SATA is still working, firmware image will be provided for full validation. Change-Id: I574d2f457b7b6831a339602a4165e959a0e2ee7d Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 9500ec152d8f9c90513811b1a92d1a8c155f514a Original-Change-Id: I233fa1a9a7f2877a97ef6834304680f82b958e82 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/241800 Original-Reviewed-by: Shawn N <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/9496 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10broadwell: Preserve VbNv around cmos_initDuncan Laurie
To ensure that boot flags (legacy, usb, signed-only) are properly restored from CMOS and used in the first boot after a battery removal or RTC reset then the VbNv region needs to be preserved around the cmos_init call. When using vboot firmware selection and VbNv is stored in CMOS then that region of CMOS will have been re-initialized by the time we call cmos_init and reset CMOS if the chipset flag was set indicating a problem. BUG=chrome-os-partner:35240 BRANCH=broadwell TEST=manual testing on samus: 1) boot in dev mode, enable dev_boot_legacy and ensure it works 2) on EC console pulse PCH_RTCRST_L low for a second 3) ensure first boot after RTC reset will still boot legacy mode 4) remove battery for a time 5) ensure first boot after battery is re-inserted will still boot legacy mode Change-Id: Ica256bbdcba6d4616957ff38e63914dd15f645c6 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 881c7841c95dec392a66eef38a7112c1f385fdfa Original-Change-Id: I4c33f183ba4b301d68ae31c41fc6663f3be857b0 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/241529 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9495 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10broadwell: Add function to apply PRR to a range of SPI flashDuncan Laurie
This function will use the next available/free protected range register to cover the specified region of flash and write protect it until the next reset. This will be used by the common MRC cache code to protect the RW_MRC_CACHE region after it is updated. In order to communicate to the common NVM code that this function is defined also enable CONFIG_MRC_SETTINGS_PROTECT variable. BUG=chrome-os-partner:28234 BRANCH=broadwell TEST=build and boot on samus Change-Id: I710c6a69f725479411ed978cc615e1bb78fb42b8 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 25365433be0f190e10a96d9946b8ea90c883b78a Original-Change-Id: I4a4cd27f9f4a94b9134dcba623f33b114299818f Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/241129 Original-Reviewed-by: Shawn N <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/9493 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10samus: Add clear_recovery_mode_switch functionDuncan Laurie
In order for recovery request to be cleared with software sync disabled we need to implement this function in the mainboard. BUG=chrome-os-partner:28234 BRANCH=samus TEST=boot in recovery with software sync disabled, ensure that the next boot will not boot in recovery again. Change-Id: Ie9c845396dfc6ab65296b2f18a86e23590c833d6 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 430f85608cc3b59a68a86dba64ffe428bfc216a9 Original-Change-Id: Iac15b6a1b23cc971231339439bceb013f4a031bd Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/241052 Original-Reviewed-by: Shawn N <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/9492 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10samus: Set current backlight PWM valueDuncan Laurie
With recent changes in the 3.14 kernel and the switch to not using X the panel backlight is not geting turned on until chrome is started which means the splash screen is not visible. If we set the backlight PWM in coreboot then it will at least turn on for the early boot process. BUG=chrome-os-partner:31549 BRANCH=samus TEST=boot on samus in normal mode and see the boot splash logo Change-Id: I81e6b90617acb181b4de3365f8f56ec3b846b78b Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: f850fe3faff268a64f18e6bd176ec1126b921e3b Original-Change-Id: I622bef8af9bb6b753fe228b33ecdc4aae76af131 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/240853 Original-Reviewed-by: Shawn N <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/9491 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10broadwell: Turn off panel backlight in S5 SMI handlerDuncan Laurie
In order for some panels to meet spec when the system is put into S5 by way of power button during firmware (i.e. not by the OS) then it needs to turn off the backlight and give it time to turn off before going into S5. If the OS properly sequences the panel down then the backlight enable bit will not be set in this step and nothing will happen. BUG=chrome-os-partner:33994 BRANCH=broadwell TEST=build and boot on samus Change-Id: Ic86f388218f889b1fe690cc1bfc5c3e233e95115 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: e3c9c131a87bae380e1fd3f96c9ad780441add56 Original-Change-Id: I43c5aee8e32768fc9e82790c9f7ceda0ed17ed13 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/240852 Original-Reviewed-by: Shawn N <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/9490 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10broadwell: Skip steps when disabling PCIe portDuncan Laurie
When disabling PCIe ports skip steps if no card is detected. This prevents the loop from timing out on each empty slot. BUG=chrome-os-partner:31424 BRANCH=broadwell TEST=build and boot on samus, check that this code is no longer timing out when disabling PCIe ports Change-Id: I84ee0e0e325784b3af06abe70420c07cf6e13ed2 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 4d759e2350dd00ceb7df196ac7008729dc1e4cef Original-Change-Id: Idd88f0f1191a5465a0d8dcca07b5c3a5c5ca8855 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/240851 Original-Reviewed-by: Wenkai Du <wenkai.du@intel.com> Original-Reviewed-by: Shawn N <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/9489 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10broadwell: Remove XHCI workarounds on WPTDuncan Laurie
The workarounds in ACPI methods for D0/D3 transition that are used on haswell/LPT do not all apply to broadwell/WPT. BUG=chrome-os-partner:28234 BRANCH=broadwell TEST=build and boot on samus, test USB functionality and wake and ensure the device still does into D3 state Change-Id: Ic3a75f5bf50e826ade7d942b48cfebb75cf976e6 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 1b54d105957ee80ca34048c42fb8f241731281cf Original-Change-Id: I877afd51fc6c9b7906e923b893fc31bdf2cd1090 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/240850 Original-Reviewed-by: Shawn N <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/9488 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10broadwell: Only do pre-graphics delay when running option romDuncan Laurie
This changes the broadwell graphics init path to only do the delay before initializing graphics when running chromeos if we are also going to execute the option rom. BUG=chrome-os-partner:33671 BRANCH=samus TEST=build and boot on samus Change-Id: Idb7d39b22f7f6dc3be6dfbd2fa3cc2e33d78a397 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: f7ed93504a74760f16acb8fb3c6c57ac514b7260 Original-Change-Id: I350f85738efe3d17152de4f025adbfd52ae15b95 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/228882 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9474 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10PCI - Add interrupt disable bit definitionLee Leahy
BRANCH=none BUG=None TEST=Build Braswell/Strago Change-Id: I11a4c02af3b40edf2252b9e20298941b99f31d21 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 1629d7454a3d4adb8930d14849c41c9a711f4c9a Original-Change-Id: Ie907637f7c823de681ef2e315e803dffc6ad33d3 Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/241081 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/9487 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10samus: Add ACPI binding for rt5677 codec SPIBen Zhang
We'll need to find a real ACPI device ID for the rt5677 SPI driver. "RT5677AA" is temporary. BUG=chrome-os-partner:33495 BRANCH=samus TEST=load firmware via SPI; hotword detection works Change-Id: I6dc55c4641c27a38570debe841a6afeb048eb868 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: f0d7013b62c78deb82db1a431f079c79eded5270 Original-Change-Id: Ifb4a1b12776669e21c0b7c4679246717d72981ad Original-Signed-off-by: Ben Zhang <benzh@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/235902 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/9486 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10broadwell: Fix PCIe ports programming sequences to enable HSIOPCWenkai Du
HSIOPC/GPIO71 is used to control power to VCCHSIO, VCCUSB3PLL and VCCSATA3PLL in S0. PCH will drive HSIOPC low when all the high speed I/O controllers (xHCI, SATA, GbE and PCIe) are idle. This patch added a few additional PCIe programming steps as required in 535127 BIOS Writer Guide Rev 2.3.0 to enable this power saving mode. BUG=none BRANCH=none TEST=tested on Paine watching GPIO71 toggling as expected Change-Id: Ica6954c125ec3129e2659168f1f23dc861ce5708 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: e38f9ef57c480ca5ee420020eb80a1adb3c381d3 Original-Change-Id: I88ef125c681c8631e8b887f7ccf017b90b8c0f10 Original-Signed-off-by: Wenkai Du <wenkai.du@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/238580 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/9482 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10samus: Add RT5677 ACPI/DT bindings with _DSDDuncan Laurie
To support the ACPI device specific properties that conform to the existing devicetree bindings for this codec (in upstream kernels) add a _DSD object to the existing codec device. BUG=chrome-os-partner:29649 BRANCH=samus TEST=build and boot on samus Change-Id: Ice808ba7bf2f0378ac5a38afd27dbf6c8cac0da5 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: b3fc2d7e5a5878b1fff7627f803b883b38fea28d Original-Change-Id: I344636171a3086a72087314503bfc99de5945b1f Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/238857 Original-Reviewed-by: Ben Zhang <benzh@chromium.org> Reviewed-on: http://review.coreboot.org/9483 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10broadwell: Update SATA Gen3 TX adjustment registersDuncan Laurie
The registers that were used here are for CPT/PPT and not for HSW/BDW chips. Update this to update just the Gen3 TX Output Voltage Downscale Amplitude Adjustment field in the SATA ECR T88. BUG=chrome-os-partner:28234 BRANCH=samus,auron TEST=build and boot on samus Change-Id: I94b702dc4a3c98678ba048ff9cfa4a85cc5b1eed Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 4c5816cc647b84266751e8a591eb85d7735fee12 Original-Change-Id: I98ec9678938a6675828721d5b57683077f555d21 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/238800 Original-Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/9484 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10broadwell: Add a few bits to finalize stepDuncan Laurie
Added a few bits to set in finalize step from scrubbing BWG and reference code. BUG=chrome-os-partner:28234 BRANCH=broadwell TEST=build and boot on samus Change-Id: I7b0c4dd3f14c06175c973561760ad1bdafd46fbb Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 3802aef908849fe6ea2bb0034d884064154ae9da Original-Change-Id: Ia62055b32be039eef84a0f60f0ba307eb5dce6a1 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/239958 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9485 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10baytrail: fix the coding error on PCIe L1 exit latencyKevin L Lee
The original code uses L1EXIT_MASK to shift the bit for PCIe L1 exit latency, the code should use L1EXIT_SHIFT for bit shifting. BUG=chrome-os-partner:34037 BRANCH=None TEST=build and boot on candy, verify B0:D28:F0 + 4Ch [17:15] set to 010b. Correspond WIFI device performance got improvement. Signed-off-by: Kevin L Lee <kevin.l.lee@intel.com> Change-Id: I3ac5b6319b726aa16cdb9678face89022d979517 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 381827e3d92c9e786cd8ebe412586968662fb4be Original-Change-Id: I8171f80720830cfa76f26778ae31c7590a723b92 Original-Reviewed-on: https://chromium-review.googlesource.com/234673 Original-Reviewed-by: Kenji Chen <kenji.chen@intel.com> Original-Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Original-Tested-by: Kenji Chen <kenji.chen@intel.com> Original-Commit-Queue: Kenji Chen <kenji.chen@intel.com> Reviewed-on: http://review.coreboot.org/9480 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10TPM: Reduce buffer size to fix stack overflowJulius Werner
The TPM driver by default allocates a 4K transfer buffer on the stack, which leads to lots of fun on boards with 2K or 3K stack sizes. On RK3288 this ends up writing over random memory sections which dependent on the memlayout of the day might contain timestamp data (no big deal) or page tables (-> bad time). This patch fixes the problem by reducing the buffer size to slightly above 1K, which still seems to work as far as I can tell. There was already some really odd code that #undef'ed this value and redefined it with the lower number in one .c file (unfortunately not the one with the buffer declaration), with no explanation whatsoever... I'm removing that and just assume the smaller value will be fine for everything. BRANCH=veyron BUG=None TEST=Booted Pinky and Falco. Change-Id: I440a5662b41cbd8b7becab3113262e1140b7f763 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 3d3288041b6629b7623b9d58816e782e72836b81 Original-Change-Id: Idf80f44cbfb9617c56b64a5c88ebedf7fcb4ec71 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/236976 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9481 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10Baytrail: Prior to PCI scan, wait for LCTL to be active in 50 msKevin Hsieh
Using REG_PCI_POLL32 to check if the LINK is active with 50ms timeout. BRANCH=none BUG=chromium:431169 TEST=Test on Enguarde, compile ok and boot OS Change-Id: If98ab4e31d17ec4e62d68b93edcec6d9aee87367 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: cf692ae9aebb43ab46cb07d36b62b300b16be1dc Original-Change-Id: I490e6ffa40979628edf52a7444808b6d25a6e83d Original-Signed-off-by: Kevin Hsieh <kevin.hsieh@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/231777 Original-Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/9478 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10tpm: Remove error message for unknown resource typeDuncan Laurie
This is being triggered because the base address is added, but there is nothing that needs done with it in set_resources step and the ERROR message is tripping suspend resume test scripts. BUG=chrome-os-partner:33385 BRANCH=samus,auron TEST=boot on samus and check for ERROR strings, successfully run suspend_stress_test without failures Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/231603 (cherry picked from commit bb789492965d92e309a913dc7b9f09f7036c5480) Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: I565c8af954f1c5a406d2c65f01c274e9259e43ec Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 9062734d884f814dc880589ee615b4d7e1fdc61a Original-Change-Id: I2b5f44795f1ee445d509b29bd56f498aea7b7fe3 Original-Reviewed-on: https://chromium-review.googlesource.com/231604 Original-Commit-Queue: Duncan Laurie <dlaurie@chromium.org> Original-Tested-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9476 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10Broadwell: Set boot_mode of pei_data before running reference codeKenji Chen
Some actions are needed and some are not on the way resume from S3. BRANCH=master BUG=chrome-os-partner:33025,chrome-os-partner:33796 TEST=Built the image and confimed the boot_mode is correctly configured. Signed-off-by: Kenji Chen <kenji.chen@intel.com> Change-Id: If400df94f970a55f3921a5a2df24038d28beb489 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 40e719618ec101235cdb1755933e719abd873239 Original-Change-Id: Ia042ea8c63c2306e9d6a80d8efa66c4fc0722d85 Original-Reviewed-on: https://chromium-review.googlesource.com/229615 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Commit-Queue: Kenji Chen <kenji.chen@intel.com> Original-Tested-by: Kenji Chen <kenji.chen@intel.com> Reviewed-on: http://review.coreboot.org/9475 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10samus: Move board version to a separate fileDuncan Laurie
This combines the board version reading and parsing to a separate file that is compiled in both romstage (for early serial output) and ramstage (for smbios tables). It also adds a new board version that is wrapped back to number zero as we are running out of available IDs. BUG=chrome-os-partner:32895 BRANCH=samus TEST=build and boot on samus EVT1 and EVT2 and check for proper board versions reported in console and smbios. Change-Id: I8c8f17708ced7167277a98529ff4597589f53095 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 3ab8bba1021a8dd41dd2210ba73efd2231eb596c Original-Change-Id: I2aa03e7486a9581f94dc4e12f6f29eb0c5b3bdbb Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/229041 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9473 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10tpm: Add ramstage driver and interrupt configurationDuncan Laurie
This adds a ramstage driver for the TPM and allows the interrupt to be configured in devicetree.cb. The interrupt vector is set like other PNP devices, and the interrupt polarity is set with a register configuration variable. These values are written into locality 0 TPM_INT_VECTOR and TPM_INT_ENABLE and then all interrupts are disabled so they are not used in firmware but can be enabled by the OS. It also adds an ACPI device for the TPM which will configure the reported interrupt based on what has been written into the TPM during ramstage. The _STA method returns enabled if CONFIG_LPC_TPM is enabled, and the _CRS method will only report an interrupt if one has been set in the TPM itself. The TPM memory address is added by the driver and declared in the ACPI code. In order to access it in ACPI a Kconfig entry is added for the default TPM TIS 1.2 base address. Note that IO address 0x2e is required to be declared in ACPI for the kernel driver to probe correctly. BUG=chrome-os-partner:33385 BRANCH=samus,auron TEST=manual testing on samus: 1) Add TPM device in devicetree.cb with configured interrupt and ensure that it is functional in the OS. 2) Test with active high and active low, edge triggered and level triggered setups. 3) Ensure that with no device added to devicetree.cb that the TPM is still functional in polling mode. Change-Id: Iee2a1832394dfe32f3ea3700753b8ecc443c7fbf Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: fc2c106caae939467fb07f3a0207adee71dda48e Original-Change-Id: Id8a5a251f193c71ab2209f85fb470120a3b6a80d Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/226661 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9469 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10tpm: Move the LPC TPM driver to a subdirectoryDuncan Laurie
This moves the LPC TPM driver to drivers/pc80/tpm so it can be turned into a ramstage driver with a chip.h It includes no other changes yet. BUG=chrome-os-partner:33385 BRANCH=samus,auron TEST=emerge-samus coreboot Change-Id: Iac83e52db96201f37a0086eae9df244f8b8d48d9 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: be2db391f9da80b8b75137af0fe81dc4724bc9d1 Original-Change-Id: I60ddd1d2a3e72bcf169a0b44e0c7ebcb87f4617d Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/226660 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9468 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10broadwell: Increase I2C SDA hold timing to 300nsChiranjeevi Rapolu
I2C bus SDA hold time can be marginal with 60ns value, especially when there is level shifter on the bus. So program it to 300ns based on Fast-mode specification, which is between 0 to 900ns. Apply the same timing for Standard-mode as well. Refer to original bug on BayTrail chrome-os-partner:28092, this is to carry forward the fix to Broadwell. BRANCH=chromeos-2013.04 BUG=chrome-os-partner:33378 TEST=suspend resume test, watch for I2C errors Change-Id: I93200b141602163903f5c9f52b94013bcf3382a5 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 72b82a1d5d836594e7d0f95972cc0dc91ae7ff8c Original-Change-Id: I995d6868a44f2578a6d0b18dd5e8548f3c3cd494 Original-Signed-off-by: Chiranjeevi Rapolu <chiranjeevi.rapolu@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/226386 Original-Reviewed-by: Wenkai Du <wenkai.du@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/9467 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10broadwell: add RCBA posting read after writingWenkai Du
MEI PCI device has internal logic to flush out the posted writes before returning completion for non-posted request. When doing a RCBA write to function disable and then using the PCI CFG RD cycle, need to do RCBA posting read after writing to it to make sure the write went through. As Aaron sugegsted, abstracted function disable path to a common function. BUG=chrome-os-partner:33048 TEST=run warm and cold reboot testing Change-Id: I40d374f1712a9137b3b1eac6bbf2d71078840406 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: f10b368e01aae1fc5dda63f7ac0641dd2636c949 Original-Change-Id: I87aa8ccd604446263fc3621c9a01839a5a75b644 Original-Signed-off-by: Wenkai Du <wenkai.du@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/223715 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/9462 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10Broadwell: Synchronization with FRC for Root Port Power ManagementKenji Chen
BUG=chrome-os-partner:31424 TEST=Build a image and run on Samus proto boards to confirm if the settings are applied correctly. Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Change-Id: I9147da86ce26ce7ef1c7034bc3dde0b27b63befa Original-Commit-Id: 1717505a3fdf41c5972b1c929872577247f9e3b5 Original-Signed-off-by: Kenji Chen <kenji.chen@intel.com> Original-Change-Id: I8138507506771148420a585fd12897a3bfe91916 Original-Reviewed-on: https://chromium-review.googlesource.com/221387 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/9463 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10broadwell: Skip DDI-A enable in S3 resumeDuncan Laurie
DDI-A should not need re-enabled in the resume path, just the resume path when we did not execute VBIOS. BUG=chrome-os-partner:28234 BRANCH=samus,auron TEST=build and boot on samus, test suspend+resume Change-Id: I29d67591ac903bc1d712a956462bcf4a764ef2eb Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: c3fbeac10f3834a6d848154aa3449672871b13df Original-Change-Id: Iaf7d083c5c92c42b7a117e2d2c9546ada6bf5f76 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/221988 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9461 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10broadwell: Add support for ACPI \_GPE._SWSDuncan Laurie
In order to report the GPE that woke the system to the kernel coreboot needs to keep track of the first GPE wake source and save it in NVS so it can be returned in \_GPE._SWS method. This is similar to the saving of PM1 status but needs to go through all the GPE0_STS registers and check for enabled and triggered events. A bit of cleanup is done for areas that were touched: - platform.asl was not formatted correctly BUG=chrome-os-partner:8127 BRANCH=samus,auron TEST=manual: - suspend/resume and wake from EC event like keyboard: ACPI _SWS is PM1 Index -1 GPE Index 112 ("special" GPIO27) - suspend/resume and wake from RTC event: ACPI _SWS is PM1 Index 10 GPE Index -1 (RTC) - suspend/resume and wake from power button: ACPI _SWS is PM1 Index 8 GPE Index -1 - suspend/resume and wake from touchpad: ACPI _SWS is PM1 Index -1 GPE Index 13 - suspend/resume and wake from WLAN: ACPI _SWS is PM1 Index -1 GPE Index 10 Change-Id: I574f8cd83c8bb42f420e1a00e71a23aa23195f53 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: d4e06c7dfc73f2952ce8f81263e316980aa9760f Original-Change-Id: I9bfbbe4385f2acc2a50f41ae321b4bae262b7078 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/220324 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9460 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10baytrail: Switch from ACPI mode to PCI mode for legacy supportMarc Jones
Most Baytrail based devices MMIO registers are reported in ACPI space and the device's PCI config space is disabled. The PCI config space is required for many "legacy" OSs that don't have the ACPI driver loading mechanism. Depthcharge signals the legacy boot path via the SMI 0xCC and the coreboot SMI handler can switch the device specific registers to re-enable PCI config space. BUG=chrome-os-partner:30836 BRANCH=None TEST=Build and boot Rambi SeaBIOS. Change-Id: I87248936e2a7e026f38c147bdf0df378e605e370 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: dbb9205ee22ffce44e965be51ae0bc62d4ca5dd4 Original-Change-Id: Ia5e54f4330eda10a01ce3de5aa4d86779d6e1bf9 Original-Signed-off-by: Marc Jones <marc.jones@se-eng.com> Original-Reviewed-on: https://chromium-review.googlesource.com/219801 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Mike Loptien <mike.loptien@se-eng.com> Original-Tested-by: Mike Loptien <mike.loptien@se-eng.com> Reviewed-on: http://review.coreboot.org/9459 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10southbridge/intel/fsp_rangeley/ : Spellcheck + Formattingnicky sielicki
Changes: acpi.c - Capitalize an acronym. early_spi.c - Spelling error. gpio.c - Capitalization of acronym + sentences. gpio.h - Capitalization of sentences. lpc.c - Capitalization of sentences. soc.c - Spelling error + capitalization of acronym. I just wanted to go through the process of commiting something onto Gerrit. Change-Id: Iad2ac5409f883c5b7cbc25e4e296f386ad7e13d0 Signed-off-by: nicky sielicki <nlsielicki@wisc.edu> Reviewed-on: http://review.coreboot.org/9510 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <gaumless@gmail.com>
2015-04-10vboot: Remove unused 2lib header pathRandall Spangler
Before the change to use vb2_api.h, coreboot needed to know where to find the vboot2 header files. Now those are all included by vb2_api.h, so coreboot doesn't need to know about firmware/2lib/include (and in fact, the 2lib directory is about to go away). BUG=chromium:423882 BRANCH=none TEST=emerge-veyron_pinky coreboot Original-Change-Id: I7f69ca9cf8d45c325219efceca0cb8d1340f7736 Original-Signed-off-by: Randall Spangler <rspangler@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/233223 Original-Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> (cherry picked from commit b4d4a2da1c8b5a5f8f8da51f009227d3a616b096) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I4006f38835ea0f927142a8133bc24caaf2b7a214 Reviewed-on: http://review.coreboot.org/9447 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10vboot: Include vb2_api.h, instead of lower-level vboot2 header filesRandall Spangler
This will allow vboot2 to continue refactoring without breaking coreboot, since there's now only a single file which needs to stay in sync. BUG=chromium:423882 BRANCH=none TEST=emerge-veyron_pinky coreboot CQ-DEPEND=CL:233050 Original-Change-Id: I74cae5f0badfb2d795eb5420354b9e6d0b4710f7 Original-Signed-off-by: Randall Spangler <rspangler@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/233051 Original-Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> (cherry picked from commit df55e0365de8da85844f7e7b057ca5d2a9694a8b) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I999af95ccf8c326f2fd2de0f7da50515e02ad904 Reviewed-on: http://review.coreboot.org/9446 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2015-04-10vboot2: Reduce minimum required work buffer sizeJulius Werner
Apparently our initial submission of 16K was a little too generous for the vboot2 work buffer, and I hear that we should also be well within bounds for 12K. This patch reduces the minimum asserted by memlayout so some of our low-mem boards can get a few more kilobytes back for discretionary spending. Also changes the required minimum alignment to 8 since that's what the current vboot code aligns it to anyway, and add a warning comment to make it clearer that this is a dangerous number people should not be playing with lightly. BRANCH=None BUG=None TEST=Built and booted on Pinky. Original-Change-Id: Iae9c74050500a315c90f5d5517427d755ac1dfea Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/232613 Original-Reviewed-by: Randall Spangler <rspangler@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 64e972f10363451cd544fdf8642bd484463703bc) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I362b8c33cf79534bb76bd7acda44d467563fe133 Reviewed-on: http://review.coreboot.org/9445 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2015-04-10vboot: add physical recovery switch supportDaisuke Nojiri
PHYSICAL_REC_SWITCH is set n by default and y for panther and stumpy. BUG=none BRANCH=ToT TEST=Built nyan_blaze using vboot1/2. Built falco, lumpy, nyan, blaze, parrot, rambi, samus, storm, pinky with default configuration. panther and stumpy are not tested because they currently don't build on ToT. Original-Change-Id: Ic45f78708aaa7e485d2ab459fd1948524edb412f Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/227940 Original-Reviewed-on: https://chromium-review.googlesource.com/229602 Original-Reviewed-by: Randall Spangler <rspangler@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit edb2ba347b48887ffe450586af0351e384faad59) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I277f665cd4f3e1c21745cdc5c7a2cfe148661abe Reviewed-on: http://review.coreboot.org/9444 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2015-04-10vboot2: update fw_version_tpm when creating vboot1 shared dataDaisuke Nojiri
This changes copies firmware version from vboot2 shared data to vboot1 shared data. This fixes FAFT firmware_TPMVersionCheck test. BUG=none BRANCH=ToT TEST=firmware_TPMVersionCheck passed on Nyan Kitty. Original-Change-Id: Idfd282931421dc16cd1aa82c7ccb6c6790a4d0d7 Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/230186 Original-Reviewed-by: Randall Spangler <rspangler@chromium.org> Original-Tested-by: Yen Lin <yelin@nvidia.com> (cherry picked from commit 1f590741893bee75d872184eba01c62e92455816) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I205b651976d047923815efcd45b114cc7bf866e4 Reviewed-on: http://review.coreboot.org/9443 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2015-04-10ramoops: Add support for passing ramoops region through cb tables.Furquan Shaikh
CQ-DEPEND=CL:228856 BUG=chrome-os-partner:33676 BRANCH=None TEST=ramoops buffer verified on ryu. Original-Change-Id: I29584f89ded0c22c4f255a40951a179b54761053 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/228744 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit e8b2c8b75c51160df177edc14c90e5bd3836e931) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I5fdeb59056945a602584584edce9c782151ca8ea Reviewed-on: http://review.coreboot.org/9442 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10chromeos: Add correct dependency on HAVE_ACPI_TABLES for gvns and ramoops.Furquan Shaikh
CQ-DEPEND=CL:228856 BUG=chrome-os-partner:33676 BRANCH=None TEST=Compiles successfully for samus, link, rush_ryu. Original-Change-Id: I8499cab5dd08981a558688964b99b65d78bde476 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/228743 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit e6aa03752ba8c22b303f3fa590cbc9cf938872ef) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: Ib229756d8dece6f5670460702413f74bc2c692df Reviewed-on: http://review.coreboot.org/9441 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2015-04-10vboot: reduce references to parent's files in MakefilesDaisuke Nojiri
this change also allows vboot1 code to use flash as nvram device. BUG=none BRANCH=ToT TEST=Built nyan_blazw using vboot1/2. Built falco, lumpy, nyan, blaze, parrot, rambi, samus, storm, pinky with default configuration. Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Change-Id: Ie97a4436d4fc10851a535adfdb45c4d499e45b5d Original-Reviewed-on: https://chromium-review.googlesource.com/229598 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 8ac8ff28bab1337782e8694275bb2c644b86f38a) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: Ief087fedbf29b4b82c1668ad5603c121323dcbf2 Reviewed-on: http://review.coreboot.org/9440 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2015-04-10vboot: fix invalid check for the returned value from spi_flash->writeDaisuke Nojiri
spi_flash->write returns non-zero on error and zero on success, not the number of bytes written. BUG=none BRANCH=ToT TEST=Booted storm. Verified successfully nvdata was saved. Original-Change-Id: If50cc1a62a4f06398d1830cca60085b6f925fff3 Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/229389 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Randall Spangler <rspangler@chromium.org> (cherry picked from commit 1e8cdbdb07e99c3f72c35f76d68144f46107acd9) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I216e97f734da8d4b52c2da8329f4143b7b0656cd Reviewed-on: http://review.coreboot.org/9439 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2015-04-10cbtables: Add RAM config informationDavid Hendricks
This adds the RAM config code to the coreboot tables. The purpose is to expose this information to software running at higher levels, e.g. to print the RAM config coreboot is using as part of factory tests. The prototype for ram_code() is in boardid.h since they are closely related and will likely have common code. BUG=chrome-os-partner:31728 BRANCH=none TEST=tested w/ follow-up CLs on pinky Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: Idd38ec5b6af16e87dfff2e3750c18fdaea604400 Original-Reviewed-on: https://chromium-review.googlesource.com/227248 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> (cherry picked from commit 77dd5fb9347b53bb8a64ad22341257fb3be0c106) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: Ibe7044cafe0a61214ac2d7fea5f7255b2c11829b Reviewed-on: http://review.coreboot.org/9438 Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2015-04-10vboot: adding VBSD_BOOT_FIRMWARE_WP_ENABLED logicGediminas Ramanauskas
BUG=chrome-os-partner:33395 BRANCH=none TEST=emerge and test using crossystem Original-Change-Id: I0d49f85219d45c837a7100e0195bef86da2c6cdd Original-Signed-off-by: Gediminas Ramanauskas <gedis@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/227546 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 5a2868e04140973691136adfd7d9e6d1aa1f6dae) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I93c1ea9ce1270c2c143fd44ead2291dfbc114c00 Reviewed-on: http://review.coreboot.org/9437 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2015-04-10fmap: use CBFS for all other than x86 platformsVadim Bendebury
The architectiure check in fmap.c is in fact used to delineate between platforms where SPI flash is mapped to memory address space and where it needs to be accessed through CBFS. In fact cosmos board uses an ARM SOC which also maps SPI flash to processor address space, this will have to be addressed when that SOC's support is introduced, for now let's just presume that all but X86 platforms require CBFS layer to access fmap. BRANCH=none BUG=chrome-os-partner:31438 TEST=none Original-Change-Id: Id135dc63278555a7fc5039a568fb28864f7cb8d1 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/226180 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit b3c04f84504380066c54a6dec93781a4f25a5fc6) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I3a0a70fe583b69b1c9cd8729817bd7062126e1a9 Reviewed-on: http://review.coreboot.org/9436 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2015-04-10chromeos: Add a function to copy VPD WiFi calibration data to CBMEMVadim Bendebury
This patch adds functions looking in the VPD for WiFi calibration data, and if found, copying the calibration blobs into CBMEM. Two possible key names templates are used: wifi_base64_calibrationX and wifi_calibrationX, where X is replaced by the WiFi interface number. Up to four interfaces can be provisioned. The calibration data will be retrieved from CBMEM by the bootloader and placed into the device tree before starting the kernel. The structure of the WiFi calibration data CBMEM entry is defined locally: it is a concatenation of the blob names and their contents. Each blob is padded as necessary to make sure that the size divisible by four. To make sure that the exactly required amount of memory is allocated for the CBMEM entry, the function first scans the VPD, caching the information about the available blobs and calculating their combined size. Then the required size CBMEM entry is allocates and the blobs are copied into it. BRANCH=storm BUG=chrome-os-partner:32611 TEST=when this function is called, and the VPD includes calibration data blobs, the WIFI entry shows up in the list of CBMEM entries reported by coreboot. Original-Change-Id: Ibe02dc36ff6254e3b9ad0a5bd2696ca29e1b2be3 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/225271 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 9fe185ae5fdc1a896bf892b498bff27a3462caeb) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: Ia60f0c5c84decf9854426c4f0cb88f8ccee69046 Reviewed-on: http://review.coreboot.org/9435 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10vboot: move vboot files to designated directoryDaisuke Nojiri
This moves vboot1 and vboot2 files to their designated directory. Common code stays in vendorcode/google/chromeos. BUG=none BRANCH=none TEST=built cosmos, veyron_pinky, rush_ryu, nyan_blaze, samus, parrot, lumpy, daisy_spring, and storm. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Change-Id: Ia9fb41ba30930b79b222269acfade7ef44b23626 Original-Reviewed-on: https://chromium-review.googlesource.com/222874 Original-Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> Original-Tested-by: Daisuke Nojiri <dnojiri@chromium.org> (cherry picked from commit cbfef9ad40776d890e2149b9db788fe0b387d210) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: Ia73696accfd93cc14ca83516fa77f87331faef51 Reviewed-on: http://review.coreboot.org/9433 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10build system: Fix SeaBIOS integration with multilib compilersPatrick Georgi
SeaBIOS doesn't like CC and LD to contain arguments, so split those out. Change-Id: Id651719d529adfa8602a3e4f6685228330f36432 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9378 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Kevin O'Connor <kevin@koconnor.net>
2015-04-10mainboard/biostar: Add support for Biostar AM1ML ver7.xSergej Ivanov
Adds AM1ML board. This board has AM1 Socket and supports all new AM1 APUs from AMD. Based on asrock/imb-a180 board. Successfully tested with SeaBIOS and Linux 3.8.x and Windows XP. Successfully tested audio, video, network, PS/2 keyboard and mouse, PCIe x16, COM port, SATA and USB. LPT port is not tested yet and it’s unknown if it’s work. Change-Id: I9ebb9acc590d38e47579adc263f45ae3f607684e Signed-off-by: Sergej Ivanov <getinaks@gmail.com> Reviewed-on: http://review.coreboot.org/9293 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
2015-04-10vendorcode/amd/agesa/f16kb: Enable support for AM1 socketSergej Ivanov
Adds option FORCE_AM1_SOCKET_SUPPORT to disable package type mismatch check between cpu and northbridge. Default agesa for kabini doesn't know about AM1 socket so it returns FALSE, that stops memory config code. With this hack current agesa version supports the AM1 socket. Change-Id: I99e9cec5cd558087092cf195094df20489f6d3b5 Signed-off-by: Sergej Ivanov <getinaks@gmail.com> Reviewed-on: http://review.coreboot.org/9291 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
2015-04-10southbridge/amd/agesa/hudson: Fix LPC_DEV definitionSergej Ivanov
In agesa code for hudson southbridge LPC_DEV is not defined, but used. Define LPC_DEV as done in southbridge/amd/cimx/sb800. This fixes it. Change-Id: Ie7db791e9eb607008e70e446fc6fd28114742750 Signed-off-by: Sergej Ivanov <getinaks@gmail.com> Reviewed-on: http://review.coreboot.org/9292 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
2015-04-10google/cosmos: don't enable CHROMEOS by defaultPatrick Georgi
This isn't done in upstream. Change-Id: Ief1fea0f231d609372f065f6f6aee7bceaf31efc Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9458 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10util/bimgtool: Add verification modeVadim Bendebury
When only one argument is passed on the command line, consider this argument the name of the BIMG formatted file, and verify its integrity. Update the help/usage text to match new behavior. BRANCH=none BUG=none TEST=when the corrupted coreboot BIMG image is passed as the only argument, this utility reports the problem. With the build fixed, the check passes without errors (the second invocation below). $ build/util/bimgtool/bimgtool /build/urara/firmware/coreboot.rom.serial Data header CRC mismatch at 0 $ build/util/bimgtool/bimgtool /build/urara/firmware/coreboot.rom.serial $ Change-Id: I9f0672caa38e3d27917471fc5137ede4ca466e9a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3e631c311dbf2fb04714e437f95c41629155527f Original-Change-Id: Ie56f87f99838891d8e341d7989c614efbcabe0cd Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/227522 Original-Reviewed-by: Zdenko Pulitika <zdenko.pulitika@imgtec.com> Original-Tested-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Reviewed-on: http://review.coreboot.org/9452 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10ipq806x: Remove extra INCLUDESPatrick Georgi
That variable isn't used anymore and the include statement is already covered in CPPFLAGS_common further down that file. Change-Id: I3e4fd3281dc0d3f73b238e121dbdfc0d29102b27 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9448 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10google/rush: Add I2C1 init and audio clock enable/resetsTom Warren
This should allow the max98090 codec to play beeps via AHUB/I2S1 thru the depthcharge sound driver. BUG=none BRANCH=none TEST=Saw max98090 codec init signon and register dump. No sound yet. Change-Id: I1ee0b61f5cbfe587ebd16b7dd9dce08d9d62c2c5 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f4ee2ce3704711a9e00531b7599a1bcf194203ec Original-Change-Id: I0bc8401e76b2c80a01083ac933a39f6cd4d1b78a Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/229496 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Mike Frysinger <vapier@chromium.org> Reviewed-on: http://review.coreboot.org/9429 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10tegra132: Add routine to enable all audio periphs under AHUBTom Warren
If all devices under AHUB (AUDIO/I2S/DAM/ADX/etc) aren't clocked and taken out of reset, any access to any audio peripheral will hang the system. BUG=none BRANCH=none TEST=built both Rush and Ryu OK. Change-Id: Iee8e33f005c5abaf09a14104c0b243b06eb4af24 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0016bd533864942225f2fb8e08ce871a186f2746 Original-Change-Id: I741d5ba4dd8bd963b6d261fbf41cfb77c274cb79 Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/229910 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Mike Frysinger <vapier@chromium.org> Reviewed-on: http://review.coreboot.org/9428 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10tegra132: Add I2C1 support to funitTom Warren
I2C1 was missing in the funit/i2c/addressmap tables/code. BUG=none BRANCH=none TEST=Built Rush and Ryu. Built Rush w/code in mainboard.c to enable I2C1 for the MAX98090 audio codec - codec could be configured. Change-Id: I0c678d21546eedb7404a1d3d4329da777430fc97 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4b623097a2adc4464c17bceed96ec3838beda985 Original-Change-Id: Ibe4f012fa2d427b95cd4672687132b47576b6a9a Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/229574 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9427 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10google/rush_ryu: Add support for event logFurquan Shaikh
BUG=chrome-os-partner:33764 BRANCH=None TEST=Event logs verified on ryu across multiple boots. Change-Id: Iff4a60b3904ef0fcdd2513df579db8f5877808de Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: fbe6290de7eaed0d66a26cc2389181a8d38a59d6 Original-Change-Id: I50d052bb15ec6616b0bf82bf1f1acf9080f4c54b Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/229415 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9426 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10rtc: Add an RTC driver for the TI TPS65913 PMIC.Furquan Shaikh
The TPS65913 PMIC has an RTC built into it. This change adds a driver for it which implements the new RTC API. BUG=chrome-os-partner:33764 BRANCH=None TEST=Compiles and boots to kernel prompt on ryu. Timestamps for event log verified across multiple boots. Change-Id: I49ec9b78afc53f1cbd4be09e448cdae6077fb710 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c16c11e620c830e7a73a2a24fe4823ccea0f3c39 Original-Change-Id: If1d549ea2361d0de6be75fd24b9e9810a6df7457 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/229414 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9425 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10elog: Hide elog_flash_offset_to_address() from SMMFurquan Shaikh
Change-Id: Iaef9d4755f07ca03ca823831c3272183b5d6aed1 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 7c3db3d5c8e00b6c273ae240da137062597749aa Original-Change-Id: I5e38966fe06aa3302a7c1b536f5ffd8bb22d4947 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/229413 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9450 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10elog: Fix typecast issues related to 64-bit compilation.Furquan Shaikh
BUG=chrome-os-partner:33764 BRANCH=None TEST=Compiles successfully for ryu and nyan. Change-Id: I036fd42d5cd4b71bcb68eea0fdd9a4e1aa4711e9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 7c3db3d5c8e00b6c273ae240da137062597749aa Original-Change-Id: I5e38966fe06aa3302a7c1b536f5ffd8bb22d4947 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/229413 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9424 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-04-10arm64: Implement PSCI command supportAaron Durbin
Provide support for SoCs to participate in PSCI commands. There are 2 steps to a command: 1. prepare() - look at request and adjust state accordingly 2. commit() - take action on the command The prepare() function is called with psci locks held while the commit() function is called with the locks dropped. No SoC implements the appropriate logic yet. BUG=chrome-os-partner:32136 BRANCH=None TEST=Booted PSCI kernel -- no SMP because cmd_prepare() knowingly fails. Spintable kernel still brings up both CPUs. Change-Id: I2ae4d1c3f3eac4d1060c1b41472909933815d078 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 698d38b53bbc2bc043548792cea7219542b5fe6b Original-Change-Id: I0821dc2ee8dc6bd1e8bc1c10f8b98b10e24fc97e Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/226485 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9423 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-04-10arm64: secmon: add entry point for turned on CPUsAaron Durbin
Newly turned on CPUs need a place to go bring its EL3 state inline with expectations. Plumb this path in for CPUs turning on as well as waking up from a power down state. Some of the infrastructure declarations were moved around for easier consumption in ramstage and secmon. Lastly, a psci_soc_init() is added to inform the SoC of the CPU's entry point as well do any initialization. BUG=chrome-os-partner:32112 BRANCH=None TEST=Built and booted. On entry point not actually utilized. Change-Id: I2af424c2906df159f78ed5e0a26a6bc0ba2ba24f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: dbefec678a111e8b42acf2ae162c1ccdd7f9fd40 Original-Change-Id: I7b8c8c828ffb73752ca3ac1117cd895a5aa275d8 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/228296 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9422 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-04-10ryu: Add display_start apiJimmy Zhang
Enable display only developer and recovery mode. Will add in the actual display supporting functions in coming patches. BRANCH=none BUG=chrome-os-partner:31936 TEST=build and test on ryu Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Change-Id: I0d312fd132dc310813432f4d8a28ad16c9bb36aa Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: dd1bd56e83532c77d675f72b301b413cbcf3f489 Original-Change-Id: Idfa24d23c81baaedb944d2b9835255edad4e422b Original-Reviewed-on: https://chromium-review.googlesource.com/226904 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Jimmy Zhang <jimmzhang@nvidia.com> Reviewed-on: http://review.coreboot.org/9421 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-04-10ryu: Enhance pmic access functionsJimmy Zhang
1. Add page address, an i2c address, into register address table 2. Add pmic read function 3. Add more registers and setting values. BRANCH=none BUG=chrome-os-partner:31936 TEST=build and test on ryu Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Change-Id: Ieef0737205b20add3ff8990f62dd8585a4e8c557 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 6dcf42c299e25023991be331b724acd0fd9f32c2 Original-Change-Id: I227b3e9390e6fc020707d4730c19945760df6ca2 Original-Reviewed-on: https://chromium-review.googlesource.com/226902 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Jimmy Zhang <jimmzhang@nvidia.com> Original-Tested-by: Jimmy Zhang <jimmzhang@nvidia.com> Reviewed-on: http://review.coreboot.org/9420 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10ryu: audio: Enable RT5677 audio codecTom Warren
Take codec out of reset (GPIO_PH1 aka CODEC_RST_L) and enable LDO2 (GPIO_PR2/KB_ROW2 aka AUDIO_ENABLE). Muxes are setup and the two GPIOs are set to output and driven high. BUG=chrome-os-partner:32582 BRANCH=none TEST=RealTek ALC5677 codec shows up in I2C6 scan at address 0x2D, can read/write registers. Change-Id: I236850452d401fd89b4f59eb03f132c0be32fb20 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4fe3b0c1a3f5d6264b83d7a7e2363dc3f3235cbf Original-Change-Id: Iedce7bb9f8e61d3b8cd693fc5e567323d89f8046 Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/228920 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9419 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10ryu: Select pwr btn polarity based on board idFurquan Shaikh
Proto 0,1,2 boards had pwr btn active high. Proto 3 onwards boards will have pwr btn active low. Thus, select power btn polarity based on board id. BUG=chrome-os-partner:33545 BRANCH=None TEST=Compiles successfully and boots to kernel prompt on ryu proto 1. Change-Id: I9b06b10358b91d40cfdb418ef8cf4da1ae833121 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 7100a42b53a09ed4cb298f88d6f804f46fecacb5 Original-Change-Id: Icdf51b9324385de00f5787e81018518c5397215f Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/229011 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9418 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10util/bimgtool: Use CRC 16 instead of CRC x25.Ionela Voinescu
Switched to CRC 16 as it's 40% faster than CRC x25. Both CRC 16 and CRC x25 are supported and either can be selected through define directives. BUG=chrome-os-partner:31438 TEST=built urara bootblock and verified content of bootblock.bin, observed expected content; ran it on Pistachio FPGA and observed that its content is read properly by bootrom. BRANCH=none Change-Id: I36dec6ec2d6616343f97cc8b6486c0a3e4ea49ba Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 6d9318097ca9270bc245e7de4aff5f78dfbc1606 Original-Change-Id: If1a78350e0b48d91bfe64ead45f852f44ba3cf9a Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/226840 Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Original-Commit-Queue: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/9415 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-04-10gpio: compile gpio.c at all stagesDavid Hendricks
Since gpio.c is more generic now and will be used in various stages (ie for board_id()), compile it for all stages. BUG=none BRANCH=none TEST=compiled for peppy and veyron_pinky Change-Id: Ib5c73f68db92791dd6b42369f681f9159b7e1c22 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ef4e40ccf6510d63c4a54451bdfea8da695e387e Original-Change-Id: I77ec56a77e75e602e8b9406524d36a8f69ce9128 Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/228325 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9414 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: build bot (Jenkins)
2015-04-10marvell/bg4cd: add gpio.h to fix broken buildDaisuke Nojiri
BUG=none BRANCH=tot TEST=built for cosmos Change-Id: I070915941e61630bb57e8e43f7cb9169a6ecfe07 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 2bb9b9f6731a3f30494b3be7e98e0882fd27b517 Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Change-Id: I17679c3c2a3d0cad40500a80e75e047237435b0f Original-Reviewed-on: https://chromium-review.googlesource.com/232518 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9511 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10gpio: decouple tristate gpio support from board IDDavid Hendricks
This deprecates TERTIARY_BOARD_ID. Instead, a board will set BOARD_ID_SUPPORT (the ones affected already do) which will set GENERIC_GPIO_SUPPORT and compile the generic GPIO library. The user is expected to handle the details of how the ID is encoded. BUG=none BRANCH=none TEST=Compiled for peppy, nyan*, storm, and pinky Change-Id: Iaf1cac6e90b6c931100e9d1b6735684fac86b8a8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 93db63f419f596160ce2459eb70b3218cc83c09e Original-Change-Id: I687877e5bb89679d0133bed24e2480216c384a1c Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/228322 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9413 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10gpio: add a function to read GPIO array as base-2 valueDavid Hendricks
This adds gpio_base2_value() which reads an array of 2-state GPIOs and returns a base-2 value, where gpio[0] represents the least significant bit. BUG=none BRANCH=none TEST=tested with follow-up patches for pinky Change-Id: I0d6bfac369da0d68079a38de0988c7b59d269a97 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 27873b7a9ea237d13f0cbafd10033a8d0f821cbe Original-Change-Id: Ia7ffc16eb60e93413c0812573b9cf0999b92828e Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/228323 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9412 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2015-04-10gpio: cosmetic changes to tristate_gpios.cDavid Hendricks
This patch makes a few cosmetic changes: - Rename tristate_gpios.c to gpio.c since it will soon be used for binary GPIOs as well. - Rename gpio_get_tristates() to gpio_base3_value() - The binary version will be called gpio_base2_value(). - Updates call sites. - Change the variable name "id" to something more generic. BUG=none BRANCH=none TEST=compiled for veyron_pinky and storm Change-Id: Iab7e32f4e9d70853f782695cfe6842accff1df64 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c47d0f33ea1a6e9515211b834009cf47a171953f Original-Change-Id: I36d88c67cb118efd1730278691dc3e4ecb6055ee Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/228324 Reviewed-on: http://review.coreboot.org/9411 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10rk3288: Adjust CBFS header and ROM offsetsJulius Werner
Our CBFS header offset on rk3288 was very low and overlapped with the end of the bootblock on recent Pinky builds. This can create all kinds of fun effects like BSS variables suddenly being initialized to something else than zero, in an effect that jumps somewhere else for every slightest code size change. This patch moves the CBFS header offset up a bit and the CBFS ROM offset down (because there's really no point in leaving such a large gap). This resolves our immediate booting problems, and I'll also start on a patch to add further checks somewhere that catch these overlaps in the future. BRANCH=None BUG=None TEST=Created a Pinky image from the exact same commit version as the official 6443.0.0 build, with a KERNELREVISION string of the exact same length as the builder (which for some arcane reason is different than running emerge locally, shifting the whole bootblock around with it). Confirmed that I saw the same "Not enough room for another sub-pagetable!" hang, and that this patch fixes it. Change-Id: I9e59a282b3cd0af3b0d224d64c10b7c4d312ad02 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 1a142cd2c51c6f51a1597c21ad513feb151e0938 Original-Change-Id: I8be5b7b7e87021cc1b3a91d336e8d233546ee188 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/228326 Original-Reviewed-by: Gediminas Ramanauskas <gedis@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9410 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10rk3288: don't log LAST_TSHUT bithuang lin
Since the LAST_THSUT bit is uncertain value when it cold-reboot, we remove the printout about this status bit in coreboot. BUG=chrome-os-partner:33521 TEST=Boot on veyron_pinky rev2 Change-Id: I3b9791ffdffeff0721e3d86378db6255c5abc9ea Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 16464d3229ad1001952ef1b50fe3e606d1583462 Original-Change-Id: I258750797e32c28f86e73a01eede005e890a6906 Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/228391 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9409 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10rk3288: slowly raise to max cpu voltage to prevent overshoothuang lin
slowly raise to max cpu voltage to prevent overshoot, and in our experience,when cpu run in 1.8GHz,the vdd_cpu must up to 1.4V BUG=chrome-os-partner:32716, chrome-os-partner:31896 TEST=Boot on veyron_pinky rev2,check the rk808 buck1 voltage 1400mv and measure the overshoot is 1440mv Change-Id: I759840bd8cf57a5589bf1862d04803f80f804164 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 567f616ff091883ed3275b407859c9399db981b2 Original-Change-Id: I9bb739b49ae4b4f7a60133fa38b0fe51b95c0d78 Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/226753 Original-Reviewed-by: Doug Anderson <dianders@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9408 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10ryu: update board id definitionsAaron Durbin
There are changes in upcoming board revs that need to take different action depending on board revision. Update the enumeration to reflect upcoming reality. BUG=chrome-os-partner:33578 BRANCH=None TEST=Built and booted. Change-Id: Ib51393e04d3255bbd44e5d77a2a7903109beebf4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: de8d629678c0ae17af9f7145e04d95f43c927ee0 Original-Change-Id: I64cdeab806e7a665051f1d47bbf044413f7a1196 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/227681 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9407 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-04-10ryu: remove board id normalizationAaron Durbin
The gpio_get_tristates() function prints out the values observed while processing the GPIOs. Additionally, the values for the normalization were completely consecutive. Therefore, this indirection can be removed. BUG=chrome-os-partner:33578 BRANCH=None TEST=Built and booted. Change-Id: I088a2f1c7601c014a7f8a9eb228efa9bb80f1e01 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 02e52554b9cbf85034feb9aedc50f09b70893e32 Original-Change-Id: I17d85891087e3128790329a5f05cbdab4cbc950e Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/227680 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9406 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10tpm: allow 0 as valid i2c bus numberDaisuke Nojiri
tpm driver uses bus=0 as indication of uninitialized tpm device. this change allows 0 as a valid i2c bus number. BUG=None BRANCH=ToT TEST=Built cosmos. Change-Id: Ie8d285abff11643cc3efc0fa30e4afcc3ca1c0d5 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 493077b68cf46b08f0d1ddfe57bf6064d714d537 Original-Change-Id: Iac55e88db4ef757a292270e7201d8fdd37a90b50 Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/226294 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9405 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10google/storm: Minor board ID changesDan Ehrenberg
- Add the Whirlwind board ID to the enum - Replace comparisons of the board ID with 0 to the proto0 constant TEST=Booted Storm with this coreboot version BUG=none BRANCH=none Change-Id: I53be0b06c3444936a8bd67653e03b93bcb87e328 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 7e055ef27ef1e07be09d80b2298384889214bf0d Original-Change-Id: I75c7c98732c3d4569611de54d7aa149dd3b0fb7d Original-Signed-off-by: Dan Ehrenberg <dehrenberg@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/225460 Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/9404 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10chromeos: add another VPD access APIVadim Bendebury
The new API allows to find VPD objects in the VPD cache. There is no need for the caller to allocate or free the per object memory. The existing API (cros_vpd_gets) now uses the new function as well. BRANCH=storm BUG=chrome-os-partner:32611 TEST=verified that MAC addresses still show up in the device tree on the booted storm device Change-Id: Id06be315981cdaa2285fc1ec61b96b62b1178a4b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 99a34344448a5521cee8ad3918aefb1fde28417d Original-Change-Id: I6c0b11bb844d6235930124d642da632319142d88 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/225258 Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/9403 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10storm: Initialize clock, pinmux for NAND if present on boardDan Ehrenberg
This patch runs basic NAND initialization code on Proto 0.2 boards which have been reworked for NAND. It makes sense to do this in coreboot for two reasons: - In general, it is reasonable for coreboot to initialize clocks and such in preparation for depthcharge's use. Waiting times can be pooled, and the initialization itself here is very fast. - There is a kernel bug which requires that the clock is already initialized before the kernel loads NAND support. coreboot is a more sensible place to put a workaround than depthcharge because depthcharge initializes things lazily, but when booting from USB, depthcharge won't need to look at NAND. This change involves bringing in an additional header file, ebi2.h, from U-Boot. TEST=Booted a kernel from USB and verified that NAND came up without any depthcharge hacks, whereas previously a USB-booted kernel would be unable to access NAND even with the same drivers compiled in due to an initialization failure. BUG=chromium:403432 BRANCH=none Change-Id: I04e99cb39d16848a6ed75fe0229b8f79bdf2e035 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 9be29da5ccad9982f146ae00344f30598ef2371c Original-Signed-off-by: Dan Ehrenberg <dehrenberg@chromium.org> Original-Change-Id: I1760ecb4e47438311d80e34326e45578c608481c Original-Reviewed-on: https://chromium-review.googlesource.com/225277 Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/9402 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10gpio: Remove non-ternary tristate mode, make ternaries easierJulius Werner
The function to read board IDs from tristate GPIOs currently supports two output modes: a normal base-3 integer, or a custom format where every two bits represent one tristate pin. Each board decides which representation to use on its own, which is inconsistent and provides another possible gotcha to trip over when reading unfamiliar code. The two-bits-per-pin format creates the additional problem that a complete list of IDs (such as some boards use to build board-ID tables) necessarily has "holes" in them (since 0b11 does not correspond to a possible pin state), which makes them extremely tricky to write, read and expand. It's also very unintuitive in my opinion, although it was intended to make it easier to read individual pin states from a hex representation. This patch switches all boards over to base-3 and removes the other format to improve consistency. The tristate reading function will just print the pin states as they are read to make it easier to debug them, and we add a new BASE3() macro that can generate ternary numbers from pin states. Also change the order of all static initializers of board ID pin lists to write the most significant bit first, hoping that this can help clear up confusion about the endianness of the pins. CQ-DEPEND=CL:219902 BUG=None TEST=Booted on a Nyan_Blaze (with board ID 1, unfortunately the only one I have). Compiled on Daisy, Peach_Pit, Nyan, Nyan_Big, Nyan_Blaze, Rush, Rush_Ryu, Storm, Veryon_Pinky and Falco for good measure. Change-Id: I3ce5a0829f260db7d7df77e6788c2c6d13901b8f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 2fa9545ac431c9af111ee4444d593ee4cf49554d Original-Change-Id: I6133cdaf01ed6590ae07e88d9e85a33dc013211a Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/219901 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9401 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10gpio: Extend common GPIO header, simplify function namesJulius Werner
We've had gpiolib.h which defines a few common GPIO access functions for a while, but it wasn't really complete. This patch adds the missing gpio_output() function, and also renames the unwieldy gpio_get_in_value() and gpio_set_out_value() to the much easier to handle gpio_get() and gpio_set(). The header is renamed to the simpler gpio.h while we're at it (there was never really anything "lib" about it, and it was presumably just chosen due to the IPQ806x include/ conflict problem that is now resolved). It also moves the definition of gpio_t into SoC-specific code, so that different implementations are free to encode their platform-specific GPIO parameters in those 4 bytes in the most convenient way (such as the rk3288 with a bitfield struct). Every SoC intending to use this common API should supply a <soc/gpio.h> that typedefs gpio_t to a type at most 4 bytes in length. Files accessing the API only need to include <gpio.h> which may pull in additional things (like a gpio_t creation macro) from <soc/gpio.h> on its own. For now the API is still only used on non-x86 SoCs. Whether it makes sense to expand it to x86 as well should be separately evaluated at a later point (by someone who understands those systems better). Also, Exynos retains its old, incompatible GPIO API even though it would be a prime candidate, because it's currently just not worth the effort. BUG=None TEST=Compiled on Daisy, Peach_Pit, Nyan_Blaze, Rush_Ryu, Storm and Veyron_Pinky. Change-Id: Ieee77373c2bd13d07ece26fa7f8b08be324842fe Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 9e04902ada56b929e3829f2c3b4aeb618682096e Original-Change-Id: I6c1e7d1e154d9b02288aabedb397e21e1aadfa15 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/220975 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9400 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10storm: retrieve MAC address from VPDVadim Bendebury
Retrieving MAC address from VPD should be the board responsibility, add a call to the recently introduced function. BRANCH=storm BUG=chromium:417117 TEST=verified that MAC addresses still show up in the device tree on storm Change-Id: Ib8ddc88ccd859e0b36e65aaaeb5c9473077c8c02 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 285cb256e619ef41c7f11680b3fa5310b1d93cf1 Original-Change-Id: I3913b10a425d8e8621b832567871ed4861756381 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/223797 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9399 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2015-04-10chromeos: move VPD MAC address retrieval functionVadim Bendebury
Retrieval of the MAC address from the VPD is a Chrome OS specific feature, required just on one platform so far. There is no need to look for the MAC address in the VPD on all other Chrome OS boards. BRANCH=storm BUG=chromium:417117 TEST=with the upcoming patch applied verified that MAC addresses still show up in the device tree on storm Change-Id: If5fd4895bffc758563df7d21f38995f0c8594330 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: fb4906ac559634321a01b4814f338611b9e98b2b Original-Change-Id: I8e6f8dc38294d3ab11965931be575360fd12b2fc Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/223796 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9398 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10arm64: secmon: pass online CPUs to secmonAaron Durbin
Instead of relying on CONFIG_MAX_CPUS to be the number of CPUs running a platform pass the number of online cpus from coreboot secmon. That allows for actually enabled CPUs < CONFIG_MAX_CPUS. BUG=chrome-os-partner:32112 BRANCH=None TEST=Booted SMP kernel. Change-Id: Iaf1591e77fcb5ccf5fe271b6c84ea8866e19c59d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3827af876c247fc42cd6be5dd67f8517457b36e7 Original-Change-Id: Ice10b8ab45bb1190a42678e67776846eec4eb79a Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/227529 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9397 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10arm64: psci: use struct cpu_action to track startup entryAaron Durbin
The struct cpu_action already tracks entry/arg pointers. Use that instead of duplicating the same information. BUG=chrome-os-partner:32112 BRANCH=None TEST=Built and booted. Change-Id: I70e1b471ca15eac2ea4e6ca3dab7d8dc2774a241 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: cdddfd8d74d227cb5cbdf15b6871480839fa20d8 Original-Change-Id: I4070ef0df19bb1141a1a47c4570a894928d6a5a4 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/227549 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9396 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10arm64: secmon: prepare for passing more state into secmonAaron Durbin
The current implementation of secmon assumes just entry/arg are passed to secmon for starting up a CPU. That's lacking in flexibility. Therefore change secmon_params to contain both the BSP and secondary CPUs' entry/arg information. That way more information can be added to secmon_params when needed. BUG=chrome-os-partner:32112 BRANCH=None TEST=Built and booted SMP kernel using PSCI and spin table. Change-Id: I84c478ccefdfa4580fcc078a2491f49f86a9757a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c5fb5bd857a4318174f5b9b48e28406e60a466f8 Original-Change-Id: Iafb82d5cabc806b6625799a6b3dff8d77bdb27e9 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/227548 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9395 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10arm64: secmon: wait for all CPUs to enter secmonAaron Durbin
There is state within the system that relies on having all CPUs present in order to proceed with initialization. The current expectation is that all CPUs are online and entering the secure monitor. Therefore, wait until all CONFIG_MAX_CPUs show up. BUG=chrome-os-partner:32112 BRANCH=None TEST=Can get all CPUs up in kernel using PSCI. Change-Id: I741a09128e99e0cb0c9f4046b1c0d27582fda963 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 030535b7c9821b40bf4a51f88e289eab8af9aa13 Original-Change-Id: Ia0f744c93766efc694b522ab0af9aedf7329ac43 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/227547 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9394 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10git: add rebase helper scriptPatrick Georgi
This is a script we have been using to rewrite commit messages when upstreaming coreboot patches from the Chromium OS tree into coreboot upstream. Change-Id: I5442279c099dafe55cc97ccf09ee2bc2df4eca5f Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/9299 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10serial: Combine Tegra and Rockchip UARTs to generic 8250_mmio32Julius Werner
We have two drivers for a 100%-identical peripheral right now, mostly because we couldn't come up with a good common name for it back when we checked it in. That seems like a pretty silly reason in the long run. Both Tegra and Rockchip SoCs contain UARTs that use the common 8250 register interface (at least for the very basic byte-per-byte transmit and receive parts we care about), memory-mapped with a 32-bit register stride. This patch combines them to a single 8250_mmio32 driver (which also fixes a problem when booting Rockchip without serial enabled, since that driver forgot to check for serial initialization when registering its console drivers). The register accesses are done using readl/writel (as Rockchip did before), since the registers are documented as 32-bit length (with top 24 bits RAZ/WI), although the Tegra SoC doesn't enforce APB accesses to have the full word length. Also fixed checkpatch stuff. A day may come when we can also merge this driver into the (completely different, with more complicated features and #ifdefs) 8250 driver for x86 (which has MMIO support for 8-bit register stride only), both here and in coreboot. But it is not this day. This day I just want to get rid of a 99% identical file without expending too much effort. BUG=None TEST=Booted on Veyron_Pinky and Nyan_Blaze with and without serial enabled, both worked fine (although Veyron has another kernel issue). Change-Id: I85c004a75cc5aa7cb40098002d3e00a62c1c5f2d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e7959c19356d2922aa414866016540ad9ee2ffa8 Original-Change-Id: Ib84d00f52ff2c48398c75f77f6a245e658ffdeb9 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/225102 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9387 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10armv7-m: set stack pointer to _estackDaisuke Nojiri
this change sets the stack pointer to the value specified in memlayout.ld before jumping to the bootblock. BUG=none BRANCH=ToT TEST=Built cosmos and all other current boards. Change-Id: Ic1b790f27bce431124ba70cc2d3d3607c537564b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d50fd02db8bf10147fd808f3030e6297b9ca0aad Original-Change-Id: I4bb8cea7435d2a0e2c1ced050c3366d2e636cb8a Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/225420 Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/9384 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10armv7-m: add bootblock entry pointDaisuke Nojiri
this adds an entry point jumping to main for the bootblock. BUG=None BRANCH=ToT TEST=Built coreboot for cosmos Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Change-Id: I1c9ea6ba63a1058e09613d969fe00308260037be Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 662d0083f25008b55b9bc5fbce9e30e6b80c2c65 Original-Change-Id: I74f2f5e3b3961ab54a7913e6b3a3ab0e6fd813a3 Original-Reviewed-on: https://chromium-review.googlesource.com/225205 Original-Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> Original-Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/9382 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10armv7-m: add empty cache routinesDaisuke Nojiri
armv7-m does not have cache but adding empty cache functions allow us to transparently use code handling entering and leaving stages. BUG=none BRANCH=ToT TEST=Built coreboot for cosmos Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Change-Id: I23415b273c90401cd81f2bc94b2d69958f134c6a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 960453bf5d5fbf7dc75343b1cccaa62b6b8ec30c Original-Change-Id: Ief0c8a949e7e14d68473e7a093a8642d6058ccc6 Original-Reviewed-on: https://chromium-review.googlesource.com/225206 Original-Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> Original-Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9383 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10bg4cd: set bootblock and verstage architecture to armv7-mDaisuke Nojiri
this sets the proper architecture for bg4cd's bcm, which is armv7-m. BUG=none TEST=built cosmos BRANCH=none Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Change-Id: I6af25080c10a245a1fc884acb2a705f0b5d96309 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: fc04fd26f1f2634115fc9bcefd6eee5611c80659 Original-Change-Id: I3334c3ba27a3582ce0fe5b484a5a22c8441a4c11 Original-Reviewed-on: https://chromium-review.googlesource.com/224773 Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Original-Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> Original-Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: http://review.coreboot.org/9381 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>