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2023-02-05mb/google/skyrim/var/frostflow: Override SPI flash bus speedFrank Wu
Add configuration to bump up the SPI flash bus speed from 66 MHz to 100 MHz starting the board version of the current phase. BUG=b:260127676 TEST=Build and boot to OS in Frostflow with 100 MHz SPI bus speed. Observe that the boot time improved by 100 ms compared to 66 MHz SPI flash bus speed. firmware log: SPI fast read speed: 100 MHz At 66 MHz: Total Time: 1,563,384 At 100 MHz: Total Time: 1,462,570 Change-Id: I9435f4ad0d3541b040703dc9a453badbd080dc09 Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72694 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-02-05vc/amd/pi: Fix "No such file or directory"Elyes Haouas
Fix: cc1: error: src/vendorcode/amd/pi/00670F00: No such file or directory [-Werror=missing-include-dirs] cc1: error: src/vendorcode/amd/pi/00670F00/binaryPI: No such file or directory [-Werror=missing-include-dirs] cc1: error: src/vendorcode/amd/pi/00670F00/Include: No such file or directory [-Werror=missing-include-dirs] cc1: error: src/vendorcode/amd/pi/00670F00/Proc: No such file or directory [-Werror=missing-include-dirs] cc1: error: src/vendorcode/amd/pi/00670F00/Proc/Common: No such file or directory [-Werror=missing-include-dirs] cc1: error: src/vendorcode/amd/pi/00670F00/Proc/CPU: No such file or directory [-Werror=missing-include-dirs] cc1: error: src/vendorcode/amd/pi/00670F00/Proc/CPU/Family: No such file or directory [-Werror=missing-include-dirs] cc1: error: src/vendorcode/amd/pi/00670F00/Proc/Fch: No such file or directory [-Werror=missing-include-dirs] cc1: error: src/vendorcode/amd/pi/00670F00/Proc/Fch/Common: No such file or directory [-Werror=missing-include-dirs] Change-Id: I745f4fc421c91c413fe0d3155d3494ed9704eeb6 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71855 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-02-05util/scripts/testsoc: Pass arguments to abuildMartin Roth
This allows the user to pass one or more arguments through the testsoc script to abuild. Example: testsoc -K SOC_AMD_CEZANNE -a "--skip_unset BOARD_GOOGLE_NIPPERKIN" Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ic2bc8d656022560ed1eebf6eee0512d3633ebe84 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72766 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-04soc/amd/phoenix/chipset.cb: update USB portsFelix Held
Not exactly sure about the usb4_xhci controllers, but for now I assume those will behave like any other XHCI controller. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I22384f58e245a1486793831d29d22e9c618f646c Reviewed-on: https://review.coreboot.org/c/coreboot/+/72773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-02-04soc/amd/phoenix/chipset.cb: add remaining PCI devicesFelix Held
The PCI Device ID Assignments table from PPRs #57019 Rev 1.65 and PPR #57396 Rev 1.54 were used as a reference. Some devices will need to have ops added in future patches. Since the xhci_2 device isn't there any more, also drop it from the mainboard devicetrees. The actual USB port configuration on xhci_0 and xhci_1 is updated in the next patch. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I49721bc44fa1e2a0118a8c3ac79a36aee64be687 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72771 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-02-04soc/amd/phoenix/chipset.cb: rename GPP bridges on device 2Felix Held
Now that the PCIe ports on device 1 are added, rename the aliases for the PCIe ports on device 2 to have a common naming scheme. For phoenix the device alias names are based on the device and function number the bridge is connected to. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5f5698408019bb9222b599dd78540ca1b187b56d Reviewed-on: https://review.coreboot.org/c/coreboot/+/72737 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-04soc/amd/phoenix/chipset.cb: add missing GPP bridges on device 1Felix Held
Only the PCIe ports on the functions of device 2 were present in the devicetree and had the amd_external_pcie_gpp_ops ops assigned. Add the missing PCIe ports on the functions of device 1 and assign the amd_external_pcie_gpp_ops ops to them. This SoC uses a slightly different naming scheme for its PCIe GPP ports. Previously the PCIe GPP bridge number from the PCI Device ID Assignments table from the PPR was used. Those bridge numbers are one less than the function numbers of the device. This is due to function 0 being a dummy bridge to avoid having to shuffle around the function numbers when the first bridge is unused, since the PCIe specification mandates the function 0 to be implemented if any other function on the same device is implemented. In order for the device aliases to be consistent with the PCIe device and function numbers which is way more commonly used and also what lspci shows and what goes into the DXIO descriptors, change the naming scheme of the aliases. This was checked with PPR #57019 Rev 1.65 and PPR #57396 Rev 1.54. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib5c62c1df585877d9b6986a462a3636d4f2eb4c7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72736 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-04mb/google/skyrim: Update ASPM settings for the NVMe deviceMartin Roth
This enables L1.2 for the SSD port. link_hotplug is unused on Mendocino, so remove it while I'm here, just as code cleanup. This has no functional difference. Enabling L1.2 on other devices currently causes problems. Debug is ongoing. BUG=b:265890321 TEST=Build & boot, look at states enabled in lspci. Test device functionality. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I8940856a127c8a4ba45148cbbf07a08b621beb4d Reviewed-on: https://review.coreboot.org/c/coreboot/+/72391 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-02-04soc/intel/meteorlake: Enable MRC Fast BootSubrata Banik
This patch requests FSP to enable the MRC fast boot feature along with FSP v2473. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: If4a621e55c853505f7a702181ae5a70dc56d5b5a Reviewed-on: https://review.coreboot.org/c/coreboot/+/72745 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-04mb/google/rex: Use OV13B10 sensor for Proto 1 SKUsSubrata Banik
This patch drops the WFC sensor OV8856 (reused from the Brya chassis) support for Rex and added support for Rex specific UFC sensor OV13B10. BUG=b:267264348 TEST=WFC MIPI cameras have been enabled using google/rex Proto 1. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ic785b82db4368f40d91921f29c218cf417938541 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70226 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-02-04Revert "UPSTREAM: mb/google/rex: Enable SaGv"Subrata Banik
Enabling `SaGv` along with FSP v2473 is causing blank display issue. Mostly likely we shouldn't enable SaGv yet on Intel MeteorLake. BUG=b:267446159 TEST=Able to see ChromeOS UI in consecutive boot. This reverts commit cbca81c5946384843197c08401c4266f45fef4a2. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ifbcc36515f7550c183c40e5af94684f5c3e39a7a Reviewed-on: https://review.coreboot.org/c/coreboot/+/72774 Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-04soc/amd/cezanne/chipset.cb: add missing ops for GPP GFX bridgesFelix Held
Commit b171f768127d ("soc/amd/*: Hook up GPP bridges ops to devicetree") missed adding the amd_external_pcie_gpp_ops ops to the gpp_gfx_bridge PCIe ports, so add them. Those devices were previously covered by the PCI_DID_AMD_FAM17H_MODEL60H_PCIE_GPP_D1 PCI device ID in the list that got removed in the referenced commit. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I55434bf486569b32901b3840193a09cc5955abb2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72735 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-04soc/amd: Use common reset code for PCO SoCMartin Roth
This switches the Picasso SoC to use the common reset code. Picasso supports warm resets, so set the SOC_AMD_SUPPORTS_WARM_RESET flag. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I52515b20ef6c70b137f176d95480757b16bd8735 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72755 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-04soc/amd: Use common reset code for PHX & Glinda SoCsMartin Roth
This switches the Phoenix & Glinda SoCs to use the common reset code. Cezanne and newer do not support warm reset, so use cold resets in all cases (including the OS). Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I4593fa9766ac9e988722a02e355c971e147b8fae Reviewed-on: https://review.coreboot.org/c/coreboot/+/72754 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-04soc/amd: Use common reset code for CZN & MDN SoCsMartin Roth
This switches the Cezanne & Mendocino SoCs to use the common reset code. This patch does not change any behavior on those chips. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ie05c790573e4e68f3ec91bacffcc7d7efb986d79 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72659 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-04soc/amd: Create AMD common reset codeMartin Roth
This allows us to use the same file for PCO, CZN, MDN, PHX, & Glinda. PCO supports the warm reset, and future chips can support it by setting the SOC_AMD_SUPPORTS_WARM_RESET option. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ib6459e7ab82aacbe57b4c2fc5bbb3759dc5266f7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72658 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-04util/amdfwtool: add comment about reused PSP firmware type 0x5fFelix Held
On family 15h and 16h processors with PSP, the PSP firmware type 0x5f corresponds to AMD_FW_PSP_SMUSCS, while on family 17h and 19h this corresponds to AMD_FW_TPMLITE. Add comments to those two enum values to clarify this. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia5c125ec6a0eb548f58a457f9040278391d2101c Reviewed-on: https://review.coreboot.org/c/coreboot/+/72713 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bao Zheng <fishbaozi@gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-04util/autoport: Use chipset.cb referencesArthur Heymans
TESTED with x220 logs. Change-Id: I89023b6c6dd5d985168331fbb12b2fc36fb65dc3 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72597 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-02-04mb/*: Replace SNB PCI devices with references from chipset.cbArthur Heymans
Removing default on/off from mainboard devicetrees is left as a follow-up. Change-Id: I74c34a97ea4340fb11a0db422a48e1418221627e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69502 Reviewed-by: Jakub Czapiga <jacz@semihalf.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-02-04include/bootstate.h: Fail compilation on invalid bootstate hooksArthur Heymans
No BS_ON_EXIT hooks are run on BS_PAYLOAD_BOOT or BS_OS_RESUME, so don't allow these hooks. Change-Id: I318165f0bd510aed3138d3612dd3e264901aba96 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72708 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-02-04soc/intel/*: Fix dead bootstate codeArthur Heymans
No bootstate hook is called on exit of BS_OS_RESUME or BS_PAYLOAD_BOOT. Change-Id: I2b5b834d0663616a9523fd119f007e3bac8e7bf2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72707 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com>
2023-02-04mb/google/skyrim: Add EC_HOST_EVENT_PANIC to SCI maskRob Barnes
Adding EC_HOST_EVENT_PANIC to SCI mask allows the EC to interrupt the Kernel when an EC panic occurs. If system safe mode is also enabled on the EC, the kernel will have a short period to extract and save info about the EC panic. BUG=b:266696987 BRANCH=None TEST=Observe kernel ec panic handler run when ec panics Change-Id: I9b50ab3c0bcef192ef89f173852cda222f1533c7 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72455 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Tim Van Patten <timvp@google.com>
2023-02-04mb/starlabs/starbook/adl: Enable HPD GPIOSean Rhodes
Enable the HPD GPIO so that the USB-C port can be used for DisplayPort. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: If93d08f64cf7b09bb47622bdc7f22280b8a48174 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72431 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-04amdfwtool: Add entry RIB whose subprog equals 1Zheng Bao
For the PHX, it uses subprog 0. For the PHX2, it uses subprog 1. Change-Id: Ib013f264fc9940ad95e559fe19bba72c06a19625 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72507 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-02-04mb/intel/mtlrvp: Enable CNVi BT Core and WifiHarsha B R
This patch enables CNVi_BT Core and Wifi for mtlrvp based on mtlrvp schematics. 1. Enable CNVi BT Core in device tree 2. Enable CNVi Wifi (pci 14.3) device in device tree BUG=b:224325352 BRANCH=None TEST=Able to observe corresponding UPD configuration with FSP dump and able to boot mtlrvp (LP5/DDR5) to ChromeOS. CNVi Mode = 1 Wi-Fi Core = 1 BT Core = 1 BT Audio Offload = 0 BT Interface = 1 Signed-off-by: Harsha B R <harsha.b.r@intel.com> Change-Id: I22575bf31b540f9dc1149a2766268285001b72f4 Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72695 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-02-04soc/intel/tgl: Move ME FSR structures to pertinent headerDinesh Gehlot
This patch moves ME host firmware status register structures to ME header file. It also marks unused structure fields to reserved. The idea here is to decouple ME specification defined structures from the source file `.c` and keep those into header files so that in future those spec defined header can move into common code. The current and future SoC platform will be able to select the correct ME spec header based on the applicable config. It might be also beneficial if two different SoC platforms would like to use the same ME specification and not necessarily share the same SoC directory. BUG=b:260309647 Test=Able to build and boot. Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: Ib96fcb86fd2c3fe16f23c8f038f4930a832a5b01 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72416 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-02-03soc/intel/apl: Move cpu cluster to chipset.cbArthur Heymans
Change-Id: I7eaf625e5acfcefdae7c81e186de36b42c06ee67 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72704 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2023-02-03mb/google/brya0,skolas4es,skolas: disable Tccold HandshakeSelma Bensaid
The patch disables Tccold Handshake to prevent possible display flicker issue for skolas board. Please refer to Intel doc#723158 for more information. BUG=b:221461379 BRANCH=firmware-brya-14505.B TEST=Boot to OS on Skolas, verify upd setting. Change-Id: Ic184a61c27abd729667cd181d8f9954f58b67856 Signed-off-by: Selma Bensaid <selma.bensaid@intel.com> Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68636 Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-03soc/intel/alderlake: Hook up DisableDynamicTccoldHandshake to dev treeKane Chen
This commit provides a dev tree setting for partners to enable/disable TccoldHandshake for the sighting in doc:723158 BUG=b:221461379 BRANCH=firmware-brya-14505.B TEST=compile ok and FSP UPD is config properly Change-Id: Ica13b98204acebef7f0b9a4411b4ac19f53cad6e Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68635 Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-03vendorcode/intel/fsp: Expose DisableDynamicTccoldHandshakeBora Guvendik
Expose DisableDynamicTccoldHandshake in header so that coreboot can disable it. BUG=b:221461379 BRANCH=firmware-brya-14505.B TEST=Boot to OS, check UPD value in debug FSP build. Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: I0d953f37a2f0dac58fd339e3fe0dc847d5e6d892 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72693 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-03soc/intel/alderlake: Add a few missing definitions in iomap.hJeremy Compostella
Some reserved address range listed in Alder Lake Platform Firmware Architecture Specification document 626540 section 6.4 ADL - System Memory Map such as North TraceHub ranges were missing. Details about North TraceHub (aka. Intel TraceHub) can be found in Intel Trace Hub (Intel TH) Developer's Manual document 671536. BUG=b:264648959 TEST=Compilation successful Change-Id: I14803a7297c8c5edefe564d92bfe7314f6769942 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72635 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-02-03soc/intel/alderlake: Add a missing RPL-P power limits configurationJeremy Compostella
This patch adds the {MCH:a706, TDP:28W} missing 28W configuration. BUG=b:267666609 BRANCH=firmware-brya-14505.B TEST=Power Limit are properly set on skolas 28W Change-Id: Ice35d622eeec5799c53de086430d00dc8789097e Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72734 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-02-03util/scripts/testsoc: Only select mainboardsFred Reitberger
The testsoc script was pulling in odd results when the -K option matched options in sources, Makefiles, and device trees. Adding another grep to limit the list to just Kconfig matches ensures that only actual mainboards are built. TEST="./util/testsoc -K PICASSO" no longer tries to build mainboard "0" Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I3860df4520a5594fb9c1a06e75487520b7d5d275 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72655 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-03mb/google/nissa/var/craask: Add DPTF settings for 15W CPURen Kuo
Add ADL-N 15W CPU thermal settings. BUG=b:265101768 TEST=emerge-nissa coreboot Change-Id: I325704d6fc4ddaf56eaddd6a69bc619588df99cd Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71860 Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Reka Norman <rekanorman@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-02-03mb/google/rex: update touchscreen report EN pin settingIvy Jian
Removed workaround since the latest schematics fixed. Power Sequencing of ELAN6918 (in ACPI) after this patch `POWER enabled -> RESET deasserted -> Report EN enabled` BUG=b:247029304 TEST=Verified ELAN touch panel is working as expected after booting Google/rex device to ChromeOS. Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Change-Id: I19629262776f7e0cccbdebb2285890d177a8a8a6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72725 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-02-02soc/intel/alderlake: Add entries to eventLog on invocation of early SOLTarun Tuli
If we show the user early signs of life during CSE FW sync or MRC (re)training, log these to the eventLog (ELOG_TYPE_FW_EARLY_SOL). These can be used to ensure persistence across global reset (e.g. after CSE sync) so that they can be later retrieved in order to build things such as test automation ensuring that we went through the SOL path/display initialized. BUG=b:264648959 TEST=event shows in eventlog after CSE sync and/or MRC Change-Id: I8181370633a1ecff77b051d3110f593c3eb484a2 Signed-off-by: Tarun Tuli <taruntuli@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71295 Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2023-02-02util/cbfstool: Add eventLog support for ELOG_TYPE_FW_EARLY_SOLTarun Tuli
In order to support logging events for when we show early signs of life to the user during CSE FW syncs and MRC trainings add support for the ELOG_TYPE_FW_EARLY_SOL type. BUG=b:266113626 TEST=verify event shows in eventlog CSE sync/MRC training Change-Id: I3913cb8501de9a2605266cf9988a7195576cb91d Signed-off-by: Tarun Tuli <tarun.tuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71296 Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2023-02-02commonlib: Add ELOG_TYPE_FW_EARLY_SOL eventLog typeTarun Tuli
Add a new eventLog type of ELOG_TYPE_FW_EARLY_SOL to support logging when we show early signs of life to the user. BUG=b:266113626 TEST=event shows in eventlog after CSE sync and/or MRC Change-Id: I3bd5a250c0be824dbbad0236cee7d61a1ffdbc6c Signed-off-by: Tarun Tuli <tarun.tuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72670 Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2023-02-02soc/intel/xeon_sp: add Kconfig file for SPR-SPJonathan Zhang
Intel SPR-SP (Sapphire Rapids Scalable Processor) was product launched on Jan. 10, 2023. Change-Id: I14cf115b02d8edff9b48e744b798a3b1ba18b8bf Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72439 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Simon Chou <simonchou@supermicro.com.tw> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2023-02-02mb/google/dedede/var/dibbi: Update devicetree and GPIO tableLiam Flaherty
Create overridetree and GPIO config based on latest schematic: 1. Update PCIe ports 2. Update USB ports 3. Remove unused I2Cs 4. Remove unused peripherals (SD card, eDP, speakers) 5. Add LAN 6. Thermal policy for updated temp sensors BUG=b:260934185, b:260934719 BRANCH=dedede TEST=build Change-Id: I4789be2eee1d01288031bc1e8ee5c9d6df71f9fe Signed-off-by: Liam Flaherty <liamflaherty@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71882 Reviewed-by: Adam Mills <adamjmills@google.com> Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-02drv/i2c/ptn3460: Use PTN_EDID_LEN instead of constantJan Samek
Contents of the EDID are passed by a reference to an array of length 0x80, for which the macro 'PTN_EDID_LEN' has already been around. This patch makes use of this macro within the driver and mainboard implementation utilizing it. BUG=none TEST=A successful build of mc_apl{1,4,5,7} and mc_ehl3 mainboards. Change-Id: If7d254aaf45d717133bb426bd08f8f9fe5c05962 Signed-off-by: Jan Samek <jan.samek@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72653 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2023-02-02mb/google/brya: Skip locking for GPP_F14 GPIOMaulik Vaghela
This is regarding issues observed on multiple Brya and Nissa variant such as Skolas and Nivviks. Issue is that once coreboot sets GPE_EN bit for the GPIO pin and locks it, kernel is not able to change the control bit. Hence kernel is not able to control the IRQ on the pin when required. This issue was root caused to the patch which was setting GPE_EN bits for the GPIOs before locking. Ref: commit 38b8bf02d820 ("intelblocks: Add function to program GPE_EN before GPIO locking") This patch skips the locking for GPP_F14 to allow kernel to configure it later during reboot or shutdown as required. BUG=b:254064671 BRANCH=None TEST=Shutdown works on Skolas and Brya board with the patch. Signed-off-by: Maulik Vaghela <maulikvaghela@google.com> Change-Id: I7e4a6ac4668028bcd5fa400b9aa8eccf36a79620 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72648 Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-02mb/google/skolas: Skip locking for GPP_F14 GPIOMaulik Vaghela
There is an existing issue for skolas boards where board wakes up from shutdown immediately due to touchpad wake signal. This issue was root caused to the patch which was setting GPE_EN bits for the GPIOs before locking. Ref: commit 38b8bf02d820 ("intelblocks: Add function to program GPE_EN before GPIO locking") Later issue was found to be with GPP_F14 configuration for skolas boards. While shutting down, kernel is not able to disable IRQ for touchpad due to GPE_EN register getting locked and it is preventing shutdown of the board. This patch skips the locking for GPP_F14 to allow kernel to configure it later. BUG=b:254064671 BRANCH=None TEST=Shutdown works on Skolas board with the patch. Nissa Bug: 234097956 Signed-off-by: Maulik Vaghela <maulikvaghela@google.com> Change-Id: I09cf1af1f5ab11b06073755374ee8a306984d557 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72426 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-02configs/builder/config.ocp.tiogapass: Add CONFIG_BOARD_OCP_TIOGAPASSJohnny Lin
Otherwise configurations in src/mainboard/ocp/tiogapass/Kconfig cannot be selected by make defconfig KBUILD_DEFCONFIG=configs/builder/config.ocp.tiogapass Change-Id: I88d5619269a6a9c09e84061642206a17c91db042 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72642 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2023-02-02include/cpu/amd/mtrr: drop unused TOP_MEM_MASK definitionsFelix Held
Neither TOP_MEM_MASK nor TOP_MEM_MASK_KB is used, so drop the two definitions. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0b2dfb7be27884dffb948876aabb73f99834c281 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72649 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-02-02amdfwtool: Set the level of RIB file as level 2Zheng Bao
It is about AB recovery layout which only has level 2. Change-Id: I836f11ca0bf5ad37e5093419465244a5c83318cb Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72508 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-02-02ifdtool: Introduce region_name_fmapPatrick Rudolph
Instead of directly accessing the region_name array use a helper function. This allows to move the region name array to a separate file. Change-Id: Ifc810da1628cebd2728d0185502c462ff9428597 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68694 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-02-02ifdtool: Add missing chipset_namePatrick Rudolph
Add denverton soc chipset name. Change-Id: I0fd8494123490d6ccc21af2ed30c30d50ddb4e8e Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68693 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-02ifdtool: Drop chipset without IFDPatrick Rudolph
Drop unused chipsets that do not use an IFD. Change-Id: I999e5e5d2063b8d33819fb22296ed486e1194cbb Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68692 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-02-02ifdtool: Cleanup IFDv1 detectionPatrick Rudolph
Change https://review.coreboot.org/c/coreboot/+/54305 "util/ifdtool: Use -p platform name to detect IFDv2 platform and chipset" made the '-p' argument mandatory for IFDv2 platforms. Drop the IFDv2 platform CHIPSET_C620_SERIES_LEWISBURG from IFDv1 detection. Change-Id: If29f8718b7aa696cdc07deef4c98be9a68c66f10 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68680 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-02util/ifdtool: Add Wellsburg supportPatrick Rudolph
Wellsburg is IFDv2 compatible in most fields, but not in all. It only has 8 regions and the flash master bits match the defines for IFDv1 and thus has an "IFDv1.5" descriptor. Add a new enum for IFDv1.5 descriptor and use them to properly operate on this IFD. The 'SPI programming guide' is inconsistent and mentions 6 regions in one place, but 7 regions in another chapter. Tests showed that it actually supports 7 regions. Add support using the -p argument to specify Wellsburg platform. The previous patch made sure that only 8 regions are used and that no corruption can happen when operating in IFDv2/IFDv1.5 mode. Tested on Intel Grangeville. Documents used: Intel Document Id: 516552 Intel Document Id: 565117 Change-Id: I651730b05deb512478d059174cf8615547d2fde4 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Co-developed-by: Julian Elischer <jrelis@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-02-02soc/intel/meteorlake: Enable V1p05-PHY supply external FET controlSubrata Banik
This patch enables S0i2.2 by letting 1.5V Phy supply to control the externa FET. BUG=b:256805904 Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I8771c11ce3b305343c7e96510e1375538d5e7f04 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72709 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2023-02-02nb/intel/{sandybridge,haswell}: Generate IOAPIC DMAR entries from hwBill XIE
Use acpi_create_dmar_ds_ioapic_from_hw() to generate DMAR entries. This can restore s3 resume capability for Sandy Bridge platforms lost after commit d165357ec37c ("sb,soc/intel: Use register_new_ioapic_gsi0()"). Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Change-Id: I83e735707cd9ff30aa339443593239cd7e3e4656 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72513 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-02-02soc/mediatek/mt8188: Remove the GPIO setting of USB1_DRV_VBUSLiju-Clr Chen
USB1_DRV_VBUS is used to provide 5V power for USB on MT8188 EVB and it's not used on Geralt. Therefore, remove the GPIO setting of USB1_DRV_VBUS. TEST=read usb data successfully. BUG=b:236331724 Change-Id: Iffea7b288c83c81648d4c7ca30d2f0961f9853ff Signed-off-by: Liju-Clr Chen <liju-clr.chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72641 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-01soc/qualcomm/sc7280: Memlayout change to support new Crypto sha updateVenkat Thogaru
With New Crypto upgrade we need to have 1 block of 4Kb increase in romstage, by which we can see an improvement of Boot performance by 100 msec. BUG=b:218406702 TEST=Validated on qualcomm sc7280 development board Boot performance improved by 100 msec observed. Change-Id: I9f5c8a79993fc1c529fae5cea4c4182663643ddd Signed-off-by: Sudheer Kumar Amrabadi <quic_samrabad@quicinc.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72646 Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com>
2023-02-01soc/qualcomm/common/qup: Avoid double decompress of gsi_fw blobSudheer Kumar Amrabadi
During boot, gpi_firmware_load gets called twice because there are 2 serial engines. Thus gsi_fw blob is also decompressed twice and is written to base addresses of SEs. This is redundant. Perform the decompression once on first call and save the header in static variable which can be reused in next call. BUG=b:262426214 TEST=Validated on qualcomm sc7280 development board Saving of 80ms observed while testing with 130 boot cycles. Change-Id: If98a3974f0791dffdf675c02cc28375d0485c485 Signed-off-by: Vijaya Nivarthi <vnivarth@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71927 Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-01soc/amd/mendocino: Force resets to be coldMartin Roth
Like Cezanne, Mendocino does not support warm resets. Change all resets (including resets in the OS) to cold resets (like Cezanne). BUG=b:248221908 TEST=Run suspend_stress_test, then reboot Change-Id: I1fbb4cc6eb6e6de9616d00d0191ccf3c0ac55278 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72486 Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com>
2023-02-01soc/intel/jsk: Move ME FSR structures to pertinent headerDinesh Gehlot
This patch moves ME host firmware status register structures to ME header file. It also marks unused structure fields to reserved. The idea here is to decouple ME specification defined structures from the source file `.c` and keep those into header files so that in future those spec defined header can move into common code. The current and future SoC platform will be able to select the correct ME spec header based on the applicable config. It might be also beneficial if two different SoC platforms would like to use the same ME specification and not necessarily share the same SoC directory. BUG=b:260309647 Test=Able to build and boot. Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: I58faed286718f5eab714cd39001177e50feb4f8b Reviewed-on: https://review.coreboot.org/c/coreboot/+/72414 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-02-01soc/intel/skl: Move ME FSR structures to pertinent headerDinesh Gehlot
This patch moves ME host firmware status register structures to ME header file. It also marks unused structure fields to reserved. The idea here is to decouple ME specification defined structures from the source file `.c` and keep those into header files so that in future those spec defined header can move into common code. The current and future SoC platform will be able to select the correct ME spec header based on the applicable config. It might be also beneficial if two different SoC platforms would like to use the same ME specification and not necessarily share the same SoC directory. BUG=b:260309647 Test=Able to build and boot. Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: Ic42c67163fe42392952499293e91e35537cb9147 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72415 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-02-01soc/intel/cnl: Move ME FSR structures to pertinent headerDinesh Gehlot
This patch moves ME host firmware status register structures to ME header file. It also marks unused structure fields to reserved. The idea here is to decouple ME specification defined structures from the source file `.c` and keep those into header files so that in future those spec defined header can move into common code. The current and future SoC platform will be able to select the correct ME spec header based on the applicable config. It might be also beneficial if two different SoC platforms would like to use the same ME specification and not necessarily share the same SoC directory. BUG=b:260309647 Test=Able to build and boot. Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: I34d3c4a60653fe0c1766cd50c96b8d3fe63637d1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72412 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-02-01soc/intel/mtl: remove DPTF from D-states list used to enter LPMEran Mitrani
The D-state list lists the devices with the corresponding D-state that the devices should be in, in order to enter LPM. DPTF is not mentioned in Intel's document 595644 as one of the devices. This CL removes it to avoid a potential error seen in ADL devices as mentioned in commit 3fd5b0c4cdeb ("soc/intel/adl: remove DPTF from D-states list used to enter LPM") TEST=Built and tested on Rex, saw SSDT generated properly. BUG=b:231582182 Signed-off-by: Eran Mitrani <mitrani@google.com> Change-Id: I9192ed9a7fb59ebba14f6d5082b400534b16ca72 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72603 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-01ec/google/wilco/acpi: Add DPTF RCDP() methodMatt DeVillier
The Windows DPTF drivers expect this method, and if not present appear to hang. Adding this method fixes DPTF under Windows on drallion. Modeled after existing method used by chrome-ec. TEST=build/boot Win11 on google/drallion, verify DPTF functional. Change-Id: I6570345379da413273251ecf5209c4997aac9b11 Original-patch-by: Coolstar <coolstarorganization@gmail.com> Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72578 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2023-02-01mb/google/brya/var/omnigul: Add memory configAmanda Huang
Configure the rcomp, dqs and dq tables based on the schematic. BUG=b:264340545 BRANCH=firmware-brya-14505.B TEST=FW_NAME=omnigul emerge-brya coreboot Change-Id: I82ca8aa9c3535983d5c506c15dbc69e7be926fa0 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71930 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Marx Wang <marx.wang@intel.com>
2023-02-01mb/google/brya/var/omnigul: Select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFSJamie Chen
This patch selects USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS for Google/Omnigul variant which intends to achieve a unified AP firmware image across UFS and non-UFS skus. BUG=b:263846075 TEST=FW_NAME=omnigul emerge-brya coreboot Change-Id: I90ae116ccccde48792aeafaa683c7420a95c9886 Signed-off-by: Jamie Chen <jamie_chen@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72509 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-01mb/google/geralt: Add USB3 HUB reset funtion to bootblockBo-Chen Chen
After powering on the device, we need to pull USB3_HUB_RST_L up to enable USB3 Hub. TEST=boot kernel from USB ok BUG=b:264841530 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Signed-off-by: Liju-Clr Chen <liju-clr.chen@mediatek.com> Change-Id: I8df35efb78e90a5b3314840fe2eae81d6e501242 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72594 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-01Documentation: Fix broken tablesNicholas Chin
- The 4.19 release notes included a list of outstanding issues formatted as a markdown table, which is not supported by Recommonmark. Reformat as an embedded reStructuredText table. - The table of boards supported on the 4.18 branch did not include row separators causing all rows to be rendered in a single row of cells. - Technotes/console.md had a typo in the rST table formatting which generated warnings in the Sphinx build, causing the table to not be rendered in the resulting html. Change-Id: I86e2c5d6d20e6002b87efc4688fc11b24b341227 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72623 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-02-01amdfwtool: Remove the duplicated entry RIBZheng Bao
It should be PSP_RIB_FILE which is already there. Change-Id: Ie7471489bd34554e357510b04473102d002f9988 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72506 Reviewed-by: ritul guru <ritul.bits@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-02-01mb/prodrive/atlas/data.vbt: Fix VBT lane countMaximilian Brune
Currently there is a problem, where two Displayports are not working. To be precise: TCP0 and TCP1 (Type-C Port 0/1) are not working. Setting the lane count of the TCP0 and TCP1 to x1 works fine. Setting the lane count of the TCP0 and TCP1 to x2 does not work. Setting the lane count of the TCP0 and TCP1 to x4 does not work. The reason for that is currently unknown. This change sets the lane count of the TCP0 and TCP1 Port to x1 length in the VBT binary. Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I182b528275152bf5adcb01a56816afd65674aed3 Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72610 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-01crossgcc: Upgrade LLVM version 15.0.6 to 15.0.7Elyes Haouas
Change-Id: I3198b065316b98f2d26360c4e65055e7460ea707 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71884 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-02-01mb/intel/mtlrvp: Modify the print messageHarsha B R
This patch updates the print message to start with uppercase, 'board' to 'Board'. BUG=b:224325352 BRANCH=None TEST=Able to observe proper print message when invalid board id is configured. Signed-off-by: Harsha B R <harsha.b.r@intel.com> Change-Id: Ie82df940cbd1eba9c5d485b48648c2bc8f234aae Reviewed-on: https://review.coreboot.org/c/coreboot/+/72638 Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Usha P <usha.p@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-01crossgcc: Upgrade CMake from version 3.25.0 to 3.25.2Elyes Haouas
Change-Id: Iaf0988997c6644e0e4f02d60a1d6de0e498e19bc Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71889 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-01Documentation/gerrit_guidelines: Fix newlinesNicholas Chin
Markdown does not render newlines unless there is an empty line in between the lines of text. Several command examples and a list were missing these empty lines, causing their content to be rendered inline with the preceding text. Fix this by adding triple backticks around code blocks and bullet points to rows of text in a list. Change-Id: I9c1d2b81acdeb378346c68bced0cdbfeeb81bf26 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72625 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-01treewide: Remove duplicated include <device/pci.h>Elyes Haouas
<device/pci.h> chain-includes <device/pci_def.h> & <device/pci_type.h>. Change-Id: I4e5999443e81ee1c4b1fd69942050b47f21f42f8 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72626 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-31soc/amd/glinda/acpi: use acpigen_write_processor_deviceFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iec9cf7c195fa5cb5c8d992aeab400d05cbe801c2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72494 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-01-31soc/amd/phoenix/acpi: use acpigen_write_processor_deviceFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I103cdce8c23ff4adbf1057fa26bd67275f2ab0e5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72493 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-01-31soc/amd/mendocino/acpi: use acpigen_write_processor_deviceFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I036dcddf89e8d865d0dc3ef0bd9e48842d8bf6c3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72492 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-01-31soc/amd/cezanne/acpi: use acpigen_write_processor_deviceFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I77a91c0a6d937772bf25fa936cec8a710b9acf72 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72491 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-01-31soc/amd/picasso/acpi: use acpigen_write_processor_deviceFelix Held
In CB:71614 Kyösti pointed out that ACPI_GPE0_BLK is the wrong address to assign to proc_blk_addr; the correct one would be ACPI_CPU_CONTROL. When looking a bit closer into this, it turned out that acpigen_write_processor is generating deprecated AML opcodes, so replace the acpigen_write_processor call with a call to the newly added acpigen_write_processor_device function that also doesn't have the proc_blk_addr and proc_blk_len parameters. The information about the IO port for entering C-states is already written into an SSDT by acpigen_write_CST_package which is likely also the reason why the wrong proc_blk_addr value wasn't noticed for a very long time. TEST=Mandolin still boots Ubuntu 22.04 LTS and Windows 10 and no possibly related errors show up. Linux gets the expected C-state information from the _CST package inside the processor device scope. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie67416e19e431029dd12da66ad44ddfa8586df03 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72490 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-01-31acpi/acpigen: introduce acpigen_write_processor_deviceFelix Held
The ACPI PROCESSOR_OP has been deprecated in ACPI 6.0 and dropped in ACPI 6.4 and is now permanently reserved. As a replacement, DEVICE_OP with the special HID ACPI0007 should be used instead. This special HID was introduced in version 3 of the ACPI spec. To have a function to generate this, acpigen_write_processor_device is introduced. The CPU index is used as UID which can be assumed to be unique. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ifb0da903a972be134bb3b9071f81b441f60917d1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72469 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-01-31mb/google/skyrim/var/winterhold: Update DPTC settings for SMTEricKY Cheng
Follow thermal team's request on b/248086651 comment#27. Update the thermal table setting for each mode and the conditions of temperature switching. BUG=b:248086651 TEST=emerge-skyrim coreboot Change-Id: Ida10d9b10c33dea11440879afda07c04c1eccb9f Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72006 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Jon Murphy <jpmurphy@google.com>
2023-01-31vendorcode: Add VariableFormat.hPatrick Rudolph
Add the EDK2 variable format header in order to access the SPI flash variable store. https://github.com/tianocore/edk2/blob/edk2-stable202005/MdeModulePkg/Include/Guid/VariableFormat.h Commit Hash: 9d510e61fceee7b92955ef9a3c20343752d8ce3f Change-Id: Ibe44925555a7d1d2361dd48c0325b840bd68e0ca Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61959 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-31soc/amd/common/block/include/acpi: drop MMIO_ACPI_CPU_CONTROL defineFelix Held
This register isn't used in coreboot and isn't defined in the Picasso PPR #55570 Rev 3.18. To enter a lower C-state, a read request to a special IO port is done. The base address of this group of IO ports is configured in set_cstate_io_addr via the MSR_CSTATE_ADDRESS and that read won't leave the CPU. IIRC trying to put the MMIO mapping for entering the lower C-states into the _CST package didn't work as expected when it was tried on I think Cezanne. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib189993879feaa0a22f6810c4bd5c1a0bc8c5a27 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72497 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-01-31soc/intel/ehl: Move ME FSR structures to pertinent headerDinesh Gehlot
This patch moves ME host firmware status register structures to ME header file. It also marks unused structure fields to reserved. The idea here is to decouple ME specification defined structures from the source file `.c` and keep those into header files so that in future those spec defined header can move into common code. The current and future SoC platform will be able to select the correct ME spec header based on the applicable config. It might be also beneficial if two different SoC platforms would like to use the same ME specification and not necessarily share the same SoC directory. BUG=b:260309647 Test=Able to build and boot. Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: I7dfd331e70f6d03c88248ca5147dbe6785a8e69d Reviewed-on: https://review.coreboot.org/c/coreboot/+/72413 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-01-31soc/intel/alderlake: Pick an unused and safer graphics address spaceJeremy Compostella
It turns out that the [0xfa000000-0xfaffffff] range conflicts with some North TraceHub address space ranges ([0xfad00000-0xfadfffff] and [0xfacfc000-0xfacfffff]). Experiments have established that this conflicting range results in an unpected PIPE A underrun issue reported by i915 and some visible flickers on the display during boot. The [0xf0000000-0xffffffff] range is a crowded memory space with resources statically assigned to some devices but also some ranges used at various point in the boot flow by the FSP. To not run into any other potential conflicts, we want to pick a unused memory space. But at this early stage of the boot, we do not have full knowledge of what memory space is going to be used by the FSP. As a result, we decided to pick the [0xaf000000-0xafffffff] range as: 1. It does not conflicting with any coreboot memory space usage 2. It is the address the FSP uses by default for GFX MMIO BAR0 and as such should not conflict with any FSP memory space usage. BUG=b:264648959 BRANCH=firmware-brya-14505.B TEST=No flickers observed on boot Change-Id: I6a00350ff4007bb7692d2ff6598b946cc6123302 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72605 Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-01-31console: Print architecturePatrick Rudolph
Useful to see which architecture x86_32 or x86_64 coreboot was built for. Change-Id: I34eec64ac32254c270dcbb97e20a7e6be0f478fc Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59761 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
2023-01-31soc/intel/apl: Ensure CPU_CLUSTER linked_list bus existsArthur Heymans
This fixes a NULL pointer deref introduced by 69cd729 (mb/*: Remove lapic from devicetree). Change-Id: I816fddfe3efe3c3aefe1b2ee28426dc1e1f3c962 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72599 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-01-31util/sconfig: Remove lapic devices from devicetree parsersArthur Heymans
This is all handled at runtime now, so there is no need to have the ability to statically add lapics to the devicetree. Change-Id: I0746eb808a2956ac75f76c8189a9ecf190e33ce9 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69378 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-31src/sbom: Add code documentation + fix misspellingMaximilian Brune
Functionality wise nothing changed, except that the first misspellings caused SBOM_BIOS_ACM_PATH and SBOM_SINIT_ACM_PATH to not work before. - Fix misspelling of CONFIG_BIOS_ACM_PATH -> CONFIG_SBOM_BIOS_ACM_PATH - Fix misspelling of CONFIG_SINIT_ACM_PATH -> CONFIG_SBOM_SINIT_ACM_PATH - Put SBOM_COMPILER_ handling into Kconfig instead of Makefile - Reorder CONFIG_ paths (for readablity) - Add in code comments (for readablity) Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: If67bc3bd0d330b9b5f083edc4d1697e92ace1ea0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72379 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-01-31soc/intel/common/block: Add LPC BIOS decode lockTim Chu
The LPC BIOS decode lock bit is defined in EBG EDS documentation. Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Change-Id: I60df7e6da2b22b8eeb2094aeb5ee9667043bb30b Reviewed-on: https://review.coreboot.org/c/coreboot/+/71954 Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-01-31crossgcc: Upgrade mpfr from 4.1.1 to 4.2.0Elyes Haouas
Changes: https://www.mpfr.org/mpfr-current/#changes Change-Id: Ife757d7a8247c11338ca795109044cdccdf86733 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-01-31crossgcc: Upgrade mpc from 1.2.1 to 1.3.1Elyes Haouas
Change-Id: I2d98c3b4c7edaf3ff097f5739c7cc0cd13592e91 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70530 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-01-31crossgcc/buildgcc: Add missing "\" at build_NASMElyes Haouas
"\" is missing at the end of CC line for build_NASM. Change-Id: Ic29ee731def31f958f939efe19bdb55b503eb6ba Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72512 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-01-31drivers/intel/fsp2_0: Simplify check for CONFIG_SAVE_MRC_AFTER_FSPSDavid Hendricks
This uses a simpler form of #if to check if CONFIG_SAVE_MRC_AFTER_FSPS is enabled, referencing the Kconfig variable only once and defaulting to the original behavior if not. Change-Id: I4711c1474d9a3a5c685dd31561619c568fab075c Signed-off-by: David Hendricks <david.hendricks@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72587 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-31mb/amd: Include <gpio.h> instead of <soc/gpio.h>Elyes Haouas
<gpio.h> chain-include <soc/gpio.h>. Change-Id: I48191064fcee53ca843a537aa36bdbbd57736bf2 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72588 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-01-31configs/config.facebook_fbg1701.sbom: Fix var namesMaximilian Brune
The variables defined in this defconfig are incorrectly named, therefore fix them. Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I9299be96f8c44d6a87d380f4f942c4d26af7050d Reviewed-on: https://review.coreboot.org/c/coreboot/+/72477 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-01-30src/mainboard: Remove unnecessary space after castsElyes Haouas
Change-Id: Id8e1a52279e6a606441eefe30e24bcd44e006aad Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69815 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
2023-01-30mb/siemens/mc_ehl3/gpio.c: Disable PSE GBE0 GPIOJan Samek
Since the PSE GBE0 MAC has been disabled on this board in commit 343644006f89 ("mb/siemens/mc_ehl3/devicetree.cb: Remove TSN GbE 0"), therefore disable the corresponding GPIOs as well. BUG=none TEST=Test link detection and IP assignment on the remaining ports (PSE GBE1 and PCH GBE0) of mc_ehl3. Change-Id: Ifa055f58894688471d68b9b93fcb994fdcb2a568 Signed-off-by: Jan Samek <jan.samek@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72449 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-30util/crossgcc/buildgcc: Remove extra "/" at the end of IASL_BASE_URLElyes Haouas
Change-Id: I8df1d93a8b0a0d562c7ae5a9f1a70f2eb26499c9 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71976 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-30mb/*: Remove lapic from devicetreeArthur Heymans
The parallel mp code picks up lapics at runtime, so remove it from all devicetrees that use this codebase. Change-Id: I5258a769c0f0ee4bbc4facc19737eed187b68c73 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69303 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-01-30payloads/external/LinuxBoot: Update u-root releases in Kconfigeliassouza
Building LinuxBoot with u-root newers releases can providing a better experience, Change-Id: Ie98f434c5296b7ba7c3750a766b244c747421baa Signed-off-by: eliassouza <eliascontato@protonmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72465 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-03 12:09:57 +0000