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We have constant CONFIG_CBB==0, replace ill dev_find_slot()
with safe pcidev_on_root();
Change-Id: Ieb2030fa3d77a9f49fc5faf12b92b5f00f49d354
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/26482
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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We have constant CONFIG_CBB==0, replace ill dev_find_slot()
with safe pcidev_on_root();
Change-Id: If536adf11aacef8faa3455692285552f97531df9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/26483
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add possibility to update microcode from BLOBs repo.
No need to copy headers around which have an unclear license.
Tested on wedge100s:
* Microcodes are included into FIT.
* Still boots to Linux.
* 3rdparty/blobs at dd00ad1260ef1dc0ba8c55c06ab10c7639dc3eb1
Change-Id: I8ecfb7302a7fc847a51934942f6d323a4f96abba
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/30324
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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Note that while these boards had entry 0x0ff0 in comparison
to 0x0ffc of the get_default_pci1234() initialisation, the
implementation of get_pci1234() unconditionally overrides
the first entry.
Change-Id: I8bec612f84fe3c3a0c21fc1e10629368857e9c5e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30649
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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All these boards use the same default initialiser.
As this is initialized late after device enumeration,
it can't really be used to alter platform configuration.
Change-Id: I30fc0298081df0442ec4e9a527340b93a3cd6106
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30648
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Only bus_sb700[0] is evaluated.
Change-Id: Ie2cbbdebed3ae03da916d02919cd6a5d36f53562
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30647
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Only bus_sb800[0] is evaluated.
Change-Id: I8ae0e6facbbe302b71692cf98a0292ee7d3bdca1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30646
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Only bus_sp5100[0] is evaluated.
Change-Id: I42a5040ea70a84fb674f2c616c6eba7b23dcdc29
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30645
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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It's expected that further analysis shows this to
always evaluate to 0.
Change-Id: I68599b961ca3b5e3652539c5d825a00444958d1b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30644
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: I301ed4024f1dd6fb2009d59b2992830d4f17ee2f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30639
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Values in the array are not used anywhere.
Change-Id: Iee92f903db97533709d54d1f214f2f23a1fab06b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30638
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Values in the array are not used anywhere.
Change-Id: I608b8c2e21bc515c56a27982815c1da43f3bb976
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30637
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: I8756a81324ba3d4374bb6b06f7f0ddade6ba530f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30636
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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It mirrors value of sysconf.sbdn.
Change-Id: I3ea42280a1bdceffebb6b5c85aee18347734ee4e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30635
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: I3b95ec5746077b49cd6dca64d0f884a3d1c362fb
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30634
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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It mirrors value of sysconf.sbdn.
Change-Id: I3cb611f1ea33da19e63523bc0fe99f2792eebc57
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30633
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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They evaluate to const zero and obscure PCI_DEVFN() use.
Change-Id: I8bd8dced62094d5ee8e957241ac29ead054f5c05
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30632
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: I7dc943f3376e9b706d3d486231525df85f806858
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30631
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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It has to be called once before PIRQ and MP table generation.
Change-Id: I238c6b4810404d320b36d4f6b4a161c1ff11c8d3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30630
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Also remove global ramstage-y += get_bus_conf.c, this is
specific to amdfam10.
Change-Id: I49b604ebff6bcfe85518b2c3896ab798c3c7878d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30629
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Value of the global is never evaluated.
Change-Id: I74106b0f5f033053288882a5bcd3c1dba3235ac0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30628
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: I68bb9c4301c846fe2270cd7c434f35a79ab25572
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30627
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: I819cfcda55995237a8431fdb3291274ab968cd3b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30626
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Copy-paste, boards do not set this.
Change-Id: I4c0795a483948b1e357388a5ad639c3f1950bbc8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30625
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Based on IT8786E-I V0.4.1 datasheet with following remark:
"Please note that the IT8786E-I V0.4.1 is
applicable only to the D version."
Signed-off-by: Kyösti Mälkki <kyosti.malkki@3mdeb.com>
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ibf6e290abb01ae1b6b28173a83e88d1d99663ad4
Reviewed-on: https://review.coreboot.org/c/30334
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Change-Id: Ib1057541dc0decd98921f3c84de3c08f10cd802e
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/30344
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Commit a5072af67d85 ("util/autoport: Use romstage.c instead of
early_southbridge.c") changed where the SPD map is. Reflect that.
Change-Id: Id0bd1778617371bac5921c4eae63d0beb088216c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30655
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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These few cases lacked a proper devfn parameter in the
form of PCI_DEVFN(dev, fn).
Change-Id: Iad0b214df12dee65360d07e887a960b0c73a3e4f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/26481
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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Semantics of dev_find_slot() are ill in the sense that
it only works after device enumeration has completed in
ramstage. Plan is to declare it as deprecated.
Introduce pcidev_on_root() and pcidev_path_on_root()
functions to replace cases where this was called with
static argument bus == 0. New implementation only walks
the root bus of the PCI tree, while old one walked
the entire linked list of devices.
Introduce pcidev_path_behind() to replace cases where
argument bus != 0. The required parent node is typically
one of the PCIe root functions that you locate using
pcidev_on_root() above.
New forms are safe to use with early devicetree and
before PCI bus numbers have been assigned.
Change-Id: Ie20598d48b4cf6e35e45fc90804bad4728437fc6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/26447
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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Definitions of these types are arch-agnostic. Shared device
subsystem files cannot include arch/pci_ops.h for ARM
and arch/io.h for x86.
Change-Id: I6a3deea676308e2dc703b5e06558b05235191044
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/29947
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Use of device_t is deprecated.
Change-Id: Ie05869901ac33d7089e21110f46c1241f7ee731f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/30047
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Use the `git-format' tool to sanitise coreboot commits such that
they conform to coreboot's coding style.
This fancy piece of machinary allows one to have LibFormat from
Clang to automatically check your commit conforms to coreboot's
coding style, fix any issues automatically and provides you a
diff you may review and apply at your convenience.
N.B. When the `clang-format' binary is not found we issue a warning
that the test was skipped and carry on as usual. Hence, this is
strictly non-enforcing at this current time. You may use it at your
leisure.
Change-Id: If49017ea82f0707efd47cae5978a286a9af8f3b7
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: https://review.coreboot.org/c/8037
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Update to latest version of iasl:
(From the acpica.org changelogs)
* Fixed a regression introduced in version 20180927 that could cause the
compiler to fault, especially with NamePaths containing one or more
carats (^). Such as: ^^_SB_PCI0
* Added a new remark for the Sleep() operator when the sleep time
operand is larger than one second. This is a very long time for the
ASL/BIOS code and may not be what was intended by the ASL writer.
* Implemented detection of extraneous/redundant uses of the Offset()
operator within a Field Unit list. A remark is now issued for these.
For example, the first two of the Offset() operators below are
extraneous. Because both the compiler and the interpreter track the
offsets automatically, these Offsets simply refer to the current
offset and are unnecessary. Note, when optimization is enabled, the
iASL compiler will in fact remove the redundant Offset operators and
will not emit any AML code for them.
Change-Id: I46a1b1be44328aa2172f4741e9fd0c9b0f4e0430
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/28944
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Update toolchain to the following software versions:
o Python 3.5.1 -> 3.7.0
o LLVM 6.0.0 -> 7.0.0
o Expat 2.2.1 -> 2.2.5
o MPC 1.0.3 -> 1.1.0
o MPFR 3.1.5 -> 4.0.1
Change-Id: I66c6138c7b65c73a89b3cf980bb08950d8fffe6a
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/28887
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This was already disabled and mostly incompatible
with romstage having stack in CAR.
Change-Id: I1fe02bef668a5bc8ce3d5a1d8090670752b10c3e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30621
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Enable acoustic noise mitgation for sarien platform, the slow slew rates
are fast time dived by 8.
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I5d38a1e03af08f106e2422a319b34c3fb54bdf28
Reviewed-on: https://review.coreboot.org/c/30448
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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The result is that i82801{g,i,j}x now use the correct _PRT table for
their root port number.
Change-Id: I92bba3c669f3e6a44a42e19a88a33dfcfc2b9b42
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30528
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
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Change-Id: I45144f9c397ff9a0be011990ba33db9ffef351e7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30527
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
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Sync'ing the sku_ids list in the master sku sheet for Pantheon.
BUG=b:121207221
BRANCH=firmware-nami-10775.B
TEST=emerge-nami coreboot chromeos-bootimage
Change-Id: Ic03c3a6fe238f2692ce15c45016115087380c0ca
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/30412
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
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Add DRAM support for google kukui.
BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Kukui
Change-Id: I1ed01404343745c883b22a648966327bdcabc5c2
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/28438
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
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Write a range of memory with special pattern, and read it back to check
whether the read value same as write.
The test pattern include 8bit offset read write, 16 bit offset read
write, 32bit offset read write, and cross testing.
BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Kukui, and inits DRAM successfully with related
patches.
Change-Id: I30d5fbd3db2acf36e3058ba4f34558b981fba78c
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/28845
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: You-Cheng Syu <youcheng@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Kukui, and inits DRAM successfully with related
patches.
Change-Id: Id1e8862ff6feb9628d37fe5300780ff56865a563
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/28844
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
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BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Kukui, and inits DRAM successfully with related
patches.
Change-Id: Ia20de54633bf1077bd469df75ccb4390308e0b97
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/28843
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: You-Cheng Syu <youcheng@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Use already defined ARRAY_SIZE macro.
Change-Id: Ie22e3557e958b562816921a985411dd55c712142
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/29860
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: I1e0009677fda44faab2021e1c44827fdba803061
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/30612
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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PCIe graphics for display output still doesn't work, but that is now
listed in the Haswell-specific documentation.
Change-Id: I28c50db353b2b965eb847b379d9e1944cb720c77
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/c/30273
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Change-Id: If0339831550f6c70e8056f78633e9a402f35a793
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/c/30455
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch is from Linux, commit 3856081eede2. The commit message there
is:
> commit 3856081eede297b617560b85e948cfb00bb395ec
> Author: Y.C. Chen <yc_chen@aspeedtech.com>
> Date: Thu Feb 23 15:52:33 2017 +0800
>
> drm/ast: Fix AST2400 POST failure without BMC FW or VBIOS
>
> The current POST code for the AST2300/2400 family doesn't work properly
> if the chip hasn't been initialized previously by either the BMC own FW
> or the VBIOS. This fixes it.
>
> Signed-off-by: Y.C. Chen <yc_chen@aspeedtech.com>
> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> Tested-by: Y.C. Chen <yc_chen@aspeedtech.com>
> Acked-by: Joel Stanley <joel@jms.id.au>
> Cc: <stable@vger.kernel.org>
> Signed-off-by: Dave Airlie <airlied@redhat.com>
Tested on a Supermicro X10SLM+-F with an AST 2400 where the BMC flash
chip has been completely erased. Before the patch, the display resembled
a rainbow. After the patch, the display works well.
Original-Signed-off-by: Y.C. Chen <yc_chen@aspeedtech.com>
Original-Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Original-Tested-by: Y.C. Chen <yc_chen@aspeedtech.com>
Original-Signed-off-by: Dave Airlie <airlied@redhat.com>
Change-Id: I72efcf907fbd1263fe21d4f36fe900b305419c44
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/c/30507
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Follow instrcution from https://doc.coreboot.org/acpi/gpio.html to
implement GPIO toggling method, covered for both CNP_LP and CNP_H pch.
BUG=N/A
TEST=Build and boot up fine on sarien platform, add an dummy STSX in
DSDT table, read back from iotools to confirm the GPIO tx state get
updated.
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I006a6a8fc580c73ac0938968397a628a4ffe504f
Reviewed-on: https://review.coreboot.org/c/30461
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This means that any PCIe device placed in a PEG slot should now work.
During S3 resume, link training sometimes does not complete before
device enumeration. However, no tangible issues have been observed.
Fixing it would introduce a rather large delay in S3 resume.
There are a few minor shortcomings:
- Using PEG for display output is not yet supported.
- Only PEG2 is supported. An extra (unknown) training sequence is said to
be needed for PEG3.
- The ACPI _PRT method is not yet generated, so legacy interrupt routing
doesn't work for devices with multiple functions.
Tested on an ASRock H81M-HDS. Using a Radeon HD 6450 graphics card works
under GNU/Linux, with PRIME [1]. An x1 PCIe card was also tested in the
PEG slot, and it appears functional.
[1]: https://wiki.archlinux.org/index.php/PRIME
Change-Id: I786ecb6eccad8de89778af7e736ed664323e220e
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/c/30272
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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If PCIe root port `n` is disabled, then `rpc.ports[n - 1]` remains NULL.
The existing Lynx Point systems probably don't end up dereferencing
NULL pointers this way. However, it might occur on a system using
Flexible I/O to remap PCIe root ports to other functions.
Tested on an ASRock H81M-HDS and an Acer C720 (Google Peppy). No issues
presented themselves.
Change-Id: I2c22fa36217766c2c4d6e8046f99989063066b16
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/c/30079
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Using a linked C file is the standard approach for GPIO settings.
Change-Id: I6a5ca65bc1553bd382589d67379eafd03dc0b0a3
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/c/30503
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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The existing SATA ACPI code for Lynx Point implements some methods and
devices, but not completely. These methods are optional and only used in
IDE mode. The code was likely copied from bd82x6x, where it has since
been removed.
As a result, many remarks produced by iasl about unreferenced objects
are eliminated.
Tested on an ASRock H81M-HDS and an Acer C720. No issues with SATA
were observed.
Change-Id: I808a9dff7b9ba34239ffd95fa4cb9b39b10c4b62
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/c/30149
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This either sets unwanted or unnecessary settings.
Tested. Everything still works fine.
Change-Id: I0f552dea1b37cdc17c9dd26a0294b59063cdc2be
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30402
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Use smm-$(CONFIG_HAVE_SMI_HANDLER) instead of smm-y
Change-Id: I0f91bc3e6c8ab31d837ab89af62d700b35c1e01b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/30485
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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HAVE_SMI_HANDLER already selected in broadwell/Kconfig file.
Change-Id: Ic40b5296eae78cd83c59212042d94424251524b1
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/30484
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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HAVE_SMI_HANDLER already selected in skylake/Kconfig file.
Change-Id: I754cf41a4f97d1e692ad4209e4a59987dce2624b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/30483
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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HAVE_SMI_HANDLER is selected here: broadwell/Kconfig
Change-Id: I50c664198a954f661416c8cb1ced05f8775d8e07
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/30478
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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HAVE_SMI_HANDLER is already selected here: bd82x6x/Kconfig
Change-Id: I920800bb7c67cb5efd5dac0a9338a76214de2cab
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/30477
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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HAVE_SMI_HANDLER is already selected in soc/intel/skylake/Kconfig
Use "smm-$(CONFIG_HAVE_SMI_HANDLER)" in Makefile.inc files.
Change-Id: Ia60e34ee03958b05f2ac0c326632b6dd9f02a2e0
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/30476
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Change-Id: I4f9d0cfc9a5bfa259d734f194b015e7be1694ceb
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30472
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
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Change-Id: I9f979e63378b1e0090a57849038eaafeb20d7a40
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30471
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
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The existing code has several messages that are only printed when the
DEBUG variable is set. These messages are not verbose, and are quite
useful to see how the script is progressing. So, print them
unconditionally.
Change-Id: I8f78e4563f0b4a42f831194a6e526284c2fbcd92
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/c/30550
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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crosfirmware.sh has dependencies that might not be installed on some
systems. If a dependency is missing, provide a clear message about the
issue and how to resolve it.
Change-Id: I265bd03666f1273d3c22b60aae860c48c758005b
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/c/30549
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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It's quite useful to know the download progress, as it can take a while
even with a fast connection. For example, the peppy recovery image is
~600 MiB. It also lets the user know that disk space is being filled.
Change-Id: I8c175f9095478ffe33c95b7ef9907c25b5f10f8c
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/c/30548
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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On some systems, such as Debian 9.6, `parted` and `debugfs` are located
in /sbin. Adding /sbin to PATH means that this script can work when run
as a regular user.
Change-Id: I151dba467e2b196f13093334273dae8a05865491
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/c/30547
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: Ic099d0f052db5ef6a699d54b26028bae2fae4770
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/c/30546
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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ENABLE_VMX is CPU specific and it is already enabled here:
src/cpu/intel/common/Kconfig
Change-Id: I130738aa3758a9212bab10f90edb7b2ab6830597
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/30605
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Cases of *dev = PCI_DEV(b,d,f) are invalid. Not caught
because files only build with __SIMPLE_DEVICE__ defined.
Remove cases of testing __SIMPLE_DEVICE__ in files that
are not build for ramstage.
Change-Id: If10a0efa187c9b1d9a5577008aa46f050f0aa309
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30497
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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This patch ensures to make memory protected range between
01C00000h - 01FFFFFFh as per winbond spi datasheet
https://www.winbond.com/resource-files/w25q256jv%20spi%20revb%2009202016.pdf
section 7.1.15
BUG=none
BRANCH=none
TEST=build for hatch.
Change-Id: I52d8dbba14bd060b48a7fe8ee009219413ef89ca
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/30552
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch ensures to make memory protected range between
01C00000h - 01FFFFFFh as per winbond spi datasheet
https://www.winbond.com/resource-files/w25q256jv%20spi%20revb%2009202016.pdf
section 7.1.15
BUG=none
BRANCH=none
TEST=build and boot dragonegg.
Change-Id: Ife451233f60ef680088babbc824bfc5a17078cb9
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/30551
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: If981fa3db12b3a4fe1411f4cce9bac8564697769
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/25466
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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Add reset delay in power resource to prevent from failing to bind after
unbinding. And boards including yorp series - bobba / phaser and bip series
- ampton are affected.
BUG=b:121286833
BUG=b:117474421
BUG=b:121019320
BRANCH=None
TEST=emerge-octopus coreboot,
verified that WACOM touchscreen can re-bind successfully.
Change-Id: Icf690fc8e9450d559b642d1c88e29ff5d52c5488
Signed-off-by: Marco Chen <marcochen@chromium.org>
Reviewed-on: https://review.coreboot.org/c/30422
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Set PchCnvimode to Auto if CNVi is enabled in device tree. This will
allow FSP to configure CNVi.
Change-Id: I4f77fe5e9f561d3b498403e42dfc7afdcfaedf6f
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/30516
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch enables CNVi wifi for hatch
1. Enable CNVi device in device tree
2. Configure GPIO pad config for CNVi
BUG=b:120914069
BRANCH=none
TEST=check if code compiles correctly and verify GPIO configuration with
schematics
Change-Id: I0c5542737d3a629b6a40116b4aa8ab6cbdd6a4dc
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/30436
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Correcting order of display related GPIOs and also adding not connected
pin definitions for display GPIOs
BUG=b:120914069
BRANCH=none
TEST=check if code compiles with changes.
Change-Id: I9498284d263516f65513d6395883b6b09dd70fd5
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/30544
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
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Add code to update microcode from cbfsfiles using assembly.
Change-Id: I8bd192f3f345651db0010239f99293ae63b00652
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/27091
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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This patch enables the x4 NVME device for hatch,
* Enable the Root port 9.
* Assign the usage type for clock source.
* Configure the GPIO for CLK SRC 1.
BUG=b:120914069
BRANCH=none
TEST=USE="-intel_mrc -bmpblk" emerge-hatch coreboot.
Change-Id: I69be6b21a5ae5962877a5c38180b5ffac532fed4
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/30431
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch adds the configurations for,
* USB 2.0 ports.
* USB 3.0 ports.
* Enables USB xHCI controller.
* GPIO config for USB2_OC2 and USB2_OC3.
* Add the ACPI objects to configure USB ports.
BUG=b:120914069
BRANCH=none
TEST=USE="-intel_mrc -bmpblk" emerge-hatch coreboot.
Change-Id: Ia7b25c25b8208c678aeae3a32033611b69b54062
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/30457
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch enables the SATA for hatch,
* Enable the SATA port 1.
* Configure the GPIO for SATA.
BUG=b:120914069
BRANCH=none
TEST=USE="-intel_mrc -bmpblk" emerge-hatch coreboot.
Change-Id: Iaf800d1531688c3d3b82600038ea1d7160ae4b0b
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/30435
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Macro hides that dev_find_slot() takes two arguments.
Change-Id: I639af31b9d4a2d702dfd2baebddbb8352e8bf9b9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30498
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
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The feature is used to enable PCI MMIO accesses behind
PCIe links (or bridges) before PCI enumeration has been
completed.
Add the feature for bootblock, verstage and postcar, it
is required with add-on PCIe serial cards for early
console output. It's up to the board specific code to
configure PCIe root port prior to calling console_init()
for this to work.
Remove feature from ramstage, it bypasses any resource
allocations and bus number assignments.
For the moment PCI configuration support before ramstage
is available only on ARCH_X86.
Also switch from device_t to pci_devfn_t.
Change-Id: I08acec68b6f17f4d73d30039cc41274492ea4f45
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30496
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Fix build for POSTCAR_STAGE=y.
Also add driver for bootblock and verstage.
Change-Id: If57033353c07854e21b630c58ad69931eb572da9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30495
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
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Add symbols for the non C_ENVIRONMENT_BOOTBLOCK builds
and use them for stack guards.
Change-Id: Ib622eacb161d9a110d35a7d6979d1b601503b6f4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30491
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
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The same file was replicated three times for certain
soc/intel bootblocks, yet there are no indications or need to do
chipset-specific initialisation.
There is no harm in storing the TSC values in MMX registers
even when they would not be used.
Change-Id: Iec6fa0889f5887effca1d99ef830d383fb733648
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30393
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Platforms with SSE=y or SSE2=y will invoke romcc with -mcpu=k7.
This implicitly enabled romcc to consume MMX registers, if XMM
set was consumed first.
Explicitly tell romcc not to clobber MMX set.
Change-Id: I37f1d6ea01873036712dfbb32bb1dcd5d769e85d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30392
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
Platforms have moved to POSTCAR_STAGE=y.
Change-Id: I79c87e546805dbe0a4c28ed95f4d12666734eb79
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30489
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Change-Id: I01ecb9a16099ac6189ce3f0bdbd43c23ad7c621d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30488
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This board runs well with coreboot. The documentation part of this
commit lists what works and what doesn't.
Tested with GRUB 2.02 as a payload, loading SeaBIOS 1.12.0 which then
boots FreeBSD 11.2. It has also been tested with GRUB directly booting
Debian GNU/Linux 9.6 (kernel 4.9).
Change-Id: I291573d4651bdffe24eb841033ea6189fcbf8502
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/c/30357
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: I7fdf8934187d2786fdac23ed4460147867c25044
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/30460
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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New emmc DLL values for Fleex.
BUG=b:120561055
TEST=Boot to OS, chromeos-install, mmc_test
Change-Id: Id0022e9d0f0a7802113bbf193decff3c8aaa04f8
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/30226
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The function pch_log_state() was overlooked when making the smi
relocation code common.
Change-Id: I878772f1a93105b828e50f37e105d04988ba0bdf
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30426
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Change-Id: I9090be3ccaa8a61312293e9da3679a752a908062
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30403
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Processor graphics is disabled on, for example, the C222 and C224
chipsets.
The change to resource assignment in northbridge.c prevents the following
warning that occurs when the IGD is disabled:
> skipping PCI: 00:00.0@3 fixed resource, size=0!
Tested on a Supermicro X10SLM+-F, which has the IGD disabled by the
chipset. The graphics memory is reclaimed and no issues were observed.
Also tested on an ASRock H81M-HDS. This board has an IGD, but no
regressions were observed.
Change-Id: I86d4aef50b6588f08b86c9758a4b95ccd65e9a96
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/c/30271
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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The existing code sets DEVEN with the intention of enabling the IGD and
Mini-HD audio. However, according to the datasheet [1] and some testing
on hardware, the bits in DEVEN are set by default if and only if the
straps/fuses say the device should be enabled. To illustrate this, here
are a few initial values of DEVEN on some Haswell systems:
Supermicro X10SLM+-F: 0x0000002d
ASRock H81M-HDS: 0x00000039
Acer C720: 0x000000b1
On the X10SLM+-F, the IGD is disabled by default, and PEG10 & PEG11
are enabled by default. On the C720, the PEG devices are all disabled
by default, while the IGD and Mini-HD audio are already enabled.
There are two issues that result from the existing behaviour: PEG
devices are unconditionally disabled, and devices are set as enabled
when it's not actually possible to enable them.
So, don't touch the DEVEN register at this stage, as there are no
benefits.
Interestingly, on an Acer C720 (Google Peppy), a PCI device 00:04.0
appears. It is a thermal sensor. `powerstat` was used to measure idle
power usage over 30 minutes under Debian GNU/Linux 9.6. There was no
change in reported power draw.
[1] Desktop 4th Generation Intel® Core TM Processor Family, Desktop
Intel® Pentium® Processor Family, and Desktop Intel® Celeron®
Processor Family Datasheet – Volume 2 of 2.
December 2013, revision 003, document number 328898.
Change-Id: I242f9138472de5a0b26b5852f632b53b2920132d
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/c/30269
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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This allows devices to be properly disabled when they are set to `off`
in the devicetree, or when a device has its `enabled` property set to
false.
A message is printed stating that a device is being disabled, even if
it was already disabled via DEVEN. However, it could be useful to have
this information, so such messages are kept.
The device 00:04.0 is a thermal sensor on the Acer C720, but it has not
been named as such in this patch. This is because the public datasheets
never formally acknowledge what the device is, and how it might differ
across platforms.
Tested on a Supermicro X10SLM+-F. The Mini-HD audio is disabled now,
silencing a warning from Linux.
Also tested on an Acer C720 (Google Peppy). Disabling "device 4" from
devicetree.cb works.
Also tested on an ASRock H81M-HDS. For this device, and all other test
devices, there were no regressions observed.
Change-Id: If1504e620967449a09f113a7c771a1ec30380644
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/c/30270
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Internal pull up need to be enabled for GPD3 as power button pin for
PCH according cannonlake pch EDS vol1 table 17-1. Without that pin will
stay floating and hook up XDP can cause system shutdown as power buttone
event will trigger.
BUG=N/A
TEST=Hook up XDP on sarien platform, able to boot up into OS and stay
at power up state.
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: Ibe21da5f4a0797a3d62b36899f023908b46c25bf
Reviewed-on: https://review.coreboot.org/c/30374
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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* Enable host bridge.
* Enable CSME.
* Enable Power Management Controller.
* Enable Primary to Side Band Bridge Controller.
* Enable SmBus Controller.
BUG=b:120914069
BRANCH=None
TEST=code compiles with the changes
Change-Id: I2fbf0ece845a7114ce5ab7f6482a935d9275deee
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/c/30465
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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On some platforms SVI command completion is not reported by
voltage regulator. Because of that CPU got stuck in invalid
P-State, which resulted in lower frequency and inability to
reboot platform without performing cold reset.
Change-Id: I260c997f3a0f4547041785a3b9de78e34d22812a
Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/30367
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Piotr Król <piotr.krol@3mdeb.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: I9878e6d962004003e2c05a6cdb8ecb0a3a02ae66
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/30352
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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