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Change-Id: I972516443bc57e193aefd54516ca994087d92054
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82844
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
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This patch flips the polarity of CONFIG_USE_1G_PAGES_TLB into
CONFIG_NEED_SMALL_2MB_PAGE_TABLES which is off by default, meaning
CPUs added in the future will automatically build the smaller 1GB pages.
We can expect support for this feature to be available on all future CPU
generations (with the possible exception of embedded edge cases), so
this default setting should make mistakes less likely and keep
maintenance effort lower. (Besides, enabling the support where it
doesn't work fails fast, whereas keeping it disabled where it could work
is an inefficiency that can easily go overlooked for a long time.)
While this is technically a CPU feature, not a northbridge feature, we
support a lot more individual CPUs than northbridges in the pre-SoC era,
and they tend to be closely coupled anyway. So select the option at the
northbridge level for older CPUs to keep things simpler.
Change-Id: I2cf1237a7fb63b8904c2a3d57fead162c66bacde
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82792
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Change-Id: Ib95cb55add23fa172f187cbcb475958767f8a923
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82905
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Based on lotso EVT schematics update gpio settings.
BUG=b:333494257
TEST=emerge-brox coreboot chromeos-bootimage and boot on
Change-Id: I13485cc7ccd8b15352f5e21ad9336aa2b3d35749
Signed-off-by: Jian Tong <tongjian@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82573
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Shelley Chen <shchen@google.com>
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Updating from commit id 41af345:
2024-03-11 19:11:14 -0600 - (microcode-20240312 Release)
to commit id 5278dfc:
2024-05-31 18:42:47 -0600 - (microcode-20240531 Release)
This brings in 2 new commits:
5278dfc microcode-20240531 Release
27ace91 microcode-20240514 Release
Change-Id: Ia34ba03a9c2f206be760133edbbadcc541ff273b
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82789
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
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ARM SoC supports FEAT_CCIDX after ARMv8.3. The register field
description of CCSIDR_EL1 is different when FEAT_CCIDX is implemented.
If numsets and associativity from CCSIDR_EL1 are not correct, the system
would hang during mmu_disable().
Rather than assuming that FEAT_CCIDX is not implemented, this patch
adds a check to dcache_apply_all to use the right register format.
Reference:
- https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/12770
BUG=b:317015456
TEST=mmu_disable works on the FEAT_CCIDX supported SoC.
Change-Id: I892009890f6ae889e87c877ffffd76a33d1dc789
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82636
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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ARM SoC supports FEAT_CCIDX after ARMv8.3. The register field
description of CCSIDR_EL1 is different when FEAT_CCIDX is implemented.
If numsets and associativity from CCSIDR_EL1 are not correct, the system
would hang during mmu_disable().
Rather than assuming that FEAT_CCIDX is not implemented, this patch
adds a check to dcache_apply_all to use the right register format.
Reference:
- https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/12770
BUG=b:317015456
TEST=mmu_disable works on the FEAT_CCIDX supported SoC.
TEST=manually add mmu_disable to emulation/qemu-aarch64/bootblock.c and
verify with the command
qemu-system-aarch64 -bios \
./coreboot-builds/EMULATION_QEMU_AARCH64/coreboot.rom -M \
virt,secure=on,virtualization=on -cpu max -cpu cortex-a710 \
-nographic -m 8192M
Change-Id: Ieadd0d9dfb8911039b3d36c9419af4ae04ed814c
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82635
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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Based on schematic, update slot number for PCIe port used for NIC
controller.
Change-Id: I7a1ead8f7e4588db45303041e60dbfe27ee12ea7
Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82899
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
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There's two copies of the `get_cxl_mode()` function to map the OCP VPD
value to the values expected by platform code. As this is unnecessary,
have a single copy of this function in the OCP VPD driver code. As the
`get_cxl_mode()` function is Xeon-SP only, keep it in a separate file.
This change simplifies things for boards using OCP VPD for CXL and has
no impact for boards *not* using OCP VPD:
- Boards not using OCP VPD can still define get_cxl_mode() in mainboard
code as needed, just like they were able to do before.
- Boards using OCP VPD but without CXL (`SOC_INTEL_HAS_CXL` is not
enabled), this code won't get compiled in at all (see `Makefile.mk`).
- Boards using OCP VPD and CXL will automatically make use of this
`get_cxl_mode()` definition, which should be the same for all boards.
It is possible that this may need to be expanded/adapted in the future,
which is easy to handle in a follow-up commit when the need arises.
TEST=Build and boot on intel/archercity CRB
Change-Id: I935c4eb5b2392e2d0dc01b9f66d46c79b8141ea7
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82224
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
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POSTCAR_STAGE is already selected in XEON_SP_COMMON_BASE
Change-Id: I3f94e6cc76c8f376119ffa8ec43fa1a43fb40977
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82795
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
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Set GSC_SOC_INT_ODL to GPP_A17 instead of GPP_A13.
BUG=b:333486830
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot
Change-Id: I065fdf2a66036c6df1e16dda3b2a684b5202cccc
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82717
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ib8f7ac7e586390a1d25cbe84d6d4c3ba31ff078f
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82843
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
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Change-Id: I950b8859b51fb61edc0cf1115f6665378bc0b836
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82887
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I50e874790dedcb6bf3b3ac8368821f22611aa3b7
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82894
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Just follow the examples of other payloads and simply remove the build
directory of said payload.
Change-Id: Idf2a8f3b9ecbb300514d2d1deede76785fd402b7
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82897
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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Set LpDdrDqDqsReTraining to 1 for xol. Value 0 will cause black screen
issue.
Reference: https://review.coreboot.org/c/coreboot/+/79527
> FSP default value for LpDdrDqDqsReTraining is 1. For boards
> that didn't set LpDdrDqDqsReTraining to any value, 0 was being
> assigned and it caused black screen issue.
BUG=b:332980211
BRANCH=brya
TEST=Built and verified there is no black screen issue during power
on/off test for over 100 cycles.
Change-Id: Ia346ce559b4509ea1a63abe28b12ad909f9b7b0d
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82778
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Due to system spec change, change audio codec ALC5650 to ALC5682I-VS
BUG=b:329787697
TEST= USE="-project_all project_bujia" emerge-brask coreboot
Change-Id: I38e5c58b3ef3fbe709b98601975ae3821bb77213
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
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Update generated FSP headers for Alder Lake N from v5021.00
Changes include:
- Add FspProducerDataHeader.h header file
- Open Usb4CmMode & CnviWifiCore Upd in FspsUpd.h
- Update UPD Offset in FspsUpd.h
BUG=b:296433836
TEST=Able to build and boot google/nivviks
Change-Id: Ieb4cc8f2f83d8f6e821894f0ec2e56262a25743c
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82780
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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This reverts commit 79503ef515967ffceab7bd2a16a381e6a02c3d30.
The Intel FSP repository at https://github.com/intel/FSP.git currently
lacks the Client ADL-N headers. The existing coreboot code references
the "IoT/AlderLakeN/" directory for these headers, but it is missing the
crucial FspProducerDataHeader.h file. Without this header, the ADL-N
platform is unable to utilize the appropriate MRC version needed for
updating MRC caches. This patch aims to restore the necessary FSP
headers for the ADL-N platform within the vendorcode directory.
Change-Id: I99e9d5a07b4ca8d1666e3fd50d3d363ed5d4618e
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82779
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Wflex-array-member-not-at-end & Wcalloc-transposed-args are
not supported when using GCC older than GCC-14.
Use them only when supported.
Change-Id: I11c1e729569c8130bd254a10454c5066a72974d6
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82785
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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This adds another external payload to coreboot. The payload has been
heavily based on u-boots UEFI implementation.
The leanefi payload is basically a translator from coreboot to UEFI. It
takes the coreboot tables and transforms them into UEFI interfaces.
Although it can potentially load any efi application that can
handle the minimized interface that leanefi provides, it has only
been tested with LinuxBoot (v6.3.5) as a payload. It has been optimized
to support only those interfaces that Linux requires to start.
Among other leanefi does not support:
- efi capsule update (also efi system resource table)
- efi variables
- efi text input protocol (it can only output)
- most boot services. mostly memory services are left (e.g. alloc/free)
- all runtime services (although there is still a very small runtime
footprint that is planned to be removed in the near future)
- TCG2/TPM (although that is mostly because of laziness)
The README.md currently provides more details on why.
The payload currently only supports arm64 and has only been tested
on emulation/simulator targets. The original motivation was to get ACPI
on arm64 published to the OS without using EDK2. It is however also
possible to supply the leanefi with a FDT that is published to the OS.
At that point one would however probably use coreboot only instead of
this shim layer on top. It would be way nicer to have Linux support
something else than UEFI to propagate the ACPI tables, but it requires
to get the Linux maintainer/community on board. So for now this shim
layer ciruimvents that.
LBBR Test:
// 1. dump FDT from QEMU like mentioned in aarch64 coreboot doc
// 2. compile u-root however you like (aarch64)
// 3. compile Linux (embed u-root initramfs via Kconfig)
// 4. copy Linux kernel to payloads/leanefi/Image
// 5. copy following coreboot defconfig to configs/defconfig:
CONFIG_BOARD_EMULATION_QEMU_AARCH64=y
CONFIG_PAYLOAD_NONE=n
CONFIG_PAYLOAD_LEANEFI=y
CONFIG_LEANEFI_PAYLOAD=y
CONFIG_LEANEFI_PAYLOAD_PATH="[path-to-linux]/arch/arm64/boot/Image"
CONFIG_LEANEFI_FDT=y
CONFIG_LEANEFI_FDT_PATH="[path-to-dumped-DTB]"
// 6. compile coreboot
make defconfig
make -j$(nproc)
// 7. run qemu like mentioned in coreboot doc (no FIT)
// 8. say hello to u-root and optionally kexec into the next kernel
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I4093378e89c3cb43fb0846666de80a7da36b03f1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78913
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ron Minnich <rminnich@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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Change-Id: I5e67e370d4eb8fe28227843bbca34db06ad84b26
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82786
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This reverts commit f4acef92.
Reason for revert: '-Wflex-array-member-not-at-end' is new command
option came with GCC-14. older versions will not support it.
Change-Id: I179d0bc0db3e863645ae4c87e1534c5c20025dfb
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82758
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The Razer Blade Stealth Kaby Lake has 2 variants. One is the H2U
variant, as originally committed, with the SKU number RZ09-01962, also
known as the 2016 model, and the H3Q model with SKU numbers RZ09-01963
and RZ09-01964, known as the Mid 2017 model. This commit adds support
for the H3Q model. With respect to coreboot, there are few known
differences:
1. Only the H2U has TPM.
2. The USB ports are different.
3. The screen size (and therefore VBIOS Table) is different.
4. The hda_verb is very slightly different.
5. The gpio is different.
Change-Id: I493a651e52c2eb938daa67a05e9caaa784020fa4
Signed-off-by: Reagan Bohan <xbjfk.github@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82506
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Apply commit c6b65c1a811e ("soc/intel/alderlake: Enable USB2 port reset
message on Type-C ports") to Meteor Lake.
This change is added to address the issue of USB3 ports downgrading to
high speed during low power modes and not returning back to super speed.
The patch enables port reset event on USB2 ports. This event is
is passed to USB3 upstream ports to upgrade back to super speed (USB3)
after a downgrade during low power state.
Change-Id: Iac702a8d8edd2b3b7e03abcac020be7e45335821
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82730
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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linux_trampoline.c generation is broken with latest crossgcc-i386
toolchain. Fix the issue to enable the building.
../cbfstool/linux_trampoline.S: Assembler messages:
../cbfstool/linux_trampoline.S:100: Error: no instruction mnemonic
suffix given and no register operands; can't size
instruction
<builtin>: recipe for target '../cbfstool/linux_trampoline.o'
failed
TEST=Build and boot on intel/archercity CRB
cd util/cbfstool/
rm linux_trampoline.c
make linux_trampoline.c
Change-Id: I7faca296f946bb4e9fd510661357925e5dcf9a6b
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82704
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: I1ed280c1e62e0f094fd40d2165892240f76de390
Fixes: 29f1b791270b ("mb/system76/rpl: Add Adder WS 4 as a variant")
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82725
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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Ensure per-board smart amp init is configured. Fixes speaker output on
oryp12.
Change-Id: I40ff1889dd144bf83ef85979a55535493aa7abdd
Fixes: 8b9716e2269d ("mb/system76/rpl: Add Oryx Pro 12 as a variant")
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82726
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
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Change-Id: I55f2730f7277a3c699b86ded5864e9690d92d518
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82700
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The comment that the PchHdaAudioLink UPDs only configure GPIOs is
incorrect. Setting this to 1 is needed to enable HDA audio link.
Same exact situation as with Alder Lake in CL 71715.
Change-Id: Iecbe106ae18b5a8b53c04a5335a4e4c4ae27c7a0
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82685
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
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Initial commit is a copy of ec/system76/ec from tag v24.02.1 (commit
0a280ff7) with string changes. Dasharo-specific features will be added
in subsequent commits, similar to how Librem EC support was added in
changes 52390 and 52391.
Change-Id: Ic7c3d9413488026548514963eb78accc28e41e06
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82671
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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coreboot needs to figure out top of memory to place CBMEM data. On some
non-x86 QEMU virtual machines, this is achieved by probing the RAM space
to find where the VM starts discarding data since it's not backed by
actual RAM. This behaviour seems to have changed on the QEMU side since
then, VMs using the "virt" model have started raising exceptions/errors
instead of silently discarding data (likely [1] for example) which has
previously broken coreboot on these emulation boards.
The qemu-aarch64 and qemu-riscv mainboards are intended for the "virt"
models and had this issue, which were mostly fixed by using exception
handlers in the RAM detection process [2][3]. But on 32-bit RISC-V we
fail to initialize CBMEM if we have 2048 MiB or more of RAM, and on
64-bit RISC-V we had to limit probing to 16383 MiB because it can run
into MMIO regions otherwise.
The qemu-armv7 mainboard code is intended for the "vexpress-a9" model VM
which doesn't appear to suffer from this issue. Still, the issue can be
observed on the ARMv7 "virt" model via a port based on qemu-aarch64.
QEMU docs for ARM and RISC-V "virt" models [4][5] recommend reading the
device tree blob it provides for device information (incl. RAM size).
Implement functions that parse the device tree blob to find described
memory regions and calculate the top of memory in order to use it in
mainboard code as an alternative to probing RAM space. ARM64 code
initializes CBMEM in romstage where malloc isn't available, so take care
to do parsing without unflattening the blob and make the code available
in romstage as well.
[1] https://lore.kernel.org/qemu-devel/1504626814-23124-1-git-send-email-peter.maydell@linaro.org/T/#u
[2] https://review.coreboot.org/c/coreboot/+/34774
[3] https://review.coreboot.org/c/coreboot/+/36486
[4] https://qemu-project.gitlab.io/qemu/system/arm/virt.html
[5] https://qemu-project.gitlab.io/qemu/system/riscv/virt.html
Change-Id: I8bef09bc1bc4e324ebeaa37f78d67d3aa315f52c
Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80322
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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This reverts commit b3db3abd6311924930f3250c9f9fc3157fbbf7da.
Reason for revert: `Wcalloc-transposed-args` is new command option came with GCC-14. older versions will not support it.
Change-Id: I74ef8de1f7d38e1e0519c3b41e79fd9b11d8e16f
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82759
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Obviously one should return NULL if a FDT is not valid an not the other
way around.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I77c0e187b841e60965daac17025110181bdd32bc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82773
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
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Change-Id: Ibe551a4c83f416ba30326077aa165818cf79c1fd
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82648
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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- Add Rex64 board to Kconfig menu
- Enable building for Rex64 with x86_64 support
Change-Id: I02e2c49b4aeb2cb98d9d0cb66717db18c3f96d45
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82625
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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The crashlog code in intel/common/block and meteorlake soc
was casting integer addresses directly to pointer types,
which caused compilation errors in x86_64 bit builds.
This commit fixes the issue by using uintptr_t for casting
integer addresses to pointer types before dereferencing.
BUG=b:329034258
TEST=Successfully build Meteor Lake (rex) in both x86_32 and
x86_64 modes.
Change-Id: I2d0814a8b767270ec140341bfb51d0782469545d
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82481
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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Update used USB port[2][3](type-a) setting for nova.
BUG=b:328711879
TEST=emerge-constitution coreboot chromeos-bootimage
Change-Id: I63cf97b23627feac05743f2a6e514a33fcaf7dff
Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82703
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
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For multi-SKU/SoC supports, IIO domain layouts are returned from FSP
HOBs. Add _OSC ASL generation utils so that static IIO domain layout
definition file per SKU/SoC are not needed any more.
The _OSC generation codes is a thin AML generation layer which
further invokes \_SB.POSC which is defined in ASL. The ASL handler
is able to handle boot-time generated info as parameters while keeps
good readability for the ease of maintenance. In this case, firmware
granted capabilities are calculated in boot time and passed to ASL
handler as parameters.
TEST=Build and boot on intel/archercity CRB
Change-Id: Ibd3bfa2428725fe593754436d5ed75a3a11b4cdc
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82034
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
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This commit removes config guard around FSPM_ARCH_UPD from the
FspApi.h header file. This change is done to ensure
that this header file can be used with both x86_32 and x86_64
architectures and also with different FSP specification versions.
The following modifications are made:
- Removes PLATFORM_USES_FSP2_X86_32 config guard around
FSPM_ARCH_UPD, this was added to isolate the structure from
x64 build. This is not really required since the x64 build uses
FSP2.4 structures.
BUG=b:343428206
TEST=Verified x86_32 and x86_64 builds on Meteor Lake board (Rex)
Change-Id: Idc849de73723036323f81dfd055730f6669cd52e
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82425
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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The devicetree entry and gpio.c updated as per the schematics of Trulo
to map the OC fault signals from A0/A1 USB ports.
BUG=b:335858378
TEST= Able to build google/trulo
Change-Id: Ic17debc5eecebca8c000c43a660e1b52d2932f2a
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82637
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
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EnableMultiPhaseSiliconInit upd is deprecated and has been
removed starting with v2.4 of FSP specification. Multi-phase
silicon initialization is mandatory for all FSP implementations
compliant to v2.4.
The following modifications are made:
- In fsp_params.c and silicon_init.c EnableMultiPhaseSiliconInit
update is guarded so that it will get included only if FSP2.4
is not selected.
BUG=b:329034258
TEST=Verified x86_32 and x86_64 builds on Meteor Lake board (Rex)
Change-Id: Icdbf3bacc0a05975fc941b264fd400d74f506fce
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82699
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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* Conditionally select FSP 2.4 when x86_64 support is available
(HAVE_X86_64_SUPPORT).
* Default to FSP 2.3 otherwise.
* Adjust default FSP header path to align with architecture.
BUG=b:242829490
TEST=Able to build google/rex in both 32-bit and 64-bit mode.
Change-Id: Ib77a34c6bf7bca3485a197f109d1550ac3d51cc0
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82624
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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This change allows eSOL to be enabled on production Meteor Lake silicon
even when 64-bit support is not present. eSOL support is still TBD for
64-bit FSP hence, skip adding this support for 64-bit build.
TEST=Able to build and boot google/rex64 w/o eSOL.
Change-Id: I16762e5b74ae0aaa3c28730479a1fd9defc4d93c
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82716
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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<gpio.h> is supposed to chain-include <soc/gpio.h>.
Change-Id: Ib25581bd2c8dd38cdd0396561ce5f9a782365f14
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82691
Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This commit introduces new header files of V3471.91 for the x86_64
architecture in the fsp2_0/meteorlake directory. FSP2.4 brings FSP
64-bits support and the soc Kconfig file has been updated to select
this new header path when FSP2.4 is in use.
BUG=b:329034258
TEST=Verified x86_32 and x86_64 builds on Meteor Lake board (Rex)
Change-Id: Ib41b57e794311db729ac65a968f562aa127e86c3
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82473
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
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This commit moves FSP V3471.91 header files for Meteor Lake
into a new x86_32 directory to better organize the files based
on the architecture. The Kconfig file has been modified accordingly
to reflect the new paths of the relocated headers.
BUG=b:329034258
TEST=Verified x86_32 and x86_64 builds on Meteor Lake board (Rex)
Change-Id: Id30186a8b1b5a9082f498e18a3378f5e9907b668
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82424
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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This commit updates the type definitions for FSP parameters in the
Meteor Lake platform to ensure compatibility with the FSP2.4
specification, that supports 64-bit builds for the first time and
this also ensures that parameter types works for both 32-bit
and 64-bit builds.
- In fsp_params.c, FSPS_ARCH_UPD macro is changed to
FSPS_ARCHx_UPD which supports FSP2.4 and older specifications.
Special handling is added for FspEventHandler assignment to handle
as the variable type is different in both cases.
- In meminit.c, the type for SPD pointers is changed from uint32_t
to efi_uintn_t to support both 32-bit and 64-bit builds.
BUG=b:329034258
TEST=Verified x86_32 and x86_64 builds on Meteor Lake board (Rex)
Change-Id: Ide220f60184135a6488f4472f69a471e2b383e2a
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82177
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Since this mainboard no longer uses the FSP GOP driver, the DDI port
settings are no longer necessary. The GOP driver was used in the initial
phase of development where we used Tianocore as payload for some test
cases. Finally, this mainboard uses a self-made Linux payload, which
does the graphic initialization.
BUG=none
TEST=Boot into Linux and check if graphic works correctly
Change-Id: Ie9e135fbc2627546d6ef95d7d5ff3e9a9222b5d2
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82663
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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The Adder WS 4 (addw4) is a Raptor Lake-HX board.
Tested with a custom edk2 UefiPayloadPkg.
Working:
- PS/2 keyboard
- I2C HID touchpad
- Both DIMM slots (with Crucial CT8G48C40S5)
- M.2 NVMe SSDs
- All USB ports
- MicroSD card reader
- Webcam
- Ethernet
- WiFi/Bluetooth
- Integrated graphics using Intel GOP driver
- Backlight controls on Linux 6.8
- DisplayPort output over USB-C
- Internal microphone
- Internal speakers
- Combined headset + mic 3.5mm audio
- 3.5mm microphone input
- S3 suspend/resume
- Booting Pop!_OS Linux 22.04 with kernel 6.8.0
- TPM 2.0 device
Not working:
- Discrete/Hybrid graphics
- Detection of devices in TBT slot on boot
Change-Id: I4a6819cbcf64f68237008adebdd7eb196336514c
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82595
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The Oryx Pro 12 (oryp12) is a Raptor Lake-HX board.
Tested with a custom edk2 UefiPayloadPkg.
Working:
- PS/2 keyboard
- I2C HID touchpad
- Both DIMM slots (with Crucial CT8G48C40S5)
- M.2 NVMe SSDs
- MicroSD card reader
- Webcam
- Ethernet
- WiFi/Bluetooth
- Integrated graphics using Intel GOP driver
- Backlight controls on Linux 6.8
- Internal microphone
- Internal speakers
- Combined headset + mic 3.5mm audio
- 3.5mm microphone input
- S3 suspend/resume
- Booting Pop!_OS Linux 22.04 with kernel 6.8.0
- TPM 2.0 device
Not working:
- Discrete/Hybrid graphics
- Thunderbolt
Change-Id: I11cf2dbd1512ebae44e0109bdb78e6eafa027444
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82596
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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Some drives block the CPU from reaching C10 during S0ix suspend without
the RTD3 configs.
Fixes suspend with the following drives:
- Kingston KC3000 (SKC3000D/4096G)
- Kingston HyperX (SHPM2280P2H/240G)
- Solidigm P44 Pro (SSDPFKKW010X7)
The following drives continue to work:
- Samsung 970 Evo (MZVLB250HAHQ)
- WD Black SN770 (WDS250G3X0E)
- WD Green SN350 (WDS240G2G0C-00AJM0)
- WD Blue SN570 (WDS100T3B0C)
Change-Id: Ia369727d0f1aa5ff546cfb5700a63063730e8248
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Tested-by: Levi Portenier <levi@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82597
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
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MKBP device is required for passing events from input sources to AP.
Input sources include buttons (power, volume); switches (lid, tablet
mode) and sysrq.
BUG=b:342227155
TEST=Able to build coreboot for mtlrvp platform and switch tablet
mode.
Change-Id: I630421c83784bb4492486d72290b9e8cdada1d47
Signed-off-by: Jay Patel <jay2.patel@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82612
Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
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Change-Id: Ia4f5d4140eeb8625c5ee41e38f048658db28a199
Signed-off-by: Maciej Pijanowski <maciej.pijanowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79684
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Code dealing with PAE can be used outside of memset_pae(). This change
extracts creation of identity mapped pagetables to init_pae_pagetables()
and mapping of single 2 MiB map to pae_map_2M_page(). Both functions are
exported in include/cpu/x86/pae.h to allow use outside of pgtbl.c.
MEMSET_PAE_* macros were renamed to PAE_* since they no longer apply
only to memset_pae().
Change-Id: I8aa80eb246ff0e77e1f51d71933d3d00ab75aaeb
Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82249
Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Sundance support FM101 WWAN, use wwan_power.asl to handle the
power off sequence
BUG=b:343139385
TEST=Build and boot on sundance
Change-Id: I82085172db370ab5a6c0f77afe6042c53b89e43e
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82683
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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Modify the Goodix touchscreen from new vendor and remove 3 unused
touchscreens. According to the information provided by the key-part
team.
BUG=b:340689681
TEST=Build and check Goodix touchscreen can work.
Change-Id: I1e6349e80431aadf27cd72b8439b01f95348071d
Signed-off-by: Roger Wang <roger2.wang@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82427
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
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Currently Samsung eMMC (KLMBG2JETD-B041) can't power on to OS nomally.
According to Intel provides eMMC DLL delay patch that tuning on each
Sundance different eMMC system to modify some system can't boot to OS problem.
BUG=b:342057438
TEST=Build and check each SKU eMMC can work.
Change-Id: I29d4305bbe5f91d822d947cae942b654e80a8a57
Signed-off-by: Roger Wang <roger2.wang@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82602
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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Change-Id: I9ed1a82fcd3fc29124ddc406592bd45dc84d4628
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82666
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
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<stdio.h> header is used for input/output operations (such as printf,
scanf, fopen, etc.). Although some input/output functions can manipulate
strings, they do not need to directly include <string.h> because they
are declared independently.
Change-Id: Ibe2a4ff6f68843a6d99cfdfe182cf2dd922802aa
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82665
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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- Added `$(obj)/libpayload-config.h` as a dependency for the `lib`
target.
- This ensures the config header is up-to-date before building the
library.
TEST=Able to build google/rex.
Change-Id: If26336f6261aadf611fa5338c4300873156cc3da
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82687
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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Change-Id: I75909ce85eed549d9094ba6f62d93656621d9f0d
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82679
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ic03d9ac883a92d52467d563f048446871b928712
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82678
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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GCC-14 documentation says "The first argument to calloc is documented to
be number of elements in array, while the second argument is size of
each element, so calloc(n, sizeof (int)) is preferred over
calloc(sizeof(int), n)."
Change-Id: I77b6f4d2eda487b087ba5665b588999633c33e8d
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82658
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I7d7ad562eeff7247b7377b6570d489faee0aeda0
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82669
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
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Commit 4c7e97b26a34 ("Update fsp submodule to upstream master branch")
included an update to the VBT from 240 to 250, breaking parsing of
existing VBTs.
After that commit, the VBT was parsed as (from gaze16-3060-b):
[DEBUG] PCI: 00:02.0 init
[INFO ] GMA: Found VBT in CBFS
[INFO ] GMA: Found valid VBT in CBFS
[INFO ] framebuffer_info: bytes_per_line: 4096, bits_per_pixel: 32
[INFO ] x_res x y_res: 1024 x 768, size: 3145728 at 0xd0000000
[DEBUG] PCI: 00:02.0 init finished in 6 msecs
When the expected output is:
[DEBUG] PCI: 00:00:02.0 init
[INFO ] GMA: Found VBT in CBFS
[INFO ] GMA: Found valid VBT in CBFS
[INFO ] framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
[INFO ] x_res x y_res: 1920 x 1080, size: 8294400 at 0xd0000000
[DEBUG] PCI: 00:00:02.0 init finished in 6 msecs
Generate blobs for the new version using Intel Display Configuration
Tool (DisCon) v3.3, based on the existing 237 and 240 VBTs.
(For our edk2 payload, the UEFI GOP driver was updated to 17.0.1077.)
Tested on all affected systems:
- darp7
- galp5
- gaze16-3050
- gaze16-3060
- gaze16-3060-b
- lemp10
- oryp8
Tested:
- Boot splash displays on screen again
- Firmware setup menu is rendered, at correct resolution
Change-Id: I918356d9f660b985ee4408ef77544fbd071ab35f
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Tested-by: Daniel Sutton <daniel@system76.com>
Tested-by: Jacob Kauffmann <jacob@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82246
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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Select MAINBOARD_USE_EARLY_LIBGFXINIT for brox to enable SOL image.
This patch enables Sign of Life image during MRC training.
BUG=b:335369811
TEST=Able to boot to ChromeOS with SOL image.
CPU log:
[SPEW ] bootmode is set to: 0 (boot with full config)
[0.384818] DP PHY mode status not complete
[0.388911] DP PHY mode status not complete
[0.393197] DP PHY mode status not complete
[0.397484] DP PHY mode status not complete
[0.401771] DP PHY mode status not complete
[0.406057] DP PHY mode status not complete
[0.410345] DP PHY mode status not complete
[0.414632] DP PHY mode status not complete
[0.418916] DP PHY mode status not complete
[0.423203] DP PHY mode status not complete
[0.427491] DP PHY mode status not complete
[0.431777] DP PHY mode status not complete
[INFO ] Informing user on-display of memory training.
[DEBUG] FMAP: area COREBOOT found @ 1877000 (7901184 bytes)
[WARN ] CBFS: 'preram_locales' not found.
[ERROR] ux_locales_get_text: preram_locales not found.
[DEBUG] FMAP: area RW_ELOG found @ f20000 (16384 bytes)
[INFO ] ELOG: NV offset 0xf20000 size 0x4000
elogtool list:
0 | 2024-05-10 02:26:07-0700 | Log area cleared | 4088
1 | 2024-05-10 02:26:07-0700 | Early Sign of Life | MRC Early SOL Screen Shown
2 | 2024-05-10 02:26:51-0700 | Memory Cache Update | Normal | Success
3 | 2024-05-10 02:27:09-0700 | System boot | 4
4 | 2024-05-10 02:27:09-0700 | Firmware Splash Screen | Enabled
5 | 2024-05-10 02:27:11-0700 | System Reset
6 | 2024-05-10 02:27:11-0700 | Firmware vboot info | boot_mode=Developer | fw_tried=A | fw_try_count=0 | fw_prev_tried=A | fw_prev_result=Unknown
7 | 2024-05-10 02:27:18-0700 | ACPI Enter | S5
8 | 2024-05-10 02:27:36-0700 | System boot | 5
9 | 2024-05-10 02:27:36-0700 | Firmware Splash Screen | Enabled
10 | 2024-05-10 02:27:37-0700 | System Reset
11 | 2024-05-10 02:27:37-0700 | Firmware vboot info | boot_mode=Developer | fw_tried=A | fw_try_count=0 | fw_prev_tried=A | fw_prev_result=Unknown
Change-Id: I1d4795825960bc58f8f7ef494b01aa975f3bc346
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81931
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com>
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Change-Id: I46f799ad255993ac42dab11b5c1d2608daa52b42
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82645
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch adds initial PCI device entries into the baseboard
devicetree.cb.
TEST=Able to build google/trulo.
Change-Id: I6ec25b98379cf7c8cbdb5be94d9f3ea43878620c
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82652
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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This patch marks unused USB ports (USB2.0/TCSS) empty to avoid
prompting wrong dmesg as below.
```
usb usb2-port3: Cannot enable. Maybe the USB cable is bad?
```
Trulo variants to override the USB ports as per the target
board design.
TEST=Able to build google/trulo.
Change-Id: I6240e66ed3d1a7198c1a526fdca2483910157235
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82651
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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This patch adds chip config entries for EC host cmd and memory map
ranges.
TEST=Able to build Google/Trulo.
Change-Id: Id4b0f3bba934c8da56b6d7ca8579b46b6cccac28
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82650
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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Add a new proximity type to represent the sub-NUMA cluster (SNC).
This patch adds necessary Xeon-SP common code level support for
SNC support. When SNC on, each SNC cluster will have a proximity
domain. DIMMs and CPU cores are attached to SNC proximity domains
instead of the processor proximity domains.
With SNC, there are 3 types of proximity domains,
PD_TYPE_PROCESSOR, PD_TYPE_GENERIC_INITIATOR and PD_TYPE_CLUSTER.
proximity domain type checks in Xeon-SP codes are updated to
correctly handle the adding of the new type.
This patch doesn't actually enable SNC. To fully enable SNC, SoC
codes need to override soc_get_cluster_count(), soc_set_cpu_node_
id() and memory_to_pd(), and call soc_set_cpu_node_id() in its
per-CPU init routine.
Change-Id: I32558983780f302ff4893901540a90baebf47add
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Co-authored-by: Ziang Wang <ziang.wang@intel.com>
Co-authored-by: Gang Chen <gang.c.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81443
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
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IO resource creation utils taking 'from' and 'to' as parameters
use uint16_t for them, where 'to' equals the resource limit plus
1. When a resource is with a limit of 0xFFFF, the value of 'to'
will be clipped to 0x0000 by uint16_t. Fix this problem by use
uint32_t and checks the effective range to make sure it no larger
than UINT16_MAX + 1.
TEST=Build and boot on intel/archercity CRB
TEST=Build on intel/avenuecity CRB
Change-Id: Ie83045683094d6330c1676809f83acf30175cc90
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82192
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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It might be benefical to have utils for domain resource window
creation so that the correct IORESOURCE flags used could be
guaranteed.
TEST=Build and boot on intel/archercity CRB
TEST=Build on intel/avenuecity CRB
Change-Id: I1e90512a48ab002a1c1d5031585ddadaac63673e
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82103
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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<stdarg.h> header is used to define macros for handling variable
argument lists in functions like printf. It does not depend on the string
or memory manipulation functions provided by <string.h>.
So let follow conventions and include only the necessary headers in each
header file.
Change-Id: I07ffc65b7feefb8ec4ab8dd268113f9ed8d24685
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82664
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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DDR3 and LPDDR3 share the same PART_NUM and PART_LEN.
So use the same macro.
This is to prepare SPD de-duplication in following patch.
Change-Id: Iea824a847b5072b1cbaa38dc38deae1d484d5b16
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82409
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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The secure buffer shrank from 42 MB to 32 MB, decreasing the total
OP-TEE image size from 80 MB to 70 MB.
BUG=b:246837563
TEST=emerge-geralt coreboot
build coreboot and verify SVP works well
Change-Id: I6729e65f83ef994fe59b5bd4ed098e6d3a847695
Signed-off-by: Gavin Liu <gavin.liu@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82634
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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Both acpi_create_madt_sci_override and acpi_sci_int have special
handling for the ACPI_NO_PCAT_8259 case, but those cases weren't exactly
obvious, so add a comment with the reason for that.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia6dcf59d5ab9226c61e9c4af95a73a07771b71d1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82643
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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AOOSTAR R1 is a Chinese NAS based on Intel N100 (Alder Lake N), with
two 3.5" HDD slots, an M.2 NVMe 2280 SSD slot and a single DDR4-3200
SODIMM slot up to 32GB. It also comes with 2x 2.5Gb Intel NICs,
Intel AX200 WiFi + BT and USB-C Alt-DP Power Delivery.
Working:
- DDR4 RAM (tested with Crucial 16GB 3200MHz CL22)
- Automatic FAN control (IT8613E Super I/O)
- M.2 NVME slot
- 2x SATA ports (Issue on 3.5" HDD, see below)
- USB 2.0 ports
- USB 3.0 ports
- USB-C port with Alt-DP and PD
- HDMI / DisplayPort ports
- 2x 2.5Gb NICs
- WiFi + BT
- MicroSD card reader
- ASPM (Unavailable on stock)
- Linux (Arch Linux, kernel 6.8.7-arch1-1) UEFI booting with EDK2
- Windows 10 UEFI booting with EDK2
Broken:
- Power button (OFF->ON broken, ON->OFF works)
- 3.5" SATA HDDs (Detected only after reboot)
Untested:
- Internal audio
- S3
My motivation for doing this port is enabling ASPM, as it makes a
great difference on idle power consumption (from 8.4W to 5W measured
from the wall).
The last remaining annoyance of this port is the power button not
working. I spent a few hours double checking the Super I/O registers but
then I gave up. A workaround for this is to use the "ON after power
loss" feature and reconnect the power cord to turn on the board.
It's not a big problem for a NAS that will stay ON 24/7.
Any hint on the power button or 3.5" HDD issue is welcome.
VBT extracted from vendor UEFI firmware version 1AXFE 0.01 x64
(Build date and time 11/29/2023 10:57:44)
Compiled with FSP GOP video initialization, using IFD descriptor
and ME blob extracted from vendor UEFI firmware (see above).
The board can be flashed externally using a 1.8V adapter, I used a
CH341a modded for 3.3V I/O. Internal flashing works, as flash is
not read/write protected.
Patchset 5: Re-enabled dptf, added default options to Kconfig.
Patchset 7: Configured USB port mapping and overcurrent, USB3.0 works
Patchset 8: Fixed microSD card reader
Patchset 13: Change Super I/O Fan configuration to reduce fan noise
Change-Id: I9414eb742b6b90459e010b038c1994537e9801a5
Signed-off-by: Federico Amedeo Izzo <federico@izzo.pro>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82010
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Adjust setting as recommended by power team.
Add ramstage.c in Makefile.inc to set psys_pl2_watts in
variant_devtree_update().
Also copy CPU power limit values from ovis baseboard.
BUG=b:320410462
BRANCH=firmware-rex-15709.B
TEST=FSP debug emerge-ovis coreboot intelfsp
check overrides setting
[INFO] CPU PsysPL2 = 178 Watts
[INFO] Overriding PsysPL2 (178)
[INFO] Overriding power limits PL1 (mW) (19000,28000) PL2 (mW)
(64000, 64000) PL4 (W) (120)
Change-Id: I9ce3a8f843a87e81d404778aaf250b876b6801eb
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82200
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
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Adjust settings as recommended by thermal team.
Set PL1 max value tdp_pl1_override from 28W to 33W.
PL2, PL4 remain the same as CPU default.
BUG=b:308704811
BRANCH=firmware-rex-15709.B
TEST=emerge-ovis coreboot chromeos-bootimage
built bootleg and verified test result by thermal team
Change-Id: Iad0bca913496dda666ba9bcfe5f6fce1a6396692
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82615
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Adjust settings as recommended by thermal team.
Set tcc_offset value to 5 in devicetree.
BUG=b:308704811
BRANCH=firmware-rex-15709.B
TEST=emerge-ovis coreboot chromeos-bootimage
built bootleg and verified test result by thermal team
Change-Id: I30f54ae6017c54c91ff9b432bba0ebd5bfc65ab9
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82614
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Eric Lai <ericllai@google.com>
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Adjust settings as recommended by thermal team.
Update DPTF parameters based on b:308704811#comment4.
BUG=b:308704811
BRANCH=firmware-rex-15709.B
TEST=emerge-ovis coreboot chromeos-bootimage
built bootleg and verified test result by thermal team
Change-Id: I710682771bd0679ae4b44dd43be68f60e8984b2e
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82434
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Eric Lai <ericllai@google.com>
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The code used to reserve MEMSET_PAE_PGTL_SIZE (20 KiB) for page used
for clearing the memory above 4 GiB that was assumed to be 2 MiB page.
memset_pae() checks only the alignment and not the size of this region,
so no error was reported by it.
In most cases this reserved memory in 2-4 MiB range, and because this
range isn't usually used by coreboot (architectural stuff is located in
lower 1 MiB, coreboot tables and ramstage are close to TOLUM and payload
isn't yet loaded when the broken code is executed), it never caused any
problems.
Change MEMSET_PAE_PGTL_SIZE to MEMSET_PAE_VMEM_SIZE and fix wrong macro
definition to reserve properly sized region.
Change-Id: I0df15b0d1767196fe70be14d94428ccdf8dbd5d3
Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82397
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
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Call acpi_create_madt_irqoverride from acpi_create_madt_sci_override
with the correct parameters instead or re-implementing the same
functionality.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I7e6ee0eed837c2d46da62092b7cc5669dc177d8d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82644
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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This excludes Devicetree blob files from the list of files to check for
superfluous whitespaces. A DTB file has recently been added in commit
33079b8174 ("lib/device_tree: Add some FDT helper functions").
Change-Id: Ic25ee5361163446370c530cccefa3bf085895d15
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82638
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Change-Id: Ib704f7659d3b431ce7eebb4432c5b1a4272de3d2
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77147
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch introduces x86_64 (64-bit) support to the payload, building
upon the existing x86 (32-bit) architecture. Files necessary for 64-bit
compilation are now guarded by the `CONFIG_LP_ARCH_X86_64` Kconfig
option.
BUG=b:242829490
TEST=Able to verify all valid combinations between coreboot and
payload with this patch.
Payload Entry Point Behavior with below code.
+----------------+--------------------+----------------------------+
| LP_ARCH_X86_64 | Payload Entry Mode | Description |
+----------------+--------------------+----------------------------+
| No | 32-bit | Direct protected mode init |
+----------------+--------------------+----------------------------+
| Yes | 32-bit | Protected to long mode |
+----------------+--------------------+----------------------------+
| Yes | 64-bit | Long mode initialization |
+----------------+--------------------+----------------------------+
Change-Id: I69fda47bedf1a14807b1515c4aed6e3a1d5b8585
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81968
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Both the processor local APIC structure and the processor local x2APIC
structure use the same flag bit definitions. ACPI spec 6.4 was used as a
reference.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8101c2ea874c8b12b130dbe9a0a7e0f0d94adffa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82641
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
|
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The multiple APIC flags table from the ACPI specification version 6.4
was used as a reference.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I36f67ca21465bc8753bb36896ee05669de6de333
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82640
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Implement the two architectural tables: processor and cache.
Note that SoC/board code should override core-thread count
and, for spec-compliance, create CBMEM_ID_MEMINFO.
Change-Id: Iedae0f26f168bd6d3af866e35d9d39ddb01abc15
Signed-off-by: Benjamin Doron <benjamin.doron@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78285
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Implement support for generating an SMC to call a trusted monitor. Some
functions are provided to read the SoC ID from the monitor, if
supported.
Change-Id: I158db0b971aba722b3995d52162146aa406d1644
Signed-off-by: Benjamin Doron <benjamin.doron@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78284
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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get_cxl_mode() is the interface for CXL mode config check used by
SoC codes. It could be implemented by mechanisms outside of the
SoC codes, e.g. board codes or OCP VPD driver.
Move the interface declaration out of soc/util.h to a dedicated
header, a.k.a., soc/config.h, so that the implementation codes do
not need to include soc/util.h where there are lots of irrelevant
definitions. Future SoC config check interfaces could be added
to soc/config.h as well.
The default weak implementation is moved out of util.c to
config.c as well.
TEST=Build and boot on intel/archercity CRB
Change-Id: Ia0302b0d3fd93c49e1d6f64e8159f59d50f33e20
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82293
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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While the SoC-level defaults for VGA_BIOS_ID are the expected correctly
remapped PCI VID/PID of the GPU which matches the PCI VID/DID inside the
VBIOS file, some mainboards override the VGA_BIOS_ID setting to the
non-remapped PCI ID. This resulted in coreboot not finding the VBIOS
file after commit 42f0396a1028 ("device/pci_rom: rework PCI ID remapping
in pci_rom_probe"). The proper solution would be to not override this
SoC-level config in neither the mainboard code nor some external config
file. This however requires adding/using some mechanism to tell SeaBIOS
which VBIOS image to use for the GPU device. Once this is implemented,
the SoC default for VGA_BIOS_ID shouldn't be overridden any more and
this patch can be reverted again.
This sort-of reverts parts of commit 42f0396a1028 ("device/pci_rom:
rework PCI ID remapping in pci_rom_probe"), but it still tries to find
the VBIOS image with the expected remapped PCI ID and only adds trying
the non-remapped PCI ID as a fallback when the file with the remapped
PCI ID doesn't exist and prints a notice in that case. Before the patch
referenced above, using the correct remapped PCI VID/DID resulted in a
warning about the CBFS file with the non-remapped name not being found,
but first checking the remapped version solves that problem.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I7cd8e2036250f4ca2239b04cd070bbf0778b13aa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82592
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
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Change-Id: I8445ac2e1bfca6cbf9d4d544318eec666948a8c4
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82623
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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This adds the Authors from the 24.02 tag to the 24.05 tag.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Icb53c62c9a122ccdf2548cc2eebc8b0316a844ef
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82617
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The pre-release notes never capture everything, so we need to do an
update to finalize them after the release is tagged.
This captures on additional SoC added right before the release and
updates the statistics.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Id3efcd15597e4fee0bdbca76e474974ae32d3263
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82613
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Integrate head.S directly into libc and remove all instances of head.o.
* Drop 'separate class' entry for head.S.
* Drop special treament for head.o inside lpgcc.
* Change the .text in `x86/head.S` to `.section .text._entry`.
* Drop arch/mock/head.c, initially added as a dummy file.
Change-Id: I156d781908fcc38d455bbf9f2c29e5ab95c7775a
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82478
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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This moves the multiboot header into its own include file, simplifying
head.S and making it easier to include/exclude the multiboot header
based on config options.
BUG=b:242829490
TEST=Able to build and boot google/rex.
Change-Id: I59a22dfe36044b4dd64a5b028a134be7a7d02a48
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82533
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch tries to simplify the baseboard/variant GPIO programming
for Google/Trulo. The idea is to let each variant maintain
its own complete GPIO PAD configuration table instead of having a
back-and-forth call between baseboard and variants.
With this patch coreboot performing GPIO programming is now much
simpler where the common code block calls into respective variants
and gets the gpio table prior to the pad configuration.
BUG=b:334826281 ([TWL] Decouple GPIO from baseboard to variant)
TEST=Able to build google/orisa.
Change-Id: I4ab88ac094a45c608cd894feb5eeec24b867527a
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82629
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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