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2015-07-21google/glados: add new boardPatrick Georgi
Change-Id: I0c196ff84484717c59c59d11bb7230b5920e0654 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10997 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-21intel/common: remove printk in pre_console_init()rsatapat
printk called before console init causes sluggish execution because of Rx timeout. BRANCH=None BUG=chrome-os-partner:40857 TEST=Built for sklrvp and tested LPSS logs on RVP3 and Kunimitsu. Change-Id: I61d5c0f5a4e93695bcba90b7ac7d4f68e2d625be Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 77c58702c8279c6d9c6ae1c946bf1b76df20714d Original-Change-Id: Ib85029456059248cc2c88aaccba4fa12cc5a76be Original-Signed-off-by: rsatapat <rishavnath.satapathy@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/284823 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Wenkai Du <wenkai.du@intel.com> Original-Tested-by: Wenkai Du <wenkai.du@intel.com> Reviewed-on: http://review.coreboot.org/10996 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-21Skylake: Initialize GPIOs for UART2rsatapat
FSP will initialize GPIOs during TempRamInit. So configure LPSS UART2 GPIOs in native mode after TempRamInit. BRANCH=none BUG=chrome-os-partner:41374 EST=Build and boot on RVP3. Check LPSS logs on UART2 Change-Id: I8016dd76a5bc06e90f9460273be7e83c5e8f8bb1 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: eb72e715ef3f566e900727ac8b9494bca1d5971c Original-Change-Id: If1b1a1047ebd5e5f170d91972d11c51aa6fd84a9 Original-Signed-off-by: rsatapat <rishavnath.satapathy@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/281604 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Wenkai Du <wenkai.du@intel.com> Original-Tested-by: Wenkai Du <wenkai.du@intel.com> Reviewed-on: http://review.coreboot.org/10995 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-21Skylake: Only support UART2 as debug port, clean up the restNaveen Krishna Chatradhi
On Skylake, only UART2 is supported as debug port and the macros INTEL_PCH_UART_CONSOLE_NUMBER, INTEL_PCH_UART_CONSOLE and the partial code for UART0, 1 are cleaned up for Skylake and Sklrvp, Kunimitsu and Glados boards. BRANCH=none BUG=chrome-os-partner:40857 TEST=Built for kunimitsu, checked the coreboot logs on LPSS UART2 Change-Id: I2fbcfb1d1ca6f59309a77c67d022cf4f5da7f7c0 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e714c18d462bc7bdd7068309fb6be77da6973642 Original-Change-Id: I9343abd90ce685ea2d676047dccbefad7457b69f Original-Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/285793 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Wenkai Du <wenkai.du@intel.com> Original-Tested-by: Wenkai Du <wenkai.du@intel.com> Reviewed-on: http://review.coreboot.org/10994 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-21intel fsp: remove CHIPSET_RESERVED_MEM_BYTESAaron Durbin
FSP 1.1 platforms should be conforming to the spec. In order to ensure following specification remove the crutch that allows FSP to no conform. BUG=chrome-os-partner:41961 BRANCH=None TEST=Built. Change-Id: I28b876773a3b6f07223d60a5133129d8f2c75bf6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c3fe08c5af41867782e422f27b0aed1b762ff34a Original-Change-Id: Ib97027a35cdb914aca1eec0eeb225a55f51a4b4b Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/285187 Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/10993 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-07-21cyan/strago: Disable wwanJagadish Krishnamoorthy
Disabling the wwan gpio line since wwan is not used. BRANCH=none BUG=none TEST=wwan should not connect to network on cyan/strago. Change-Id: I9d2e5d5b185a4622218e894d3b092afe15e09289 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 9a20c602b3bb768baa38b17e21cb4e5b0d9249ef Original-Change-Id: Ib8d5fd15a172ef898ce675a85c2ea3e5f5c79144 Original-Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/285304 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10992 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-07-21Braswell: Remove GOP from normal boot mode.Abhay Kumar
Removing GOP initialization in normal mode since we don't need to show splash screen in normal mode. GOP will get initialized in dev and recovery mode. BRANCH=none BUG=None TEST=Splash screen will come only in dev or recovery mode. Change-Id: Ia5e12cf45d723f2f14c447e29b78119552d5e1ea Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 79d1c877343704ea51143b922d9ac9209be4d4b5 Original-Change-Id: Id5ca99757427206413483d07b4f422b4c0abfa5d Original-Signed-off-by: Abhay <abhay.kumar@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/285300 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10990 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-07-21skylake: re-enable PCIe L1 sub statesAaron Durbin
All boards should have their L1 sub states working now so re-enable the defaults. BUG=chrome-os-partner:41861 BRANCH=None TEST=Built and booted glados into OS. PCIe devices show up still. Change-Id: Ic040fa108a662e15bb97cf8b0961f0f56683e146 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 380491f8267e60c3c6bc62486aaf21e201fcfd36 Original-Change-Id: Idc6923b1fdd1c20d463eb7782be112f90b9adbfd Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/285170 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/10989 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-07-21Sklrvp: Select PCIEXP_L1_SUB_STATE config symbolNaveen Krishna Chatradhi
This patch selects the config symbol PCIEXP_L1_SUB_STATE to enable L1 substate for PCIe. BRANCH=None BUG=chrome-os-partner:42331 TEST=Build for sklrvp; boot and check "dmesg | grep iwl" shows "L1 enabled and LTR enabled" Change-Id: I97552c7700649a9f5d8646a03027c5c5e0b477b4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d3115816fbdd11c7f8ff418e0b5c86b8650c8b83 Original-Change-Id: Iaf307cb2d623cc1ce97b01d15a6b42569fd0c0c4 Original-Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/284775 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Wenkai Du <wenkai.du@intel.com> Reviewed-on: http://review.coreboot.org/10988 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-07-21skylake: honor pcie root port settings already in chip.hAaron Durbin
For some unkonwn reason the pcie root port settings weren't being honored in the device tree. Fix that omission. BUG=chrome-os-partner:41861 BRANCH=None TEST=Built with CONFIG_DISPLAY_UPD_DATA and noted devicetree settings were being honored. Change-Id: Id880eca57544efb13f5cbbc06b2634c86b7c5d29 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 2d00e68ce6cfcb3d63d69848f4a8ce232f6c1257 Original-Change-Id: Idd37d65374842294f4b0c91eb841c6d1d93e92ee Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/285027 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/10987 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-07-21skylake: Show SPI controller if enabled in devicetree.cbDuncan Laurie
Unhide the SPI controller PCI device if it is enabled in devicetree.cb so flashrom can do its job. BUG=chrome-os-partner:37711 BRANCH=none TEST=run flashrom -r on glados Change-Id: Ie567f970149700d29df0ae09db4962f36cf24219 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 172eac55ad6134fe5e347e37c055b383e3b03245 Original-Change-Id: Ia77b559cc607794aecc25d6d469224d855199568 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/284948 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10986 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-21cyan: Enable EC software syncRavi Sarawadi
BUG=chrome-os-partner:40526 BRANCH=None TEST=Verify that system boots when used with coreboot and EC versions that also have Software Sync enabled. Change-Id: I6ed562fa51d83ddf16fc74d35db7c0004f57c79e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 090a66c50fac21808c4721a32b1728cc904f1b00 Original-Change-Id: Ia4d87d9a177c579567c03ae113889a277ffecee0 Original-Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/283573 Original-Commit-Queue: Divya Jyothi <divya.jyothi@intel.com> Original-Tested-by: Divya Jyothi <divya.jyothi@intel.com> Original-Reviewed-by: Shawn N <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/10985 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-21Revert "northbridge/amd/pi: Add support for memory settings"Marc Jones
This is breaking the build right now. Reapply once the correct headers are in place. This reverts commit 406effd59075cab212c5bf9c1a12759c8fad50a4. Change-Id: I34b8717820ed58b462d4e7793711ee98fb8b882f Reviewed-on: http://review.coreboot.org/11020 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-21amd/hudson: Fix makefile FWM location checkMarc Jones
Fix typo. Use the correct math helper int-lt. Change-Id: Ia5e722020c75595dfcfb853ea8238fb8391f9a04 Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/10980 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-21braswell: clean up \_PR entriesJagadish Krishnamoorthy
All \_PR entries needs to be changed from CPU# to CP## so that it can support more cores. BRANCH=none BUG=chrome-os-partner:38734 TEST=build and boot cyan/strago boards. Change-Id: I80a79ec8edbce46826140470645b7532ae361f91 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ca269a7ffcd2ef16fcef93851e68c2d91104e3e1 Original-Change-Id: I48e73742dc3b11ee6e96f70bcd2d10d01609ad7c Original-Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/285700 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10991 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-20northbridge/amd/pi: Add support for memory settingsDave Frodin
This adds support for binarypi based boards that have to make adjustments to the memory configuration settings. A PlatformMemoryConfiguration[] table that describes the memory configuration must be defined in the mainboard folder. Change-Id: I5e4b476a4adf3dd1f3b7843274a81ecb243d10ab Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/10672 Tested-by: build bot (Jenkins) Reviewed-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-07-18cbfstool: Deduplicate code to merge empty filesPatrick Georgi
The code for removing a file had its own merge routine. Use the generic one instead. Change-Id: I90ed007ab86f78a2728f529fa0143c5c1dfbbdc3 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/10967 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-07-18cbfstool: rename checksum to attributes_offsetPatrick Georgi
So far it's still unused, but its purpose will change: It will become an offset to another structure that contains additional file attributes. This change is compatible because the binary format doesn't change and so far the field was always set to 0, which can serve nicely as 'unused' field. Change-Id: I2dafb06866713d43a236556f9492641526270837 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10933 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-07-18Makefile: Fix KCONFIG_AUTOHEADER dependenciesStefan Reinauer
This makes the Makefile more robust when changing the file name or changing the .config outside of make *config Change-Id: Ifc013cc3ef899a7846742a961261ac50bc67e27b Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10970 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-07-18libpayload: usb: Add support for SuperSpeed hubsJulius Werner
This patch adds support for the SuperSpeed half of USB 3.0 hubs, which previously prevented SuperSpeed devices behind those hubs from working. BRANCH=None BUG=chrome-os-partner:39877 TEST=Played around with multiple hubs and devices on Oak and Falco, can no longer find a combination that doesn't work. Change-Id: I20815be95769e33d399b7ad91c3020687234e059 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3db96ece20d2304e7f6f6aa333cf114037c48a3e Original-Change-Id: I2dd6c9c3607a24a7d78c308911e3d254d5f8d91d Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/284577 Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> Original-Tested-by: chunfeng yun <chunfeng.yun@mediatek.com> Reviewed-on: http://review.coreboot.org/10958 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-18libpayload: usb: xhci: Prevent address reuseJulius Werner
We have been trying to avoid reassigning previously used USB addresses to different devices since CL:197420, because some devices seem to take issue with that. Unfortunately, that patch doesn't affect XHCI: those controllers insist on chosing addresses on their own. The only way to prevent them from reusing a previously assigned address is to not disable that slot at all. This patch implements address reuse avoidance on XHCI by not disabling slots when a device is detatched (which may occur both on physical detachment or if we simply couldn't find a driver for that device). Instead, we just release as many resources as we can for detached devices (by dropping all endpoint contexts) and defer the final cleanup until the point where the controller actually runs out of resources (a point that we probably don't often reach in most firmware scenarios). BRANCH=none BUG=chrome-os-partner:42181 TEST=Booted an Oak plugged into a Servo without having a driver for the SMSC network chip, observed that it could still enumerate the next device afterwards. Kept unplugging/replugging stuff until the cleanup triggered and made sure the controller still worked after that. Also played around a bit on a Falco without issues. Change-Id: Idfbab39abbc5bc5eff822bedf9c8d5bd4cad8cd2 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 88c6bcbc41156729c3c38937c8a4adebc66f1ccb Original-Change-Id: I0653a4f6a02c02498210a70ffdda9d986592813b Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/284175 Original-Tested-by: Nicolas Boichat <drinkcat@chromium.org> Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10957 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-18amd/pi: Increase assumption for maximum CBFS file header sizePatrick Georgi
The new attributes increase the header size, breaking this assumption. Change-Id: Ib23862f27650b39133deafb74a24327b098b6e86 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10942 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-07-18cbfstool: move fill value to cbfs.hPatrick Georgi
Change-Id: Ie05db6d43219c65d08e2221009875f81eb29b630 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/10968 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-07-18intel/kunimitsu: Fix Kconfig symbol typePatrick Georgi
BOOT_MEDIA_SPI_BUS is int, not hex. Change-Id: I5cbcc3889a025caab921208037c8a61d224078a7 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/10973 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-07-17soc/intel: Remove microcode terminatorsStefan Reinauer
They have been removed in the rest of the code already. http://review.coreboot.org/#/c/4506/ Change-Id: I232cc2ccd4dd90359de4ab710486db65667500f4 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10964 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-07-17intel/sklrvp: remove trailing whitespacePatrick Georgi
Change-Id: If933a70992a6ae8228eef8d4f0386387b4e4549d Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/10966 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-07-17skylake: remove whitespace from ASL filesStefan Reinauer
Found by the commit hooks. Change-Id: I9baa90ca0111ddc9cb69cbb7dd17f63e8a98a04f Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10965 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-17mainboard/google: Add Braswell based Cyan boardLee Leahy
Add initial files for the cyan board. Matches chromium tree at 927026db This board uses the Braswell FSP 1.1 image and does not build without the FspUpdVpd.h file. BRANCH=none BUG=None Test=Build and run on cyan Change-Id: I935839be033c25e197e78fbee306104b4162a99a Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10182 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-17mainboard/intel: Add Skylake based Kunimitsu boardLee Leahy
Initial files to support the Kunimitsu board. Matches chromium tree at 927026db This board uses the Skylake FSP 1.1 image and does not build without the FspUpdVpd.h file. BRANCH=none BUG=None TEST=Build and run ChromeOS on kunimitsu Change-Id: I1017a66bc811af51a0921e864b589ce2cb618082 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10836 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-17mainboard/intel: Add Skylake based RVP3 boardLee Leahy
Initial files to support the Intel Skylake RVP3 Matches chromium tree at 927026db This board uses the Skylake FSP 1.1 image and does not build without the FspUpdVpd.h file. BRANCH=none BUG=None TEST=Build and run on sklrvp Change-Id: I5e7fff8f62a737e627e25c1e03e343d6167041ea Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10343 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-17mainboard/intel: Add Braswell based Strago boardLee Leahy
Add the initial files to support the Intel RVP for Braswell. Matches chromium tree at 927026db This board uses the Braswell FSP 1.1 image and does not build without the FspUpdVpd.h file. BRANCH=none BUG=None TEST=Build and run ChromeOS on strago Change-Id: I5cb2efe3d8adf919165c62b25e08c544b316a05a Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10052 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-17lint/gitconfig: Enable checkpatch.pl checking of commitsStefan Reinauer
This patch enables running the checkpatch script on the code portion of each commit as part of the pre-commit hook. At this point there is no checking of the commit message in place (e.g. for typos) Change-Id: I7cdf0692cf372986e411f4aba4691417b73c7511 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/8419 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-07-17indent style fix for lapic_cpu_init.cJonathan A. Kollasch
Change-Id: I2821aaed1bc6324e671f68e4e4effb9dd006dcd9 Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: http://review.coreboot.org/10922 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-17Remove unused Kconfig symbols in c codeMartin Roth
The BROKEN_CAR_MIGRATE symbol was removed in commit a6371940 - x86 cache-as-ram: Remove BROKEN_CAR_MIGRATE option The symbol DISABLE_SANDYBRIDGE_HYPERTHREADING is from Sage, and was never added to the coreboot.org codebase. Change-Id: I953fe7c46106634a5a3fcdaff88b39e884f152e6 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/10941 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-07-16libpayload: usb: dwc2: support split transactionYunzhi Li
With split transaction, dwc2 host controller can handle full- and low-speed devices on hub in high-speed mode. This commit adds support for split control and interrupt transfers BUG=None TEST=Connect usb keyboard through hub, usb keyboard can work BRANCH=None Change-Id: If7a00db21c8ad4c635f39581382b877603075d1a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4fb514b7f7f7e414fa94bfce05420957b1c57019 Original-Change-Id: I07e64064c6182d33905ae4efb13712645de7cf93 Original-Signed-off-by: Yunzhi Li <lyz@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/283282 Original-Tested-by: Lin Huang <hl@rock-chips.com> Original-Commit-Queue: Lin Huang <hl@rock-chips.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/10956 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-16t210: new sdram_lp0_save_params() functionYen Lin
New sdram_lp0_save_params() function for T210. Due to its size, move the function from romstage to ramstage. BUG=chrome-os-partner:40741 BRANCH=None TEST=Build ok on Smaug; and check scratch registers Change-Id: I420ac4c15262f2c6307bcd84beb6c5da0310c7c0 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 38860895938c40062a9f860f75e31a539f15992b Original-Change-Id: Iaa478969458946faedd295578fe7d72b5a32e701 Original-Signed-off-by: Yen Lin <yelin@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/277022 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/10952 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-16foster: correct odmdata in odmdata.cfgYen Lin
So odmdata has the correct UART port of 0 BUG=chrome-os-partner:40741 BRANCH=None TEST=build Foster ok; and check scratch20 register Change-Id: I2c203317e6305214b74430780f2fe7b15652873a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0a0a99ac9c7db267129e4bc3478f9bb1ece08507 Original-Change-Id: I7be10d5deb5118f1cf3e339afca94893610437f2 Original-Signed-off-by: Yen Lin <yelin@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/280291 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/10955 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-16smaug: correct odmdata in odmdata.cfgYen Lin
So odmdata has the correct UART port of 0. BUG=chrome-os-partner:40741 BRANCH=None TEST=build Smaug ok; and check scratch20 register Change-Id: I59154daa5b5627d3b594ff9505e4f02de0d4d7aa Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 814cd164ab9ed9bf2e072f3728e89ea8d7cf0343 Original-Change-Id: I2252b728775cf2550d666ead0085c0ab3b72e40b Original-Signed-off-by: Yen Lin <yelin@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/277024 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/10954 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-16t210: correct odmdata location in bctYen Lin
Correct the odmdata location in bct for T210. BUG=chrome-os-partner:40741 BRANCH=None TEST=build ok on Smaug Change-Id: I2258556ec5cf5d25782e60e084f3d5657b441c86 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 288a5d71c35fbea1812ad0c91f2c6c5f5a022363 Original-Change-Id: I0efb033442c2aafc7f44898c16b3e91946e092d5 Original-Signed-off-by: Yen Lin <yelin@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/277023 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/10953 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-16foster: add sdram_configs.cYen Lin
Add sdram_configs.c to both romstage and ramstage. BUG=chrome-os-partner:40741 BRANCH=None TEST=Build ok on Foster Signed-off-by: Yen Lin <yelin@nvidi.com> Change-Id: Ib270c837ebe355c8d16072186c2b27d1c469fd48 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 73bc1abf2821176c21179880774887eec7c858b1 Original-Change-Id: Ia80a57a81e44542ee3d5437866071d50c8c5b8cb Original-Reviewed-on: https://chromium-review.googlesource.com/280290 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Tested-by: Yen Lin <yelin@nvidia.com> Original-Commit-Queue: Yen Lin <yelin@nvidia.com> Reviewed-on: http://review.coreboot.org/10951 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-16smaug: ramstage: include sdram_configs.cYen Lin
get_sdram_config() (in sdram_configs.c) will be needed in ramstage. BUG=chrome-os-partner:40741 BRANCH=None TEST=Build ok on Smaug Change-Id: I2920f8687b6a801a91dc5b5b50fc5637057e4321 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4d3092e360b26cbda41549452aeeba9ffc0b92ed Original-Change-Id: I43a20f3178cbf5b57a3a9ca7391856787aa8cdb8 Original-Signed-off-by: Yen Lin <yelin@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/277373 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/10950 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-16smaug: Use VNBN_FLASH instead of VBNV_ECFurquan Shaikh
CQ-DEPEND=CL:285312 BUG=chrome-os-partner:36613 BRANCH=None TEST=Compiles successfully and boots to kernel prompt Change-Id: Ib90333e3331a90b4539d49e1a72833fe3385879f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 042fc1a451081780f8af35af6943130f6412ca5f Original-Change-Id: I729996c04d8bd6a627421803a59037d7c47a3e98 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/285345 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/10949 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-16t210: Reorganize memlayout.ldFurquan Shaikh
Take up space from PRERAM_CBMEM_CACHE and increase verstage and romstage sizes. BUG=chrome-os-partner:36613 BRANCH=None TEST=Compiles successfully and boots to kernel prompt Change-Id: I7fdd6c08f3ca1998a6220edd80a570816ec65ab5 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: cce3d7baa7446e227d3da41341d9e273d4195299 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/285344 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Original-Change-Id: I6d97a60b26fbbb29a875285c46724fb43b5fe5ab Original-Reviewed-on: https://chromium-review.googlesource.com/285533 Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: http://review.coreboot.org/10948 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-16t210: SPI driver cleanupFurquan Shaikh
1. Get rid of spi_delay - Instead have a tight loop to check for the spi status 2. The first check for SPI operation complete i.e. FIFOs have been processed is the SPI_STATUS_RDY bit. Thus, tegra_spi_wait should check for this bit before reading BLOCK_COUNT or any other fifo count field. 3. Flush both TX and RX FIFOs for SEND and RECV operations for PIO and DMA. 4. No need to check for rx_fifo_count == spi_byte_count to determine pio_finish operation. RDY bit should be sufficient to ensure that the SPI operation is complete. Added assert to ensure we never hit the case of RDY bit being set, yet rx_fifo_count != spi_byte_count for PIO. BUG=chrome-os-partner:41877 BRANCH=None TEST=Compiles successfully and reboot test runs successfully for 10K+ iterations. Change-Id: I1adb9672c1503b562309a8bc6c22fe7d2271768e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: de1515605e17e0c6b81874f9f3c49fd0c1b92756 Original-Change-Id: I5853d0df1bfd6020a17e478040bc4c1834563fe4 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/285141 Original-Reviewed-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Tested-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/10947 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-16t210: Correct dma_busy functionFurquan Shaikh
In case of continuous mode, use STA_ACTIVITY bit to determine if DMA operation is complete. However, in case of ONCE mode, use STA_BSY bit to determine if DMA operation on the channel is complete. BUG=chrome-os-partner:41877 BRANCH=None TEST=Compiles successfully and reboot test runs fine for 10K+ iterations Change-Id: If98f195481b18c402bd9cac353080c317e0e1168 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 927026db6fd910dac32dc218f28efcbc7b788b4e Original-Change-Id: Ib66bedfb413f948728a4f9cffce9d9c3feb0bfda Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/285140 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/10946 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-16smaug: Increase drive strength for QSPI PinmuxFurquan Shaikh
Change the drive strength for QSPI Pinmux to DRIVE_STRENGTH_2 as per recommendations from nVidia hardware engineers. BUG=chrome-os-partner:41877 BRANCH=None TEST=Compiles successfully and boots to kernel prompt Change-Id: I5a7b94acb57bbc21d277a49fd0a6b892638fc0ca Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 58d085e6acbcd0fd355b1c7efc10606312caf8e8 Original-Change-Id: I03dd288d2e335d40c83feaec7efbf10a7d3bf1e6 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/284959 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/10945 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-16t210: Add PINMUX macros for drive strengthFurquan Shaikh
BUG=chrome-os-partner:41877 BRANCH=None TEST=Compiles successfully and boots to kernel prompt Change-Id: Ic606838639d33242b227fece9cbb019d8f3b3729 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 805831489ad80e4ed335ece458f81238af704876 Original-Change-Id: I54a730c3b97c3603a5b1981089913c58af2a42db Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/284958 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/10944 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-16toolchain: Add -mgeneral-regs-only to CFLAGS for arm64Furquan Shaikh
BUG=None BRANCH=None TEST=Compiles successfully and boots to kernel prompt on smaug Change-Id: I7eb75b215798a63157bae04d9d44dbd6f95a5715 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 6e5ecf9b45fa35e3c87bf6ef4bd2ea01680c8826 Original-Change-Id: I36a20d65d7ccaa21fdeb6070d43c2bb0ae22a16b Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/285553 Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/10959 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-16release: add release scriptPatrick Georgi
Change-Id: Ib3cd29cf1875e7ad182262d7caa33ff35f28aa85 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10909 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-16cbfstool: Remove extra comma after {0, NULL} list elementSol Boucher
Trailing commas are useful for lists that can be extended. These lists are 0-terminated, and there should be no elements following that. Change-Id: Iea8c6d5579d6363e77e1f5af666948160c4a9bf9 Signed-off-by: Sol Boucher <solb@chromium.org> Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Change-Id: I1a117a9473e895feaf455bb30d0f945f57de51eb Original-Signed-off-by: Sol Boucher <solb@chromium.org> Reviewed-on: http://review.coreboot.org/10932 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-07-16cbfstool: Factor out compression algorithm listSol Boucher
Parse compression algorithm arguments using a single list. Change-Id: Idc5b14a53377b29964f24221e42db6e09a497d48 Signed-off-by: Sol Boucher <solb@chromium.org> Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Change-Id: I1a117a9473e895feaf455bb30d0f945f57de51eb Original-Signed-off-by: Sol Boucher <solb@chromium.org> Reviewed-on: http://review.coreboot.org/10931 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-07-16cbfstool: rename fieldSol Boucher
With introducing hash algorithms, 'algo' is ambiguous, so rename it to 'compression' instead. Change-Id: Ief3d39067df650d03030b5ca9e8677861ce682ed Signed-off-by: Sol Boucher <solb@chromium.org> Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Change-Id: I1a117a9473e895feaf455bb30d0f945f57de51eb Original-Signed-off-by: Sol Boucher <solb@chromium.org> Reviewed-on: http://review.coreboot.org/10930 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-07-16cbfstool: move bit swapping macros to swab.hSol Boucher
Change-Id: Id22232c45225011951e01c370e0f473af574d758 Signed-off-by: Sol Boucher <solb@chromium.org> Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Change-Id: I1a117a9473e895feaf455bb30d0f945f57de51eb Original-Signed-off-by: Sol Boucher <solb@chromium.org> Reviewed-on: http://review.coreboot.org/10929 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-07-16cbfstool: use variable length array to model cbfs_file's filenamePatrick Georgi
Change-Id: Ib056983630b2899d7e6cbcb43f6b7153f0f8e282 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10928 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-07-16cbfstool: improve specification of struct cbfs_filePatrick Georgi
Lock down its size and document some of the fields Change-Id: I09fd6c80185345da0ae17d0f4498b50995fd1ec5 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10927 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2015-07-16soc/intel: Add Skylake SOC supportLee Leahy
Add the files to support the Skylake SOC. Matches chromium tree at 927026db BRANCH=none BUG=None TEST=Build and run on a Skylake platform Change-Id: I80248f7e47eaf13b52e3c7ff951eb1976edbaa15 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10341 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-07-16soc/intel/skylake: Use Broadwell as comparision base for Skylake SOCLee Leahy
Use the Broadwell implementation as the comparison base for Skylake. BRANCH=none BUG=None TEST=None Change-Id: I22eb55ea89eb0d6883f98e4c72a6d243e819e6d8 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10340 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-16x86 realmode: Set up the 8254 timer before running option romzbao
If the 8254 is not set up, the external graphics option rom hangs and never returns. The code is tested on AMD/bettong. Change-Id: I0022de9d9a275a7d4b7a331ae7fcf793b9f4c5f5 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/10903 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-07-16AMD Merlin Falcon: Mask bit 31 of BIST while doing BIST checkzbao
This is a result of the Silcon Observation. On warm reset, the BIST is 0x80000000, which causes BIST error. We skip checking this bit. The update will be in CZ BKDG 1.05. The code is tested on AMD/bettong. Change-Id: I51c3f3567f758766079f7c8789f1ff072e1a7c53 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/10902 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-07-15amd/model_fxx rev.F: emit P-states when no intermediates existJonathan A. Kollasch
Relevant for systems having processors that only have two (the minimum and maximum) P-states, such as the Opteron 2210 at 1.0 and 1.8GHz. Change-Id: Ic66fe6d10ce495c1bf21796cb7e1eb4e11e85283 Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: http://review.coreboot.org/10910 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-15libpayload: assume cbfs file alignment is 64 bytePatrick Georgi
Change-Id: I8dfd8fbd452ce92fbca2cf095bc5e43e4a26969d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10920 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-07-15cbfs: hardcode file alignmentPatrick Georgi
Assume that it's 64 byte. Change-Id: I168facd92f64c2cf99c26c350c60317807a4aed4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10919 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-07-15cbfstool: fix alignment to 64 bytePatrick Georgi
It's not like we _ever_ changed it, so drop the option and make cbfstool use the default. always. Change-Id: Ia1b99fda03d5852137a362422e979f4a4dffc5ed Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10918 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-07-15intel/fsp_baytrail: Remove PcdEnableLan optionYork Yang
Bay Trail SOCs do not integrate LAN controller hence Baytrail FSP has no LAN control function. Remove PcdEnableLan option from UPD_DATA_REGION structure. Change-Id: I9b4ec9d72c8c60b928a6d9755e94203fb90b658f Signed-off-by: York Yang <york.yang@intel.com> Reviewed-on: http://review.coreboot.org/10837 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-07-14timestamps: clarify in ramstage when not to reinit the cacheAaron Durbin
Commit bd1499d3 fixed a bug to not re-initialize the timestamp cache in ramstage for EARLY_CBMEM_INIT. However, EARLY_CBMEM_INIT was not included. Therefore, add this condition. This will result in base_time being initialized to the passed in timestamp for !EARLY_CBMEM_INIT platforms. Change-Id: Ia1d744b3cfd28163f3339f2364efe59f7dcb719b Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10884 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-14cbmem: export base_time in timestamp tableAaron Durbin
It's helpful to know the base_time (1st timestamp) in the timestamp table because it provides more information like the accumulated time before the first timestamp was recorded. In order to maximize this information report the base time as an entry that is printed. It's called '1st timestamp'. The implementation turns all the timestamp entries into absolute times so one can observe both absolute and relative time for each marker. Change-Id: I1334a2d980e3bcc2968a3bd6493c68b9efcca7ae Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10883 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-14libpayload: store boot media information in sysinfoPatrick Georgi
Write boot media information in sysinfo, if it exists. This allows picking the right CBFS for further files in case there are several. Change-Id: I75a8ee6b93f349b9f2fab1e82826aba675949c0a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10869 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2015-07-14cbtable: describe boot mediaPatrick Georgi
This allows finding the currently used CBFS (in case there are several), and avoids the need to define flash size when building the payload. Change-Id: I4b00159610077761c501507e136407e9ae08c73e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10867 Tested-by: build bot (Jenkins)
2015-07-14abuild: Allow disabling mainboardsPatrick Georgi
There may be boards that shouldn't be built for one reason or another. Allow black-listing them by adding a file to the mainboard directory called 'abuild.disabled'. It should contain the reason that is printed by abuild and also serves as documentation for users that want to know what's going on. Change-Id: I78c3281a578e96ee40f6b101143d4f3763582350 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10917 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-07-14Braswell: Use CBFS image type nameLee Leahy
Use the simplified CBFS image type name in Makefile.inc. BRANCH=none BUG=None TEST=Build and run on cyan Change-Id: Idb62de7fce36fde38a6fbeeefdfc2dd0d75bd493 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10872 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2015-07-14libpayload: Add support for handling fmapsPatrick Georgi
They will become more common soon, so better support them now. Change-Id: I2b16e1bb7707fe8410365877524ff359aeefc161 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10868 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-07-14riscv-emulation: Set stack size to 0 in KconfigThaminda Edirisooriya
Build now decides the stack size by correctly referencing the value in /src/mainboard/emulation/qemu-riscv/memlayout.ld. Note that while the size is correct, the placement is still wrong, and causes the stack to be corrupted by the coreboot tables. Still needs to be addressed Change-Id: I86c08bd53eeb64e672fecba21e06220694a4c3dd Signed-off-by: Thaminda Edirisooriya <thaminda@google.com> Reviewed-on: http://review.coreboot.org/10870 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-07-14fmap: publish find_fmap_directory()Patrick Georgi
The fmap directory can be useful to pass to the payload. For that, we need to be able to get it. Change-Id: Ibe0be73bb4fe28afb16d4d215b979eb0be369645 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10866 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-07-14fmap: Introduce new function to derive fmap name from offset/sizePatrick Georgi
vboot passes around the offset and size of the region to use in later stages. To assign more meaning to this pair, provide a function that returns the fmap area name if there's a precise match (and an error otherwise). Change-Id: I5724b860271025c8cb8b390ecbd33352ea779660 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10865 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-07-14getac/p470: initialize timestamps in romstagePatrick Georgi
Change-Id: I2f43684bbdd48f30039fe09275043ddf203d447c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10907 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-14azalia: fix up and clean up shrinkage of boilerplate codeJonathan A. Kollasch
Should fix regression in HDA verb setup on nvidia mcp55 and intel sch southbridges. The mcp55 code could not find the mainboard's verb table because the table was not even being compiled in. The sch boards appeared to have the same issue. Intel broadwell and fsp_bd82x6x seemed to have not gotten the boilerplate shrink, so apply it to those too. Followup-to: Ib3e09644c0ee71aacb067adaa85653d151b52078 (azalia: Shrink boilerplate) Change-Id: If7aae69f5171db67055ffe220bdff392caaa5d9f Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: http://review.coreboot.org/10826 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-07-14amd/rs780: Fix typoPatrick Georgi
Change-Id: I08f7251f8fc42b9028b1fdb830546f9922ef43aa Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Found-by: YongGon Kim <ilios86@gmail.com> Reviewed-on: http://review.coreboot.org/10914 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
2015-07-14cbmem: convert x86 timestamps on OpenBSDPatrick Georgi
Change-Id: I16bfe42a00d73209307655601edaa3a8ffc9c902 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/10905 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-14intel/sandybridge/gma: Add graphics PCI Device IDs 0x0162 and 0x0152Damien Zammit
Change-Id: Ide0fd757cdd31a5b5ff184f7ab2d48e62ea50015 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: http://review.coreboot.org/10896 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-14buildgcc: Show the archive URLPaul Menzel
In case of downloading errors, the URL is handy for analyzing the cause. Change-Id: I6874cdc3c881cfdd52c80f80323536c30723654b Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/10853 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <gaumless@gmail.com>
2015-07-14amd/fam10: Add k10temp ACPI thermal zone mixin.Tobias Diedrich
This ACPI thermal zone is applicable to AMD family 10 to 14 (and some 15) CPUs. It should not be used on boards for which errata 319 (The thermal sensor of Socket F/AM2+ processors may be unreliable) is applicable. AM3 and later should be fine. Derived from src/northbridge/amd/amdk8/thermal_mixin.asl Change-Id: Id036cbf4cd717c3320a720edc452945df2b5e072 Signed-off-by: <ranma+coreboot@tdiedrich.de> Reviewed-on: http://review.coreboot.org/10617 Tested-by: build bot (Jenkins) Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2015-07-13x86: flatten hierarchyStefan Reinauer
It never made sense to have bootblock_* in init, but pirq_routing.c in boot, and some ld scripts on the main level while others live in subdirectories. This patch flattens the directory hierarchy and makes x86 more similar to the other architectures. Change-Id: I4056038fe7813e4d3d3042c441e7ab6076a36384 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10901 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-07-13x86: Port x86 over to compile cleanly with x86-64Stefan Reinauer
Change-Id: I26f1bbf027435be593f11bce4780111dcaf7cb86 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Signed-off-by: Scott Duplichan <scott@notabs.org> Reviewed-on: http://review.coreboot.org/10586 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-07-13version: allow stating the coreboot revision in .coreboot-versionPatrick Georgi
If .git doesn't exist, try to fetch the coreboot version from a file, before falling back to a hard-code. Change-Id: Idee8019c9a2b766fe69535367614c5254498335a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10908 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-07-13superio/smsc: Add support for SMSC DME1737Jonathan A. Kollasch
Change-Id: If2ba9ca48c809fe4f7dc0595a3cb3df168d630fd Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: http://review.coreboot.org/10893 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-13superio/smsc/dme1737: copy superio/smsc/lpc47b397Jonathan A. Kollasch
Change-Id: I3218bfaaa64bcad54fe97c6f887025356ccc9356 Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: http://review.coreboot.org/10892 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-13tegra124/tegra210: Include stages.h in bootblock.cStefan Reinauer
Needed for the main() prototype Change-Id: I921a77d8b131b751291d3a279b23ee18b13eca8d Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10862 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-13tegra210: Fix coding style in clock.cStefan Reinauer
Change-Id: I1a8ce0b8ec291a5ddd8fdefcda24842e2a3c692d Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10861 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-13coreinfo: Fix build output (cosmetical)Stefan Reinauer
This patch aligns the output of coreinfo with the output of libpayload, and switches from using $(Q) to .SILENT Change-Id: I6c3cdda7febc02bab9195fc98f46490c0d478a9a Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10744 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2015-07-13smaug: Set LDO2 voltage to 1.8VFurquan Shaikh
LDO2 regulator is used as an always-on reference for the droop alert circuit. Set output voltage to match kernel settings. CQ-DEPEND=CL:284649 BUG=chrome-os-partner:42305 BRANCH=None TEST=Compiles successfully and boots to kernel prompt Change-Id: I5ef4e266d8ec278dadffa846af8dc49b6d18c37e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 611465f6248cba0ddce0083b431cb7ee17bc4b4c Original-Change-Id: I58cc473452b871392d813387707a0b8288e46561 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/284879 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/10900 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-07-13t210: Apply A57 hardware issue workaround during cpu startupFurquan Shaikh
Define custom stage_entry to apply workaround for A57 hardware issue for power on reset. It is observed that BTB contains stale data after power on reset. This could lead to unexpected branching and crashes at random intervals during the boot flow. Thus, invalidate the BTB immediately after power on reset. BUG=chrome-os-partner:41877 BRANCH=None TEST=Compiles successfully and reboot test does not crash in firmware for 10K iterations. Change-Id: Ifbc9667bc5556112374f35733192b67b64a345d2 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: bc7c2fec3c6b29e291235669ba9f22ff611064a7 Original-Change-Id: I1f5714074afdfee64b88cea8a394936ca848634b Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/284869 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/10899 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-13arm64: Define stage_entry as weak symbolFurquan Shaikh
This allows SoCs/CPUs to have custom stage_entry in order to apply any fixups that need to run before standard cpu reset procedure. BUG=chrome-os-partner:41877 BRANCH=None TEST=Compiles successfully Change-Id: Iaae7636349140664b19e81b0082017b63b13f45b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 498d04b0e9a3394943f03cad603c30ae8b3805d4 Original-Change-Id: I9a005502d4cfcb76017dcae3a655efc0c8814a93 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/284867 Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/10897 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-13arm64/a57: Move cortex_a57.h under include directoryFurquan Shaikh
BUG=chrome-os-partner:41877 BRANCH=None TEST=Compiles successfully Change-Id: I8a94176a3faacb25ae5e9eaeaac4011ddf5af6a1 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 802cba6f28a4e683256e8ce9fb6395acecdc9397 Original-Change-Id: I3a5983d4a40466bc0aa8ab3bd8430ab6cdd093cc Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/284868 Original-Reviewed-by: Yen Lin <yelin@nvidia.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/10898 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-13libpayload: Fix arithmetic precedence in div_round_up()Julius Werner
Well, this is just embarrassing... BRANCH=None BUG=None TEST=None Change-Id: I7c443d2100b6861d736320ac14c1bd9965937a66 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 455e3784882ea1b76bcf8e17724869e37d9c629d Original-Change-Id: Ia33e98aeaa8e78e3e3d2c7547e673a623ea86ce2 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/284596 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/10879 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Martin Roth <gaumless@gmail.com>
2015-07-13t210: Add TZDRAM_BASE param to BL31_MAKEARGSFurquan Shaikh
1. Make TTB_SIZE Kconfig option 2. Add Kconfig option for maximum secure component size 3. Add check in Makefile to ensure that Trustzone area is big enough to hold TTB and secure components 4. Calculate TZDRAM_BASE depending upon TTB_SIZE and TZ_CARVEOUT_SIZE BUG=chrome-os-partner:42319 BRANCH=None Change-Id: I9ceb46ceedc931826657e5a0f6fc2b1886526bf8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a425d4978a467b157ea5d71e600242ebf427b5bb Original-Change-Id: I152a38830773d85aafab49c92cef945b7c4eb62c Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/284074 Original-Reviewed-by: Varun Wadekar <vwadekar@nvidia.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/10878 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-13coreinfo: fix compilationStefan Reinauer
- extra rule for config.h creation - include kconfig.h from libpayload - libpayload symbols are conflicting with gcc builtins (e.g. log2) - ALIGN() is already defined in libpayload these days - move libpayload build directory under build/ Change-Id: I2aefdde26853253d58f6cf6e186e784871c1cb5b Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10717 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-13intel raminit: improve loggingPatrick Rudolph
Print the old timB value to observes changes made. Change-Id: Iecec4918f1d95560b6e7933a169ccce83fcf073d Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: http://review.coreboot.org/10891 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
2015-07-13intel raminit: fix timB high adjust calculationPatrick Rudolph
Issue observed: Any memory DIMM placed in channel0 slots stops at "c320c discovery failed". The same memory DIMM works when placed in channel1 slots. Test system: * Intel Pentium CPU G2130 * Gigabyte GA-B75M-D3H * DIMMs: * elixir 1GB 1Rx8 PC3-10600U M2Y1G64CB88A5N * crucial 2GB 256Mx64 CT2566aBA160BJ * corsair 8GB CMZ16GX3M2A1866C9 Problem description: In case of good timmings (all bits are set) an offset of 3*64 was applied. The following test (c320c discovery) failed only on those byte-lanes. Problem solution: Don't modify timB in case of good timings measured. Final testing result: The system boots with every DIMM placed in channel 0 slots. Change-Id: Iea426ea4470640ce254f16e958a395644ff1a55c Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: http://review.coreboot.org/10889 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
2015-07-13intel raminit: whitespace fixesPatrick Rudolph
Remove whitespace errors. Change-Id: If69244a5d47424e3e984fdf782ea9d2d3c466d86 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: http://review.coreboot.org/10888 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
2015-07-13intel sandybridge: add VGA pci device idPatrick Rudolph
Add VGA pci device id 0x0152 for Intel IvyBridge CPUs. Test system: * Intel Pentium CPU G2130 * Gigabyte GA-B75M-D3H Change-Id: Ia546fdf0cc3bbd4c0ef6b5fd969232f105bceb22 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: http://review.coreboot.org/10798 Tested-by: build bot (Jenkins) Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-09 22:00:19 +0000