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2020-06-10nb/intel/x4x: Drop unused `pci_ops.h` includeAngel Pons
Tested with BUILD_TIMELESS=1, Intel DG43GT does not change. Change-Id: I58162865d596574b8a52447624f0102b8dceefa4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42156 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-10nb/intel/pineview: Use PCI bitwise opsAngel Pons
Tested with BUILD_TIMELESS=1, Foxconn D41S does not change. Change-Id: Idd6a11e95669f0a8fe9bd52359a9822b524c878c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42192 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-10amd/common: Add the macro definition for patch level MSRZheng Bao
This MSR is used for detecting if the micro code is applied successfully. Change-Id: I060eb1a31f3358341ac0d5b9105e710c351f2ce8 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42212 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-10sb,soc/amd, ACPI: Do not override FADT preferred_pm_profileKyösti Mälkki
Setting preferred_pm_profile under sb/ or soc/ overrides the default determined from SYSTEM_TYPE_xx (or possibly SMBIOS_ENCLOSURE_TYPE with followup work). This is not desireable. With the overrides removed, AMD platforms will switch from PM_UNSPECIFIED to PM_DESKTOP as their preferred profile. Boards need to either select a pre-defined SYSTEM_TYPE_xx or provide board-specific mainboard_fill_fadt() should they need to change this. As they already select SYSTEM_TYPE_LAPTOP, following boards will change to PM_MOBILE: google/kahlee hp/pavilion_m6_1035dx lenovo/g505s Change-Id: I45c4a495a4bf3422adae9e22a6e436adef252e77 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42032 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-06-10sb/amd/agesa,cimx,pi: Select COMMON_FADTKyösti Mälkki
Change-Id: Ib6a0f8a3beb3d02dfd90234b1af6eccd3cde21bb Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41924 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Mike Banon <mikebdp2@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-10soc/amd/stoneyridge,picasso: Select COMMON_FADTKyösti Mälkki
Change-Id: I0c98bf7f88c33691401ebc6b174d959dd515dd11 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41921 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-10mb,sb/amd/cimx/sb800: Remove FADT_PM_PROFILEKyösti Mälkki
The platform_cfg.h files under mainboard/ are a legacy configuration mechanism used with AGESA family14 boards. With this change following boards will have FADT preferred_pm_profile changed from PM_UNSPECIFIED to PM_DESKTOP: amd/inaqua amd/south_station amd/union_station asrock/e350m1 Change-Id: Ic28761eb238dbbaf3e8f820a29ec64b89f12bf53 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42031 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-06-10sb,soc/amd: Remove FADT_PM_PROFILEKyösti Mälkki
This was copy-paste from fam14 configuration mechanism using platform_cfg.h files. Change-Id: I7fdd89a8b1fe9c7e558841e24fb832d0cffd3454 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42030 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-10sb/intel, ACPI: Do not override FADT preferred_pm_profileKyösti Mälkki
Setting preferred_pm_profile under sb/ overrides the default determined from SYSTEM_TYPE_xx (or possibly SMBIOS_ENCLOSURE_TYPE with followup work). This is not desireable. Boards need to either select a pre-defined SYSTEM_TYPE_xx or provide board-specific mainboard_fill_fadt() should they need to change this. As they already select SYSTEM_TYPE_LAPTOP, following boards will maintain PM_MOBILE: lenovo/t400 lenovo/x200 roda/rk9 Following will change to PM_DESKTOP: aopen/dxplplusu asus/p2b emulation/qemu-i440fx emulation/qemu-q35 Change-Id: I2986eb0a8abc94507e9797cc8b64611ae4bd888a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42186 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-06-10sb/intel/i82801ix: Select COMMON_FADTKyösti Mälkki
Change-Id: Iffdce450b1d4c9984ec5efe11eff62bf9184e314 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41922 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-10sb/intel/i82371eb: Select COMMON_FADTKyösti Mälkki
Change-Id: I0b1f3e16b2a801e5fcf5f96d59922f6231d73636 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41925 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-10aopen/dxplplusu,intel/i82801dx: Select COMMON_FADTKyösti Mälkki
Move existing fadt.c file under southbridge. Change-Id: Ie2fdc715e4d1af347d25b51e83189f28cd9af014 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41923 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-09soc/amd/picasso/acpi/sb_fch: use local variable in _CRS methodsFelix Held
Use a local variable for the ResourceTemplate in the _CRS methods instead of the RBUF object. When using RBUF, iasl complained that the _CRS methods need to be serialized, since objects were created in there. Since those are only used as local variables, just use local variables for this. TEST=iasl stops complaining about those methods not being serialized and Linux still boots and there aren't any related ACPI errors or warnings. Change-Id: Ic43fcaed5a8b19dbd5634c17f34a159803ba8577 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42207 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-09mb/google/volteer: move volteer-specific GPIOs to variant gpio.cNick Vaccaro
- Move the GPIOs that are likely to be volteer-specific (mostly peripherals) to reside in variants/volteer/gpio.c so that variants don't have to override too many GPIO settings. - Modify malefor's gpio.c to adjust for the changes to baseboard's gpio.c. - Remove unused GPP_C3 (USB4_SMB_SCL) and GPP_C4 (USB4_SMB_SCA) settings. - Remove unused GPP_D9, GPP_D10, GPP_D11, and GPP_D12 settings. - Remove unused GPP_E8 (SLP_S0IX), COEX, WWAN, and SNDW related settings for malefor. - Remove unused GPP_R4 (HDA_RST_L) setting. BUG=b:157597158 TEST="emerge-volteer coreboot chromeos-bootimage", flash and boot volteer SKU4 to kernel. Change-Id: Ib2f384f539d55a3a8d4a7608336ef22aca3d8c4f Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41797 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-06-09soc/intel/tigerlake: Set FSPS UPD ITbtConnectTopologyTimeoutInMsJohn Zhao
The Connect Topology Command(CNTP) is sent with default timeout value (0x1388) along with FW CM. The CNTP is supposed to be skipped while using SW CM. While transition from FW CM to SW CM, the default timeout value could cause boot time delay up to ~10 seconds. Set this FSPS UPD ITbtConnectTopologyTimeoutInMs to be 0 in order to avoid the 10 seconds delay. Future FSP release will evaluate this ITbtConnectTopologyTimeoutInMs value. While FSP finds this UPD value being 0, FSP will skip sending CNTP. BUG=b:155893566 TEST=Built image with SW CM Thunderbolt firmware and verified no outstanding delay time while using FSP v3197 during boot to kernel. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I47e3519fd818cb56e6abd16464d8370ffddabc5b Reviewed-on: https://review.coreboot.org/c/coreboot/+/42056 Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-09vendorcode/intel/fsp: Update Tiger Lake FSP Headers for v3197Srinidhi N Kaushik
Update FSP headers for Tiger Lake platform generated based FSP version 3197 to include below additional UPD: FSPS: ITbtConnectTopologyTimeoutInMs Signed-off-by: John Zhao <john.zhao@intel.com> Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: I06d605b156c1e6f90921c20e0b8fbbe4d64916ce Reviewed-on: https://review.coreboot.org/c/coreboot/+/42046 Reviewed-by: Divya Sasidharan <divya.s.sasidharan@intel.corp-partner.google.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-09ACPI: Move redundant FADT reserved entryKyösti Mälkki
Change-Id: I35f66cdad6b8bedf4337aa8e5af7b0f1b53fe674 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42033 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-09nb/intel/x4x: Use PCI bitwise opsAngel Pons
Tested with BUILD_TIMELESS=1, Intel DG43GT does not change. Change-Id: I1bb7a7fd808cbbb45efbbfb9581c6a948323a48f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42155 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-09nb/intel/haswell: Use PCI bitwise opsAngel Pons
Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 does not change. Change-Id: I99379299f7e744a3e906bdbc46d55060d9c75d6a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42153 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-09soc/intel/tigerlake: Increase heap sizeDuncan Laurie
With SoundWire and USB4 enabled some boards are running out of memory with all of the ACPI devices and properties. Increase the heap size to accommodate. BUG=b:147462631 TEST=Successfully boot on volteer SKU5 board with SoundWire enabled, before boot was failing with "Error! memalign: Out of memory" Signed-off-by: Duncan Laurie <dlaurie@google.com> Change-Id: I0245bdfad93b381871514578e66640e7fe6fa5c4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42211 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2020-06-09mb/google/hatch/vr/puff: Set up PL2 and PsysPL2Gaggery Tsai
This patch adds correct PL2 baseline setting and PsysPL2 for different SKUs. There is no way to identify the barral jack power rating, the assumption is following that ships with the product: 1. i3/i5/i7: 90W BJ 2. Celeron/Pentium: 65W BJ For Type-C adapter, we don't have Pcritcial (10ms) data, keeps the original settings as 90% of adapter rating for PsyspL2/PL4 and PL2 as min(PL2, 0.9n) where n is adapter rating power. BUG=b:143246320 TEST=Run with U62 and Celeron CPU and ensure the PL2 settings are correct Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Change-Id: If7de614d58366158a566563990ee1ecc8c0110bc Reviewed-on: https://review.coreboot.org/c/coreboot/+/41555 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-06-09SMBIOS: Remove Kconfig SYSTEM_ENCLOSURE_TYPEKyösti Mälkki
This gets rid of the magic numbers in Kconfig. Change-Id: Ibee033b6c99e3131bb323f0d86d306dcd82f9b45 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42139 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-06-09mb/scaleway/tagada: Move override of SMBIOS_ENCLOSURE_TYPEKyösti Mälkki
Change-Id: Iaefeccadb82106667a5108a2c77e538474ae18c2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42138 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-06-09Revert "sb/amd/cimx/sb800: Fix 16-bit read/write PCI_COMMAND register"Nico Huber
This reverts commit 04506e2987162ec0f280afddd6f4acac070bbf15. Turned out that `dev->command` is only a `u8` and the way it's used here is wrong: It is not supposed to reflect the state of the register but only gathers (lower) bits to be enabled during allocation. Change-Id: Iacd2b753939e8adcf5aedd4b9cf101638a324aa6 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42163 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-09mb/google/poppy: Add retail namesAngel Pons
Taken from Chrome OS update information. Looks like nami encompasses many different devices, which would not fit in one line, so skip it. Change-Id: I53405cba269cbfc25bd4618777b946500f173e7e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42143 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2020-06-09MAINTAINERS: Add myself as some northbridges' maintainerAngel Pons
I've got hardware to test things on these northbridges, and I am quite familiar with their code. Change-Id: Ied5adbb8bad94291a1843531be8a0923464d6212 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42128 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-06-09MAINTAINERS: Add myself to x4x and pineview northbridgesAngel Pons
Change-Id: I42b1e8670f4e2ddfea7d473421e86649211eae86 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42127 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-06-09MAINTAINERS: Add myself as some mainboards' maintainerAngel Pons
I've ported some more mainboards, but forgot to update MAINTAINERS. Change-Id: I46d2cd3737d584156e8bf49a0d7ab6b0327e0063 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42126 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-06-09nb/intel/sandybridge: Use MCHBAR bitwise opsAngel Pons
Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 does not change. Change-Id: If16d8c4aef3dfd1dbeaf48d6855dd4c0ef328168 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42151 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-06-09nb/intel/sandybridge: Use PCI bitwise opsAngel Pons
Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 does not change. Change-Id: If7f3f06cd3524790b0ec96121ed0353c89eac595 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42150 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-06-09nb/intel/gm45/iommu.c: Fix regression when updating PCI commandAngel Pons
Commit 5ac723e (nb/intel: Fix 16-bit read/write PCI_COMMAND register) uses `pci_read_config8` to read the PCI command register, which does not correspond with what has been stated in the commit message. Moreover, it potentially breaks things, as the upper byte of the PCI command register is now being cleared. So, restore the original behaviour of the code, using 16-bit accesses. Fixes: 5ac723e (nb/intel: Fix 16-bit read/write PCI_COMMAND register) Change-Id: Id2c42ea8551a2fa2fa5c64e8fff8940d8304fbe0 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42148 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-06-09pci_ops.h: Turn and/or ops into update wrappersAngel Pons
Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 does not change. Change-Id: I2d3779967f357dd380928869c630a1996fdd60ec Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42147 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-06-09include/device/pci_ops.h: Add bitwise AND opsAngel Pons
For the sake of completeness, we should provide these operations. Change-Id: Ia28af94ec86319c7380d8377f7e24e5cdf55dd9c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42145 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-08mb/google/dedede: Default spk_en gpio to lowUsha P
The max98357a_platform_driver will turn on/off the speaker enable gpio based on use, so configure it low to save power. BUG=None TEST=Built dedede and tested speaker playback working. We are seeing a power saving of ~10mW. Change-Id: I070679457b06cb82633c1197b893a5d89c8b2cf0 Signed-off-by: Usha P <usha.p@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41853 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
2020-06-08soc/amd/picasso: solve MTRRs only from 4GiB and belowAaron Durbin
Use x86_setup_mtrrs_with_detect_no_above_4gb() to only solve the MTRR solution for memory up to 4GiB. This assumes 4GiB to TOM2 is marked as writeback in sys_cfg MSR. BUG=b:155426691 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: Ib8358b614682f6a97278f3a60b5ada5e607965af Reviewed-on: https://review.coreboot.org/c/coreboot/+/41898 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-08soc/amd/picasso: remove save/restore MTRRs around FSP-MAaron Durbin
AGESA FSP-M implementation is now not updating MTRRs out from under the caller. As such, remove the save/restore of MTRRs from the FSP-M call. BUG=b:155426691 Change-Id: I14f3b18dd373ce17957ef3857920e1c4e2901bbe Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42104 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-06-08soc/amd/picasso: establish full early caching memory mapAaron Durbin
The PSP does the memory training and setting up of MSRs for TOP_MEM and TOM2. Set caching up for all the DRAM areas: Enable WB caching for 1MiB->TOP_MEM, 4GiB->TOM2. Enable WC caching fro 0->1MiB except 0xa0000->0xc0000. BUG=b:155426691 Change-Id: I83916a220ea4016d4438dd4fb5be82dec5506f80 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42103 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-06-08util/amdfwtool: Add option for setting PSP/FW shared memory locationMartin Roth
This tells the PSP where in main memory to copy the vboot workbuf. BUG=b:152576063 TEST=Build sharedmem destination into AMDFW, verify shared memory gets placed at that location. Signed-off-by: Martin Roth <martin@coreboot.org> Original-Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Change-Id: Ie1e955e22632ca5cf146ac6eec0407091e81f519 Original-Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2148830 Original-Reviewed-by: Simon Glass <sjg@chromium.org> Change-Id: Id324403afa6d5a5a65ce4709be31e7f16e038da0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42044 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-08util/amdfwtool: update to allow building in any locationMartin Roth
For the verstage-on-PSP implementation, we need 2 additional copies of the AMD firmware tables at non-standard locations. These are for RW-A & RW-B fmap regions. This change allows us to build the AMD firmware tables into those regions. BUG=b:148767300 TEST=boot with psp_verstage, verify boot location Signed-off-by: Martin Roth <martin@coreboot.org> Original-Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Change-Id: I2b591b50e9b179fdfaead46ff93722fa2a155e9c Original-Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2144534 Original-Reviewed-by: Simon Glass <sjg@chromium.org> Change-Id: I7f841db8617b953dc671a9c12576145f85263581 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42043 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-08superio/nuvoton/nct6776: Reflow `pnp_dev_info` arrayAngel Pons
Each PnP device now fits in a single 96-character line. With BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical. Change-Id: Ice65ce2504877c40962de7c26e01529d53d75c8e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42132 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-06-08spi: Remove non_volatile flag from block protection interfaceDaniel Gröber
Only Winbond parts seem to support making status register writes volatile. So this flag should not be exposed in the generic interface. Change-Id: Idadb65ffaff0dd7809b18c53086a466122b37c12 Signed-off-by: Daniel Gröber <dxld@darkboxed.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41746 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-08spd/lp4x: Set manufacturer part name to blank (0x20)Furquan Shaikh
As per JEDEC spec, manufacturer part name should be set to blank (0x20). This change updates gen_spd.go to set bytes 329-348 as 0x20 and regenerates SPDs for TGL and JSL. Change-Id: I6af18d89afd7264cec7e54b38e95df83d55aa058 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42023 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-08ec/google/chromeec: Append connector device to *-switch propertiesTim Wawrzynczak
The orientation, etc. -switch properties are supposed to use the connector device (underneath the MUX device) that belongs to the port number in question. This patch finds the CONx device and uses that to pass to the acpigen API. BUG=b:154620502 TEST=on Volteer, dump SSDT and verify the *-switch properties point to \_SB.PCI0.PNC.MUX.CON0 and CON1 Change-Id: Ie65c2d750f3d9f83285e0e4cc9642110c804bbad Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42045 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2020-06-08device: Add a disabling PCIe device bus master functionJohn Zhao
A function pci_dev_disable_bus_master() is created. This function can be used to disable Thunderbolt PCIe root ports, bridges and devices for Vt-d based security platform at end of boot service. BUG=None TEST=Verified PCIe device bus master enable bit is cleared. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: Ie92a15bf2c66fdc311098acb81019d4fb7f68313 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41042 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-06-08mb/google/dedede: source soc_common_config from variants overridetreeMaulik V Vaghela
All variants are overriding soc_common_config, so source it from overridetree and remove entry from baseboard devicetree. Only keeping chipset lockdown config in baseboard which will be common across all the variants. BUG=None BRANCH=None TEST=Checked code compilation and lockdown config is applied to all variants Change-Id: I23714b721a6bb0bac785f046586790a98dc5b646 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42125 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
2020-06-07vendorcode/amd: Remove duplicate assignmentPatrick Georgi
Change-Id: I8a39e862176cd1c8a14424eb6d2bf7edabd36adb Found-by: Silvio Cesare, https://twitter.com/silviocesare/status/1268784333029965824 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42101 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-07acpi: Rename motherboard_fill_fadt() to mainboard_fill_fadt()Kyösti Mälkki
The prefix mainboard_ was used everywhere else. Change-Id: Ie576fd47301aa484cb1396e0c6f7260b7698af4d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42007 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-07mb/*: Remove some fadt.c filesKyösti Mälkki
Change-Id: I13ed3b6e8608c37c1ebe51838e4052f89a638d83 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41947 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-07soc/intel/baytrail,braswell,broadwell,quark: Select COMMON_FADTKyösti Mälkki
Some of the boards do not select SYSTEM_TYPE_LAPTOP or _CONVERTIBLE so their FADT preffered_pm_profile would change from PM_MOBILE without the added overrides here. Change-Id: I04b602b2c23fbd163fcd110a44ad25c6be07ab66 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41920 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-07drivers/mrc_cache: generate debug messages for MRC cache updateJonathan Zhang
When MRC cached data update is performed, messages are written to event log, which is flash based. For system that does not have flash based event log, the messages are lost. Added corresponding BIOS_DEBUG messages. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: I1ef4794151fea7213c8317ddc898b0e37da280b5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41981 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-07soc/intel/tigerlake/acpi: Update gpio_op.asl to ASL2.0 syntaxVenkata Krishna Nimmagadda
This change updates gpio_op.asl to use ASL2.0 syntax. This increases the readability of the ASL code. BUG=none BRANCH=none TEST="BUILD for Volteer" Signed-off-by: Venkata Krishna Nimmagadda <venkata.krishna.nimmagadda@intel.com> Change-Id: Ib54b3f7da828ce8d232fcea0639077970638f610 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41800 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Venkata Krishna Nimmagadda <Venkata.krishna.nimmagadda@intel.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-06-07mb/pcengines/apu2: Change GPIO configuration functionsKyösti Mälkki
The definitions of GPIO_xx equal IOMUX_GPIO_xx shifted by two. Change-Id: I0ee821c71c88bf535122a9526862a9d1e68bd755 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42038 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2020-06-07mb/pcengines/apu1: Use fixed acpimmio_baseKyösti Mälkki
Change-Id: Iaaa0cc0b486145517939f46943f2fee82053d98e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42037 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2020-06-07sb/intel/bd82x6x: Align some ME functionsAngel Pons
This eliminates the differences in the first part of the file. Change-Id: Ifb7d57da08e02664a28819e65bc8e9697ed38c4c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42009 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-07soc/amd/picasso/cpu.c: Make comment clearerRaul E Rangel
Explain why the flash is no longer cached. BUG=none TEST=none Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ibb18f363a215d665d53a722ed76896a75d1c5608 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42108 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-07soc/intel/jasperlake: Add JSL PMC as 'hidden' PCI deviceTim Wawrzynczak
This change allows treating the PMC as a 'hidden' PCI device on Jasper Lake, so that the MMIO & I/O resources can be exposed as belonging to this device, instead of the system agent and LPC/eSPI. Change-Id: Ie07987c68388d03359c43f64a849dc6e3f94676e Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42018 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-07mb,soc/intel: Rename acpi_fill_in_fadt() to acpi_fill_fadt()Kyösti Mälkki
Change-Id: I9025ca3b6b438e5f9a790076fc84460342362fc2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41919 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-07acpi,mb/*: Use motherboard_fill_fadt()Kyösti Mälkki
By vendor choice override fadt->preferred_pm_profile here. Change-Id: I0453c0edc9aeb86cf4f5d912613b8fa8beb63ab4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41917 Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-07acpi,soc/intel: Make soc/motherboard_fill_fadt() globalKyösti Mälkki
Change-Id: Iad7e7af802212d5445aed8bb08a55fd6c044d5bf Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41916 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-07soc/amd/picasso: Remove unnecessary includes from pmutil.cMartin Roth
While working on psp_verstage, I noticed that this file had a number of unnecessary includes. Remove them. BUG=b:158124527 TEST=Build & boot psp_verstage on trembyle Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I32188e2dda39ece9dc98d0344824d997a2e80303 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42065 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-06src: Use pci_dev_ops_pci where applicableAngel Pons
Change-Id: Ie004a94a49fc8f53c370412bee1c3e7eacbf8beb Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41944 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-06-06payloads/external: s/PROMT/PROMPT/gAngel Pons
Change-Id: Id305d9edecac9e9cd305301e9dc5af6678ef7528 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41831 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-06-06mb/asrock/b85m_pro4: Make VGA work on LinuxAngel Pons
Currently, having libgfxinit try to enable VGA will result in a hang. On the Asrock B85M Pro4, DDI E (VGA) was not being enabled in coreboot, so it did not hang. However, this renders Linux's i915 driver unable to use VGA at all. In absence of monitors with digital inputs, this is bad. To work around this problem, mark DDI E as enabled, and comment out VGA from gma-mainboard.ads for the time being. This allows one to use a VGA monitor, even if it only works after Linux drivers have taken over. Change-Id: Idd6a9e8515a1065ad3c6ddf136896fef9f0fa732 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42099 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Michael Niewöhner
2020-06-06Doc/mb/gigabyte/ga-h61m-s2pv: Fix in-circuit programmingAngel Pons
It is NOT supported. The board is not meant to be flashed externally. Change-Id: If422810e84355cb94004e5ca2b95d239804699d2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42057 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Michael Niewöhner
2020-06-06mb/razer/blade_stealth_kbl: Remove duplicate ACPI power button devicePaul Menzel
The ASL code is copied from the Purism Librem 13v3, and is not needed, as the standard fixed power button is used. It was removed for the Pursim devices in commit 2d977b2dcb (mb/purism: remove duplicate ACPI power button). Change-Id: I18155ea672e7309b367ad4170f2f00f0b3e557db Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41019 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mimoja <coreboot@mimoja.de> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-06-06mb/51nb/x210: Remove duplicate ACPI power button devicePaul Menzel
This is copied from the Purism Librem 13v3, and is not needed, as the standard fixed power button is used. It was removed for the Pursim devices in commit 2d977b2dcb (mb/purism: remove duplicate ACPI power button). Change-Id: I8fe19b8fbcc11d859a75b3dc6b9bcc42c80d13f1 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41018 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rafael Send <flyingfishfinger@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-06-06amd/agesa/hudson boards: Get rid of power button devicePaul Menzel
Port commit d7b88dcb (mb/google/x86-boards: Get rid of power button device in coreboot) to AMD AGESA Hudson boards. No idea, if this is correct for the two laptops. The Lenovo G505s also incorrectly defines two power buttons. [ 0.911423] input: Power Button as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0C0C:00/input/input1 [ 0.911434] ACPI: Power Button [PWRB] [ 0.911493] input: Power Button as /devices/LNXSYSTM:00/LNXPWRBN:00/input/input2 [ 0.912326] ACPI: Power Button [PWRF] If the generic power button device is needed, the POWER_BUTTON flag should be set in FADT. The GPE ACPI code seems to originate from commit 806def8c (I missed the svn add on r3787. These are the additional files., Add AMD dbm690t ACPI support.), and was copied over. Change-Id: I88950e15faf1b90ca6e688864bac40bf9779c32e Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40754 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mike Banon <mikebdp2@gmail.com>
2020-06-06amd/pi/hudson boards: Get rid of power button devicePaul Menzel
Port commit d7b88dcb (mb/google/x86-boards: Get rid of power button device in coreboot) to AMD AGESA Hudson boards (SOUTHBRIDGE_AMD_PI_AVALON). The GPE ACPI code seems to originate from commit 806def8c (I missed the svn add on r3787. These are the additional files., Add AMD dbm690t ACPI support.), and was copied over. Change-Id: Ibeec73c15f2282f7ab0be88f96693bcb551b3e45 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40753 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2020-06-06soc/amd/picasso: Add device operations for UART MMIO devicesFurquan Shaikh
This change adds device_operations for UART MMIO devices that provides following operations: 1. uart_acpi_name: Returns ACPI name of UART device. Generation of UART device node is not yet moved to SSDT, but will be done in follow-up CLs. 2. scan_bus: Uses scan_static_bus to scan devices added under the UART devices. This allows mainboard to add devices under the UART MMIO device. Change-Id: I18abbe88952e7006668657eb1d0c177e53e95850 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42068 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-06ec/google/wilco: Always use current value of battery status bitMathew King
According to the Wilco EC spec the BTSC bit of PWSR is always cleared when PWSR is read so that battery status change events are only triggered one time. Testing of the Wilco EC has verified this behavior. This changes the way in which the battery status change bit is used from checking the bit state against the previous value to always issuing a battery event when the BTSC bit is set. The other bits in PWSR indicate state directly and do not behave like the BTSC bit. BUG=b:157113138 TEST=Deploy on Drallion and verify that battery events are generated BRANCH=drallion, sarien Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I8fbf2ee1158ddd790b04a20b1eb27a6cce4f5c81 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42017 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-06-06src: Remove unused 'include <cpu/x86/mtrr.h>'Elyes HAOUAS
Change-Id: I3f08b9cc34582165785063580b3356135030f63e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41782 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Guckian
2020-06-06cpu/intel/haswell: Remove unused 'include <cpu/x86/bist.h>'Elyes HAOUAS
Change-Id: I5156eb97648927e5fe6e467abb8e3e055a231fec Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41686 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-06-06mb/intel/tglrvp: Add support for RT 1308Shaunak Saha
Add support for RT 1308 audio amplifier in TGLRVP. We are using the i2c generic driver here to generate the SSDT file. Datasheet:ALC-1308-CG-version-08. BUG=none BRANCH=none TEST=Build and boot tglrvp successfully. In kernel console use the "aplay -l" command to check soundcard is listed. Change-Id: I41d205a3ab87db85baf49e9e8a582c226ba5832d Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41808 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2020-06-06mb/google/octopus/variants/garg: Add G2Touch touchscreen supportTony Huang
BUG=b:156564296 BRANCH=octopus TEST=emerge-octopus coreboot Change-Id: I99b04fec88da481e21b7a05807a4f1edeb3a5bdf Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42036 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2020-06-06soc/amd/picasso: Use MSR_CSTATE_ADDRESSRaul E Rangel
This is a standard MSR. No reason for picasso to define its own. BUG=b:147042464 TEST=Boot to OS on trembyle Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Idcfae356d35ff08ced4b7e5ccfc132a8492a6824 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42087 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-06soc/amd/picasso: Remove call to setup_bsp_ramtopRaul E Rangel
We don't use amd_setup_mtrrs, bsp_topmem or bsp_topmem2 in picasso. BUG=b:147042464 TEST=Boot to OS on trembyle Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I1941934975dfea4f189347811b003a33996c887a Reviewed-on: https://review.coreboot.org/c/coreboot/+/42086 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-06-06src: Remove unused '#include <cpu/x86/smm.h>'Elyes HAOUAS
Change-Id: I1632d03a7a73de3e3d3a83bf447480b0513873e7 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41685 Reviewed-by: David Guckian Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-06drivers/pc80/rtc: Drop ARCH_X86 guard in headerKyösti Mälkki
Change-Id: I03c25ad5d9864406e1a021e39a5736ac72c8825a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38197 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-06chromeos/cr50_enable_update.c: Modify recovery flow for cr50Edward O'Callaghan
Enable Cr50 update in recovery mode, so that we can at least still update the process for most cases (that an update is pending in recovery mode is not impossible but should be unlikely in the field). Leave manual recovery unaffected so at least that would still work even if Cr50 wedges in a weird way that it thinks it has an update on every boot or something. Setting the recovery_reason to VB2_RECOVERY_TRAIN_AND_REBOOT allows the update to be applied. BUG=b:154071064 BRANCH=none TEST=builds Thanks to Julius Werner for the suggested fix. Change-Id: Iba341a750cce8334da4dcf6353ca8cd1268d170f Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41988 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-06-06soc/intel/tigerlake: Add CPU ID for TGL B0Jamie Ryu
Reference: - TGL User Guide #613584 Rev 2.2 - TGL User Guide #605534 Rev 1.0 BRANCH=none BUG=none TEST=build and boot tglrvp Change-Id: I5da80fd4ad321b1ded369c2b6c039b73fcb3773e Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41516 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-06sb/amd/cimx/sb800: Fix 16-bit read/write PCI_COMMAND registerElyes HAOUAS
Change-Id: I779387fb0c9d3ad6e16d4ccfc39c38dfe6620345 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40806 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-06-06mb/google/dedede/var/wheelie: Add memory parts and generate DRAM IDsFurquan Shaikh
This change adds memory parts used by variant wheelie to mem_list_variant.txt and generates DRAM IDs allocated to these parts. BUG=b:157862308 Change-Id: I53f6f5c832cd40068a6d4379ace849f6e8ad7a91 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41990 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-06mb/google/dedede: Drop .spd.hex files from spd/Furquan Shaikh
Now that dedede is moved to using the auto-generated SPDs, we no longer need the .spd.hex files in spd/ folder. Hence, this change drops the files. Change-Id: I026b3c61a2a88a7cd2c9842a26eb336324853add Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41882 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-06mb/google/dedede: Switch to using auto-generated SPDsFurquan Shaikh
This change switches dedede and family to using auto-generated SPDs obtained using gen_spd.go and gen_part_id.go. Change-Id: I6fadae0abcfb6e50d3cc502098ace9b668667a51 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41881 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-06mb/google/dedede: Drop selection of GENERIC_SPD_BINFurquan Shaikh
GENERIC_SPD_BIN assumes that the SPDs are all placed in mainboard and have .spd.hex as the suffix. Disable GENERIC_SPD_BIN for dedede as it already provides its own rules for SPD inclusion. In follow up changes, GENERIC_SPD_BIN can be re-enabled by updating gen_spd.go tool to use similar suffixes and allowing different paths to be provided for SPD by mainboard. Change-Id: If10144e0b2bd67884af69f60e5117e388a3ae5da Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42054 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-06mb/google/dedede/var/waddledoo: Use auto-generated Makefile.inc using ↵Furquan Shaikh
gen_part_id.go This change adds mem_list_variant.txt that contains the list of memory parts used by waddledoo and Makefile.inc generated by gen_part_id.go using mem_list_variant.txt. In the final change of the series, all dedede variants will be switched from using the current SPDs to new auto-generated SPDs. Differences in auto-generated SPD from current SPD are as follows: Part: MT53E512M32D2NP-046 WT:E Byte# Current New Explanation 4 0x15 0x16 This part has only 1 die. Hence, density per die is 16Gb. 6 0x90 0x04 1 die in package and 2 channels per die. 9 0x40 0x00 Unused by MRC. 19 0x0F 0xFF As per JEDEC spec, tckMax should be 100ns. So, value should be 0xFF as per datasheet. 123 0x00 0xE5 Fine offset for taa. Expected value is 0xE5 as per datasheet. 125 0xE1 0xE0 Fine offset for tckMin. As per datasheet tckMin is 0.468ns. So, this comes out to be 0xE0. Additionally, manufacturer name bytes are set to 0. Part: NT6AP256T32AV-J2 Waddledoo started assigning DRAM part IDs from 1. So, this change fills in Nanya part as ID 0 (though it is currently unused). Change-Id: I3879c4f3ad942eb349b52aad397333f576599bbd Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41880 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-06-06mb/google/dedede/var/wheelie: Use auto-generated Makefile.inc using ↵Furquan Shaikh
gen_part_id.go This change adds mem_list_variant.txt that contains the list of memory parts used by wheelie and Makefile.inc generated by gen_part_id.go using mem_list_variant.txt. In the final change of the series, all dedede variants will be switched from using the current SPDs to new auto-generated SPDs. Differences in auto-generated SPD from current SPD are as follows: Part: MT53E512M32D2NP-046 WT:E Byte# Current New Explanation 4 0x15 0x16 This part has only 1 die. Hence, density per die is 16Gb. 6 0x90 0x04 1 die in package and 2 channels per die. 9 0x40 0x00 Unused by MRC. 19 0x0F 0xFF As per JEDEC spec, tckMax should be 100ns. So, value should be 0xFF as per datasheet. 123 0x00 0xE5 Fine offset for taa. Expected value is 0xE5 as per datasheet. 125 0xE1 0xE0 Fine offset for tckMin. As per datasheet tckMin is 0.468ns. So, this comes out to be 0xE0. Additionally, manufacturer name bytes are set to 0. Change-Id: If307bfb1d376e32af08af4f020f9e125f6a415dd Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41879 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-06-06mb/google/dedede/var/waddledee: Use auto-generated Makefile.inc using ↵Furquan Shaikh
gen_part_id.go This change adds mem_list_variant.txt that contains the list of memory parts used by waddledee and Makefile.inc generated by gen_part_id.go using mem_list_variant.txt. In the final change of the series, all dedede variants will be switched from using the current SPDs to new auto-generated SPDs. Differences in auto-generated SPD from current SPD are as follows: Part: MT53E512M32D2NP-046 WT:E Byte# Current New Explanation 4 0x15 0x16 This part has only 1 die. Hence, density per die is 16Gb. 6 0x90 0x04 1 die in package and 2 channels per die. 9 0x40 0x00 Unused by MRC. 19 0x0F 0xFF As per JEDEC spec, tckMax should be 100ns. So, value should be 0xFF as per datasheet. 123 0x00 0xE5 Fine offset for taa. Expected value is 0xE5 as per datasheet. 125 0xE1 0xE0 Fine offset for tckMin. As per datasheet tckMin is 0.468ns. So, this comes out to be 0xE0. Additionally, manufacturer name bytes are set to 0. Part: NT6AP256T32AV-J2 Byte# Current New Explanation 4 0x14 0x15 This part has only 1 die. Hence, density per die is 8Gb. 6 0x90 0x04 1 die in package and 2 channels per die. Manufacturer name bytes are set to 0. Change-Id: I7a68a29ca3632e22f3960c9fc44acf3ce4f87c9c Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41878 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-06-06lp4x: Add new memory parts and generate SPDsFurquan Shaikh
This change adds the following memory parts to LP4x global list and generates SPDs using gen_spd.go for TGL and JSL: 1. MT53E512M32D2NP-046 WT:E 2. K4U6E3S4AA-MGCR 3. H9HCNNNCPMMLXR-NEE 4. K4UBE3D4AA-MGCR BUG=b:157862308, b:157732528 Change-Id: Ib7538247d39dfe5faab277d646f87f09103d6969 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41989 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-06mb/google/volteer: Drop spd/ folders from variants/Furquan Shaikh
Now that volteer is moved to using the auto-generated SPDs, we no longer need the spd/ folder under each variant. Hence, this change drops the spd/ folders and the SPD files within them. BUG=b:156126658 Change-Id: Icb36adeb11fd68a84df5b225db32fb8d840a530f Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41619 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-06mb/google/volteer: Switch to using auto-generated SPDsFurquan Shaikh
This change switches volteer and family to using auto-generated SPDs obtained using gen_spd.go and gen_part_id.go. BUG=b:147321551,b:155423877 Change-Id: I9ed48f0b51714b072a0459d0b70b5417a49db54f Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41618 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-06-06mb/google/volteer/var/volteer: Use auto-generated Makefile.inc using ↵Furquan Shaikh
gen_part_id.go This change adds mem_list_variant.txt that contains the list of memory parts used by volteer and Makefile.inc generated by gen_part_id.go using mem_list_variant.txt. In the final change of the series, all volteer variants will be switched from using the current SPDs to new auto-generated SPDs. Differences in auto-generated SPD from current SPD are as follows: Part: K4U6E3S4AA-MGCL Byte# Current New Explanation 6 0x95 0x94 Signal loading is not used by MRC. Set bits 1:0 to 00. 16 0x48 0x00 Signal loading is not used by MRC. Set to 0x00. 19 0x0F 0xFF As per JEDEC spec, tckMax should be 100ns. So, value should be 0xff as per datasheet. 21,22 0x55,0x00 0x54,0x05 As per datasheet, part supports CAS latencies 20,24,28,32,36. So value should be 0x54, 0x05. 24 0x8C 0x87 taa is .468ns * CAS-36 which results in byte 24 being 0x87 as per datasheet. 123 0x00 0xE5 Fine offset for taa. Expected value is 0xE5 as per datasheet. 124 0x7F 0x00 Fine offset for tckMax. Expected value is 0x00 as per datasheet. 125 0xE1 0xE0 Fine offset for tckMin. As per datasheet tckMin is 0.468ns. So, this comes out to be 0xE0. Part: K4UBE3D4AA-MGCL Byte# Current New Explanation 6 0xB5 0xB4 Signal loading is not used by MRC. Set bits 1:0 to 00. 16 0x48 0x00 Signal loading is not used by MRC. Set to 0x00. 19 0x0F 0xFF As per JEDEC spec, tckMax should be 100ns. So, value should be 0xff as per datasheet. 123 0x00 0xE5 Fine offset for taa. Expected value is 0xE5 as per datasheet. Part: H9HCNNNBKMMLXR-NEE Byte# Current New Explanation 6 0x95 0x94 Signal loading is not used by MRC. Set bits 1:0 to 00. 16 0x48 0x00 Signal loading is not used by MRC. Set to 0x00. 19 0x0F 0xFF As per JEDEC spec, tckMax should be 100ns. So, value should be 0xff as per datasheet. 21,22 0x55,0x00 0x54,0x05 As per datasheet, part supports CAS latencies 20,24,28,32,36. So value should be 0x54, 0x05. 24 0x8C 0x87 taa is .468ns * CAS-36 which results in byte 24 being 0x87 as per datasheet. 123 0x00 0xE5 Fine offset for taa. Expected value is 0xE5 as per datasheet. 124 0x7F 0x00 Fine offset for tckMax. Expected value is 0x00 as per datasheet. 125 0xE1 0xE0 Fine offset for tckMin. tckMin is calculated as (1/4267)*2 which comes out to be 0.46871. Some datasheets round this down to 0.468 and others round it up to 0.469. JEDEC spec uses 0.468. As per that, this value comes out to be 0xE0. Part: H9HCNNNFAMMLXR-NEE Byte# Current New Explanation 4 0x15 0x16 As per datasheet, density is 16Gb per logical channel. So value should be 0x16. 6 0xF9 0xB8 This device has 4 logical dies instead of 8. Also, signal loading is not used by MRC. 16 0x48 0x00 Signal loading is not used by MRC. Set to 0x00. 20,21, 0x92,0x55, 0x12,0x29, As per datasheet, part supports CAS 22 0x00 0x15 latencies 6,10,16,22,26,32,36,40. So value should be 0x12,0x29,0x15. 24 0x8C 0x96 taa is .468ns * CAS-40 which results in byte 24 being 0x96 as per datasheet. 29,30 0xE0,0x0B 0xC0,0x08 As per datasheet, this corresponds to 280ns in MTB units which is 0x08C0. 31,32 0xF0,0x05 0x60,0x04 As per datasheet, this corresponds to 140ns in MTB units which is 0x04C0. 123 0x00 0xE2 Fine offset for taa. Expected value is 0xE2 as per datasheet. 124 0x7F 0x00 Fine offset for tckMax. Expected value is 0x00 as per datasheet. 125 0xE1 0xE0 Fine offset for tckMin. tckMin is calculated as (1/4267)*2 which comes out to be 0.46871. Some datasheets round this down to 0.468 and others round it up to 0.469. JEDEC spec uses 0.468. As per that, this value comes out to be 0xE0. Part: MT53E1G32D2NP-046 WT:A Byte# Current New Explanation 4 0x15 0x16 As per datasheet, density is 16Gb per logical channel. So value should be 0x16. 5 0x21 0x29 As per datasheet, this part has 17row address bits and 10column address bits. This results in 0x29. 6 0xB5 0x94 This device has 2 logical dies. Also, MRC does not use signal loading. 16 0x48 0x00 Signal loading is not used by MRC. Set to 0x00. 12 0x0A 0x02 As per datasheet, this is 1rank and 16-bit wide channel. So, value should be 0x02. 21,22 0x55,0x00 0x54,0x05 As per datasheet, part supports CAS latencies 20,24,28,32,36. So value should be 0x54, 0x05. 24 0x8C 0x87 taa is .468ns * CAS-36 which results in byte 24 being 0x87 as per datasheet. 29,30 0xC0,0x08 0xE0,0x0B As per datasheet, this corresponds to 380ns in MTB units which is 0x0BE0. 31,32 0x60,0x04 0xF0,0x05 As per datasheet, this corresponds to 190ns in MTB units which is 0x05F0. 123 0x00 0xE5 Fine offset for taa. Expected value is 0xE5 as per datasheet. 124 0x7F 0x00 Fine offset for tckMax. Expected value is 0x00 as per datasheet. 125 0xE1 0xE0 Fine offset for tckMin. As per datasheet tckMin is 0.468ns. So, this comes out to be 0xE0. BUG=b:147321551,b:155423877 Change-Id: I3998b2cd91020130bacf371fce9b0d307304acbe Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41617 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-06-06mb/google/volteer/var/halvor: Use auto-generated Makefile.inc using ↵Furquan Shaikh
gen_part_id.go This change adds mem_list_variant.txt that contains the list of memory parts used by halvor and Makefile.inc generated by gen_part_id.go using mem_list_variant.txt. In the final change of the series, all volteer variants will be switched from using the current SPDs to new auto-generated SPDs. Differences in auto-generated SPD from current SPD are as follows: Part: H9HKNNNCRMBVAR-NEH Byte# Current New Explanation 4 0x16 0x15 As per datasheet, density is 8Gb per logical channel. So value should be 0x15. 6 0xB9 0x94 Signal loading is not used by MRC. Set bits 1:0 to 00. 2 channels 2 dies. Hence, 0x94 19 0x0F 0xFF As per JEDEC spec, tckMax should be 100ns. So, value should be 0xff as per datasheet. 29,30 0xE0,0x0B 0xC0,0x08 As per datasheet, this corresponds to 280ns in MTB units which is 0x08C0. 31,32 0xF0,0x05 0x60,0x04 As per datasheet, this corresponds to 140ns in MTB units which is 0x0460. 125 0xE1 0xE0 Fine offset for tckMin. tckMin is calculated as (1/4267)*2 which comes out to be 0.46871. Some datasheets round this down to 0.468 and others round it up to 0.469. JEDEC spec uses 0.468. As per that, this value comes out to be 0xE0. Part: MT53E1G64D4SQ-046 WT:A Byte# Current New Explanation 5 0x21 0x29 As per datasheet, this part has 17row address bits and 10column address bits. This results in 0x29. 6 0xB9 0x94 Signal loading is not used by MRC. Set bits 1:0 to 00. 2 channels, 2 dies. Hence, 0x94. 19 0x0F 0xFF As per JEDEC spec, tckMax should be 100ns. So, value should be 0xff as per datasheet. 125 0xE1 0xE0 Fine offset for tckMin. As per datasheet tckMin is 0.468ns. So, this comes out to be 0xE0. BUG=b:147321551,b:155423877 Change-Id: I28b065a00380516d8686279a92ef68b9f17e2f65 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41616 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-06mb/google/volteer/var/malefor: Use auto-generated Makefile.inc using ↵Furquan Shaikh
gen_part_id.go This change adds mem_list_variant.txt that contains the list of memory parts used by malefor and Makefile.inc generated by gen_part_id.go using mem_list_variant.txt. In the final change of the series, all volteer variants will be switched from using the current SPDs to new auto-generated SPDs. Differences in auto-generated SPD from current SPD are as follows: Part: K4U6E3S4AA-MGCL Byte# Current New Explanation 6 0x95 0x94 Signal loading is not used by MRC. Bits 1:0 set to 0. 16 0x48 0x00 Signal loading is not used by MRC. Set to 0x00. 19 0x0F 0xFF As per JEDEC spec, tckMax should be 100ns. So, value should be 0xff as per datasheet. 21,22 0x55,0x00 0x54,0x05 As per datasheet, part supports CAS latencies 20,24,28,32,36. So value should be 0x54, 0x05. 24 0x8C 0x87 taa is .468ns * CAS-36 which results in byte 24 being 0x87 as per datasheet. 123 0x00 0xE5 Fine offset for taa. Expected value is 0xE5 as per datasheet. 124 0x7F 0x00 Fine offset for tckMax. Expected value is 0x00 as per datasheet. 125 0xE1 0xE0 Fine offset for tckMin. As per datasheet tckMin is 0.468ns. So, this comes out to be 0xE0. BUG=b:155239397,b:147321551 Change-Id: I8b8bdc55314f538aff4dd1944a0b745357744d8c Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41615 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-06mb/google/volteer/var/ripto: Use auto-generated Makefile.inc using ↵Furquan Shaikh
gen_part_id.go This change adds mem_list_variant.txt that contains the list of memory parts used by ripto and Makefile.inc generated by gen_part_id.go using mem_list_variant.txt. In the final change of the series, all volteer variants will be switched from using the current SPDs to new auto-generated SPDs. Differences in auto-generated SPD from current SPD are as follows: Part: K4U6E3S4AA-MGCL Byte# Current New Explanation 6 0x95 0x94 Signal loading is not used by MRC. Bits 1:0 set to 0. 16 0x48 0x00 Signal loading is not used by MRC. Set to 0x00. 19 0x0F 0xFF As per JEDEC spec, tckMax should be 100ns. So, value should be 0xff as per datasheet. 21,22 0x55,0x00 0x54,0x05 As per datasheet, part supports CAS latencies 20,24,28,32,36. So value should be 0x54, 0x05. 24 0x8C 0x87 taa is .468ns * CAS-36 which results in byte 24 being 0x87 as per datasheet. 123 0x00 0xE5 Fine offset for taa. Expected value is 0xE5 as per datasheet. 124 0x7F 0x00 Fine offset for tckMax. Expected value is 0x00 as per datasheet. 125 0xE1 0xE0 Fine offset for tckMin. As per datasheet tckMin is 0.468ns. So, this comes out to be 0xE0. BUG=b:155239397,b:147321551 Change-Id: Ibb06443a5c7fd80915f66b806cdd7c3ae1275b05 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41614 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-06soc/intel/jasperlake: Generate LP4x SPD files using gen_spd.goFurquan Shaikh
This change uses gen_spd.go and global_lp4x_mem_parts.json.txt to generate SPD files for currently known LP4x memory parts that can be used with JSL-based mainboards. Following files are added: 1. spd-*.hex: SPD files auto-generated by gen_spd.go 2. spd_manifest.generated.txt: Manifest file auto-generated by gen_spd.go Mainboards can use the SPD files from SoC directly when creating SPD binary to add to CBFS. Change-Id: Ic52506b809c66b9f7cf25a100a959d85c67addf2 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41876 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-06soc/intel/tigerlake: Generate LP4x SPD files using gen_spd.goFurquan Shaikh
This change uses gen_spd.go and global_lp4x_mem_parts.json.txt to generate SPD files for currently known LP4x memory parts that can be used with TGL-based mainboards. Following files are added: 1. spd-*.hex: SPD files auto-generated by gen_spd.go 2. spd_manifest.generated.txt: Manifest file auto-generated by gen_spd.go Mainboards can use the SPD files from SoC directly when creating SPD binary to add to CBFS. BUG=b:147321551,b:155239397 Change-Id: Ic3935e4f6d106cbdf496fdfa28a0991e2d238fd9 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41875 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-06-06util/spd_tools/intel/lp4x: Add a global list of LP4x memory partsFurquan Shaikh
This change adds a JSON file (`global_lp4x_mem_parts.json.txt`) containing global list of LP4x memory parts to live along with the spd tools since the part information is not really any SoC or mainboard dependent and comes directly from the part datasheet. It can be shared by mainboards based on different platforms supported by the tools. BUG=b:155239397,b:147321551 Change-Id: I9e2f98fc9c1c8a7f73c9a1bfab22c996de222a32 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41874 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-06util: Add spd_tools to generate SPDs for TGL and JSL boardsFurquan Shaikh
Serial Presence Detect (SPD) data for memory modules is used by Memory Reference Code (MRC) for training the memory. This SPD data is typically obtained from part vendors but has to be massaged to format it correctly as per JEDEC and MRC expectations. There have been numerous times in the past where the SPD data used is not always correct. In order to reduce the manual effort of creating SPDs and generating DRAM IDs, this change adds tools for generating SPD files for LPDDR4x memory used in memory down configurations on Intel Tiger Lake (TGL) and Jasper Lake (JSL) based platforms. These tools generate SPDs following JESD209-4C specification and Intel recommendations (doc Two tools are provided: * gen_spd.go: Generates de-duplicated SPD files using a global memory part list provided by the mainboard in JSON format. Additionally, generates a SPD manifest file (in CSV format) with information about what memory part from the global list uses which of the generated SPD files. * gen_part_id.go: Allocates DRAM strap IDs for different LPDDR4x memory parts used by the board. Takes as input list of memory parts used by the board (with one memory part on each line) and the SPD manifest file generated by gen_spd.go. Generates Makefile.inc for integrating the generated SPD files in the coreboot build. BUG=b:155239397,b:147321551 Change-Id: Ia9b64d1d48371ccea1c01630a33a245d90f45214 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41612 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-06-06mb/google/dedede/board_info.c: Clean upElyes HAOUAS
Remove unused includes Change-Id: I7e8109870168db7f477f205a0b3020b7b2be5f5f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41541 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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