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2017-02-04x86/acpi: Add VFCT tablePatrick Rudolph
Add VFCT table to provide PCI Optiom Rom for AMD graphic devices. Useful for GNU Linux payloads and embedded dual GPU systems. Tested on Lenovo T500 with AMD RV635 as secondary gpu. Original Change-Id: I3b4a587c71e7165338cad3aca77ed5afa085a63c Signed-off-by: Patrick Rudolph <siro@das-labor.org> Change-Id: I4dc00005270240c048272b2e4f52ae46ba1c9422 Reviewed-on: https://review.coreboot.org/18192 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-02-04util/ifdtool: Fix ICH Gbe unlockPatrick Rudolph
With coreboot 4.4 switched to "Descriptor mode" for Lenovo T500 it automatically unlocks all flash regions. For Gbe region the "Requester ID" was hardcoded resulting in *dead* Gbe. Keep board specific "Requester ID" while unlocking Gbe region. Allows Lenovo T500 to boot with IFD "Descriptor mode" with unlocked flash regions. Signed-off-by: Patrick Rudolph <siro@das-labor.org> Change-Id: Ia4b5d1928e84bee42182fc83020e3a13fadc93c4 Reviewed-on: https://review.coreboot.org/18055 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-02-03mainboard/google/snappy: Set PL2 override to 15000mWHarry Pan
This patch sets PL2 override value to 15W in RAPL registers. BUG=chrome-os-partner:62110 BRANCH=reef TEST=Apply new firmware to evaluate Octane benchmark score. Change-Id: I51734051586753677129314b5273fb275c74f5d2 Signed-off-by: Harry Pan <harry.pan@intel.com> Reviewed-on: https://review.coreboot.org/18283 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-02-03mb/lenovo/x60,t60: Move EC CMOS parameters in checksummed spaceArthur Heymans
This allows for defaults to be applied to CMOS parameters when cmos checksum is incorrect. This probably results in changed cmos settings for current users of these targets. Change-Id: Ifec0093f4b0dbaa51b96812a041f0eaf5c58ee86 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/17041 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-02-03asus/f2a85-m_le: Activate IOMMU supportTobias Diedrich
Activate the IOMMU for the ASUS F2A85-M LE board. Enable the IOMMU in `devicetree.cb` and build AGESA IOMMU code by enabling the option in `buildOpts.c`. ACPI and MPTABLES interrupt routers are already present since they are syminks to the F2A85-M version. ``` $ uname -a Linux nukunuku 4.8.5 #35 SMP Sun Oct 30 19:34:55 CET 2016 x86_64 GNU/Linux $ lspci -s 0.2 00:00.2 IOMMU: Advanced Micro Devices, Inc. [AMD] Family 15h (Models 10h-1fh) I/O Memory Management Unit $ dmesg | grep -i IOMMU ACPI: IVRS 0x00000000BFFAFF70 000070 (v02 AMD AMDIOMMU 00000001 AMD 00000000) AMD-Vi: Applying erratum 746 workaround for IOMMU at 0000:00:00.2 iommu: Adding device 0000:00:01.0 to group 0 [...] iommu: Adding device 0000:00:18.5 to group 9 iommu: Adding device 0000:03:00.0 to group 8 AMD-Vi: Found IOMMU at 0000:00:00.2 cap 0x40 AMD IOMMUv2 driver by Joerg Roedel <jroedel@suse.de> ``` Change-Id: I6049fcfad53d16a99495d7a8fbc584c71e371d73 Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Reviewed-on: https://review.coreboot.org/18259 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2017-02-02ectool: Support OpenBSDSteven Dee
Adds checks for OpenBSD in all the places that were already checking for NetBSD. This fixes e.g.: ec.c:21:20: error: sys/io.h: No such file or directory which was caused by defaulting to Linux. Also, OpenBSD calls its amd64 iopl amd64_iopl instead of x86_64_iopl. This change just defines iopl appropriately depending on the OS and architecture. TEST=Build on OpenBSD 6.0 or -current from 2017-01-25. Change-Id: If6d92a9850c15cd9f8e287cc4f963d3ff881f72c Signed-off-by: Steven Dee <i@wholezero.org> Reviewed-on: https://review.coreboot.org/18260 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-02-02siemens/mc_apl1: Add new mainboardMario Scheithauer
This mainboard is based on Intel's Leafhill CRB with Apollo Lake silicon. In a first step, it concerns only a copy of intel/leafhill directory with minimum changes. Special adaptations for MC APL1 mainboard will follow in separate commits. Change-Id: If0b8a2bc21c99c3be4e6043e8febfb1b91ff0a63 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/18272 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Brenton Dong <brenton.m.dong@intel.com>
2017-02-01payloads/depthcharge: Allow generic libpayload configMarshall Dawson
Change depthcharge to not require a board-specific config file for libpayload. If the Kconfig option is selected, use the settings in libpayload/configs/defconfig instead. Change-Id: I4fd1a5915472f28e757c62f3f2415716f1fdfc71 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/18271 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-02-01Add Baytrail ChromeOS devices using variant schemeMatt DeVillier
Add new ChromeOS devices banjo, candy, clapper, glimmer, gnawty, heli, kip, orco, quawks, squawks, sumo, swanky, and winky using their common reference board (rambi) as a base. Chromium sources used: firmware-banjo-5216.334.B 32ec493 [chromeos: vboot_loader: Set...] firmware-candy-5216.310.B 519ff11 [baytrail: Preserve VbNv around...] firmware-clapper-5216.199.B 80d55e3 [baytrail: add code for...] firmware-glimmer-5216.198.B fae0770 [baytrail: add code for...] firmware-gnawty-5216.239.B 952adb7 [Gnawty/Olay: Add 2nd source...] firmware-heli-5216.392.B f1f3604 [helis: Lock ME / TXE section...] firmware-kip-5216.227.B db3c5d9 [kip: update spd for for MT41K256M16*] firmware-orco-5216.362.B 76f1651 [Orco: Adjust rx delay for norm.] firmware-quawks-5216.204.B edb60c9 [Quawks: Update SPD data] firmware-squawks-5216.152.B c6573dc [Squawks: Update SPD data] firmware-sumo-5216.382.B c62b6f23 [Ninja, Sumo: Add SPD source...] firmware-swanky-5216.238.B 233b2a7 [Swanky: update SPD table] firmware-winky-5216.265.B ce91ffc [Add to support HT Micron...] The same basic cleanup/changes are made here as with the initial BYT variant commit: - remove unused ACPI trackpad/touchscreen devices - correct I2C addresses in SMBIOS entries - clean up comment formatting - remove ACPI device for unused light sensor - switch I2C ACPI devices from edge to level triggered interrupts, for better compatibility/functionality (and to be consistent with other recently-upstreamed ChromeOS devices) - Micron 2GB SPD file for kip with updated values renamed to distinguish from same file used by other boards Change-Id: Ic66f9b539afb5aff32c4c1a8563f6612f5a2927c Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/18164 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-02-01payloads/depthcharge: Specify revision to buildMarshall Dawson
Add the capability for specifying which version of depthcharge to checkout and build. This is similar to the existing feature for SeaBIOS. The depthcharge makefile already contains some structure for checking out master vs. stable however the calling Makefile.inc ingored this feature. Add the command-line variable assignment for these, along with a tree-ish for any revision. Change-Id: I99a5b088cb0ebb29e5d96a84217b3bfa852de8ac Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/18270 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2017-02-01payloads/depthcharge: Use variable target nameMarshall Dawson
Depending on the commit to build, depthcharge may have a different target name (depthcharge vs. depthcharge_unified). Add some logic to determine which name should be used based on the commit ID being requested. Change-Id: I05b853934d13696f4bd0d79d53ff6c5f59096d1c Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/18269 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2017-02-01payloads/depthcharge: Change make target from unifiedMarshall Dawson
Drop the _unified moniker from the depthcharge build. The payload and coreboot have drifted out of sync and there is no longer a non-unified depthcharge. This patch corresponds with the depthcharge change: https://review.coreboot.org/cgit/depthcharge.git/commit/?id=74a0739 Change-Id: I8d028b14d2eee63dfdc9d3dd63695f1c58ea7984 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/18268 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-31google/veyron*: mark GPIO array non-staticPatrick Georgi
That status isn't needed and making it non-static helps gcc 4.9.2 (or any compiler that insists on "standard C" behaviour with global const initializers) Change-Id: Ib1fbd5213d262e653f31564b106095b4a28292f6 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/18266 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-31build system: mark sub-make invocations as parallelizablePatrick Georgi
We rely on gnu make, so we can expect the jobserver to be around in parallel builds, too. Avoids some make warnings and slightly speeds up the build if those sub-makes are executed (eg for arm-trusted-firmware and vboot). Change-Id: I0e6a77f2813f7453d53e88e0214ad8c1b8689042 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/18263 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-31util/xcompile: parallelize compiler checksPatrick Georgi
Speed up the execution of this script from ~6 seconds to ~1 on my system. There are some changes to its output, but they're actually _more_ correct: so far, architectures without compiler support kept compiler options for architectures that ran successfully earlier. Change-Id: I0532ea2178fbedb114a75cfd5ba39301e534e742 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/18262 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-31asus/m2v,m2v-mx_se: Unify KconfigPaul Menzel
Reorder the items to minimize the differences. Change-Id: I745ec70a990f997d87c2a0b6164ae127eb694ddf Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/17438 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-01-31src/lib: Update Makefile to keep build/spd.bin rule privateMartin Roth
The rule to make spd.bin that's in src/lib is for the 'generic_spd_bin' implementation. It wasn't guarded though, so it was generating a build warning for any other platform that generated an spd.bin file. Sample warning that this fixes: src/mainboard/gizmosphere/gizmo/Makefile.inc:42: warning: overriding recipe for target 'build/spd.bin' src/lib/Makefile.inc:298: warning: ignoring old recipe for target 'build/spd.bin' Change-Id: Iadd6743f8ae476969bf36f99b918f04c04172d1d Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/18261 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-01-31mainboard/google/reef: remove NHLT DMIC 1ch and 2ch configurationSathyanarayana Nujella
Apollolake boards should use DMIC-4ch configuration in Kernel side and use CaptureChannelMap in userspace to distinguish boards with different number of DMIC's. So, NHLT DMIC 1-ch & 2-ch endpoint configuration will not be required and hence removed. BUG=chrome-os-partner:60827 TEST=Verify internal mic capture TEST='arecord -Dhw:0,3 dmic_4ch.wav -f S16_LE -r 48000 -c 4 -d 10' works Change-Id: Ibe81290906c9e379ae49e437648ee9cd6f123ff8 Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-on: https://review.coreboot.org/18252 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-01-31mainboard/google/reef: Set edge triggered interrupt for GPIO_22Vaibhav Shankar
EC sets the logic level based on outstanding wake events. When GPIO_22 is configured as a level triggered interrupt, the events are not cleared from the interrupt handler. Hence, we'd just be re-signalling over and over causing an interrupt storm upon lid open. So, GPIO_22 needs to be configured as EDGE_SINGLE instead of LEVEL. BUG=chrome-os-partner:62458 TEST=Lid close/open. check CPU usage using top. It should not show 70% CPU usage. Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com> Change-Id: I710a690578c6e5b63be34b7fbcb21c703ef56e3a Reviewed-on: https://review.coreboot.org/18267 Tested-by: build bot (Jenkins) Reviewed-by: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-01-30vboot: Add mock functions for recovery space read/writeFurquan Shaikh
For the boards that intend to use mock tpm and have recovery mrc cache support enabled, provide mock functions to read and write mrc hash space. Reading MRC hash space returns TPM_SUCCESS as later checks take care of comparing the hash value and retraining if hash comparison fails. Thus, in case of mock tpm, device would always end up doing the memory retraining in recovery mode. BUG=chrome-os-partner:62413 BRANCH=None TEST=Verified that eve builds with mock tpm selected. Change-Id: I7817cda7821fadeea0e887cb9860804256dabfd9 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/18248 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-01-29mainboard/google/snappy: Update WDT touchscreen deviceFurquan Shaikh
Export PowerResource for WDT touchscreen device. BUG=chrome-os-partner:62311, chrome-os-partner:60194, chrome-os-partner:62371 BRANCH=reef TEST=Compiles successfully. Change-Id: Icc5be170353753201d3571c39b50e29424d4d6d3 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/18240 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-29mainboard/google/pryo: Update touchscreen device ACPI nodesFurquan Shaikh
1. For ELAN, export reset GPIO as well as PowerResource 2. For WCOM, export PowerResource BUG=chrome-os-partner:62311, chrome-os-partner:60194, chrome-os-partner:62371 BRANCH=reef TEST=Verified that touchscreen works on pyro with WCOM device on power-on as well as after suspend/resume. Change-Id: I0306e24e19bf821cd3e08fdacc0d78b494c9a92f Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/18239 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-29i2c/generic: Allow GPIOs to be put in _CRS and PowerResource in ACPIFurquan Shaikh
Linux kernel expects that power management with ACPI should always be handled using PowerResource. However, some kernel drivers (e.g. ELAN touchscreen) check to see if reset gpio is passed in by the BIOS to decide whether the device loses power in suspend. Thus, until the kernel has a better way for drivers to query if device lost power in suspend, we need to allow passing in of GPIOs via _CRS as well as exporting PowerResource to control power to the device. Update mainboards to export reset GPIO as well as PowerResource for ELAN touchscreen device. BUG=chrome-os-partner:62311,chrome-os-partner:60194 BRANCH=reef TEST=Verified that touchscreen works on power-on as well as after suspend-resume. Change-Id: I3409689cf56bfddd321402ad5dda3fc8762e6bc6 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/18238 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-01-29autoport: add missing parameter for pc_keyboard_init()Iru Cai
This fixes the build for the generated code for boards with PS/2 keyboard, since commit 448e386309c updated the pc_keyboard_init() function. Change-Id: I776b49b847985296eaca4af6d6e49ab5d6abbafe Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/18242 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-01-29mainboard/google/reef: Set IOSSTATE for trackpad I2C GPIOsVaibhav Shankar
I2C data (GPIO_132) and Clk (GPIO_133) lines are pulled low during standby states S3/S0ix. This causes leakage of power. To reduce the leakage, we have to pull these lines high during S3/S0ix. This is done by programming the IOSSTATE to HIz. Also note that we are using the internal pull ups to keep at SOC at 1.8V and the I2C lines are not floating. BUG=chrome-os-partner:62428,chrome-os-partner:61651 TEST=Enter S3/S0ix. Measure trackpad power. It should be less than 4mW. Also I2c lines should be pulled high in S3/S0ix. Change-Id: I5570ac37ec3cc41f6463dd6b858fdb56a20a1733 Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com> Reviewed-on: https://review.coreboot.org/18251 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-01-27SeaBIOS Kconfig: Update loggingMartin Roth
The SeaBIOS and coreboot log levels don't really align, so setting the SeaBIOS log level to the same as coreboot's isn't really what we want. - Update default log level to use the default SeaBIOS log level. - Update the current help text to match the new defaults. - Add help text for what is displayed at various levels. - Get rid of separate type & prompt lines. - Add comments for default seabios level & logging disabled Change-Id: I5a8b75bd44748cb94a83a77ac3a379c8a9587e7b Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/18210 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Kevin O'Connor <kevin@koconnor.net>
2017-01-27Makefile: Just error out if no .config existsMartin Roth
Currently coreboot runs the 'config' command if no .config file exists. This isn't what anyone wants, and is particularly frustrating for tools that automate the build, where the build just hangs waiting for input. Instead, just show an error message and then exit the build. Change-Id: If9e0c2c26f8273814518589a2f94c5b00fc4cefe Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/18245 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-01-27board_status/towiki.sh: Add socket LGA775Arthur Heymans
Intel Core 2 is not further specified since not all chipsets support quad cores, which could confuse users. Change-Id: I86c0a41743fe784f432347fa639d3c26604e058e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/18235 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-01-27util/docker: Update makefile target namesMartin Roth
- Use dashes instead of underscores for consistency and to match other coreboot targets - Fix a couple of places where old target names were referenced - Remove double 'help' target from .PHONEY target list Change-Id: I3b464ebf74653a8cc880e982316fd883757ec728 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/18000 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-01-27util/docker: Update makefile with command to kill docker imagesMartin Roth
Kill running docker containers before trying to remove images or containers. Change-Id: Id2de90edbe5d0dc6ecb906be7101ad9744dbd11e Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/17999 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-01-27board_status/to-wiki: Update bucketize scriptMartin Roth
- Fix TODO: restrict $1 to allowed values. - Specifically exclude 'oem' board status directories. - Exclude any directory that doesn't follow the date format to keep the script from breaking again in the future if something it doesn't recognize is pushed. Just ignore it for the wiki. - Fix shellcheck warnings. Change-Id: I2864f09f5f1b1f5ec626d06e4849830400ef5814 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/18225 Tested-by: build bot (Jenkins) Reviewed-by: Timothy Pearson <tpearson@raptorengineering.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-01-27Only add etc/ps2-keyboard-spinup when not updating an imageArthur Heymans
Without this motherboards that requires a non zero timeout for ps2 keyboards on SeaBIOS don't build when CONFIG_UPDATE_IMAGE is set. An alternative way to achieve this file would be to include a cbfsfile instead of calling cbfstool. That way the file gets updated/added both both image update and regular build. A difficulty of that approach is that it needs to convert a decimal to a binary in little endian representation, which is not a trivial thing to do in a Makefile. Change-Id: Icafba8d3e279a2e70e607abba81e3dbebfb55e4b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/18231 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-26drivers/pc80/rtc: Check cmos checksum BEFORE reading cmos valueMartin Roth
If cmos is invalid, it doesn't make sense to read the value before finding that out. Change-Id: Ieb4661aad7e4d640772325c3c6b184de1947edc3 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/18236 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-01-26google/pyro: Add USB2 phy setting overrideKevin Chiu
In order to pass type A USB2 eye diagram, USB2 port#0/#1 PHY register will need to be overridden. port#0: PERPORTPETXISET = 7 PERPORTTXISET = 1 IUSBTXEMPHASISEN = 3 PERPORTTXPEHALF = 0 port#1: PERPORTPETXISET = 7 PERPORTTXISET = 2 IUSBTXEMPHASISEN = 3 PERPORTTXPEHALF = 0 BUG=chrome-os-partner:59491 BRANCH=reef TEST=emerge-pyro coreboot Change-Id: I8e67a6f0192d1c0abf6ec4926c2a17e44c818948 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/18229 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-01-26google/pyro: Disable Wacom touchscreen probedKevin Chiu
Wacom touchscreen is i2c hid device and it's the device that always exists. So no need to set "probed" property for it. BUG=chrome-os-partner:61513 BRANCH=reef TEST=emerge-pyro coreboot Change-Id: I27fe18ceadd03029b826e0237f80132eda1089b0 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/18227 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-01-26drivers/net/rt8168: Add a macaddress cbfsfile using KconfigArthur Heymans
The default macaddress in rt8168.c can be changed with a cbfsfile called macaddress. This patch makes it possible to add such a file using Kconfig at build time. This also changes the name of the cbfsfile from "macaddress" to "rt8168-macaddress" to avoid confusion. Change-Id: I24674d8df11845167b837b79344427ce0c67f4fb Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/18088 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-01-26amd/amdht: Fix format security errorsPaul Menzel
Ubuntu’s default compiler flags for GCC [1][2] include `-Wformat -Wformat-security`, causing errors similar like the one below. ``` CC romstage/northbridge/amd/amdht/ht_wrapper.o src/northbridge/amd/amdht/ht_wrapper.c: In function 'AMD_CB_EventNotify': src/northbridge/amd/amdht/ht_wrapper.c:124:4: error: format not a string literal and no format arguments [-Werror=format-security] printk(log_level, event_class_string_decodes[evtClass]); ^ […] ``` Fix that, by explicitly using a format string. TEST=Built and booted on ASUS KGPE-D16. [1] https://stackoverflow.com/questions/17260409/fprintf-error-format-not-a-string-literal-and-no-format-arguments-werror-for "fprintf, error: format not a string literal and no format arguments [-Werror=format-security" [2] I tested with gcc (Ubuntu 5.4.0-6ubuntu1~16.04.4) 5.4.0 20160609. Change-Id: Iabe60deeffa441146eab31dac4416846ce95c32a Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/18208 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-01-25mb/intel/d510mo: Add cmos.layout and cmos.defaultArthur Heymans
Change-Id: I877d4470b697d6a6d4652ed1c60028cdcbe8df98 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/18143 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-25nb/intel/pineview: Make preallocated igd memory a cmos parameterArthur Heymans
Change-Id: Ia7fa2c290e540ff779cf8dc16147db5a248021e2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/18142 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-01-25util: Add me_cleanerNicola Corna
me_cleaner is a tool to strip down Intel ME/TXE images by removing all the non-fundamental code, while keeping the ME/TXE image valid and suitable for booting the system. The remaining code (ROMP and BUP modules) is the one responsible for the very basic initialization of the ME/TXE subsystem and can't be removed. This tool exploits the fact that: * Each ME/TXE partition is signed individually and it is possible to remove both the partition and the signature. * The ME/TXE modules are not signed directly, instead they are hashed and the list of their hashes is hashed again and signed: this means that modifying a module doesn't invalidate the signature, but only the hash of that single module. * The modules hashes are checked only when the corresponding module needs to be executed. * The system can boot after the execution of the first module (BUP, inside the FTPR partition), even if the subsequent stages fail. Currently me_cleaner works on every Intel platform with Intel ME or Intel TXE with the following limitations: * Doesn't work when Intel Boot Guard is set in Verified Boot mode. * Doesn't fully work on Nehalem yet. * On Skylake and later generations, since the partitions' internal structure has changed, me_cleaner leaves intact the FTPR partition, removing all the the other partitions. This tool has been tested on multiple platforms and architectures by different users, and seems to be stable. The reports are available here: https://github.com/corna/me_cleaner/issues/3 A more in-depth description of me_cleaner is available here: https://github.com/corna/me_cleaner/wiki/How-does-it-work%3F Change-Id: I9013799e9adea0dea0775b9afe718de5fc4ca748 Signed-off-by: Nicola Corna <nicola@corna.info> Reviewed-on: https://review.coreboot.org/18203 Tested-by: build bot (Jenkins) Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-01-25libpayload: fix buildPatrick Georgi
When .xcompile doesn't already exist, building libpayload fails because the CC variable (et al) remain empty since .xcompile is only included after the variables coming from there are evaluated. Change-Id: I73f1cbced95afcff15839604fea5fd05d81bc3d3 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/18228 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-25google/pyro: Modify Wacom touchscreen IRQ type to level-triggeredKevin Chiu
Follow i2c-hid spec definition, level trigger interrupt is required for i2c-hid device. BUG=chrome-os-partner:61513 BRANCH=reef TEST=emerge-pyro coreboot Change-Id: Ia825bd0c898e71e2ee2bf411f117a49a8fb411b6 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/18217 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-01-25nvramcui: Declare variable outside for loopPaul Menzel
Make the code C89 compatible, which doesn’t allow loop initial declarations. Older compilers use C89 by default, so just declare the variable outside. Change-Id: I3c5a8109e66f7a25687f4e4b2c72718d74276e04 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/18196 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-01-24arch/x86: do not define type of SPIN_LOCK_UNLOCKEDPatrick Georgi
This fixes building coreboot with -std=gnu11 on gcc 4.9.x Also needs fix ups for asus/kcma-d8 and asus/kgpe-d16 due to the missing type. Change-Id: I920d492a1422433d7d4b4659b27f5a22914bc438 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/18220 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-01-24Revert "chromeos: Fill in the firmware id (RO, RW A, RW B) FMAP sections"Patrick Georgi
This reverts commit 580db7fd9036134b1da4fe7340e306fee4681659. There's a (parallel) mechanism more closely aligned with how the values are filled in (fixed device part + version string) that landed from Chrome OS downstream (see commit 4399b85fdd). Change-Id: I5ccd06eadabb396452cc9d1d4dff780ea0720523 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/18205 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-24build system: don't run xcompile or git for %clean/%config targetsPatrick Georgi
It takes a long time for no gain: We don't need to update the submodules, we don't need to fetch the revision, we don't need to find the compilers, when all we want to do is to manipulate the .config file or clean the build directory. Change-Id: Ie1bd446a0d49a81e3cccdb56fe2c43ffd83b6c98 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/18182 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-24google/eve: Enable PD MCU deviceDuncan Laurie
In order for PD charge events to properly notify the OS when a charger is attached we need to enable the PD MCU device and event source from the EC. Without this change the charging still happens, but the OS does not notice and update the charge state icon in the Chrome OS UI. BUG=chrome-os-partner:62206 BRANCH=none TEST=plug in a charger to either port and see charge status updated to indicate charging in the power_supply_info tool and the Chrome OS UI. Change-Id: Ia6f63ac719b739326d313f657a68005c32f45b8d Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/18209 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-01-24mainboard/lenovo: Add new port L520Patrick Rudolph
Add support for Lenovo Thinkpad L520. The files are generated by autoport, and are successfully tested on the board. L520 has got 4MiB flash chip, that contains a "slim" ME with 1.2MiB only. The flash IC has to be desoldered, as it won't be accessible in circuit. It is located on top of the mainboard right under the touchpad. Test-setup: Extract the following blobs from vendor BIOS: * Intel Flash Descriptor * Intel Management Engine * Intel VBios The laptop has been externaly flashed. It was able to turn on the display and load SeaBIOS. Latest debian has been booted from harddisk. Latest fedora has been booted from USB flash drive. The following hardware has been tested and is working: * Display using Option Rom * PCIe wifi * Ethernet * Keyboard, trackpoint and touchpad * Some Fn functions keys * Volume Keys (except mic mute) * Status LEDs * Audio (headphone jack only) * USB ports * Native raminit dual channel (2 DDR3-1333 DIMMs tested) * SATA cdrom * SATA harddrive Broken: * Some Fn functions keys * Microphone mute button * Speakers (but headphone jack gives sound) Untested: * Expansion slot * SD card slot * Docking station * Native gfx init The EHCI debug port is the first one on the right side. Change-Id: Ic8943799b953bde09ff1daf8427ce5125a0778ca Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/18003 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-01-24cbfs-compression-tool: add to "make tools" targetPatrick Georgi
Change-Id: I7bd0a17f9b20e46aee836fef1ff0b39de8670a15 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/18202 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-24mainboard/intel/leafhill: initial leafhill board changesBrenton Dong
This commit makes the initial changes to support the Intel Leaf Hill CRB with Apollo Lake silicon. Memory parameters and some GPIOs are set. The google/reef directory is used as a template, and the same IFWI stitching process as reef is used to generate a bootable image. Apollo Lake silicon requires a boot media region called IFWI which includes assets such as CSE firmware, PMC microcode, CPU microcode, and boot firmware. Change-Id: Id92f0458548e3054d86f5faa8152d58d902f4418 Signed-off-by: Brenton Dong <brenton.m.dong@intel.com> Reviewed-on: https://review.coreboot.org/18039 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2017-01-24drivers/intel/gma/vbt: Fix style and minor issuesNico Huber
o Fix indentation and other whitespace issues, o Use `const` where applicable, o Avoid retyping the same constant literals, o Actually read PCI revision from the device (instead of using the lowest class byte). Change-Id: I2c64153c61a51a6a87848360d22f981225812a3b Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/18185 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-01-24mainboard/intel: add leafhill board directoryBrenton Dong
This commit adds the initial scaffolding for the Intel Leafhill CRB with Apollo Lake silicon. The google/reef directory is used as a template. This commit only makes the minimum changes to Kconfig and Kconfig.name needed for the build bot to not have issues. Change-Id: I088edee0e94ecfb4666fa31e08dbcfd24a81891b Signed-off-by: Brenton Dong <brenton.m.dong@intel.com> Reviewed-on: https://review.coreboot.org/18038 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2017-01-24cbfs-compression-tool: catch compression failuresPatrick Georgi
If compression failed, just store the uncompressed data, which is what cbfstool does as well. Change-Id: I67f51982b332d6ec1bea7c9ba179024fc5344743 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/18201 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-24vboot: vb2ex_printf() ignores null function nameRandall Spangler
Currently, it will print the function name as a prefix to the debug output. Make it so that a null function name won't get printed, so that it's possible to print little bits of debug output. BUG=chromium:683391 BRANCH=none TEST=build_packages --board=reef chromeos-firmware Change-Id: I046fa766773fc08a29460db1f884d7902692d182 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 853ff7176e97e5e1ab664d094e1914c9c94510aa Original-Change-Id: I1dff38e4d8ab03118e5f8832a16d82c2d2116ec9 Original-Signed-off-by: Randall Spangler <rspangler@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/431111 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/18204 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-24rockchip/rk3399: set edp pclk to 25MHzLin Huang
It may cause an edp aux transfer error if the edp pclk is set too high, so reduce it to 25MHz. BUG=chrome-os-partner:60130 BRANCH=None TEST=Build and Boot Change-Id: Id1063baa5a82637b03c0f1f754181df074ab17cc Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 8f7ce31a7483e765ae0c86f8e62ef51413ee1596 Original-Change-Id: Ibb86c12c1d7c00dc3b4cc7a6bdf3bd6e895cd9f3 Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/429410 Original-Commit-Ready: Julius Werner <jwerner@chromium.org> Original-Tested-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/18178 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-24libpayload: drivers/keyboard: report power button eventsShelley Chen
Power button events are usually dropped because the button is not in the keyboard matrix range. Add condition to forward it like other keys. BUG=chrome-os-partner:61275 BRANCH=None TEST=reboot and make sure power button selection in depthcharge's detachable menus is processed on reef. Change-Id: I86897fa8d73a56533ef62bba05458ac3d339237e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 25654e214f0ab8685d445ced62612a02be851126 Original-Change-Id: I516a0043bd7730789728d5c5498d0a0f30a2acac Original-Signed-off-by: Shelley Chen <shchen@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/428199 Original-Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://review.coreboot.org/18177 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-23google/pyro: Update DPTF settingsKevin Chiu
1. Update DPTF CPU/TSR1 passive trigger points. CPU passive point: 80 TSR1 passive point: 46 2. Update DPTF TRT Sample Period TSR1: 8s BUG=chrome-os-partner:62133 BRANCH=reef TEST=emerge-pyro coreboot Change-Id: I8fcf750ac17b8894ed3c8704eec62f5071d9cf24 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/18174 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-22.gitignore: Don’t track Tint directoryPaul Menzel
This is done already for the other payloads. Change-Id: I98eb05404c0e181ad99a61d8c97987ceadd9a53c Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/18188 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: Martin Roth <martinroth@google.com>
2017-01-22gru: kevin: define GPIOs used on both platformsVadim Bendebury
The same GPIOs are used on both platforms, definitions are added an a new .h to make it easier to re-use them across the code. BRANCH=none BUG=chrome-os-partner:51537 TEST=panel backlight still enabled on Gru as before. The rest of the GPIOs are used in the upcoming patches. Change-Id: I54ef3e8dd79670bdb037baeec91430113d11bcc1 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c58788026f28af52c650da0159b93d97269ca4a9 Original-Change-Id: I1a6c5b5beb82ffcc5fea397e8e9ec2f183f4a7e0 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/346219 Original-Tested-by: Shunqian Zheng <zhengsq@rock-chips.com> Reviewed-on: https://review.coreboot.org/18176 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-22nb/x4x/raminit: Fix programming dram timingsArthur Heymans
The results were obtained by comparing the MCHBAR registers of vendor bios with coreboot at the same dram timings. This fixes 2 issues: * 1333MHz fsb CPUs were limited to 667MHz ddr2 speeds, because with 800MHz raminit failed; * 1067MHz fsb CPUs did not boot when second dimm slot was populated. TESTED on ga-g41m-es2l on 800, 1067 and 1333MHz CPUs with DDR2 667 and 800MHz dimms. Change-Id: I70f554f97b44947c2c78713b4d73a47c06d7ba60 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/18022 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-01-22Makefile.inc: Explicitly set GNU11 as C language standardPaul Menzel
Different compiler versions use a different C language standard by default. GCC 4.9 uses GNU89 by default [1], while GCC 5.x uses GNU11 [2]. The discussion on the mailing list in thread *[RFC] Setting C99 by default* [3] resulted in the preference of C11, which results in build errors. So explicitly set it to GNU11, which is also what the current coreboot toolchain with GCC 5.3 is using. [1] https://gcc.gnu.org/onlinedocs/gcc-4.9.4/gcc/C-Dialect-Options.html [2] https://gcc.gnu.org/onlinedocs/gcc-5.4.0/gcc/Standards.html [3] https://www.coreboot.org/pipermail/coreboot/2016-November/082541.html Change-Id: If1569618f8044925ff72dcf3543480b34d4f90d6 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/17636 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2017-01-22mainboard/google/reef: Increase TSR1 trigger pointTim Chen
Update the DPTF parameters based on thermal test result. (ZHT_DPTF_EVT2_v0.4_20170120.xlsx) 1. Update DPTF TSR1 passive trigger point. TSR1 passive point: 46 BUG=chrome-os-partner:60038 BRANCH=master TEST=build and boot on electro dut Change-Id: If35e4cf2dbf7c506534c52a052598f6204d5315a Signed-off-by: Tim Chen <Tim-Chen@quantatw.com> Reviewed-on: https://review.coreboot.org/18183 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-22google/eve: Fixes for devicetree settingsDuncan Laurie
The devicetree settings were incorrect in a few places with respect to the SOC and board design: - IMVP8 VR workaround is for MP2939 and not MP2949 on Eve - IccMax values are incorrect according to KBL-Y EDS - USB2[6] is incorrectly labeled - I2C touch devices do not need probed as they are not optional - PCIe Root Port 5 should be enabled - I2C5 device should not be enabled as it is unused BUG=chrome-os-partner:58666 TEST=manually tested on Eve board Change-Id: I74e092444ead4b40c6d8091b80a691d44e2c6c7d Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/18200 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-22google/eve: Enable separate recovery MRC cacheDuncan Laurie
In order to get quick boot speeds into recovery enable the feature that allows for a separate recovery MRC cache. This requires shuffling the FMAP around a bit in order to provide another region for the recovery MRC cache. To make that shuffling easier, group the RW components into another sub-region so it can use relative addresses. BUG=chrome-os-partner:58666 TEST=manual testing on eve: check that recovery uses the MRC cache, and that normal mode does too. Check that if cache is retrained in recovery mode it is also retrained in normal mode. Also check that events show up in the log when retrain happens. Change-Id: I6a9507eb0b919b3af2752e2499904cc62509c06a Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/18199 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-22soc/intel/skylake: Include I2C code in romstageDuncan Laurie
The lpss_i2c driver is enabled in romstage, so the SOC needs to export the pre-ram compatible I2C controller info, which for skylake is in the bootblock/i2c.c file. This was not causing a compiler error in normal use, but when adding I2C debug code in romstage it failed to compile. With this added, I can now do I2C transactions in romstage. Change-Id: I0778b0497d0b6936df47c29b2ce942c8d90cf39b Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/18198 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-22google/eve: Enable keyboard backlight in bootblockDuncan Laurie
Enable the keyboard backlight as early in boot as possible to provide a indication that the BIOS is executing. Since this is bootblock it can't use the convenience function for checking for S3 resume so just read the PM1 value from the SOC and check it directly. Use a value of 75% for the current system as that is visible without being full brightness. BUG=chrome-os-partner:61464 TEST=boot on eve and check that keyboard backlight is enabled as soon as the SOC starts booting Change-Id: I9ac78e9c3913a2776943088f35142afe3ffef056 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/18197 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-01-21soc/intel/apollolake: correct GPIO 13 IRQ numberAaron Durbin
The define for GPIO_13_IRQ had the wrong IRQ number. It should be 0x70 instead of 0x6f. BUG=chrome-os-partner:62085 BRANCH=reef TEST=touch controller doesn't indicate continuous interrupts Change-Id: I3a0726db59fc1eb7736d348aecbf1082719f15b2 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/18190 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-01-21mainboard/google/reef: remove internal pullups on PP1800_S railAaron Durbin
The PP1800_S rail is turned off in S3. However, enabling internal pullups on the pins which are connected to PP1800_S results in leakage into the P1800_S rail. Fix this by disabling the internal pullups on PP1800_S rail pins. BUG=chrome-os-partner:61968 BRANCH=reef TEST=measured leakage on PP1800_S rail. Gone with this patch. Change-Id: I5ae92b31c1a633f59d425f4105b8db1c9c18c808 Signed-off-by: Aaron Duribn <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/18189 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-01-21pcengines/apu2: Add serial number in SMBIOSKyösti Mälkki
Change-Id: Ic8149b1dd19d70935e00881cffa7ead0960d1c78 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18154 Tested-by: build bot (Jenkins) Reviewed-by: Piotr Król <piotr.krol@3mdeb.com>
2017-01-21pcengines/apu2: Add SKU in SMBIOSKyösti Mälkki
Installed memory only, PCB revision cannot be detected. Change-Id: Ib6224018db3de4a7ddd9e6f7f30edc438c3f0702 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18153 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-21pcengines/apu2: Refactor reading memory strapKyösti Mälkki
Change-Id: Ie4f80619d9417200a007fc65154b97a5bc05f2f8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18152 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-21pcengines/apu2: Change SMBIOS part numberKyösti Mälkki
This string should not include manufacturer name. Change-Id: I63793b16129334ea4930b8b0264a39d7f9849bba Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18151 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-21pcengines/apu2: Remove DDI configurationKyösti Mälkki
Assembled SoC part does not have integrated graphics. Change-Id: I5d157063cd850d343df73d448e6904c188a09730 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18150 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-20nb/gm45/gma.c: Fix reported Pixel clockArthur Heymans
Change-Id: Ie1c360ac29eb30af6f4b5447add467f3c13ba211 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/18180 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-01-20lb_tables: make lb_mainboard and lb_strings record sizes 64-bit alignedRonald G. Minnich
They were sized to 32-bit alignment, this grows them to 64 bit-aligned. Change-Id: I494b942c4866a7912fb48a53f9524db20ac53a8c Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: https://review.coreboot.org/18165 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-20configs/builder: Remove pre-defined VGA bios filePhilipp Deppenwiese
Removes the pre-defined VGA bios file and id because the build system includes every vgabios. Also make the VGA output primary by default Change-Id: I87d52ef2d1e151c6e54beba64316fe9043668158 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/18181 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-01-20util/intelmetool: Try to activate the ME before scanning PCIe for itDan Elkouby
When the ME is hidden (most likely because it was disabled), it cannot be found until activate_me() is called. Change-Id: Ie1f65f61eb131577d7254af582e2709660f4da27 Signed-off-by: Dan Elkouby <streetwalrus@codewalr.us> Reviewed-on: https://review.coreboot.org/18149 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-20google/snappy: Add weida touchscreen supportWisley Chen
Add weida touchscreen as 2nd touchscreen source BUG=chrome-os-partner:61865 BRANCH=reef TEST=emerge-snappy coreboot, and verified that touchscreen works on snappy. Change-Id: If76312a62e97da9d5de18ad895e90ee6b0f0c6ae Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/18166 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-01-20google/snappy: Use exported GPIOs and ACPI regulator for touchscreenWisley Chen
ELAN touchscreen device expects firmware to export GPIOs and ACPI regulators for managing power to the device. Thus, provide the required ACPI elements for OS driver to properly manage this device. BUG=None BRANCH=None TEST=Verified that touchscreen works properly on boot-up and after suspend/resume. Change-Id: I78e0c35f60289afe338d140d90784a433ca534ae Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/18163 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-01-20soc/intel/skylake: Set FSP-S UPD PchHdaIDispCodecDisconnect to 1Barnali Sarkar
As per Audio PCH team recommendation the iDisplay Audio/SDIN2 should be disabled to bypass InitializeDisplayAudio() function call. Display Audio Codec is HDA-Link Codec, which is not supported in I2S mode BUG=chrome-os-partner:61548 BRANCH=none TEST=Tested to verify that InitializeDisplayAudio() does not get called. Change-Id: Ie0771a8653821e737d10e876313917b4b7c64499 Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/18091 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-01-20google/eve: Adjust DPTF parametersDuncan Laurie
- Remove the 0mA entry for the charger performance table - Slightly raise the passive limit for TSR2/TSR3 to 55C BUG=chrome-os-partner:58666 TEST=manual testing on P1 system Change-Id: I75c66afe04afbbdb64a45833eb938e57ff21b392 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/18172 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-20google/eve: Enable ACPI keyboard backlightDuncan Laurie
Enable the ACPI interface to EC driven keyboard backlight. BUG=chrome-os-partner:61464 TEST=manual testing on P1 system Change-Id: I13d96c13d7db726b1e8289131db65104bd302efe Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/18171 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-20google/eve: Enable pull-up on ACPRESENTDuncan Laurie
Enable an internal pull-up on ACPRESENT signal. BUG=chrome-os-partner:58666 TEST=manual testing on P1 Change-Id: I0bb86f4547272e021ffd10998faa0e2f103b0808 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/18170 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-01-19libpayload: Enable USB HID in veyron configurationPaul Kocialkowski
This enables USB HID support in the veyron config, since it seems to work correctly and is needed for interaction with depthcharge on devices without an embedded keyboard (such as veyron_mickey). Change-Id: Icae829e3a132005df17bcb6f7e6f8a190912576d Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-on: https://review.coreboot.org/17930 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-01-19mainboard/google/snappy: Disable unused devicesWisley Chen
The following devices i2c6, i2c7, spi1, spi2, uart3 are not used. BUG=none BRANCH=master TEST=emerge-snappy coreboot chromeos-bootimage Change-Id: I9bacdbdd194ce21686c1618494d113402f2bef6c Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/18140 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-19mainboard/google/reef: Ignore Audio DMIC IOSSTATEVaibhav Shankar
Audio DMIC PLL needs to be ON in S0ix to support Wake on Voice. This requires GPIO_79 and GPIO_80 to be configured as IGNORE IOSSTATE. So DMIC CLKs will be ON in S0ix. Change-Id: If91045a8664ce853366b670b9db38d620818fbab Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com> Reviewed-on: https://review.coreboot.org/18155 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-19driver/intel/fsp1_1: Fix boot failure for non-verstage caseTeo Boon Tiong
Currently car_stage_entry is defined only in romstage_after_verstage and as a result when SEPARATE_VERSTAGE is not selected, there is no entry point into romstage and romstage will not be started at all. The solution is move out romstage_after_verstage.S from fsp1.1 driver to skylake/romstage. And add CONFIG_PLATFORM_USES_FSP1_1 to fix the build and boot issue with this change. Besides that, rename the romstage_after_verstage to romstage_c_entry in more appropriate naming convention after this fix. Tested on SkyLake Saddle Brook (FSP 1.1) and KabyLake Rvp11 (FSP 2.0), romstage can be started successfully. Change-Id: I1cd2cf5655fdff6e23b7b76c3974e7dfd3835efd Signed-off-by: Teo Boon Tiong <boon.tiong.teo@intel.com> Reviewed-on: https://review.coreboot.org/17976 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-01-19soc/intel/skylake: Add SATA interrupt for APIC modeSooi, Li Cheng
Add SATA interrupt for APIC mode Change-Id: I9e0682e235715399da2c585174925c89b9116ab3 Signed-off-by: Sooi, Li Cheng <li.cheng.sooi@intel.com> Reviewed-on: https://review.coreboot.org/18130 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-01-19nb/amd/ddr3: Make the maximum CDD a signed valueTimothy Pearson
max_cdd_we_delta should be signed to allow for negative CDD. Found-by: Coverity Scan #1347355 Change-Id: Iaccd1021680296d169c26c25e339f83fbd7cc065 Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com> Reviewed-on: https://review.coreboot.org/18162 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-01-18configs/builder: Add Sandy/Ivy Bridge Thinkpad configurationsPhilipp Deppenwiese
The coreboot builder makes use of the pre defined configuration files by executing abuild with -d option. These configuration files contain a basic configuration. Change-Id: I41470fe7aaa0fdae545ad9d702326a202d0d2312 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/18161 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-18cbfstool: Don't use le32toh(), it's non-standardNico Huber
It's a BSD function, also, we missed to include `endian.h`. Just including `endian.h` doesn't fix the problem for everyone. Instead of digging deeper, just use our own endian-conversion from `commonlib`. Change-Id: Ia781b2258cafb0bcbe8408752a133cd28a888786 Reported-by: Werner Zeh <werner.zeh@siemens.com> Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/18157 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2017-01-17Revert "mainboard/google/snappy: Add PowerResource for ELAN touchscreen"Martin Roth
This reverts commit 01ba8cf7 (mainboard/google/snappy: Add PowerResource for ELAN touchscreen) Change was out of date and broke the build. Change-Id: Id47631ece1172c3f93bf6f40b8686dfd728842a9 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/18158 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-01-17SeaBIOS: Add Kconfig option to set verbosity levelStefan Tauner
Previously SeaBIOS's default was used (1). This patch defaults to coreboot's console level instead which is approximately the same verbosity as SeaBIOS and thus what a user would probably expect. Change-Id: If79e5f40c9380bb527f870eeb7d0cb43faf00beb Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at> Reviewed-on: https://review.coreboot.org/18051 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-01-17util/scripts: extend cross-repo-cherrypickPatrick Georgi
The script now automatically discovers the original branch (if known) and configures itself appropriately. Additionally, commit messages for changes coming _from_ upstream will be prefixed with "UPSTREAM: ". With the optional --cros argument, it also adds a BUG/BRANCH/TEST block at the right place in the commit message (right above the metadata) if one doesn't already exist. Change-Id: I81864ddca62fd99a9eb905d7075e5b53f58c4eb5 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/18135 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-17mainboard/google/reef: Ignore SPI IOSTANDBYLijian Zhao
SPI controller need to access flash descriptors/SFDP during s0ix exit, so all fast SPI IO can't be put into IOSTANDBY state. For reef, that will be FST_SPI_CLK_FB, GPIO_97, GPIO_99, GPIO_100, GPIO_103 and GPIO_106. BUG=chrome-os-partner:61370 BRANCH=reef TEST=Enter s0ix state in OS, after resume run flashrom to read SPI content. Change-Id: I5c59601ec00e93c03dd72a99a739add0950c6a51 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/18137 Tested-by: build bot (Jenkins) Reviewed-by: Vaibhav Shankar <vaibhav.shankar@intel.com> Reviewed-by: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-17mainboard/google/snappy: Add PowerResource for ELAN touchscreenWisley Chen
Define reset_gpio and enable_gpio for touchscreen device so that when kernel puts this device into D3, we put the device into reset. PowerResource _ON and _OFF routines are used to put the device into D0 and D3 states. BUG=chrome-os-partner:59034 BRANCH=master TEST=emerge-snappy coreboot chromeos-bootimage Change-Id: I08c05d06b2812a33b3fdff9b42b2a8e0653dd8b4 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/17366 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-17Combine Baytrail ChromeOS devices using variant schemeMatt DeVillier
Combine existing boards google/enguarde and google/ninja using their common reference board google/rambi as a baseboard. Variants contain board specific data: - DPTF ACPI components - I2C ACPI devices - RAM config / SPD data - devicetree config - GPIOs - board-specific HW components (e.g., LAN) Additionally, some minor cleanup/changes were made: - remove unused ACPI trackpad/touchscreen devices - correct I2C addresses in SMBIOS entries - clean up comment formatting - remove ACPI device for unused light sensor - switch I2C ACPI devices from edge to level triggered interrupts, for better compatibility/functionality (and to be consistent with other recently-upstreamed ChromeOS devices) The existing enguarde and ninja boards are removed. Variant setup modeled after google/auron Change-Id: Iae7855af9a224fd4cb948b854494e39b545ad449 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/18129 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-17google/enguarde,ninja: Prep for variant mergeMatt DeVillier
Minor cleanup for enguarde and ninja devices: - enguarde: correct trackpad I2C slave address - enguarde: remove unused trackpad ACPI devices - ninja: remove unused PS2 keyboard ACPI device Change-Id: I1beb34059ba318e2d496a59e4b482f3462faf232 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/18128 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-16intel: Fix copy/paste error in license textMarshall Dawson
Change all instances of "wacbmem_entryanty" to "warranty". Change-Id: I113333a85d40a820bd8745efe917181ded2b98bf Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/18136 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-01-16riscv: Move mcall numbers to mcall.h, adjust their namesJonathan Neuschäfer
The new name and location make more sense: - The instruction used to call into machine mode isn't called "ecall" anymore; it's mcall now. - Having SBI_ in the name is slightly wrong, too: these numbers are not part of the Supervisor Binary Interface, they are just used to forward SBI calls (they could be renumbered arbitrarily without breaking an OS that's run under coreboot). Also remove mcall_dev_{req,resp} and the corresponding mcall numbers, which are no longer used. Change-Id: I76a8cb04e4ace51964b1cb4f67d49cfee9850da7 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/18146 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>