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That only makes deviceid == 0 (because shifting a 16bit value by 16
bits, well...)
Change-Id: Iddca1de20760f92f70fe2d05886b488e5b48313d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Found-by: Coverity Scan #1229558
Reviewed-on: https://review.coreboot.org/15960
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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Change-Id: I5a1d1ce8ba268b08d1275f392f0b9e602860c6ab
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Found-by: Coverity Scan #1260729
Reviewed-on: https://review.coreboot.org/15957
Tested-by: build bot (Jenkins)
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Omar Pakker
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A struct pci_dev was allocated but not freed.
Change-Id: I6a8bbef6a118fc1f0aa7037e72c4d0dda9208f4b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Found-by: Coverity Scan #1353037
Reviewed-on: https://review.coreboot.org/15971
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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There can be cases where "found" wasn't initialized, do so.
Change-Id: Ifef8d61daa70e27ec39b7a8f3481d2316dfaa36e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Found-by: Coverity Scan #1347334
Reviewed-on: https://review.coreboot.org/15969
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Reserved regions showed different behavior for debug and regular builds.
Debug output was unfriendly, regular was wrong.
Print a proper error message and exit instead.
Change-Id: I9842ff61f7d554800e2041e8c4c607f22b2df79f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Found-by: Coverity Scan #1287076
Reviewed-on: https://review.coreboot.org/15968
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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(pci_read_config32(...) > 14) & 0x3 looks rather unusual (and prevents
"case 3" below from ever happening)
Change-Id: Id90655c39ff53da9569441278bbf73497d643480
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Found-by: Coverity Scan #1293139
Reviewed-on: https://review.coreboot.org/15965
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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Testing for "devfn < 0" on an unsigned doesn't work, and i2c_bus_to_devfn
returns an int (with -1 for "error"), so use int for devfn.
Change-Id: I7d1cdb6af4140f7dc322141c0c018d8418627434
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Found-by: Coverity Scan #1357450, #1357449
Reviewed-on: https://review.coreboot.org/15964
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Update RO_SECTION to match the changes in depthcharge:
https://chromium-review.googlesource.com/#/c/364261
BUG=chrome-os-partner:55713
Change-Id: I7238856cf73a62345778ea87e191a11190b7fb38
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15966
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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This patch enables DPTF support for Intel Amenia
platform, adds the ASL settings specific to Amenia
boards.
BUG=chrome-os-partner:53096
TEST=Verify that the thermal zones are enumerated
under /sys/class/thermal in Amenia board. Navigate to
/sys/class/thermal, and verify that a thermal
zone of type TCPU exists there.
Change-Id: I400e2312a20870058f3a386004fad748d3ee4460
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/15094
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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This patch enables DPTF support for Google Reef
platform, adds the ASL settings specific to Reef
boards.
BUG=chrome-os-partner:53096
TEST=Verify that the thermal zones are enumerated
under /sys/class/thermal in Reef boards. Navigate to
/sys/class/thermal, and verify that a thermal
zone of type TCPU exists there.
Change-Id: Ib43e4e9dd0d92fffc1b2c8459c552acd04ca0150
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/15640
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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After the indentation is fixed in commit *mainboard: Format
irq_tables.c* [1], the comment is redundant. So remove it.
[1] Change-Id: If254723f3013377fb3b9b08dd5eca6b76730ec4a
Change-Id: Iebbcf10ee3cef1b4cf60ea34a6b3ad51e2208671
Reviewed-on: https://review.coreboot.org/15933
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Run the command below to format the files `irq_tables.c` of (mostly AMD)
mainboards correctly with GNU indent 2.2.10.
```
$ git grep -l 'if (sum != pirq->checksum) {' | xargs indent -l
```
Fix up the following two checkpatch.pl errors manually.
```
ERROR: that open brace { should be on the previous line
#1219: FILE: src/mainboard/gigabyte/ga_2761gxdk/irq_tables.c:129:
+ uint8_t reg[8] =
+ { 0x41, 0x42, 0x43, 0x44, 0x60, 0x61, 0x62, 0x63 };
ERROR: that open brace { should be on the previous line
#1221: FILE: src/mainboard/gigabyte/ga_2761gxdk/irq_tables.c:131:
+ uint8_t irq[8] =
+ { 0x0A, 0X0B, 0X0, 0X0a, 0X0B, 0X05, 0X0, 0X07 };
```
This is needed, so that follow-up commits, fixing checkpatch.pl errors
and warnings, won’t run into conflicts with the git commit hooks, when
for example, spaces instead of tabs are used for indentation.
Change-Id: If254723f3013377fb3b9b08dd5eca6b76730ec4a
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/15932
Tested-by: build bot (Jenkins)
Reviewed-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Enable users to set the EC_EXTERNAL_FIRMWARE config flag, and actively
ignore anything related to EC firmware board names if enabled.
BUG=none
BRANCH=none
CQ-DEPEND=CL:344540
TEST=emerge-samus coreboot works
Change-Id: I02aa1e4bc0c98300105b83a12979e9368a40cbcf
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 4f0b6fd10aa89fbb38bdebf14b8a82d52e9ee233
Original-Change-Id: I39c3038d059ec3d7710b864061fcf83b8d6d4d13
Original-Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/345584
Original-Reviewed-by: Aaron Durbin <adurbin@google.com>
Original-Commit-Queue: Martin Roth <martinroth@chromium.org>
Original-Trybot-Ready: Martin Roth <martinroth@chromium.org>
Original-Tested-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/15938
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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This adds support for the Nuvoton NCT6791D Super I/O chip to the
superiotool.
The implementation is based on the Datasheet supplied by Nuvoton:
Datasheet Version: January 8th, 2016 Revision 1.11
Datasheet deviation:
- Defaults for control registers 0x20 and 0x21 are invalid.
Datasheet: 0xc562. Actual: 0xc803.
Change-Id: I8ced9738cd41960cbab7b5ea38ff19192d210672
Signed-off-by: Omar Pakker <omarpakker+coreboot@gmail.com>
Reviewed-on: https://review.coreboot.org/15252
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Change-Id: Ia6ac94a93b48037a392a9aec2cd19cd80369173f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/15953
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: I6c090f5adcc46b4e069a156c6b506a76c0aa7cb5
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/15952
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Omar Pakker
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: I133531391a20261e0926524d70c0901079076af9
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/15943
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Change-Id: I58d5c16de796a91fa14d8db78722024266c09a94
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/15934
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: Id40c1bf868820c77ea20146d19c6d552c2f970c4
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/15942
Tested-by: build bot (Jenkins)
Reviewed-by: Omar Pakker
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: I01413b9f8b77ecdcb781340f04c2fe9e24810264
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/15941
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
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Change-Id: I5aa27f06f82a8309afb6e06c9e462e5792aa9986
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/15940
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: I103167a0c39627bcd2ca1d0d4288eb5df02a6cd2
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/15935
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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The bootblock gets slightly too big, so adjust the space assigned to
it.
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
BUG=none
BRANCH=none
TEST=emerge-nyan coreboot works again.
Change-Id: Ib44d98692ae88c7cd3610c8e643d7d48ac858161
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 4b9038b018ed7a26fbce01d982b22166b328de37
Original-Change-Id: If494e49fb60c11e01ca780c84036ebf24459628c
Original-Reviewed-on: https://chromium-review.googlesource.com/346492
Original-Reviewed-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Queue: Stefan Reinauer <reinauer@google.com>
Original-Tested-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: https://review.coreboot.org/15950
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Change EVT3 board id to 5.
BUG=chrome-os-partner:55320
TEST=None.
BRANCH=None
Change-Id: I020be47e1fdbf886c7c471d7fdcace1537875b6d
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 63bd6541055172765c31a9b1220a24d4e3604cdc
Original-Change-Id: I21a8764ff95892430944778f4898d2f1d4c97fd7
Original-Signed-off-by: Kan Yan <kyan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/362391
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://review.coreboot.org/15949
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Almost all of the places where we have the degree symbol '°', it's
encoded as 0xc2 0xb0 (utf-8 encoding). There are a few places where it
is encoded as just a high ascii byte: 0xb0. Editors that support the
high ascii 0xb0 seem to support the utf-8 0xc2 0xb0 encoding as well,
but the opposite does not seem to be true.
Change the high-ascii degree symbols to utf-8 encoding.
Change-Id: I3d06289b802f45e938dc72b4c437fca56235b62b
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/15978
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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This removes the newlines from all files found by the new
int-015-final-newlines script.
Change-Id: I65b6d5b403fe3fa30b7ac11958cc0f9880704ed7
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/15975
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Turned out that there are versions of the patch command that use the
left hand side path for new files created by a patch. This behavior is
incompatible with some of our patches. Stripping the topmost dir from
the path with -p1 helps.
While touching that line, I couldn't resist to drop a command
substituion (the `echo $patch`). It really shouldn't be necessary as the
path to the patch file is already expanded in the head of the for loop.
Change-Id: I95398605db6dd54a8b08d8bc84c6602edbea6e10
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/15908
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Tested-by: build bot (Jenkins)
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Keep this enabled by default as most x86 platforms could have PCI-e
slots equipped with one of these Intel WiFi adapters.
The Kconfig entries under google boards had no function previously,
the variable was never referenced.
Change-Id: I728ce3fd83d51d4e5e32b848a2079c5fcee29349
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15931
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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Delete pbuilder since it is not needed anymore.
Change-Id: I685547e9692944b89521864fc3bee4e9a2f1139f
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/15955
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Omar Pakker
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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crosfirmware.sh and extract_blobs.sh are not executable, change that.
Change-Id: Ib04df580a9acd4a422aedbdc15013b2ef505459a
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/15922
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Omar Pakker
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Add next generation of BAPs (https://www.unibap.com/) SOC module,
called ode_e21XX.
Hardware is similar to e20XX (AMD G-Series GX-411GA Kabini),
but it includes a new AMD G-Series GX-412HC (Steppe Eagle)
and an updated Microsemi FPGA.
Changes to Olivehillplus:
- Add SuperIO Fintek F81866D
- Soldered down DDR3 with ECC
- User can choose between different DDR3 clk settings
(lowest setting can save up to 1.2W)
- Soldered down Microsemi M2S060 FPGA on PCIe lanes 2-3
Tested with:
- Payload SeaBIOS 1.9.1
- Lubuntu 16.04, Kernel 4.4.0
- Windows 10 (UART functionality)
Known problems:
- S3 not working
- IOMMU not working
Change-Id: I41f6a3334ad2128695a3f7c0a6444f1678d2626e
Signed-off-by: Fabian Kunkel <fabi@adv.bruhnspace.com>
Reviewed-on: https://review.coreboot.org/15918
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Initial copy of olivehillplus.
Change-Id: Ibe9b450c05bfad15a95852addb1465ac2d3cef61
Signed-off-by: Fabian Kunkel <fabi@adv.bruhnspace.com>
Reviewed-on: https://review.coreboot.org/15917
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Use the ACPI generator for creating the Chrome OS gpio
package. Each mainboard has its own list of Chrome OS
gpios that are fed into a helper to generate the ACPI
external OIPG package. Additionally, the common
chromeos.asl is now conditionally included based on
CONFIG_CHROMEOS.
Change-Id: I1d3d951964374a9d43521879d4c265fa513920d2
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15909
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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Due to GPE routing, raw GPIO cannot be used for indicating the wake
signal for touchpad. Instead we need to reference GPE pins.
BUG=chrome-os-partner:55670
Change-Id: Ie5d8473df4301c7beef0cae8fe84e71b2838261b
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15947
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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This is required for using GPE_* macros in devicetree.cb.
BUG=chrome-os-partner:55670
Change-Id: I8f6f536df96cf8145bb0c03ec413fb2f374301b5
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15946
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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1. Enable SoC SD_CMD/D* signals pull-down of 20k when SD-card
is removed. When SD-card is disconnected, the pull-down is
disabled.
2. Provide path for weak leakage from buffers of SD_CMD/D* signal
to be grounded. Thus dropping voltage on the SD_CMD/D* signals to ~0V.
BUG=chrome-os-partner:54421
TEST=no power leakage when SDCard isn't inserted on skylake platform
Change-Id: I567199b172841125f8916a61a76005cfdaa62eb8
Signed-off-by: Zhuo-hao.Lee <zhuo-hao.lee@intel.com>
Reviewed-on: https://review.coreboot.org/15910
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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Do not pass VBT table to fsp in normal mode and S3 resume so that
PEIM GFX will not get initialized.
Change-Id: Iab7be3cceb0f80ae0273940b36fdd9c41bdb121e
Signed-off-by: Abhay Kumar <abhay.kumar@intel.com>
Reviewed-on: https://review.coreboot.org/14575
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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We need to enable DRAM ODT on kevin/gru board to improve the
DRAM signal. Note, if the DRAM ODT is enabled and set to 120ohms,
the sdram VREF need to adjust to 840mv.
This patch also makes following changes:
1. For compatiblity with the old board, add the
"sdram-lpddr3-hynix-4GB-666-no-odt.inc" and
"sdram-lpddr3-hynix-4GB-800-no-odt.inc" files
which do not enable sdram ODT.
2. Delete the 300MHz dram inc file. The 300MHz sdram config just
reduced 666MHz to 300MHz based on the 666MHz config file, and it is
not stable, so delete it.
3. Delete the 928MHz dram inc file, 928MHz sdram config still in
debuging, delete it for now.
BRANCH=none
BUG=chrome-os-partner:54871
TEST=run "stressapptest -M 1024 -s 1000" on kevin board and pass
Change-Id: If0248e1bc4cef2c298762080f1ca018653af0521
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 78d8a28e2d3489c99c9bba2c1c9aa76812e2e33f
Original-Change-Id: I35f0685782d6fb178a95780ec77c45f565dd2194
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/358763
Original-Commit-Ready: Dan Shi <dshi@chromium.org>
Original-Tested-by: Caesar Wang <wxt@rock-chips.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/15813
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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When enabling the controller ODT, the controller vref needs to
correspond with the ODT value and DQ drive strength.
BRANCH=none
BUG=chrome-os-partner:54871
TEST=run "stressapptest -M 1024 -s 1000" on kevin board and pass
Original-Commit-Id: a7251c72b87d9f149b68d086c3252f1c668e0e80
Original-Change-Id: I7e54b3473f68a382208a0fb0b0600552fe6390ad
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/358762
Original-Commit-Ready: Dan Shi <dshi@chromium.org>
Original-Tested-by: Caesar Wang <wxt@rock-chips.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Squashed with:
rockchip/rk3399: Halt if we get an invalid odt or drv value
When we were pushing the updated sdram.c to coreboot.org, the compiler
there found that we were not initializing vref_value_dq in all code
possible code paths.
This patch updates those code paths to halt the system.
Branch=none
Bug=none
Test=Built with coreboot.org toolchain and verified that the compile
errors were gone.
Change-Id: I0ad4207dc976236d64b6cdda58d10bcfbe1fde11
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/362726
Reviewed-by: Julius Werner <jwerner@chromium.org>
Change-Id: I22a0cef6f12d9aae2ea4dcb99e7ebdd788f2cdd1
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/15812
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Update the copyright dates in the FSP 2.0 files.
Add a copyright to Kconfig.
TEST=Build and run on Galileo Gen2
Change-Id: I0ad0c5650bde0e31d01a04bcc7d22a19273fe29b
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15852
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Update the write protect GPIO reported in ACPI to GPIO_75.
Also update the controller ID to "INT3452:01" which will
point at the goldmont device and includes write protect GPIO.
BUG=chrome-os-partner:55604
BRANCH=none
TEST=verify crossystem output for wpsw_cur.
Change-Id: Ibe6a013aaab18bfa2436698298177218ca934fab
Signed-off-by: Susendra Selvaraj <susendra.selvaraj@intel.com>
Reviewed-on: https://coreboot.intel.com/7929
Reviewed-by: Petrov, Andrey <andrey.petrov@intel.com>
Tested-by: Petrov, Andrey <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/15691
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
|
|
Add new UPDs for Fspm and Fsps. Update headers to make new UPDs
available for use. New UPDs enable various memory and trace funtionality
options as well as support for zero sized IBB region.
BUG=chrome-os-partner:55513
BRANCH=none
TEST=built and tested with no regressions
Change-Id: Id1573baaa306ed4fe4353df5f27e5963cb1a76e6
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/15815
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
Including $(top) in the DOTCONFIG definition allows getting rid of the
$(top) prefix in payloads, which in turns allows providing a full path
for DOTCONFIG via the command line.
Change-Id: I7546a12cf4a2a146e32fef81121f45f83ba67ac8
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-on: https://review.coreboot.org/15826
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
Change-Id: If505021c6dd4bc1c98094dc6e4a3da1ea7753859
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/15916
Tested-by: build bot (Jenkins)
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
|
|
Try to make checkpatch a little friendlier to the coreboot project.
This is the checkpatch .conf from the Chrome OS tree.
Change-Id: Ie45d5c93f97bd58f3ea31341b47c4ee2a8f02b1e
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/15919
Tested-by: build bot (Jenkins)
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
|
|
This patch updates dptf variable in gnvs based on device
configuration by reading the device tree structure.
BUG=chrome-os-partner:53096
TEST=Verify that the thermal zones are enumerated
under /sys/class/thermal in Amenia and Reef board.
Navigate to /sys/class/thermal, and verify that a
thermal zone of type TCPU exists there.
Change-Id: I8ab34cdc94d8cdc840b02347569a9f07688e92cd
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/15620
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
This patch adds apollolake soc specific change. DPTF
ASL files are now in src/soc/intel/common so that
they can be reused but different soc can have different values
e.g., for skylake cpu soc thermal reporting device is at
Bus 0, Device 4, Function 0 while for apollolake it is Bus 0, Device 0,
Function 1. This patch adds a dptf asl file in soc directory where we
can define all values which can change across soc's and can be
included in mainboard dptf asl.
BUG=chrome-os-partner:53096
TEST=In Amenia and Reef board verify that the thermal zones are
enumerated under /sys/class/thermal in Amenia and Reef board.
Navigate to /sys/class/thermal, and verify that a thermal
zone of type TCPU exists there.
Change-Id: I888260a9c799d36512411a769f26dd30cf8d5788
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/15619
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
|
|
This patch adds the common ASL code for Intel
platforms. This is the basic ASL needed to add support
for DPTF controlled devices. We are moving
these commmon ASL files to src/soc/intel/common/acpi as
these are same codes used in all Intel platforms and
hence no need to duplicate.
BUG=chrome-os-partner:53096
TEST=Verify that the thermal zones are enumerated
under /sys/class/thermal. Navigate to
/sys/class/thermal, and verify that a thermal
zone of type TCPU exists there.
Change-Id: I01078382a9008263c6ad99f6bf07558885af6a63
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/15093
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
|
|
Change-Id: I06c1d0fe0e3d429e54d3777de679f9fc641f4eed
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/15927
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Including the terminating null, 17 characters were being written to the
field, overwriting the a byte of the size field.
Fortunately, the size was updated soon after this.
Fixes coverity warning 1229570 - Destination buffer too small.
Change-Id: I39285a9283dd9a17d638afe5b2755c7e420d7698
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/15889
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
A few things are currently missing:
- The trap handler doesn't set the stack pointer, which can easily
result in trap loops or memory corruptions.
- The SBI trampolin page (as described in version 1.9 of the RISC-V
Privileged Architecture Specification), has been removed for now.
Change-Id: Id89c859fab354501c94a0e82d349349c29fa4cc6
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/15591
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
|
And do the detection just before the initialization.
Change-Id: I9a52430262f799baa298dc4f4ea459880abe250e
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/15831
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
|
These functions are not used anywhere.
Change-Id: Ica1f4650e8774dd796be0aff00054f3698087816
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/15829
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
|
FSP temp ram init was getting called earlier from ROMCC bootblock.
Now with C entry boot block, it is needed to locate FSP header and
call FspTempRamInit.
Hence add fsp 1_1 driver code to locate FSP Temp ram and execute.
BUG=chrome-os-partner:55357
BRANCH=none
TEST=Built kunimitsu and ensure FSP Temp Ram Init return success
Change-Id: If40b267777a8dc5c473d1115b19b98609ff3fd74
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/15787
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Define LPC decode ranges for EC communication.
BUG=chrome-os-partner:55357
BRANCH=none
TEST=Built and boot kunimitsu to ensure no EC timeout error
Change-Id: Idefdd79e67e89a794195c6821fee16550d1eda53
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/15898
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Move mainboard post console init functionality (google_chrome_ec_init &
early_gpio programming) from verstage to bootblock.
Add chromeos-ec support in bootblock
BUG=chrome-os-partner:55357
BRANCH=none
TEST=Built and boot kunimitsu till POST code 0x34
Change-Id: I1b912985a0234d103dcf025b1a88094e639d197d
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/15786
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
List of activity performing in this patch
- early PCH programming
- early SA programming
- early CPU programming
- mainborad early gpio programming for UART and SPI
- car setup
- move chipset programming from verstage to post console
BUG=chrome-os-partner:55357
BRANCH=none
TEST=Built and booted kunimitsu till POST code 0x34
Change-Id: If20ab869de62cd4439f3f014f9362ccbec38e143
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch@intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/15785
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Enable cache-as-ram and prepare for c entry in bootblock.
BUG=chrome-os-partner:55357
BRANCH=none
TEST=Built and booted kunimitsu till POST code 0x2A
Credits-to: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I3412216cdf8ef7e952145943d33c3f07949da3c1
Reviewed-on: https://review.coreboot.org/15784
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Change-Id: Iba5fc92d8740d0bb7d41f8a83513ba7fb97be592
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/15900
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Update MSR's registers regarding "Intel® 64 and IA-32
Architectures Software Developer’s Manual"- April 2015.
"64-ia-32-architectures-software-developer-manual-325462.pdf"
Change-Id: I71e399c4a6fef9de6a5581b64a6918660b2f8445
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/15798
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
|
|
Change-Id: I8b7d2263591608e0ab9504262bb06eac4cb52850
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/15779
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
BUG=chrome-os-partner:55639
Change-Id: I7a536bc1cab51e7c942b2e0e48dfe18d8de08a6e
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15925
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins)
|
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BUG=chrome-os-partner:55639
Change-Id: Ie38cdbec513e2bb66e276399c8b4490cbe34a747
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15924
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins)
|
|
BUG=chrome-os-partner:55639
Change-Id: I40a28f921499ddf43d8b423f5192ac93b40254c1
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15903
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
|
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1. Currenty, boot reason is being added to elog only for some
ARM32/ARM64 platforms. Change this so that boot reason is logged by
default in elog for all devices which have CHROMEOS selected.
2. Add a new option to select ELOG_WATCHDOG_RESET for the devices that
want to add details about watchdog reset in elog. This requires a
special region WATCHDOG to be present in the memlayout.
3. Remove calls to elog add boot reason and watchdog reset from
mainboards.
BUG=chrome-os-partner:55639
Change-Id: I91ff5b158cfd2a0749e7fefc498d8659f7e6aa91
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15897
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
|
|
This is required to enable elog support in ChromeOS by default.
BUG=chrome-os-partner:55639
Change-Id: I9c97143d794de4bf220ddf67c0ca2eac2f7a326d
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15896
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
|
|
BUG=chrome-os-partner:55639
Change-Id: Idbad4f8763be18002907a62be755b2fdf7e479ec
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15895
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
|
|
BUG=chrome-os-partner:55639
Change-Id: Ie859ec3ff682e91a4d7d38d3c3cd6badf7385431
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15894
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
|
|
These files are required by storm and gale boards for enabling elog
support in ramstage.
BUG=chrome-os-partner:55639
Change-Id: I2bbfee2acf2bfe2f896a8619b1276dcea1b87f16
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15893
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
|
|
BUG=chrome-os-partner:55639
Change-Id: I3ac2b256862758bb5c9e6c2f1311972af474e8f6
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15870
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
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With VBOOT_VERIFY_FIRMWARE separated from CHROMEOS, move recovery and
developer mode check functions to vboot. Thus, get rid of the
BOOTMODE_STRAPS option which controlled these functions under src/lib.
BUG=chrome-os-partner:55639
Change-Id: Ia2571026ce8976856add01095cc6be415d2be22e
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15868
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
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VBOOT_VERIFY_FIRMWARE should be independent of CHROMEOS. This allows use
of verified boot library without having to stick to CHROMEOS.
BUG=chrome-os-partner:55639
Change-Id: Ia2c328712caedd230ab295b8a613e3c1ed1532d9
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15867
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
|
|
If the system is in recovery, store the newly generated MRC data using a
dummy version which is not legit. This ensures that on next normal boot,
new MRC data will be generated and stored.
BUG=chrome-os-partner:55699
Change-Id: Ib13e8c978dc1b4fc8817fab16d0e606f210f2586
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15828
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
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Currently, coreboot performs an erase of the entire MRC cache region on
flash if there is a version mismatch for the MRC data. Instead of doing
that, store the new MRC data in the next available slot, if there is
enough space available in the cache region.
BUG=chrome-os-partner:55699
Change-Id: Ib24a94f0a47c79941ed9f60095360ae3aad5540b
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15915
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
The slippy board was a proof of concept device that has never
made it out in the wild. Moreover, I don't think any of these
boards exist any longer.
Change-Id: I24fb08d9be35b2367e7aa64520ce5778ab861535
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15902
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
The bolt board was a proof of concept device that has never
made it out in the wild. Moreover, I don't think any of these
boards exist any longer.
Change-Id: I5ca055d448659a2b8e2eafcfc2114a6b8f8a56a4
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15901
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
The monitor/mwait is broken on Apollolake. So use ACPI legacy
mwait IO redirection as a work around
BUG=chrome-os-partner:55110
Change-Id: I2e1834130d9586b4310466d3549d19bf427ffe24
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/15890
Tested-by: build bot (Jenkins)
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
This renames the VB_SOURCE variable to VBOOT_SOURCE in the build system,
providing increased clarity about what it represents.
Since the submodule itself is called "vboot", it makes sense to use that
name in full instead of a very shortened (and confusing) version of it.
Change-Id: Ib343b6642363665ec1205134832498a59b7c4a26
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-on: https://review.coreboot.org/15824
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
This introduces a CHROMEEC_SOURCE variable used for indicating the CrOS
EC source path, with a fallback to 3rdparty/chromeec.
This allows specifying an external path for the CrOS EC source path.
Change-Id: I9792c7f21597127a385b961b65a00d44cfa37146
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-on: https://review.coreboot.org/15765
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
Quark does not support the rdmsr and wrmsr instructions. Use SOC
specific routines to configure the MTRRs on Quark based platforms.
Add cpu_common.c as a build dependency to provide access to the routine
cpu_phys_address_size.
TEST=Build and run on Galileo Gen2
Change-Id: I43b7067c66c5c55b42097937e862078adf17fb19
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15846
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Quark does not support the rdmsr and wrmsr instructions. In this case
use a SOC specific routine to support the setting of the MTRRs. Migrate
the code from FSP 1.1 to be x86 CPU common.
Since all rdmsr/wrmsr accesses are being converted, fix the build
failure for quark in lib/reg_script.c. Move the soc_msr_x routines and
their depencies from romstage/mtrr.c to reg_access.c.
TEST=Build and run on Galileo Gen2
Change-Id: Ibc68e696d8066fbe2322f446d8c983d3f86052ea
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15839
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Now hardcode maximum memory frequency capability to 800MHz, as
all chipsets in x4x family support PC2-6400 according to the datasheet.
CAS latency detection also relies on this, and has been cleaned up.
Ram initialization does not work with FSB 1333MHz / DDR2 800MHz combination,
so disable this combination for now, and reduce to 667MHz instead.
Still don't know why this is the case, but FSB1333/667 works.
These changes should now allow existing configurations to continue working,
while providing support for previously unworking configurations, due to
previous buggy CAS latency detection code.
TESTED: on GA-G41M-ES2L
CPU: E5200 @ 2.50GHz (FSB 800MHz)
2x 1GB 667MHz hynix worked @ 667
1x 2GB 800Mhz ARAM worked @ 800
1x 1GB 667Mhz StarRam worked @ 667
2x 2GB 800Mhz (generic) worked @ 800
Change-Id: I1ddd7827ee6fe3d4162ba0546f738a8f9decdf93
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/15818
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Allow bootblock to get access to the static device tree like
other early stages. device_romstage.c was renamed to
device_simple.c to better articulate the usage since it's not
just being used in romstage.
BUG=chrome-os-partner:55357
Change-Id: I3d63d2754c737cc738c09a3e3b3b468362fb78d1
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15837
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins)
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All mainboards (nyans) utilizing the cache_policy option
has it set to DCACHE_WRITETHROUGH. This option is for setting
the framebuffer's cache attribute. However, this option is
reliant on an architecture-specific enumeration. Just remove
the option and use DCACHE_WRITETHROUGH across the board. If
someone wants to reconfigure it at a later date one can
introduce a non-architecture specific option.
Change-Id: I6a0848231f5e28d36ec2d56b239bed67619fe5a7
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15838
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Convert the FSP 2.0 UPD headers from typedef to struct:
* FSP_UPD_HEADER
* FSPM_ARCH_UPD
TEST=Build and run on Galileo Gen2
Change-Id: Iab241ea07c955e95ff988a4a30103d2a112179b6
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15856
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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We set this driving control to prevent signal attenuation caused by
LVDS DRV termination.
When DA_LVDSTX_PWR_ON is not set, LVSH has no power and LVDS DRV
termination status is unknown(floating). This creates a chance that MIPI
output would be influenced. The DSI's LP signal will be half voltage
attenuation. There will be no display on panel.
When DA_LVDSTX_PWR_ON is set, LVSH and LVDS DRV termination are
effective and termination is fixed OFF. The DSI won't be influenced.
We only need to set this register once, so we set it here to prevent
repeat setting in the kernel when the system goes to recovery mode.
BUG=chrome-os-partner:55296
BRANCH=none
TEST=build pass elm and show ui
The original commit in the cros repo combined the chipset and mainboard
code changes. This has been split for the push to coreboot.org
Change-Id: I733bdd115950b71493856220414ac0dd75d28122
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 0d25a27f300acc4b65a894110d3ee0cc9676cd12
Original-Change-Id: Ie71f9cc41924787be8539c576392034320b57a49
Original-Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/360850
Original-Commit-Ready: jitao shi <jitao.shi@mediatek.com>
Original-Tested-by: jitao shi <jitao.shi@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/15808
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
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We set this driving control to prevent signal attenuation caused by
LVDS DRV termination.
When DA_LVDSTX_PWR_ON is not set, LVSH has no power and LVDS DRV
termination status is unknown (floating). This creates a chance that
MIPI output would be influenced. The DSI's LP signal will be half
voltage attenuation. There will be no display on panel.
When DA_LVDSTX_PWR_ON is set, LVSH and LVDS DRV termination are
effective and termination is fixed OFF. The DSI won't be influenced.
We only need to set this register once, so we set it here to prevent
repeatedly setting in the kernel when the system goes to recovery mode.
BUG=chrome-os-partner:55296
BRANCH=none
TEST=build pass elm and show ui
Change-Id: Ie3ccf6fb611dd5a1e2c02b7825d42a92e61268c0
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 0d25a27f300acc4b65a894110d3ee0cc9676cd12
Original-Change-Id: Ie71f9cc41924787be8539c576392034320b57a49
Original-Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/360850
Original-Commit-Ready: jitao shi <jitao.shi@mediatek.com>
Original-Tested-by: jitao shi <jitao.shi@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/15807
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Place a map file for the postcar stage and place it into
build/cbfs/fallback.
TEST=Build and run on Galileo Gen2
Change-Id: I349c06e3c610db5b3f2511083208db27110c34d0
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15845
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Move the ramstage files to the beginning of the section. Eliminate
duplicate conditionals.
TEST=Build and run on Galileo Gen2
Change-Id: I461a5b78a76bd0d2643b85973fd0a70bc5e89581
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15892
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Move the romstage files into the romstage section of the file.
Eliminate duplicate conditional statements.
TEST=None
Change-Id: Ie2d65cef3797a2c091c0cd76b147b30a765332ad
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15891
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
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Move the postcar commands to in between romstage and ramstage. Add the
stage header.
TEST=Build and run on Galileo Gen2
Change-Id: I530da6afd8ccbcea217995ddd27066df6d45de22
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15844
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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The removal of ELOG_FLASH_BASE and ELOG_FLASH_SIZE resulted
in the FMAP region for the eventlog to be honored. However,
certain systems seem to have a large eventlog region that
wasn't being used in practice. Because of the malloc() in the
eventlog init sequence a large allocation was now being requested
that can exhaust the heap. Put back the 4KiB capacity until
the resource usage is fixed.
BUG=chrome-os-partner:55593
Change-Id: Ib54b396b48e5be80f737fc3feb0d58348c0d2844
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15835
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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XIP cachelines contain the executable to run, we never want
that to get modified. With the change such erronous writes
are ignored and next cacheline miss will fetch from boot
media (SPI / FWH flash).
Change-Id: I52b62866b5658e103281ffa1a91e1c64262f3175
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15778
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Match the definition and use of these variable with haswell, such that
DCACHE_RAM_MRC_VAR_SIZE is not included in DCACHE_RAM_SIZE.
Change-Id: I5af20f63cd0cb631d39f7c7fe0e2a99ebd3ce986
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15761
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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The build fails during postcar when ULZMA compression is not selected.
Fix cbfs.c to support LZ compression for ramstage as well.
The build error is:
build/postcar/lib/cbfs.o: In function `cbfs_load_and_decompress':
/home/lee/coreboot/public/src/lib/cbfs.c:116: undefined reference to
`ulzman'
make: *** [build/cbfs/fallback/postcar.debug] Error 1
TEST=Build and run on Galileo Gen2
Change-Id: I7fa8ff33c0d32e0c5ff5de7918e13e6efb1df38e
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15841
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Separate NO_XIP_EARLY_STAGES from loading FSP-M into cache-as-RAM.
Quark executes romstage directly from the SPI flash part (in-place),
but loads FSP-M into ESRAM. This split occurs because ESRAM is too
small to hold everything while debugging.
Platforms executing FSP-M directly from the SPI flash need to select
FSP_M_XIP.
TEST=Build and run on Galileo Gen2.
Change-Id: Ib5313ae96dcec101510e82438b1889d315569696
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15848
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Enable the display of cbmem during romstage and postcar. Add a Kconfig
value to prevent coreboot images from increasing in size when this
feature is not in use.
TEST=Build and run on Galileo Gen2
Change-Id: Ib70ad517ebf7d37a7f46ba503b4432c7c04d7ded
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15842
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Build the UART drivers for the postcar stage.
TEST=Build and run on Galileo Gen2
Change-Id: I8bf51135ab7e62fa4bc3e8d45583f2feac56942f
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15843
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This allows the board to save the recovery request in case of unexpected
reboots caused by FSP.
With recovery module in vboot handling the saving of recovery reason
across reboots, there is no need to have special fsp reset handling
under soc.
BUG=chrome-os-partner:55431
Change-Id: I0b7ce14868a322072d3e60c1dae43f211b43fdbf
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15804
Tested-by: build bot (Jenkins)
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This allows the board to save the recovery request in case of unexpected
reboots caused by FSP.
BUG=chrome-os-partner:55431
Change-Id: If71802d2cba52a426f4c2db90d6c5384ed03ce68
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15803
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
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