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2021-06-16soc/intel/jasperlake: Make use of is_devfn_enabled() functionSubrata Banik
1. Replace all pcidev_path_on_root() and is_dev_enabled() functions combination with is_devfn_enabled(). 2. Remove unused local variable of device structure type (struct device *). 3. Replace pcidev_path_on_root() and dev->enabled check with is_devfn_enabled() call. TEST=Able to build and boot without any regression seen on dedede Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: I4919a1ec02df50bc41fd66d5f3a352108a7aa04c Reviewed-on: https://review.coreboot.org/c/coreboot/+/55329 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-16soc/intel/cannonlake: Make use of is_devfn_enabled() functionSubrata Banik
1. Replace all pcidev_path_on_root() and is_dev_enabled() functions combination with is_devfn_enabled(). 2. Remove unused local variable of device structure type (struct device *). 3. Replace pcidev_path_on_root() and dev->enabled check with is_devfn_enabled() call. TEST=Able to build and boot without any regression seen on CML. Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: Ib5df5fd32e2e2742d349754a942bf81ca505dd39 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55328 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-16soc/intel/apollolake: Make use of is_devfn_enabled() functionSubrata Banik
1. Replace all pcidev_path_on_root() and is_dev_enabled() functions combination with is_devfn_enabled(). 2. Remove unused local variable of device structure type (struct device *). 3. Replace pcidev_path_on_root() and dev->enabled check with is_devfn_enabled() call. TEST=Able to build and boot without any regression seen on Reef. Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: I900038dd4b2e2d89b1236bbd26bec5f34483b9f3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55327 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-16cpu/x86/mp_init: Support both xapic and x2apic with common codeArthur Heymans
Trigger mode LAPIC_INT_LEVELTRIG was only used with LAPIC_DM_INIT, specifically for (obsolete) Init Level De-assert. Level LAPIC_INT_ASSERT is required to be set for all other delivery modes other than LAPIC_DM_INIT. This reverts the two above changes that X2APIC mode support introduced to the IPI for LAPIC_DM_SMI. Change-Id: I7264f39143cc6edb7a9687d0bd763cb2703a8265 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55197 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-15tpm/tss: Remove local variablePatrick Georgi
Depending on how the "middle-end" (yes, the gcc developers are serious about that) optimizer ends up mangling the code, there may or may not be a complaint about x being used uninitialized when it's clearly not used at all. So instead, why keep x in the first place? memcpy(foo, NULL, 0) is the same as memcpy(foo, some_uninitialized_variable, 0) in that it does nothing. Change-Id: Ib0a97c3e3fd1a2a6aff37da63376373c88ac595d Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55499 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-15vc/mediatek/mt8195: Match definition with declarationPatrick Georgi
gcc 11 insists. Change-Id: Icec68ab7a3c0bce9b18e37c1b6f41603c97181e2 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55501 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-15vc/mediatek/mt8195: Fix code indentationPatrick Georgi
gcc 11 complains about it otherwise. Change-Id: Ic9b2124506f33c76902d3b44481f14182c1d74b9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55500 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-153rdparty/libhwbase: Update to latest ToTPatrick Georgi
This update adds a commit to fix building libgfxinit with gcc 11 Change-Id: I5c0e3823ab7219667f9430bce74e4f2fba0c0c3a Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55497 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-06-15src/console/init.c: Make get_log_level static inline againJakub Czapiga
CB:55356 removed static inline declarations from get_log_level(). This commit puts them back. It also changes the method of accessing static symbols in tests/console/routing-test to source file inclusion like in CB:46458 to avoid changing tested source file. Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: Iaa5dcbccb327f819374967be51ef642b1fb25e7b Reviewed-on: https://review.coreboot.org/c/coreboot/+/55473 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-15mb/lenovo/w541: Add ThinkPad W541Amersel
Add support for the ThinkPad W541 based on Peter Lemenkov's initial W541 port. Compiled and tested with SeaBIOS and Tianocore booting into Arch Linux 5.10.32-lts. The Haswell mrc.bin blob is required. Tested working: - SATA SSD - SATA DVD drive - M.2 SATA - All USB ports - SD card reader - Speakers/headphone jack - Keyboard/touchpad - libgfxinit - VGA - mini DisplayPort (Thunderbolt untested) - eDP laptop screen - NVIDIA GPU in Linux - Camera/Mic - Smartcard reader - Internal flashing when IFD is unlocked - ThinkPad basic dock (VGA, USB, Ethernet) - CMOS options - WLAN - Bluetooth - Ethernet - Using me_cleaner - All DDR3 slots Not working: - Keyboard backlight - First boot can take up to 20s (MRC.bin is slow) Untested: - Thunderbolt - Internal flashing when IFD is locked - Other ThinkPad docks (DisplayPort, DVI, Audio) - ExpressCard slot - Battery thresholds - WWAN card - Fingerprint reader - USB Debug console Signed-off-by: Justin Wu <amersel@runbox.me> Change-Id: Ia43070f51bba3cf59ba9b7d9e29e4e778efbeb08 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52659 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Peter Lemenkov <lemenkov@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-15nb/intel/sandybridge: Add x86_64 supportPatrick Rudolph
Fix compilation on x86_64 by using compatible types. The MRC blob isn't supported yet as there's no x86_32 wrapper. Tested on HP8200: * Still boots on x86_32. * Boots to payload in x86_64 Change-Id: Iab29a87d52ad3f6c480f21a3b8389a7f49cb5dd8 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44677 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-06-15cpu/x86/Kconfig: Increase SMM stack size to 0x800 on x86_64Patrick Rudolph
In x86_64 code every function call consumes 32byte of stack with no stack local variables being used. That limits the function call depth in SMM to 32 or less. Double the stack size to prevent overwriting the stack canary as seen on HP8200 and x86_64 enabled. Change-Id: Iee202ba2ae609a474d0eb3b06f49690f33f4eda8 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55449 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-06-15treewide: Disable R_AMD64_32S relocation supportPatrick Rudolph
This fixes a hard to debug hang that could occur in any stage, but in the end it follows simple rules and is easy to fix. In long mode the 32bit displacement addressing used on 'mov' and 'lea' instructions is sign-extended. Those instructions can be found using readelf on the stage and searching for relocation type R_X86_64_32S. The sign extension is no issue when either running in protected mode or the code module and thus the address is below 2GiB. If the address is greater than 2GiB, as usually the case for code in TSEG, the higher address bits [64:32] are all set to 1 and the effective address is pointing to memory not paged. Accessing this memory will cause a page fault, which isn't handled either. To prevent such problems - disable R_AMD64_32S relocations in rmodtool - add comment explaining why it's not allowed - use the pseudo op movabs, which doesn't use 32bit displacement addressing - Print a useful error message if such a reloc is present in the code Fixes a crash in TSEG and when in long mode seen on Intel Sandybridge. Change-Id: Ia5f5a9cde7c325f67b12e3a8e9a76283cc3870a3 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55448 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-06-15cpu/intel/msr.h: Sort MSRs in ascending orderAngel Pons
Sort MSR definitions in ascending order to keep things organized. Change-Id: Iadfd28014dc6f41dae7b52b1550c699c89fe8bdc Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55457 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-06-15cpu/intel/msr.h: Add license headerAngel Pons
This is most likely an oversight. Given that the coreboot project as a whole is licensed as GPLv2, add a GPL-2.0-only SPDX license identifier. Change-Id: I1acaf901e1426bd6747f8a772a498a0005b457fa Signed-off-by: Angel Pons <th3fanbus@gmail.com> Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55456 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-06-14ACPI: Refactor use of global and device NVSKyösti Mälkki
After ChromeOS NVS was moved to a separate allocation and the use of multiple OperationRegions, maintaining the fixed offsets is not necessary. Use actual structure size for OperationRegions, but align the allocations to 8 bytes or sizeof(uint64_t). Change-Id: I9c73b7c44d234af42c571b23187b924ca2c3894a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51639 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-14ChromeOS: Separate NVS from global GNVSKyösti Mälkki
Allocate chromeos_acpi in CBMEM separately from GNVS. Change-Id: Ide55964ed53ea1d5b3c1c4e3ebd67286b7d568e4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51638 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-14soc/amd/{cezanne,picasso}: Add TS_START_ROMSTAGERaul E Rangel
BUG=b:179092979 TEST=boot guybrush and see romstage tag 14:finished loading romstage 2,683,151 (10,079) 1:start of romstage 2,683,159 (8) 970:<unknown> 2,683,386 (227) 15:starting LZMA decompress (ignore for x86) 2,683,391 (5) 16:finished LZMA decompress (ignore for x86) 2,717,867 (34,476) Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ib8b3fe909140e05a89b74df526bf4f81799ad915 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55398 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-14commonlib/timestamp: Clarify wording on TS_LOAD_PAYLOADRaul E Rangel
It's helpful to know if it's the start or end of a step. BUG=b:179092979 TEST=none Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I550e2535615ff7e92c7c8a68c8b149f0a3476d1f Reviewed-on: https://review.coreboot.org/c/coreboot/+/55372 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-14mb/google/volteer/var/collis: change GPP_B2 to PLTRSTNick Vaccaro
Change GPP_B2 (EN_PP3300_SSD) to PLTRST to avoid S3 resume hang. BUG=b:174776411 BRANCH=none TEST=none Change-Id: I18ee085cde0570ef278ea3869be30471ed04e3db Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55446 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-14mb/google/volteer/var/eldrid: change GPP_B2 to PLTRSTNick Vaccaro
Change GPP_B2 (EN_PP3300_SSD) to PLTRST to avoid S3 resume hang. BUG=b:174776411 BRANCH=none TEST=none Change-Id: Icfde6b57ff5f6e49ff7804eff6e6a5819bb784bc Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55445 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-14mb/google/volteer/var/volet: change GPP_B2 to PLTRSTNick Vaccaro
Change GPP_B2 (EN_PP3300_SSD) to PLTRST to avoid S3 resume hang. BUG=b:174776411 BRANCH=none TEST=none Change-Id: Ib0858afa1b5dc9de9db87485d3e0bf6032416746 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55444 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-14mb/google/volteer/var/elemi: change GPP_B2 to PLTRSTNick Vaccaro
Change GPP_B2 (EN_PP3300_SSD) to PLTRST to avoid S3 resume hang. BUG=b:174776411 BRANCH=none TEST=none Change-Id: I19b5e1c4beebbc1ebd3d2e30bc22e8c890aaf78f Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55443 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-14mb/google/volteer/var/copano: change GPP_B2 to PLTRSTNick Vaccaro
Change GPP_B2 (EN_PP3300_SSD) to PLTRST to avoid S3 resume hang. BUG=b:174776411 BRANCH=none TEST=none Change-Id: I7d35c284b88b8828d31fff9ccafeb914542b0837 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55442 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-14mb/google/volteer/var/voema: change GPP_B2 to PLTRSTNick Vaccaro
Change GPP_B2 (EN_PP3300_SSD) to PLTRST to avoid S3 resume hang. Add GPP_B2 to the early_gpio_table. BUG=b:174776411 BRANCH=none TEST=none Change-Id: If8c253236051f6d170fab444cfc166e5d2ed7bc2 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55441 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-14mb/google/volteer/var/drobit: change GPP_B2 to PLTRSTNick Vaccaro
Change GPP_B2 (EN_PP3300_SSD) to PLTRST to avoid S3 resume hang. Add GPP_B2 to the early_gpio_table. BUG=b:174776411 BRANCH=none TEST=none Change-Id: I49f7b1b69c3c3ab5593c7230d8f631a3b54c9c9d Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55440 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-14mb/google/volteer/var/terrador: change GPP_B2 to PLTRSTNick Vaccaro
Change GPP_B2 (EN_PP3300_SSD) to PLTRST to avoid S3 resume hang. Add GPP_B2 to the early_gpio_table. BUG=b:174776411 BRANCH=none TEST=none Change-Id: I1214246bb1318869e9b6f57cb6a7e74bbe6574cc Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55439 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-14mb/google/volteer/var/delbin: change GPP_B2 to PLTRSTNick Vaccaro
Change GPP_B2 (EN_PP3300_SSD) to PLTRST to avoid S3 resume hang. Add GPP_B2 to the early_gpio_table. BUG=b:174776411 BRANCH=none TEST=none Change-Id: Ifb6b5b14cec9e6f7c68aa9b01621fdb21c885552 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55438 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-14mb/google/volteer/var/volteer2: change GPP_B2 to PLTRSTNick Vaccaro
Change GPP_B2 (EN_PP3300_SSD) to PLTRST to avoid S3 resume hang. Add GPP_B2 to the early_gpio_table. BUG=b:174776411 BRANCH=none TEST=none Change-Id: I07be950096aef42dbf4f067134e56c5849dfa02d Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55433 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-06-14mb/google/volteer/var/voxel: change GPP_B2 to PLTRSTNick Vaccaro
Change GPP_B2 (EN_PP3300_SSD) to PLTRST to avoid S3 resume hang. BUG=b:174776411 BRANCH=none TEST=none Change-Id: Ia7db2d0a1fff98d1cfb8e7e979c0a81b9f3d0e9e Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55432 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-06-14mb/google/volteer/var/baseboard: change GPP_A11 to PLTRSTNick Vaccaro
The system will hang when resuming from S3 if the SSD reset gpio is not reset early enough. Change GPP_A11 in baseboard to PLTRST to avoid an S3 resume hang. BUG=b:174776411 BRANCH=none TEST=none Change-Id: Ia78d813cb6bc689b07e8d8ead1ade6e77f925ce1 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55431 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-06-14soc/amd/common/pi/agesawrapper: use IOAPIC ID definesFelix Held
Part of the soc/amd/stoneyridge code already uses the FCH_IOAPIC_ID and GNB_IOAPIC_ID defines. Use those defines in the remaining location to make sure that the IOAPIC IDs are always consistent between the hardware register, the MADT and the IVRS ACPI tables. TEST=Timeless build of amd/gardenia results in identical binary. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I410a6560de66889b153c8a66b8dc5474ac114ba7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55429 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2021-06-14soc/intel/broadwell/pch: Drop device NVS remaindersAngel Pons
Now that device NVS is no longer used as such, stop using it to store ACPI device settings consumed by the SSDT generator. Instead, provide the get_acpi_device_state() function to allow saving ACPI device BARs and activation state from other compilation units. Also, introduce an enum and a struct to ease handling device state. Tested on out-of-tree Compal LA-A992P, SerialIO SSDT does not change. Change-Id: I9e70bf71e808651cb504399dcee489a4d1a70e67 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52521 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-14soc/intel/broadwell/pch: Replace ACPI device NVSAngel Pons
The same functionality can be provided through a runtime-generated SSDT. The remaining parts of device NVS are removed in a follow-up. Since the SSDTs are only loaded after the DSDT (if loaded at all), using SSDT-provided objects outside method bodies is not possible: the objects are not yet in OSPM's ACPI namespace, which causes in ACPI errors. Owing to this, the operation regions used by the _PS0 and _PS3 methods need to be moved into the SSDT, as they depend on the SSDT-provided BAR1 values. Tested on out-of-tree Compal LA-A992P, generated SSDT disassembles with no errors and contains expected values. Linux does not complain either. Change-Id: I89fb658fbb10a8769ebea2e6535c45cd7c212d06 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52520 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-14soc/intel/broadwell: Re-do SerialIO UART console supportAngel Pons
Use the same code from Lynx Point on Broadwell, and adjust as needed. Also add a config file to ensure the code gets build-tested. Tested on out-of-tree Compal LA-A992P (Haswell ULT), UART 0 works. Change-Id: I527024098738700d5fbaf3e27cf4db331a0322bd Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37553 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-06-14soc/intel/common/block/uart: Fix resources in ACPI modePatrick Rudolph
In ACPI mode the device cannot be enumerated and thus the payload and bootloader doesn't know about the active resources. An ACPI aware OS can use the _CRS to determine the active MMIO window. Mark the BAR0 as reserved if the device is in ACPI mode to make sure the BAR is reserved in e820 tables. Change-Id: I6079b1eb7b0c87c752515340aac8776244b30ca0 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55271 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-06-14mb/intel/adlrvp: Add board id for MR DDR5 SKUDeepti Deshatty
Add support for Maple Ridge DDR5 SKU with boardid 0x16 TEST=Verified build for ADL-P Chrome RVP Signed-off-by: Deepti Deshatty <deepti.deshatty@intel.com> Change-Id: I9f0e9072f5866b60fb8463bb90f61915c78568db Reviewed-on: https://review.coreboot.org/c/coreboot/+/52760 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.corp-partner.google.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: V Sowmya <v.sowmya@intel.com>
2021-06-14amdfwtool: Null check the pointers before using themZheng Bao
BUG=b:188769922 Reported-by: Coverity (CID:1438963) Change-Id: Ia520e33c9e4065236478665fb0ef047fa47c9b81 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54999 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-14mb/asus: Rename p8z77-series to p8x7x-seriesBill XIE
Many more asus boards using Panther Point PCH other than Z77 can be added as variants of this series. Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Change-Id: I3e0b5734658912a69ccde94d530399059502c4c4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55110 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-14mb/asus/p8z77-series: Add P8Z77-V as a variant of P8Z77 seriesBill XIE
Mainboard information can be found in the included documentation. Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Change-Id: Ic56ac0e5f93a6e818ef0666e41996718471b1cf6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54338 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-14mb/google/volteer/var/voema: Reduce stop delay time to 150ms for ELAN TSDavid Wu
Set register "generic.stop_delay_ms" to 150 to reduce power resume time. BUG=b:185308246 TEST=tested on voema Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Idd90191ee7ecbbc544121dc0b93101bea64f0e5f Reviewed-on: https://review.coreboot.org/c/coreboot/+/54275 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-14mb/google/volteer/variants/elemi: Include SPD for MT40A512M16TB-062E:RWisley Chen
Add SPD support to elemi for MT40A512M16TB-062E:R BUG=b:190020997 TEST=FW_NAME=elemi emerge-volteer coreboot chromeos-bootimage Change-Id: I548ea2ec01dd0a43442a691cf870c2bc1b58bc74 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55165 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-06-14util: Add DDR4 generic SPD for MT40A512M16TB-062E:RWisley Chen
Add SPD support for DDR4 memory part BUG=b:190020997 TEST=none Change-Id: I423131cb674e1e5ec699c7a28e5b5e6746247b2a Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55164 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-14mb/google/volteer/var/trondo: Update gpio settingsDavid Wu
This is the same settings as voxel. BUG=None TEST=FW_NAME=trondo emerge-volteer coreboot chromeos-bootimage Verify that the image-trondo.bin is generated successfully. Change-Id: I04df68ce1683fa32195df1a93f5bde2e3efe6090 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54274 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-06-14mb/google/brya: Create gimble variantMark Hsieh
Create the gimble variant of the brya0 reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:190334274 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_GIMBLE Change-Id: If425571d95b3b20910f890428fb5726ebad2fdf4 Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55300 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-143rdparty/intel-sec-tools: Fix submodule pointerAngel Pons
The commit currently being pointed to is unreachable. Use the same commit that exists in a reachable branch. Fixes: Commit 1128817ed644e86daa3972e68eb08761fd6b0da9 (3rdparty/intel-sec-tools: Update to support Boot Guard) Signed-off-by: Angel Pons <th3fanbus@gmail.com> Change-Id: I1cfc08d48fe5471592fea1013e8b43bea5d7b565 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55414 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-14mb/apple/macbookair4_2: Drop unnecessary selectAngel Pons
`GFX_GMA_PANEL_1_ON_EDP` already defaults to `y` on Sandy Bridge. Change-Id: I481754dc4f086469216c6e939c77b3c84bebea08 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55391 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Evgeny Zinoviev <me@ch1p.io> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-14lib/hardwaremain: Print individual boot state callback durationsRaul E Rangel
This is useful when trying to find which callbacks are taking the longest time. BUG=b:179092979 TEST=See bootstate durations in logs BS: callback (0xcb79d4d8) @ src/security/vboot/bootmode.c:53 (0 ms). BS: callback (0xcb79cf20) @ src/vendorcode/google/chromeos/ramoops.c:30 (0 ms). BS: callback (0xcb79cef0) @ src/vendorcode/google/chromeos/cr50_enable_update.c:160 (18 ms). Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ifb145fea32ad4e0b694bdb7cdcdd43dce4cc0d27 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55374 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-14lib/hardwaremain.c: Hide preprocessor guards in headerAngel Pons
The `location` member of `struct boot_state_callback` is conditionally guarded depending on `CONFIG(DEBUG_BOOT_STATE)` using preprocessor. It is probably intended to save some space when the `location` strings do not get printed. However, directly using the `location` member without any guards will cause a compile-time error. Plus, preprocessor-guarded code gets nasty really quickly. In order to minimise preprocessor usage, introduce the `bscb_location` inline helper function, which transforms the compile-time error into a link-time error. It is then possible to substitute preprocessor guards with an ordinary C `if` statement. Change-Id: I40b7f29f96ea96a5977b55760f0fcebf3a0df733 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55386 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-06-14mb/google/hatch: Create scout variantJeff Chase
Create the scout variant of the puff reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:187080143 BRANCH=None TEST=util/abuild/abuild -p none -t google/hatch -x -a make sure the build includes GOOGLE_SCOUT Signed-off-by: Jeff Chase <jnchase@google.com> Change-Id: I3be9d2d30821c2c9132ed94c9faf1f33b62bbc7e Reviewed-on: https://review.coreboot.org/c/coreboot/+/55173 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2021-06-14mb/google/guybrush: Update memory configurationIvy Jian
Regenerate SPD for MT53E1G32D2NP-046 WT:B with correct value of ranks. BUG=b:190692797 TEST=Build and boot to OS Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Change-Id: Icee095c7114f1d6dd960f2134db3816b367bf987 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55384 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-06-14mb/*/mptable.c: Use smp_write_pci_intsrc()Kyösti Mälkki
Split parameter '(devfn << 2) | intx' to 'devfn, intx'. Formatted with 'spatch --max-width 96' Change-Id: I17a6b3919b6e55aaa7ca2873ca713b36ebe7d3a6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55285 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-14mb/*/mptable.c: Replace magic constantsKyösti Mälkki
Read I/O APIC ID and version from hardware registers. With coccinelle below, and minor fixups. @ r1 @ expression E1, E2, E3, E4; typedef u8; @@ -smp_write_ioapic(E1, E2, E3, E4); +u8 ioapic_id = smp_write_ioapic_from_hw(E1, E4); @ r2 @ expression E1, E2, E3, E4; @@ -mptable_add_isa_interrupts(E1, E2, E3, E4) +mptable_add_isa_interrupts(E1, E2, ioapic_id, E4) @ r3 @ expression E1, E2, E3, E4, E5, E6, E7; @@ -smp_write_pci_intsrc(E1, E2, E3, E4, E5, E6, E7) +smp_write_pci_intsrc(E1, E2, E3, E4, E5, ioapic_id, E7) @ r4 @ symbol mp_INT; expression E1, E3, E4, E5, E6, E7; @@ -smp_write_intsrc(E1, mp_INT, E3, E4, E5, E6, E7) +smp_write_intsrc(E1, mp_INT, E3, E4, E5, ioapic_id, E7) Change-Id: I20799f0c09cf0292661e1f3cb93373b2c68b7314 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55284 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-06-14security/vboot: Add timestamps when loading verstageRaul E Rangel
We are not currently tracking how long it takes to load verstage. The enum values already exist, they just weren't used. BUG=b:179092979 TEST=Dump timestamps 501:starting to load verstage 2,280,656 (1) 502:finished loading verstage 2,340,845 (60,189) Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I2cde58cb8aa796829a4e054e6925e2394973484b Reviewed-on: https://review.coreboot.org/c/coreboot/+/55370 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-13soc/amd/cezanne: Supply SMBIOS/DMI Type 17 dataNikolai Vyssotski
Enable generation of DMI Type 17 data on Cezanne. BUG=b:184124605 TEST="dmidecode --type 17" in OS on Majolica Change-Id: Iaa89ee1ce6efa0280f17a443e07571a1190873a6 Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52230 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-06-13soc/amd/picasso: Move Type 17 DMI generation to commonNikolai Vyssotski
Move dmi.c code to common/fsp to be shared among different SOCs. BUG=b:184124605 Change-Id: I46071556bbbbf6435d9e3724bba19e102bd02535 Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52746 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-06-13soc/amd/cezanne: call boot_with_psp_timestampKangheui Won
if VBOOT_STARTS_BEFORE_BOOTBLOCK is set, call boot_with_psp_timestamp to migrate PSP timestamps into x86 timestamp table. Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: I4d51802145263145d40908889de29147af54f50f Reviewed-on: https://review.coreboot.org/c/coreboot/+/55405 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-06-13mb/google/cherry: get SKU ID from EC (CBI)Rex-BC Chen
The SKU ID for Cherry is retrieved via CBI interface. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Icefa016c2e5f68bd194f76d2252856835c65b8e8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55383 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2021-06-12util/intelp2m/fsp: Fix wrong register decoding for direction and interruptBenjamin Doron
Using the wrong registers to build the fields led to incorrect GPIO direction and interrupt trigger values. Change the calls to fix the tables. Change-Id: Icbeeb1fec6a863d0f86659c21924e15ae6765d47 Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54973 Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-12arch/x86/mptable: Add smp_write_ioapic_from_hw()Kyösti Mälkki
Add variant that reads I/O APIC ID and version from hardware registers. Change-Id: I01bec5f40c6ea60446a28767c7a1725dc25d0ae3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55283 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-06-12arch/x86/ioapic: Add get_ioapic_id() and get_ioapic_version()Kyösti Mälkki
Change-Id: I4ad080653c9af94a4dc73d93ddc4c8c117a682b9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55282 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-12mainboard/google/brya: Enable software syncBoris Mittelberg
This change removes the GBB flag that disables SW sync BUG:184229267 TEST:manually running chromeos-firmwareupdate Signed-off-by: Boris Mittelberg <bmbm@google.com> Change-Id: Ie8b759a0cdb0c3a0a6458f64c16216459f076e27 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55400 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-12mb/google/volteer/var/volet: remove USB4_GEN3 configuration for volet.Sheng-Liang Pan
volet don't support usb4, remove it to prevent USBC(P0) issue. BUG=b:189740531 TEST=build and verify USB(P0) disaply out normal Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: Ia78c7cee76ec2e3a5334ad8805a0d45616aade93 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55344 Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-11soc/amd/cezanne: remove warm reset flag codeFelix Held
The warm reset bit in the NCP_ERR register doesn't behave as the PPR [1] suggested; no matter if something was written to the register, the NCP_WARM_BOOT bit never got set and the NCP_ERR register in I/O-space always reads back as 0x7f. [1] checked with PPR for AMD Family 19h Model 51h A1 (CZN) #56569 Rev 3.01 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I569372db9f36ec7bbc741f4d7312ade312daa70b Reviewed-on: https://review.coreboot.org/c/coreboot/+/55101 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-11docs/flashmap: state the endianness of FMAPKrystian Hebel
Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com> Change-Id: Idf6d46ed262b18c176d69352e333c56f4fdff66a Reviewed-on: https://review.coreboot.org/c/coreboot/+/55041 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-06-11commonlib/lz4_wrapper.c: do not use bitfieldsKrystian Hebel
Order of bits in bitfields is implementation-defined. This makes them non-portable, especially across systems using different endianness. This change removes bitfields and uses masking and shifting instead. Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com> Change-Id: Ief7d87ddb25c9baa931f27dbd54a4ca730b6ece7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55040 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-06-11drivers/intel/gma: Restructure IGD opregion init codeMAULIK V VAGHELA
Restructuring opregion VBT related code to make it more generalize for future revision of opregion spec. Moved logic to locate VBT from different region (CBMEM, PCI option ROM or VBIOS) into separate function. Created a new function to check if extended VBT region is required. This will be helpful in the subsequent changes to determine if extended VBT region is needed and handle memory allocation accordingly. BUG=None BRANCH=None TEST=check the address of extended VBT region and address is coming correctly. Change-Id: I479d57cd326567192a3cd1969f8125ffe1934399 Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55318 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-06-11soc/amd/stoneyridge: Set missing RTC offsets for day alarm and centuryAnand K Mistry
On Linux, in order to set wake alarms >24 hours, the RTC Date Alarm field must be set to a valid non-zero value. If not, there are two consequences: 1. Alarms >24 hours don't work 2. The kernel will refuse to enter suspend because it can't resume as expected to service the alarm. Since the RTC Date Alarm and RTC AltCentury fields are supported on Stoneyridge, set them. This is a mirror of commit 041fcf5902 ("soc/amd/picasso/acpi: Set missing RTC offsets") for picasso. BUG=b:187516317 TEST=On a Chrome OS 'grunt' device, run `time powerd_dbus_suspend --suspend_for_sec=172800` and verify the system suspended and woke up after 48 hours BRANCH=grunt Signed-off-by: Anand K Mistry <amistry@google.com> Change-Id: I10831b982662e680fa71aa81d02935e1b7e7a7a1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55001 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-06-11mb/google/guybrush: Add EC_HOST_EVENT_HANG_DETECT to wake maskRob Barnes
Add EC_HOST_EVENT_HANG_DETECT to S3/S5/S0ix wake mask. This event is sent when the EC detects the AP didn't fully enter a sleep state. BUG=b:186571086 TEST=Trigger hang detect while AP is in S0ix, AP wakes from S0ix Change-Id: I09ccf609fc453c19b4fb1ddaa5a0c86d7a85aad1 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55365 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-06-11sc7280: Add target specific GPIO pin definitionsTaniya Das
Add GPIO pin details specific to SC7280 chipset for the consumers to be able to request for the gpio functionality as per their requirement. BUG=b:182963902 TEST=Validated on qualcomm sc7280 development board Signed-off-by: Taniya Das <tdas@codeaurora.org> Change-Id: I63bcaed78a6eeb0e6fad857b89d40181613e50cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/55077 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-06-11drivers/spi: Add winbond chip detailsShaik Sajida Bhanu
Added winbond W25Q512NW chip details. Change-Id: I5545c9431891f7fa74c1527591fb7c3cd3aba687 Signed-off-by: Shaik Sajida Bhanu <sbhanu@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55375 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-06-11mb/google/brya: Update PMC Descriptor for Alder lake A0(0x906a0) siliconSridhar Siricilla
The patch updates PMC Descriptor which is part of Descriptor Region if system equipped with Alder lake A0 silicon. This change allows to use unified Descriptor Region for Alder lake A0(CPU ID:0x906a0) and B0 (CPUD ID:0x906a1) silicons. BUG=B:187431859 TEST=Verified PMC Descriptor getting modified for Alder lake B0 silicon if not updated. coreboot logs appear as below with this patch: On First boot after flashing the image: coreboot-coreboot-unknown.9999.4589c0f Wed Jun 9 18:23:43 UTC 2021 bootblock starting (log level: 8)... CPU: Genuine Intel(R) 0000 CPU: ID 906a0, Alderlake Platform, ucode: 0000001a .. FMAP: Found "FLASH" version 1.1 at 0x1804000. FMAP: base = 0x0 size = 0x2000000 #areas = 32 FMAP: area SI_DESC found @ 0 (4096 bytes) SF: Detected 00 0000 with sector size 0x1000, total 0x2000000 Erasing flash addr 0 + 4 KiB Update of PMC Descriptor successful, trigger GLOBAL RESET Next boot after GLOBAL RESET: coreboot-coreboot-unknown.9999.4589c0f Wed Jun 9 18:23:43 UTC 2021 bootblock starting (log level: 8)... .. FMAP: area SI_DESC found @ 0 (4096 bytes) SF: Detected 00 0000 with sector size 0x1000, total 0x2000000 Update of PMC Descriptor is not required! VBOOT: Loading verstage. .. CBFS: Found 'fallback/verstage' @0x2264c0 size 0x16b08 in mcache @0xfef84d38 Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I6d9a2ce0f0b3e386eefa1962ce706b58f31a8576 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55254 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-06-11soc/intel/{common,alderlake}: Use generic name "Alderlake Platform"Sridhar Siricilla
Since common CPU ID between ADL-P and ADL-M CPU IDs, the patch renames all ADL-P and ADL-M Silicon CPUID macros and defines generic name "Alderlake Platform" as macro value. Also, this will avoid log ADL-M for ADL-P CPU and vice-versa. Although currently name field of "cpu_table" points to only "Alderlake Platform, but it is retained asa placeholder in future difference platforms. Please refer EDS doc# 619501 for more details. The macros are renamed as below: CPUID_ALDERLAKE_P_A0 -> CPUID_ALDERLAKE_A0 CPUID_ALDERLAKE_M_A0 -> CPUID_ALDERLAKE_A1 CPUID_ALDERLAKE_P_B0 -> CPUID_ALDERLAKE_A2 TEST=Verify boot on Brya. After change, relevent coreboot logs appear as below: CPU: ID 906a1, Alderlake Platform, ucode: 00000119 CPU: AES supported, TXT supported, VT supported MCH: device id 4601 (rev 03) is Alderlake-P PCH: device id 5181 (rev 00) is Alderlake-P SKU IGD: device id 46b0 (rev 04) is Alderlake P GT2 Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: Ia06d2b62d4194edd4e104d49b340ac23305a4c15 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55252 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-11soc/intel/elkhartlake: Update FSP-S FuSa related settingsLean Sheng Tan
Further add initial Silicon UPD settings for FuSa (Functional Safety). Disable all by default, due to FSP binary enable all by default. Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: I88264ba3e3f9f54ad949c55b230082d1fa289fa4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55342 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-11cpu/x86/lapic: Replace LOCAL_APIC_ADDR referencesKyösti Mälkki
Note that there are assumptions about LAPIC MMIO location in both AMD and Intel sources in coreboot proper. Change-Id: I2c668f5f9b93d170351c00d77d003c230900e0b4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55194 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-11soc/intel/elkhartlake: Update FSP-S PM & Thermal related configsLean Sheng Tan
Further add initial Silicon UPD settings for thermal and power management stuffs. Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: I04ded059c36f18925b7a74c934fef2566c3db8fa Reviewed-on: https://review.coreboot.org/c/coreboot/+/55335 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2021-06-10security/vboot: Add support for ZTE spacesAseda Aboagye
This commit adds support for the Chrome OS Zero-Touch Enrollment related spaces. For TPM 2.0 devices which don't use Cr50, coreboot will define the RMA+SN Bits, Board ID, and RMA Bytes counter spaces. The RMA+SN Bits space is 16 bytes initialized to all 0xFFs. The Board ID space is 12 bytes initialized to all 0xFFs. The RMA Bytes counter space is 8 bytes intialized to 0. BUG=b:184676425 BRANCH=None TEST=Build and flash lalala, verify that the ZTE spaces are created successfully by undefining the firmware antirollback space in the TPM such that the TPM undergoes factory initialization in coreboot. Reboot the DUT. Boot to CrOS and run `tpm_manager_client list_spaces` and verify that the ZTE spaces are listed. Run `tpm_manager_client read_space` with the various indices and verify that the sizes and initial values of the spaces are correct. TEST=Attempt to undefine the ZTE spaces and verify that it fails due to the unsatisfiable policy. Signed-off-by: Aseda Aboagye <aaboagye@google.com> Change-Id: I97e3ae7e18fc9ee9a02afadbbafeb226b41af0eb Reviewed-on: https://review.coreboot.org/c/coreboot/+/55242 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-10security/tpm/tss/tcg-2.0: Add `tlcl_set_bits()`Aseda Aboagye
This commit adds support for the TPM2_NV_SetBits command to the TLCL. This command is used to set bits in an NV index that was created as a bit field. Any number of bits from 0 to 64 may be set. The contents of bits are ORed with the current contents of the NV index. The following is an excerpt from lalala undergoing TPM factory initialization which exercises this function in a child commit: ``` antirollback_read_space_firmware():566: TPM: Not initialized yet. factory_initialize_tpm():530: TPM: factory initialization tlcl_self_test_full: response is 0 tlcl_force_clear: response is 0 tlcl_define_space: response is 14c define_space():197: define_space: kernel space already exists tlcl_write: response is 0 tlcl_define_space: response is 14c define_space():197: define_space: RO MRC Hash space already exists tlcl_write: response is 0 tlcl_define_space: response is 14c define_space():197: define_space: FWMP space already exists tlcl_write: response is 0 tlcl_define_space: response is 0 tlcl_write: response is 0 tlcl_define_space: response is 0 tlcl_write: response is 0 tlcl_define_space: response is 0 tlcl_set_bits: response is 0 tlcl_define_space: response is 0 tlcl_write: response is 0 factory_initialize_tpm():553: TPM: factory initialization successful ``` BUG=b:184676425 BRANCH=None TEST=With other changes, create a NVMEM space in a TPM 2.0 TPM with the bits attribute. Issue the command and verify that the TPM command succeeds. Signed-off-by: Aseda Aboagye <aaboagye@google.com> Change-Id: I6ca6376bb9f7ed8fd1167c2c80f1e8d3c3f46653 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55241 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Bob Moragues <moragues@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-10mb/google/guybrush: Move variant_has_fpmcu() after eSPI initMartin Roth
Currently variant_has_fpmcu() is called very early in bootblock, before eSPI is initialized. When checking CBI for its presence, that causes an error and nothing else can be read from CBI in bootblock. Moving it slightly later in bootblock doesn't hurt anything from a timing standpoint, and allows CBI to be read. BUG=None TEST=See CBI get read and the FPMCU field read correctly. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I6de44119e92c8820b266f9f07287706c7d4eb505 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54740 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-06-10vboot: Assign 2 to EC_EFS_BOOT_MODE_TRUSTED_RODaisuke Nojiri
This patch assings 2 to EC_EFS_BOOT_MODE_TRUSTED_RO to make coreboot set VB2_CONTEXT_EC_TRUSTED when the GSC reports TRUSTED_RO. Old GSC doesn't use 2. So, the new BIOS won't mistakenly set VB2_CONTEXT_EC_TRUSTED. BUG=b:180927027, b:187871195 BRANCH=none TEST=build Change-Id: I11a09d0035a4bd59f80018c647ca17e3318be81e Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55373 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-10cpu/x86/lapic: Drop read/write_around aliasesKyösti Mälkki
Change-Id: Ia3935524e57885ca79586f1f4612020bb05956ab Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55195 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-06-10drivers/intel/fsp2_0: Add timestamps for loading FSPM & FSPSMartin Roth
The loads of the FSPM and FSPS binaries are not insignificant amounts of time, and without these timestamps, it's not clear what's going on in those time blocks. For FSPM, the timestamps can run together to make it look like that time is still part of the romstage init time. Example: 6:end of verified boot 387,390 (5,402) 13:starting to load romstage 401,931 (14,541) 14:finished loading romstage 420,560 (18,629) 970:loading FSP-M 450,698 (30,138) 15:starting LZMA decompress (ignore for x86) 464,173 (13,475) 16:finished LZMA decompress (ignore for x86) 517,860 (53,687) ... 9:finished loading ramstage 737,191 (18,377) 10:start of ramstage 757,584 (20,393) 30:device enumeration 790,382 (32,798) 971:loading FSP-S 840,186 (49,804) 15:starting LZMA decompress (ignore for x86) 853,834 (13,648) 16:finished LZMA decompress (ignore for x86) 888,830 (34,996) BUG=b:188981986 TEST=Build & Boot guybrush, look at timestamps. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I5796d4cdd512799c2eafee45a8ef561de5258b91 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52867 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-06-10tests/console: Add tests for log message routing behaviorPatrick Georgi
Change-Id: Id978cfe4fa45fef9edbc3d3b55606ff6973521c5 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55356 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
2021-06-10tests: Rework mocking facilityPatrick Georgi
Using the linker's --wrap feature has the downside that it only covers references across object files: If foo.c defines a() and b(), with b calling a, --wrap=a does nothing to that call. Instead, use objcopy to mark a weak and global so it can be overridden by another implementation, but only for files originating in src/. That way mocks - implemented in tests/ - become the source of truth. TEST=Had such an issue with get_log_level() in a follow-up commit, and the mock now takes over. Also, all existing unit tests still pass. Change-Id: I99c6d6e44ecfc73366bf464d9c51c7da3f8db388 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55360 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
2021-06-10cpu/x86/lapic: Separate stop_this_cpu()Kyösti Mälkki
Function is needed with PARALLEL_MP and excluding guard will be added to the source file. The incompatibilities with X2APIC_SUPPORT have been fixed so the exclusion is removed here too. Change-Id: I5696da4dfe98579a3b37a027966b6758f22574aa Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55193 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-10cpu/x86/lapic: Add wait_ipi_completion() helpersKyösti Mälkki
Change-Id: Ib9c404cb55b96dcc5639287c214c5c8f468c0529 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55192 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-10cpu/x86/lapic: Add lapic_busy() helperArthur Heymans
Change-Id: Ife127d6dc8241cccb9d52236a9152da707f0e261 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55191 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-10cpu/x86/lapic: Add lapic_send_ipi() helperArthur Heymans
Change-Id: I7207a9aadd987b4307ce8b3dd8dbfd47d0a5768e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55190 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-10cpu/x86/lapic: Do not inline some utility functionsKyösti Mälkki
They are not __always_inline and specially enable_lapic() will become more complex to support X2APIC state changes. Change-Id: Ic180fa8b36e419aba07e1754d4bf48c9dfddb2f3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55258 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-10cpu/x86/lapic: Add lapic_update32() helperKyösti Mälkki
Change-Id: I57c5d85d3098f9d59f26f427fe16829e4e769194 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55187 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-10cpu/x86/lapic: Regroup LAPIC accessorsKyösti Mälkki
Change-Id: I4347fc6542f59f56bd8400181efa30247794cf96 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55186 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-10soc/intel/elkhartlake: Fix gpio_soc_defs.h variable typoLean Sheng Tan
Fix GPIO_COM2_END from GPIO_RSVD_2 to GPIO_RSVD_12. Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: I670f4bec8f141da73428010371754746a455df25 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55334 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-10soc/intel/elkhartlake: Use FSP from FSP repo by defaultLean Sheng Tan
Select 'HAVE_INTEL_FSP_REPO' so that the FSP binary from the FSP repository is used by default. Also, use the FSP headers from the FSP repository instead. Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: I0c1bcb07ed0f73e1d5ada5f6f16b84816c4ef3d7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55229 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-10soc/mediatek/mt8195: Add base addresses for displayJitao Shi
Add disp_dsc/disp_merge/dp_intf/edptx base addresses. BUG=b:189985956 Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> Signed-off-by: Jason-JH.Lin <jason-jh.lin@mediatek.com> Change-Id: I694da1449154e5b167c10d6d43d25ee2c5c0ec36 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55332 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-10soc/mediatek/mt8195: add power and power control for eDPJitao Shi
1. Add API of TVD_PLL1 mt_pll_set_tvd_pll1_freq() for setting rate. 2. Add API of TVD_PLL1 edp_mux_set_sel() for mux sel. 3. Add eDP power domain control. BUG=b:189985956 Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> Change-Id: I9e43e0ffeb7b8bcd1786a8d2f5acbf22d5ab501f Reviewed-on: https://review.coreboot.org/c/coreboot/+/55346 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-10include/limits.h: Add file (read: borrow from Linux)Angel Pons
Copied from Linux file `include/vdso/limits.h` with some adjustments. Change-Id: I427d88b1d630fdc3c3e9c1b0e475adbf448d801a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55319 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-10device/pnp: Always provide `pnp_unset_and_set_config`Angel Pons
The `pnp_unset_and_set_config` function was only available when building with `ENV_PNP_SIMPLE_DEVICE` set. Add the complementary definition using device pointers, for the sake of completeness. Change-Id: I2a21e635f41f3f786057500fa96a2b3116e30d76 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55255 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Máté Kukri <kukri.mate@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-06-10nb/haswell/gma: Add Desktop GT1.5 (HD 4400) Device IDMate Kukri
Change-Id: Idc7c38206b1ddfe486298cd3921fcb762a89ec51 Signed-off-by: Mate Kukri <kukri.mate@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55243 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-10soc/intel/tigerlake: Move MAX_CPUS to KconfigAndy Pont
Most of the Kconfig files for Intel SOC devices define the MAX_CPUS value within src/soc/intel/*/Kconfig. Move the definition there for Tiger Lake and remove from the mainboard Kconfig files. Signed-off-by: Andy Pont <andy.pont@sdcsystems.com> Change-Id: If145b9eb5d99821f4ce513118e4417d05f821ef5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55307 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-06-10vc/intel/fsp/fsp2_0/alderlake: Update MemInfoHob.h for new FSPEric Lai
Sync the MemInfoHob.h with current FSP code. BUG=b:190339677 TEST=dmidecode -t 17 can show the memory information. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ifd3e6a264131437c67d17ec80f37f5e8d0a03a79 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55302 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>