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2020-11-02pci_ids: Add PCI IDs for CNVi WiFi/BT controllersFurquan Shaikh
This change adds PCI IDs for CNVi WiFi/BT controllers for CML, GLK, ICL, JSL and TGL. Change-Id: Id45f65d0ef5a7782c08ddd70eb22b26072c8ef4b Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46863 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-11-02drivers/wifi/generic: Add support for CNVi dummy device opsFurquan Shaikh
This change reorganizes drivers/wifi/generic to add a new device_operations structure for dummy CNVi device. This is done to make the organization of CNVi PCI device in devicetree consistent with all the other internal PCI devices of the SoC i.e. without a chip around the PCI device. Thus, with this change, CNVi entry in devicetree can be changed from: ``` chip drivers/wifi/generic register "wake" = "xxyyzz" device pci xx.y on end # CNVi PCI device end ``` to: ``` device pci xx.y on chip drivers/wifi/generic register "wake" = "xxyyzz" device generic 0 on end # Dummy CNVi device end end # CNVi PCI device ``` The helper functions for ACPI/SMBIOS generation are also accordingly updated to include _pcie_ and _cnvi_ in the function name. Change-Id: Ib3cb9ed9b81ff8d6ac85a9aaf57b641caaa2f907 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46862 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-02drivers/wifi/generic: Split wifi_generic_fill_ssdt into two functionsFurquan Shaikh
This change splits `wifi_generic_fill_ssdt()` into following two functions: 1. `wifi_ssdt_write_device()`: This function writes the device, its address, _UID and _DDN. 2. `wifi_ssdt_write_properties()`: This function writes the properties for WiFi device like _PRW, regulatory domain and SAR. This split is done so that the device write can be skipped for CNVi devices in follow-up CLs. It will allow the SoC controller representation for CNVi PCI device to be consistent with other internal PCI devices in the device tree i.e. not requiring a chip driver for the PCI device. Because of this change, _PRW and SAR will be seen in a separate block in SSDT disassembly, but it does not result in any functional change. Observed difference: Before: Scope (\_SB.PCI0.PBR1) { Device (WF00) { Name (_UID, 0xAA6343DC) Name (_DDN, "WIFI Device") Name (_ADR, 0x0000000000000000) Name (_PRW, Package() { 0x08, 0x03 }) } } After: Device (\_SB.PCI0.PBR1.WF00) { Name (_UID, 0xAA6343DC) Name (_DDN, "WIFI Device") Name (_ADR, 0x0000000000000000) } Scope (\_SB.PCI0.PBR1.WF00) { Name (_PRW, Package() { 0x08, 0x03 }) } Change-Id: I8ab5e4684492ea3b1cf749e5b9e2008e7ec8fa28 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46861 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-11-02drivers/wifi/generic: Move ACPI functions to a separate fileFurquan Shaikh
This change reorganizes the WiFi generic driver to move the ACPI functions to a separate file. This change is done to reduce the noise in generic.c file and improve readability of the file. Change-Id: If5fafb5452fb5bad327be730fcfc43d8a5d3b8ec Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46860 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-11-02drivers/wifi/generic: Move SMBIOS functions to a separate fileFurquan Shaikh
This change reorganizes the WiFi generic driver to move the SMBIOS functions to a separate file. This change is done to reduce the noise in generic.c file and improve readability of the file. Change-Id: I38ed46f5ae1594945d2078b00e8315d9234f36d7 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-11-02drivers/wifi/generic: Use acpigen_write_ADR_pci_deviceFurquan Shaikh
This change uses the helper function `acpigen_write_ADR_pci_device()` to write _ADR object for the WiFi device. Change-Id: I3ba38f3ec4d8024209840e93bebf2d39bbef7685 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46858 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-11-02soc/amd/picasso: Put transfer buffer into common ld fileMartin Roth
Instead of having the same linker layout for the transfer buffer between the x86 & PSP linker layout scripts, put the common layout into a file shared between the other linker scripts. BUG=None TEST=Boot zork board, verify the buffers are aligned. BRANCH=Zork Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: Ib9d9d8b046bc9e9e7a4ee939324960bfc44c3508 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46900 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-11-02mb/google/volteer: Disable DPTF active policy for terrador and todorDavid Wu
Terrador and Todor are fanless design, so disable DPTF active policy. BUG=b:171019363,b:170699797 BRANCH=volteer TEST=build and verify by thermal team Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I53a33b8706d7a7d4013a2a5627a620223fcffc3e Reviewed-on: https://review.coreboot.org/c/coreboot/+/46874 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-02ec/hp/kbc1126: Support using a different GPEIru Cai
HP EliteBook Folio 9480m uses the HP KBC1126 EC ACPI interface, but with a different GPE, so add a Kconfig option to support using a different GPE. Change-Id: I3b78567e1387c96bf173e4370aa3c836bbddac0b Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45576 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-02vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3425Srinidhi N Kaushik
Update FSP headers for Tiger Lake platform generated based on FSP version 3425. Previous version was 3373. BUG=b:172045149 BRANCH=none TEST=build and boot delbin Cq-Depend:chrome-internal:3373431 Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: I58d165d452c8c6ae2eec92524109a568f7e581a9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47041 Reviewed-by: Dossym Nurmukhanov <dossym@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-31docs/librem_mini: update CPU, known issues sectionMatt DeVillier
Both 8565U and 8665U CPUs are used in the Librem Mini. SATA issue updated based on addition of HSIO PHY tuning params and resulting changes. Change-Id: I33a093ccfea077402e1b3651f9ca5d6d8a2818f8 Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46983 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-10-31.gitignore: Ignore .test/.dependencies globallyPatrick Georgi
These were originally ignored only inside util/ but these files shouldn't be tracked anywhere. Change-Id: Ie0846bd8bdd6e52f420f9dd2e72a8a922102ff90 Signed-off-by: Patrick Georgi <patrick@georgi.software> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47012 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-31Makefile: Remove possibly illegal characters from doxyplatformMartin Roth
The CONFIG_MAINBOARD_PART_NUMBER string can have characters in it that don't work in the doxyplatform make script under sh, so change any non-alphanumeric characters to an underscore. Also strip all the quotes - they aren't needed. The spaces in the "QEMU x86 i440fx/piix4" platform are one example of this. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I10bc6a8a245a34e89c859ff46835bde35aaa4286 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46287 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-10-31cpu/x86/lapic: rename virtual wire mode initialization functionFelix Held
Clarify what the function does by renaming it from do_lapic_init() to lapic_virtual_wire_mode_init(). Change-Id: Ie4430bf0f6c6bf0081b6aaeace351092bcf7f4ac Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47020 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-31{cpu,nb}/intel/haswell: Drop unnecessary `UL` suffixAngel Pons
Tested with BUILD_TIMELESS=1, Google Wolf does not change. Change-Id: I029ab0dccbf7b61d641cccf79b491fabf97ab74a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46720 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-31sb/intel/lynxpoint: Drop unnecessary `UL` suffixAngel Pons
With BUILD_TIMELESS=1, Asrock B85M Pro4 and Google Wolf do not change. Change-Id: I9ba4097cd82c4ff68315a40e1e955e4ed9a43862 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46719 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-31sb/intel/lynxpoint: Use common code to generate HPET tableAngel Pons
There's no need to reinvent the wheel. Change-Id: If6b90c9a7a00af0322c6dd15d2c4ecf2c513d0cc Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46977 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-31cpu/intel/common: correct MSR for the Nominal Performance in CPPCMichael Niewöhner
The "Nominal Performance" is not the same as the "Guaranteed Performance", but is defined as the performance a processor can deliver continously under ideal environmental conditions. According to edk2, this is the "Maximum Non-Turbo Ratio", which needs to be read from MSR_PLATFORM_INFO instead of IA32_HWP_CAPABILITIES. Correct the entry in the CPPC package. Test: dumped SSDT from Supermicro X11SSM-F and checked decompiled version Change-Id: Ic2c27fd3e14af18aa4101c0acd7a5ede15d1f3a9 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46464 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-30mb/google/volteer: Remove RIPTO support for cameraDaniel Kang
GPIO D4 was used for camera reset for both front and rear cameras (RCAM_RST_L/FCAM_RST_L) in RIPTO. For later volteer versions, GPIO F15 is dedicated to the rear camera reset (RCAM_RST_L). Before, BOARD_GOOGLE_VOLTEER flag was used for setting the right RCAM_RST_L per volteer version. However, we don't support RIPTO anymore. Also using flags for different volteer version support can be error-prone. Removing RIPTO support. BUG=b:171726823 BRANCH=none TEST=Build and boot volteer proto2 or later version. Camera should work without an issue. Signed-off-by: Daniel Kang <daniel.h.kang@intel.com> Change-Id: I961fc17092887b4807c12c95f7139bb7e7b33e91 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46826 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-30cpu/x86/sipi_vector.S: Use correct suffix for btsJacob Garber
The assembler is warning that the bts instruction is ambiguous, so use the correct suffix btsl. See also commit 693315160e (cpu/x86/sipi_vector.S: Use correct op suffix) Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Change-Id: I2eded0af1258e90926009544683b23961d99887b Reviewed-on: https://review.coreboot.org/c/coreboot/+/46928 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-30x86: Add a minimal example SoC along with a boardNico Huber
The min86 example SoC code along with the example mainboard should serve as a minimal example how a buildable x86 SoC code base can look like. This can serve, for instance, as a basis to add new SoCs to coreboot. Starting with a buildable commit should help with the review of the actual code, and also avoid any regressions when common coreboot code changes. As the example code itself is build-tested, it should advance with coreboot and can't rot like documentation might. It also serves as a check what APIs need to be implemented with the default Kconfig settings. Change-Id: Id76ab15fe77ae3e405c43f9c8677694f178be112 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45710 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-30mb/google/volteer: Separate power resource for VCMDaniel Kang
The camera privacy LED blinks during the boot and this gives a wrong impression to the users that the camera is being used during the power up. The blink happens when the camera module is probed and a series of kernel patches and coreboot patches are being submitted to resolve the issue. The kernel patches are submitted to the chromium gerrit. https://chromium-review.googlesource.com/2403386 https://chromium-review.googlesource.com/2403387 https://chromium-review.googlesource.com/2403385 https://chromium-review.googlesource.com/2403384 https://chromium-review.googlesource.com/2403383 https://chromium-review.googlesource.com/2403382 https://chromium-review.googlesource.com/2403381 https://chromium-review.googlesource.com/2403380 This is to separate the power resource for the VCM so that it can be controlled by the driver and suppress the LED turn on. BUG=b:169049942 BRANCH=none TEST=Build and boot volteer board. Monitor camera privacy LED and check if it blinks. It should not blink. Signed-off-by: Daniel Kang <daniel.h.kang@intel.com> Change-Id: Id51c98e42c5f20e231d8096c9d2d98deebc7c968 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45159 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Tomasz Figa <tfiga@google.com>
2020-10-30mb/google/octopus/var/fleex: Disable XHCI LFPS power management by skuEric Lai
LTE module Fibocom L850-GL is lost after idle overnight, with this workaround, host will not initiate U3 wakeup at the same time with device, which will avoid the race condition. If this option is set in the devicetree, the bits[7:4] in XHCI MMIO BAR + offset 0x80A4 (PMCTRL_REG) will be updated from default 9 to 0. BUG=b:169645448 BRANCH=octopus TEST=build coreboot with DisableXhciLfpsPM being set to 1 and flash the image to the device. Run following command to check if bits[7:4] is set 0: >iotools mmio_read32 "XHCI MMIO BAR + 0x80A4" Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I3a04320b0e2441dce540a5afdc461f12de45c41b Reviewed-on: https://review.coreboot.org/c/coreboot/+/46868 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marco Chen <marcochen@google.com>
2020-10-30soc/intel/xeon_sp: Call common soc_get_num_cpus()Marc Jones
Use a common function to get the number of CPUs for each soc. This removes a #if for different function names in the common code. Change-Id: I3348d37fcae72247731e465ec2a65d9583a2f180 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46970 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2020-10-30soc/intel/xeon_xp: Combine cpx and skx acpi.cMarc Jones
Prepare for common ACPI. Combine cpx and skx acpi.c into a single file in xeon_sp. This is almost the last step in using common/block acpi. Change-Id: I5f40eb7909bb796907682c548219c7515f2ae4d1 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46600 Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-30soc/intel/xeon_sp/skx/acpi.c: Update with cpx changesMarc Jones
Prepare for common ACPI. This primarily makes the skx madt table generation match cpx. There are a few other small changes to remove unused code and make the files match. Change-Id: I71a59181226d79c40a4af405653c50c970fb720b Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46599 Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-30cpu/x86: increase timeout for CPUs to check in after 2nd SIPIJonathan Zhang
Increase timeout for CPUs to check in after 2nd SIPI completion from 10ms to 100ms. Update logging level for mp init failure cases from BIOS_DEBUG to BIOS_ERR. Without this patch, "mp initialization failure" happens on some reboots on DeltaLake server. As consequence, not all 52 cpus come up in Linux: [root@localhost ~]# lscpu ... CPU(s): 40 Also following Hardware Errors are seen: [ 4.365762] mce: [Hardware Error]: Machine check events logged [ 4.366565] mce: [Hardware Error]: CPU 0: Machine Check: 0 Bank 9: ee2000000003110a [ 4.367561] mce: [Hardware Error]: TSC 0 ADDR fe9e0000 MISC 228aa040101086 [ 4.368563] mce: [Hardware Error]: PROCESSOR 0:5065b TIME 948438164 SOCKET 0 APIC 0 microcode 700001d With this patch, no such failure is observed with 370 reboots. Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: Iab10f116dd4af152c24d5d8f999928c038a5b208 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46898 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-30soc/intel/tigerlake: Enable TCSS XHCI device and define port aliasesDuncan Laurie
Enable the USB4 XHCI driver and remove the ACPI name entry from the SOC level function. Define aliases for the USB2/3 ports on north and south XHCI devices in chipset.cb so they can be referenced in the mainboard devicetree. BUG=b:151731851 TEST=define usb ports by reference in volteer devicetree and ensure they get properties added in SSDT for both north and south XHCI device. Signed-off-by: Duncan Laurie <dlaurie@google.com> Change-Id: I724ca874d3a3f6a2b43a700b0b10f77f25c53ee0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46852 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-30soc/intel/common/block/usb4: Add TCSS XHCI driver for SSDT generationDuncan Laurie
In order to generate ACPI entries for USB devices attached to the USB4/TBT/TCSS/North XHCI device it needs to have a driver that will enumerate static devices on the bus. This driver does that and nothing else. BUG=b:151731851 TEST=boot on volteer and check for USB devices on \_SB.PCI0.TXHC.RHUB Signed-off-by: Duncan Laurie <dlaurie@google.com> Change-Id: I5a2ff1cd1bed557e793d45119232cf87032ddd7b Reviewed-on: https://review.coreboot.org/c/coreboot/+/46851 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-30soc/intel/xeon_sp: Move read_msr_ppin() to common util.cMarc Jones
Move CPX and SKX read_msr_ppin() to common util.c file. Update drivers/ocp/smbios #include to match. Change-Id: I4c4281d2d5ce679f5444a502fa88df04de9f2cd8 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46479 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2020-10-30soc/intel/xeon_sp: Move common chip.c codeMarc Jones
Move common CPX and SKX chip.c code to chip_common.c. Change-Id: I158882ab15659858c2b13b4a3e02a26ef8d4ed3c Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46478 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2020-10-30soc/intel/xeon_sp/skx: Simplify pci_domain_read_resourceMarc Jones
Use a simpler pci_domain_read_resource for the stacks. This makes it the same as the cpx function, since both get the stack information from the FSP. This will be merged with common xeon cpx/skx in a later patch. Change-Id: I0130ce671fe9ff04e48021a0c5841551210aa827 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46308 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-30soc/intel/xeon_sp/skx: Add resource allocator helpersMarc Jones
Add and use resource allocator helper functions from cpx. It also simplifies the allocator by removing IORESOURCE_PCI64 from the resource type check. It isn't needed since it is an attribute of IO and MEM and will be added with the appropriate type. This clean up matches CPX and will help with merging in the future. Change-Id: I5812b07ba00eeafb4d1e826e9cdf9a659b0248bb Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46306 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-30lib/libpayload: Replace strapping_ids with new board configuration entryTim Wawrzynczak
There are currently 3 different strapping ID entries in the coreboot table, which adds overhead. The new fw_config field is also desired in the coreboot table, which is another kind of strapping id. Therefore, this patch deprecates the 3 current strapping ID entries (board ID, RAM code, and SKU ID), and adds a new entry ("board_config") which provides board ID, RAM code, SKU ID, as well as FW_CONFIG together. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I1ecec847ee77b72233587c1ad7f124e2027470bf Reviewed-on: https://review.coreboot.org/c/coreboot/+/46605 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-30fw_config: Make fw_config_get() publicTim Wawrzynczak
Further patches will make use of this raw 64-bit value. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I161893c09da6a44265299f6ae3c3a81249a96084 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46604 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-30fw_config: Convert fw_config to a 64-bit fieldTim Wawrzynczak
We all knew this was coming, 32 bits is never enough. Doing this early so that it doesn't affect too much code yet. Take care of every usage of fw_config throughout the codebase so the conversion is all done at once. BUG=b:169668368 TEST=Hacked up this code to OR 0x1_000_0000 with CBI-sourced FW_CONFIG and verify the console print contained that bit. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I6f2065d347eafa0ef7b346caeabdc3b626402092 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45939 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-30tigerlake mainboards: switch to devtree aliases for PMC MUX connectorsTim Wawrzynczak
Now that soc_get_pmc_mux_device() is gone, the PMC MUX connector devices can be hooked up together via devicetree aliases. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ib51764da5b3c029f9ac7ac60199a0aedfc7f29b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45878 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-30soc/intel/tigerlake: Replace soc_get_pmc_mux_device with device pointersTim Wawrzynczak
Now that device aliases can be used in the devicetree, the hacky function 'soc_get_pmc_mux_device' can be removed and replaced with pointers to the devices the function was supposed to return (1 for each port). Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ie00834c79bd5304998adaccb388ae74a108192b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45747 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-30cpu/intel/Makefile.inc: Use correct Kconfig symbolsAngel Pons
Guard CPU code using CPU Kconfig symbols instead of northbridge symbols. Change-Id: I0e5d7fc2e042381b96d2fbdfa34a3d4bf58201f9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46943 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-30mb/google/volteer/variants/volteer2: I2C5 trackpad bus freq 400 kHzJohnny Li
The current I2C5 bus frequency is 367 kHZ, which does not meet the spec. This change updates scl_lcnt, scl_hcnt, scl_hcnt value for I2C5 to bring the bus frequency closer to 400kHz. BUG=b:153588771 TEST=Verified that I2C5 frequency is between 389-396kHz. Signed-off-by: Johnny Li <johnny_li@wistron.corp-partner.google.com> Change-Id: If0803a74ba9071acf15486ce4038261c1681a92f Reviewed-on: https://review.coreboot.org/c/coreboot/+/46142 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-10-30{soc/amd,sb/amd/hudson}: Fix generating the ACPI mcfgArthur Heymans
The last argument for acpi_fill_mcfg() is the last PCI bus, which is an uint8_t, not the total number of busses, which overflows the argument if CONFIG_MMCONF_BUS_NUMBER is 256. Change-Id: I8887e14128dbe54688eb6e803d6694b7c29956c1 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35872 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2020-10-30vc/amd/fsp: Update bl_errorcodes_public.hMartin Roth
Replace the initial bl_errorcodes_public.h (a temporary, minimal version) with the full version released by AMD. BUG=None TEST=Build BRANCH=Zork Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I82585c74d74139a96419b9bffe1df3b8c344eb5f Reviewed-on: https://review.coreboot.org/c/coreboot/+/45943 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-30soc/amd/picasso: Fix the PSP SMI trigger infoMarshall Dawson
Align coreboot's PSP MboxBiosCmdSmmInfo setup to how AGESA's PSP library was implemented. The trigger address must be an SMI trigger register. Assign one of the reserved triggers to the PSP. The #define of SMITYPE_PSP 33 is still correct and is intentionally unmodified. This patch should be innocuous as the system doesn't currently support SMI-based features of the PSP. The call only exists so the PSP will honor a mailbox command during S3 suspend. BUG=b:171815390 TEST=Run SST on Morphius BRANCH=Zork Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I74029271a522a4f23e54fd76f99a8e3eb0dd4d55 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46854 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-30amdfwtool: Take a config file instead of command line parametersZheng Bao
To verify the consistency, see if timeless builds with and without this patch result in identical coreboot.rom files. BUG=b:154032833 TEST=Build & boot on mandolin Change-Id: Icae73d0730106aab687486e555ba947796e5e757 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-30cbfs: Hook up to new CBFS implementationJulius Werner
This patch hooks coreboot up to the new commonlib/bsd CBFS implementation. This is intended as the "minimum viable patch" that makes the new implementation useable with the smallest amount of changes -- that is why some of this may look a bit roundabout (returning the whole metadata for a file but then just using that to fill out the rdevs of the existing struct cbfsf). Future changes will migrate the higher level CBFS APIs one-by-one to use the new implementation directly (rather than translated into the results of the old one), at which point this will become more efficient. Change-Id: I4d112d1239475920de2d872dac179c245275038d Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38422 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-30commonlib/bsd: Add new CBFS core implementationJulius Werner
This patch adds a new CBFS implementation that is intended to replace the existing commonlib/cbfs.c. The new implementation is designed to meet a bunch of current and future goals that in aggregate make it easier to start from scratch than to adapt the exisiting implementation: 1. Be BSD-licensed so it can evetually be shared with libpayload. 2. Allow generating/verifying a metadata hash for future CBFS per-file verification (see [1][2]). 3. Be very careful about reading (not mmaping) all data only once, to be suitable for eventual TOCTOU-safe verification. 4. Make it possible to efficiently implement all current and future firmware use cases (both with and without verification). The main primitive is the cbfs_walk() function which will traverse a CBFS and call a callback for every file. cbfs_lookup() uses this to implement the most common use case of finding a file so that it can be read. A host application using this code (e.g. coreboot, libpayload, cbfstool) will need to provide a <cbfs_glue.h> header to provide the glue to access the respective CBFS storage backend implementation. This patch merely adds the code, the next patch will integrate it into coreboot. [1]: https://www.youtube.com/watch?v=Hs_EhewBgtM [2]: https://osfc.io/uploads/talk/paper/47/The_future_of_firmware_verification_in_coreboot.pdf (Note: In early discussions the metadata hash was called "master hash".) Change-Id: Ica64c1751fa37686814c0247460c399261d5814c Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38421 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-30util/docker: Add sdcc to our build nodesPatrick Georgi
core-ec will need it. Change-Id: Id7d677a6f92ce266f893372a2540d77abb613707 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46940 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2020-10-30.gitignore: Split into subdirectory filesPatrick Georgi
There's no need for the global list of files to ignore, so use git's ability to work with more local configuration. Change-Id: I50882e6756cbc0fdfd899353cc23962544690fb3 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46879 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-30drivers/soundwire/alc711: Add Realtek ALC711 soundwire deviceAnil Kumar
Bug=None Test=Enabled the device on TGLY RVP and tested that the codec is reflected in SSDT. Checked sound card binding works and soundwire drivers are enabled in kernel. Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Change-Id: Ia7358927fe8531e609ebe070bef259a2bbc09093 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46303 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-10-30soc/intel/broadwell: Drop reg-script to finalize PCHAngel Pons
Tested on out-of-tree Acer Aspire E5-573, still boots. Change-Id: I3b9ae75842e3ec1ecd02323d104a9f1d45564172 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46710 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-30soc/intel/broadwell: Relocate PCH finalisation codeAngel Pons
Change-Id: I94a4194e935fddb99645ed2929bdd70583c2fd5b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46709 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-30soc/intel/broadwell: Get rid of `cpu_is_ult`Angel Pons
It is only used in a single file, on two functions that already check whether coreboot is running on a Haswell or a Broadwell processor. Change-Id: I86e1061f722e6d6855190c2fd863d85fc24a1ee0 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46708 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-30soc/intel/broadwell: Inline CPUID helpersAngel Pons
These functions are small and used in various stages. Inline them. Change-Id: I0d15012f264dbb0ae2eff8210f79176b350b6e7f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46707 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-30soc/intel/broadwell: Move PCH code into pch subdirAngel Pons
Change-Id: Icb57eb89b4f225298e43ae27970dc1e27fb6e222 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46706 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-30soc/intel/broadwell: Separate PCH in devicetreeAngel Pons
Flesh out the PCH configuration into a separate chip. Keep it within the Broadwell SoC directory for now, to ease moving files around. The boards were prepared beforehand and the devicetrees require next to no changes. Tested on out-of-tree Acer Aspire E5-573, still boots. Change-Id: I28d948f3e6d85e669d12b29516d867c1d1ae9e1a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46700 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-30Revert "broadwell: update processor power limits configuration"Angel Pons
This reverts commit fa42d568a00e5daadd35722790c529539227130e. Reason for revert: Passes in an incompatible structure and only happens to boot by chance. Moreover, Broadwell will soon be merged with Haswell and this requires Broadwell to not depend on any Intel common SoC code. Tested on out-of-tree Acer Aspire E5-573, PL values are correct again. Change-Id: I6e8e000dba8ff09fab4e6f174ab703348dcd6a96 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45011 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-30soc/intel/broadwell/cpu.c: Re-add `configure_thermal_target`Angel Pons
Commit 360684b (soc/intel/common: add TCC activation functionality) made Broadwell use common SoC code. However, this makes Broadwell depend on SoC code, which prevents splitting Broadwell into CPU, northbridge and southbridge, a stepping stone before merging with Haswell and Lynxpoint. Tested on out-of-tree Acer E5-573, still boots. Change-Id: Ib7ab4e75bd4416dde4612e67405a871da569008a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46731 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-30mb/google/auron: Add SATA PCI device to overridetreeAngel Pons
`chip` entries are only hooked up via device nodes to the tree. A `chip` without a `device` below it does nothing. To allow variants to override SATA tuning parameters, ensure a device exists under the PCH chip scope. Without this change, some variants would not properly override the SATA tuning parameters after extracting the PCH parts into a different chip. TEST=Sanity-check static.c and verify overridetrees override properly. Change-Id: I013dbe1403567b93c8ee0e66f76481f2a3f42796 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46769 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-30mb/purism/librem_bdw: Prepare devicetree for PCH splitAngel Pons
Tested with BUILD_TIMELESS=1, all variants remain identical. Change-Id: I0fe6de35f7471ce173df40db1444153623544f00 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46705 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-30mb/intel/wtm2: Prepare devicetree for PCH splitAngel Pons
Tested with BUILD_TIMELESS=1, coreboot.rom remains identical. Change-Id: I75d6594f9576c96a585526c652a070cb9616dbe9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46704 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-30mb/google/jecht: Prepare devicetree for PCH splitAngel Pons
Tested with BUILD_TIMELESS=1, all variants remain identical. Change-Id: I0fa486b8a0fc8be974f37d0bb4eb77a254e8cd86 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46703 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-29mb/google/volteer: correct memory id for elemiWisley Chen
BUG=b:170604353 BRANCH=volteer TEST=emerge-volteer coreboot, and boot into kernel. Change-Id: If354aa158f3ad60193268f38278a44f9c99bf3db Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46770 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-29hatch: Create ambassador variantMatt Ziegelbaum
Create the ambassador variant of the puff reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.2.0). BUG=b:171561514 BRANCH=None TEST=util/abuild/abuild -p none -t google/hatch -x -a make sure the build includes GOOGLE_AMBASSADOR Signed-off-by: Matt Ziegelbaum <ziegs@chromium.org> Change-Id: Ib0e3a813a120a4a8e984f3a89dc3ba100d94da95 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46829 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-29soc/intel/xeon_sp: Move function debug macrosMarc Jones
Move the macros for printing debug information to debug.h in the common console include directory and device include file. These are available if the platform selects DEFAULT_CONSOLE_LOGLEVEL_8. The macros could be used by any platform. Change-Id: Ie237bdf8cdc42c76f38a0c820fdc92e81095f47c Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46093 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2020-10-29include/device/device.h: Move resource debug macrosMarc Jones
Add general debug macros that print resource information. These are available to select if DEFAULT_CONSOLE_LOGLEVEL_8. The macros are helpful in debugging complex resource allocation with multiple buses. The macros are moved from soc/intel/xeon_sp, where they were originally developed. Change-Id: I2bdab7770ca5ee5901f17a8af3a9a1001b6702e4 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46304 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2020-10-29mb/intel/adlrvp: Add dq_pins_interleaved into 'struct mb_cfg'Subrata Banik
List of changes: 1. Split mem_cfg for DDR4 and LPDDR4 as per board_id 2. Move dq_pins_interleaved into board-specific memory configuration information TEST=Able to build and boot DDR4 and LPDDR4 ADLRVP SKUs. Change-Id: I6ef19209767c810426bba0c8bc48178bf2e2a110 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46873 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-29soc/mediatek/mt8192: Do dram full calibrationHuayang Duan
If no correct params were found in flash, do dram full calibration. Full calibration will load blob, dram.elf. Blob version: v3, size: 320KB. Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Change-Id: I2d4437a4e4c770de084927018d4dd3f2e8b87fb1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44570 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-10-29mb/asus/f2a85-m_pro: Enable super-I/O LDNs 0x0f and 0x14Nico Huber
The LDNs don't have a 0x30 register to enable them. However, with the devices set to `off`, coreboot won't configure them. Change-Id: Iaea37c88524904a1dae8a6d3b5f07c6ea25bc3b2 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46021 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-29mb/asus/f2a85-m_pro: Clean up super-I/O GPIO settingsNico Huber
Drop useless writes to read-only registers and don't re-write default 0x00 values. In detail: * Don't write read-only status registers. * Don't try to write input bits in data registers (iow. mask data values: `data &= ~io`). * Don't write data registers if all GPIOs are set as inputs (`io == 0xff`). * Don't write default 0x00 for inversion and multiplex registers. Note: Both GPIO0 and WDT1 values look spurious. Maybe they were dumped with the virtual devices disabled? Change-Id: I7d948d6b697285e61e4352b7354b924dbf511e9a Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46020 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-29mb/asus/f2a85-m_pro: Comment and group super-I/O GPIO settingsNico Huber
Change-Id: I8f5a87d006f8bf20af40f7a4f09b1e4b597ba79f Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46019 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-29mb/asus/f2a85-m_pro: Enable GPIO0 on the super I/ONico Huber
It is enabled by the vendor firmware. Also drop spurious `io 0x60 = 0x00` setting. It's the default anyway and the resource is kept disabled (it's controlled by the virtual LDN 2e.008). This fixes the hang in `PCI: 00:14.3 init` when doing `outb(0, DMA1_RESET_REG)`. Fixes: 2f8192bc ("asus/f2a85m_pro: Fix superio type in devicetree") Change-Id: I351c93033bf2afd824eb6baa8d7625e7a33a295a Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46015 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-28payloads/filo: Set stable tag to something that buildsNico Huber
Also rename the prompt to "tested" to make it more obvious that there is no really stable version. Change-Id: Ib719fe5c30783a53ddad2a2dc2d9ecda37a05ac2 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46849 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2020-10-28soc/intel: deduplicate ACPI timer emulationMichael Niewöhner
The code for enabling ACPI timer emulation is the same for the SoCs SKL, CNL, ICL, TGL, JSL and EHL. Deduplicate it by moving it to common code. APL differs in not having the delay settings. However, the bits are marked as "spare" and BWG mentions there are no "reserved bit checks done". Thus, we can write them unconditionally without any effect. Note: The ACPI timer emulation can only be used by SoCs with microcode supporting CTC (Common Timer Copy) / ACPI timer emulation. Change-Id: Ied4b312b6d53e80e71c55f4d1ca78a8cb2799793 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45951 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-28mb/ocp/tiogapass/dsdt: Remove unnecessary commentsMaxim Polyakov
Change-Id: I6a16e2f829219f2eba8acd3ae7f371238c0d8de1 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45767 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2020-10-28ifdtool: add "reserved" regionsStefan Reinauer
This will let you at least dump / add these regions. Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Change-Id: I195ba5e93823603e712cd16cecbb48141302bed6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46822 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2020-10-28mb/google/zork: Revert temp acpi backlight fixJosie Nordrum
Remove code to turn on backlight during ACPI mode because backlight has been properly enabled in ACPI. BUG=b:158087989 BRANCH=Zork TEST=tested backlight during reboot and suspend Signed-off-by: Josie Nordrum <JosieNordrum@google.com> Change-Id: I3bf06042aa19e4559127d611d401f0ba0516b3a6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46823 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-28mb/google/zork: Generate acpi methods in mainboard.cJosie Nordrum
Generate acpi methods which enable and disable backlight during _INI, _WAK, and _PTS. BUG=b:158087989 BRANCH=Zork TEST=check backlight during reboot and suspend Signed-off-by: Josie Nordrum <JosieNordrum@google.com> Change-Id: I2f3434dc92de1f697693ff69ca15bd76647b89a2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46671 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-28soc/amd/picasso/acpi: Include platform.aslJosie Nordrum
Include platform.asl to link acpi methods for _INI, _WAK, and _PTS to correctly enable backlight in OS for zork. BUG=b:158087989 BRANCH=Zork TEST=check backlight during reboot and suspend Signed-off-by: Josie Nordrum <JosieNordrum@google.com> Change-Id: I702f807a5907d85d083295cf339ba9d31b246627 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46670 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-28soc/amd/common/acpi: Create platform.asl to define acpi transitionsJosie Nordrum
Define device _WAK, _PTS, and _INI acpi methods with callbacks into mainboard methods if provided. BUG=b:158087989 BRANCH=Zork TEST=tested backlight during reboot and suspend Signed-off-by: Josie Nordrum <josienordrum@google.com> Change-Id: I8020173a15db1d310459d5c1de3600949b173b00 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46669 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-28sec/intel/txt/Kconfig: Remove the menu for including ACMsArthur Heymans
This is consistent with how other binaries (e.g. FSP) are added via Kconfig. This also makes it more visible that things need to be configured. Change-Id: I399de6270cc4c0ab3b8c8a9543aec0d68d3cfc03 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46455 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-28sec/intel/txt/Makefile.inc: Include ACMs using Kconfig variablesArthur Heymans
The Kconfig variables are used in the C code for cbfs file names but not in the Makefiles adding them. Change-Id: Ie35508d54ae91292f06de9827f0fb543ad81734d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46454 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-28drivers/mrc_cache: Fix size comparison in mrc_cache updateTim Wawrzynczak
`mrc_cache_needs_update` is comparing the "new size" of the MRC data (minus metadata size) to the size including the metadata, which causes the driver to think the data has changed, and so it will rewrite the MRC cache on every boot. This patch removes the metadata size from the comparison. BUG=b:171513942 BRANCH=volteer TEST=1) Memory training data gets written the on a boot where the data was wiped out. 2) Memory training data does not get written back on every subsequent boot. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I7280276f71fdaa492c327b2b7ade8e53e7c59f51 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46824 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-28mb/google/nightfury: Set internal pull-down for GPP_D19Seunghwan Kim
Add internal pull-down for GPP_D19 to improve DMIC noise issue on nightfury. BUG=b:171669255 BRANCH=firmware-hatch-12672.B TEST=Built and checked GPP_D19 voltage after booting Change-Id: Ie63f260be3d6a55f91908db59312b3b0a8af98f4 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46816 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bob Moragues <moragues@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-10-28mb/ocp/tiogapass/acpi: Exclude uncore.asl from _SB scopeMaxim Polyakov
The corresponding devices and objects are already included in the System Bus ACPI scope inside uncore.asl. There is no need to do this again in the DSDT of the motherboard. Change-Id: I98a8d60b585e2eafd76948baea0f249a029bae09 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45766 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-28src/soc/intel/xeon_sp: Fill in the cache information in SMBIOS type 7Morgan Jang
TEST=Execute "dmidecode -t 7" to check if cache error correction type and cache sram type is correct for each cache level Change-Id: Ibe7c6ad03a83a6a3b2c7dfcfafaa619e690a418d Signed-off-by: Morgan Jang <Morgan_Jang@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46119 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-28soc/intel/xeon_sp/cpx: Set SLEEP_BUTTON flag in ACPI FADTMorgan Jang
Keep SLEEP_BUTTON flag in ACPI FADT to indicate that no sleep button is present on Cooperlake platform. Change-Id: I2ce435a7bda780b2d2ed00be3f3a8a080c4434ab Signed-off-by: Morgan Jang <Morgan_Jang@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46833 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-28mb/ocp/deltalake: Rename motherboard_fill_fadt()Jingle Hsu
Rename motherboard_fill_fadt() to the common override mainboard_fill_fadt() function to override FADT. Tested=On OCP Delta Lake, verify FADT PM Profile is set to Enterprise Server. Signed-off-by: Jingle Hsu <jingle_hsu@wiwynn.com> Change-Id: Ie9ea7cc6e712d0aca57bbeac1a4154921d123be4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46836 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-28mb/google/asurada: Pass reset gpio parameter to BL31CK Hu
To support gpio reset SoC, we need to pass the reset gpio parameter to BL31. Signed-off-by: CK Hu <ck.hu@mediatek.com> Change-Id: I2ae7684a61af76693605cc0bcf8d20c8992c7bff Reviewed-on: https://review.coreboot.org/c/coreboot/+/46388 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-28mb/google/asurada: Configure pinctrl for SD and MMCWenbin Mei
The pins for SD and MMC must be configured properly so we can access them in payloads. Signed-off-by: Wenbin Mei <wenbin.mei@mediatek.com> Change-Id: Ie6bdffb987d5acf286645550f1c53f294f71c38a Reviewed-on: https://review.coreboot.org/c/coreboot/+/46685 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-10-28security/vboot: fix policy digest for nvmem spacesAndrey Pronin
This CL fixes the policy digest that restricts deleting the nvmem spaces to specific PCR0 states. BRANCH=none BUG=b:140958855 TEST=verified that nvmem spaces created with this digest can be deleted in the intended states, and cannot be deleted in other states (test details for ChromeOS - in BUG comments). Change-Id: I3cb7d644fdebda71cec3ae36de1dc76387e61ea7 Signed-off-by: Andrey Pronin <apronin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46772 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-27mb/google/octopus/var/garg: Disable XHCI LFPS power management by skuKevin Chiu
LTE module Fibocom L850-GL is lost after idle overnight, with this workaround, host will not initiate U3 wakeup at the same time with device, which will avoid the race condition. If this option is set in the devicetree, the bits[7:4] in XHCI MMIO BAR + offset 0x80A4 (PMCTRL_REG) will be updated from default 9 to 0. BUG=b:171478764 BRANCH=octopus TEST=build coreboot with DisableXhciLfpsPM being set to 1 and flash the image to the device. Run following command to check if bits[7:4] is set 0: >iotools mmio_read32 "XHCI MMIO BAR + 0x80A4" Change-Id: I213fed2b56f216747b2727b69f97d46d8c0c872e Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46701 Reviewed-by: Marco Chen <marcochen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-27mb/google/octopus/var/garg: fix LTE power sequence in reboot stateKevin Chiu
invoke LTE power off function to meet LTE power sequence while DUT is in reboot state. BUG=b:167565015 BRANCH=octopus TEST=build and verify on the DUT with LTE Change-Id: I825cefb524ddaf9a9cb6add31c2ee0eea484f978 Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46022 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Marco Chen <marcochen@google.com> Reviewed-by: Henry Sun <henrysun@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-27device: Rephrase bus master Kconfig optionFelix Singer
Change-Id: I902915133035fb2adff7edd9c931d4b1d3e7dc40 Signed-off-by: Felix Singer <felix.singer@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46341 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-27util/testing: Allow what-jenkins-does to skip lint testingMartin Roth
The linters touch every file under src and probably util. This makes it difficult to see what files have been accessed by the builder. The JENKINS_SKIP_LINT_TESTS variable will only be set on the jenkins build that looks for unused files. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I12fa31641c2a72c5e07be1c4958467f7165f21bb Reviewed-on: https://review.coreboot.org/c/coreboot/+/46807 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-10-27util/testing: Update test-abuild output directoriesMartin Roth
This matches the what-jenkins-does target. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I20b455e0161dcebf2eb9022bd142bbec99937a19 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46806 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-10-27util/docker: Update atime mount point options for jenkinsMartin Roth
- The ccache files don't need atime. - Enable strict atime for the git repos. This will help find unused files. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I94bcc55ea5c5a74f3ad0292ca50b74874a0d920d Reviewed-on: https://review.coreboot.org/c/coreboot/+/46804 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-10-27util/docker: Update agent-root to node-root for jenkinsMartin Roth
Jenkins has changed the name of the build directory, so it's not currently building out of memory, it's writing to the SSD. This changes the build back to tmpfs. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Iefcf53757862feb2025aa5696f9f5dbce9dd70dd Reviewed-on: https://review.coreboot.org/c/coreboot/+/46803 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-10-27util/docker: Add tests to coreboot-sdk build processMartin Roth
This tests some of the basic targets that coreboot-sdk needs to be able to run. I was running most of these tests manually after creating the sdk image, but adding it into the Dockerfile makes sure they get run. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I0d4a2ad82042733a7966edb8ccf927676618977c Reviewed-on: https://review.coreboot.org/c/coreboot/+/46802 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-10-27util/docker: Update coreboot-sdk consolidate coreboot buildMartin Roth
Because docker saves a container for every run command, by breaking the coreboot build into 3 commands, it greatly increased the size of the docker containers needed. When combined as one run command, the coreboot repo that is downloaded, along with the coreboot test build are deleted before the container is created. Since those directories are deleted in a later run command, they don't even make it into the final container, and just force coreboot-sdk users to download extra data for no reason. While splitting the build may help with debugging failures when creating the docker container, that debugging can be done locally by splitting up a working copy. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Ia28ee4e22c0a76dc45343755c45678795308adca Reviewed-on: https://review.coreboot.org/c/coreboot/+/46801 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-10-27util/docker: Update coreboot-sdk to set python2 as defaultMartin Roth
Even though both python2 and python3 are now installed to the SDK, the default python program is not. This sets the default to python2. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I4220c316df86cb2481143a79fadb70fc734e6879 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46800 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>