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2013-02-19romcc: Don't fail on function prototypesPatrick Georgi
Instead, ignore them. One is as non-standard as the other and ignoring is more convenient since we don't need to guard prototypes with #ifndef __ROMCC_ all the time. Change-Id: I7be93a2ed0966ba1a86f0294132a204e6c8bf24f Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/2424 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com> Reviewed-by: Marc Jones <marcj303@gmail.com>
2013-02-19build system: Retire REQUIRES_BLOBPatrick Georgi
REQUIRES_BLOB assumes that all blob files come from the 3rdparty directory, builds failed when all files were configured to point to other sources. This change modifies the blob mechanism so that cbfs-files can be tagged as "required" with some specification what is missing. If the configured files can't be found (wrong path, missing file), the build system returns a list of descriptions, then aborts. Change-Id: Icc128e3afcee8acf49bff9409b93af7769db3517 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/2418 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marcj303@gmail.com>
2013-02-19AMD S3: Change S3_VOLATILE_POS to S3_DATA_POSZheng Bao
S3_DATA_POS defines address where the whole S3 data is stored. Change-Id: I4155a0821e74a3653caaead890e5fec5677637aa Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/2438 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-by: Marc Jones <marcj303@gmail.com>
2013-02-19RTC: Use the correct index when setting the default monthDave Frodin
Change-Id: I947a8b7ccd6141f164d1e63f7b8f524efa6c00f2 Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/2442 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-19armv7: init stack to 0xdeadbeef to detect stack overflowsDavid Hendricks
This adds a simple loop which initializes the stack to 0xdeadbeef which is used by checkstack(). Change-Id: I8aecf7bfb1067de68c4080c1fcb7eefa28fd04a7 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2421 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-02-18Persimmon: drop useless DDR3 voltage code copied from InaguaJens Rottmann
Inagua can use GPIOs 178,179 to switch VMEM to 1.5, 1.35 or 1.25 V, which it does according to data read from the SO-DIMM's SPD EEPROM. On Persimmon (according to DB-FT1 rev. D schematics) both GPIOs are unconnected, there is no way to change the 1.5 V DDR3 voltage (save unsoldering a resistor). The whole code copied over from Inagua is useless. Removed the code, instead a comment hints at Inagua, for people who do designs based on Persimmon but do have a way to change VMEM. The line ...->DDR3Voltage = VOLT1_5; is supposed to make the AGESA DDR3 code select the RAM timings for the actually supplied voltage instead of the hoped-for but unavailable lower voltage. I have no idea how to test this, but in any case it can't hurt. Change-Id: Id098e09418b665645814a6ee2d41a3bff72238ba Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de> Reviewed-on: http://review.coreboot.org/2448 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2013-02-18Persimmon: disable APU PCIe port 3Jens Rottmann
According to DB-FT1 rev. D schematics the APU PCIe lane 3 is unconnected. Reflect this fact in the mainboard code. Change-Id: Ic98f4a63ef971628df7fbf97f56b80ebe7cb8517 Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de> Reviewed-on: http://review.coreboot.org/2447 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2013-02-18Persimmon: adapt PCIe reset code copied from Inagua to actually match PersimmonJens Rottmann
Comparing Persimmon and Inagua schematics and Coreboot code show the PCIe reset code has been blindly copied even though it doesn't suit the Persimmon at all. The Inagua can employ GPIOs 21, 25, 02 to manually reset devices on APU PCIe lanes 0/1, 2, 3 respectively. (Appearently the motivation for this is to revive buggy PCIe gen1 devices which got confused by PCIe gen2 signal training.) However the Persimmon not only doesn't support this, it even needs these 3 pins for the PCI interface! Instead it uses GPIO50 to reset devices on lanes 0-2 all at once. Lane 3 is unconnected anyway. This patch adapts the Persimmon mainboard code according to the DB-FT1 rev. D schematics. Change-Id: I05a657d9bf8cc59acc4f5174eb20375165c860c7 Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de> Reviewed-on: http://review.coreboot.org/2446 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2013-02-18Kconfig: string option doesn't work properly inside choice sectionJens Rottmann
At least not in menuconfig. Move it after the endchoice. Change-Id: I87d2f70e7c1fbe539cd78cb602a39335b2886d8d Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de> Reviewed-on: http://review.coreboot.org/2443 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2013-02-18cbfstool: Fix compile warnings caused by incorrect data types.Hung-Te Lin
The "offset" in cbfs-mkpayload should be printed as type %lu instead of %d as `gcc` rightfully warns about. gcc -g -Wall -D_7ZIP_ST -c -o /srv/filme/src/coreboot/util/cbfstool/cbfs-mkpayload.o cbfs-mkpayload.c cbfs-mkpayload.c: In function ‘parse_fv_to_payload’: cbfs-mkpayload.c:284:3: warning: format ‘%d’ expects argument of type ‘int’, but argument 3 has type ‘long unsigned int’ [-Wformat] cbfs-mkpayload.c:296:3: warning: format ‘%d’ expects argument of type ‘int’, but argument 3 has type ‘long unsigned int’ [-Wformat] This warning was introduced in the following commit. commit 4610247ef1744ccabbcc6bfc441a3583aa49f7b5 Author: Patrick Georgi <patrick@georgi-clan.de> Date: Sat Feb 9 13:26:19 2013 +0100 cbfstool: Handle alignment in UEFI payloads Reviewed-on: http://review.coreboot.org/2334 Change-Id: I50c26a314723d45fcc6ff9ae2f08266cb7969a12 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/2440 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2013-02-18cbfstool: Add `-Werror` to make all warnings into errorsPaul Menzel
Ensure that no changes with warnings are committed. Although using `-Werror` is debatable [1][2]. [1] http://blog.flameeyes.eu/2009/02/future-proof-your-code-dont-use-werror [2] http://gcc.gnu.org/onlinedocs/gcc/Warning-Options.html Change-Id: I402f2d82dd4087d8a575b0a85305a02ef04bb537 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2441 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-02-18AMD S3: Program the flash in a bigger data packetZheng Bao
According to spi.c in src/southbridge/amd/agesa/hudson readwrite = (bytesin + readoffby1) << 4 | bytesout; We can see that Hudson limits the SPI programming data packet size as 15. We used to write data to SPI in dword mode. It didn't take full advantage of the data packet size. We need to leverage that to speed up programming time. Change-Id: I615e3c8e754e58702247bc26cfffbedaf5827ea8 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/2306 Tested-by: build bot (Jenkins) Reviewed-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-02-18AMD S3: Fix typo vol*a*tile in southbridge KconfigZheng Bao
Change non-volitile to non-volatile. Change-Id: Idfc7db3b3dcf078f0f3134fc62679bed439a4fd2 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/2437 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
2013-02-18AMD Family12h: Fix warningsMartin Roth
Add needed prototypes to .h files. Remove unused variables and fix types in printk statements. Add #IFNDEFs around #DEFINEs to keep them from being defined twice. Fix a whole bunch of casts. Fix undefined pre-increment behaviour in a couple of macros. These now match the macros in the F14 tree. Change a value of 0xFF that was getting truncated when being assigned to a 4-bit bitfield to a value of 0x0f. This was tested with the torpedo build. This fixes roughly 132 of the 561 warnings in the coreboot build so I'm not going to list them all. Here is a sample of the warnings fixed: In file included from src/cpu/amd/agesa/family12/model_12_init.c:35:0: src/include/cpu/amd/amdfam12.h:52:5: warning: redundant redeclaration of 'get_initial_apicid' [-Wredundant-decls] In file included from src/cpu/amd/agesa/family12/model_12_init.c:34:0: src/include/cpu/amd/multicore.h:48:5: note: previous declaration of 'get_initial_apicid' was here src/northbridge/amd/agesa/family12/northbridge.c:50:10: warning: no previous prototype for 'get_node_pci' [-Wmissing-prototypes] src/northbridge/amd/agesa/family12/northbridge.c: In function 'get_hw_mem_hole_info': src/northbridge/amd/agesa/family12/northbridge.c:302:13: warning: unused variable 'i' [-Wunused-variable] src/northbridge/amd/agesa/family12/northbridge.c: In function 'domain_set_resources': src/northbridge/amd/agesa/family12/northbridge.c:587:5: warning: format '%lx' expects argument of type 'long unsigned int', but argument 3 has type 'device_t' [-Wformat] src/northbridge/amd/agesa/family12/northbridge.c:587:5: warning: format '%lx' expects argument of type 'long unsigned int', but argument 3 has type 'device_t' [-Wformat] src/northbridge/amd/agesa/family12/northbridge.c:716:1: warning: format '%x' expects argument of type 'unsigned int', but argument 3 has type 'long unsigned int' [-Wformat] In file included from src/mainboard/amd/torpedo/agesawrapper.h:31:0, from src/northbridge/amd/agesa/family12/northbridge.c:38: src/vendorcode/amd/agesa/f12/AGESA.h:1282:0: warning: "TOP_MEM" redefined [enabled by default] In file included from src/northbridge/amd/agesa/family12/northbridge.c:34:0: src/include/cpu/amd/mtrr.h:31:0: note: this is the location of the previous definition In file included from src/mainboard/amd/torpedo/agesawrapper.h:31:0, from src/northbridge/amd/agesa/family12/northbridge.c:38: src/vendorcode/amd/agesa/f12/AGESA.h:1283:0: warning: "TOP_MEM2" redefined [enabled by default] src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c: In function 'PcieInputParserGetNumberOfComplexes': src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c:99:19: warning: operation on 'ComplexList' may be undefined [-Wsequence-point] src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c: In function 'PcieInputParserGetLengthOfPcieEnginesList': src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c:126:20: warning: operation on 'PciePortList' may be undefined [-Wsequence-point] src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c: In function 'PcieInputParserGetLengthOfDdiEnginesList': src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c:153:19: warning: operation on 'DdiLinkList' may be undefined [-Wsequence-point] src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c: In function 'PcieInputParserGetComplexDescriptorOfSocket': src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c:225:17: warning: operation on 'ComplexList' may be undefined [-Wsequence-point] src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PciePhyServices.c:246:1: warning: no previous prototype for 'PcieFmForceDccRecalibrationCallback' [-Wmissing-prototypes] In file included from src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieComplexConfig.c:58:0: src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/LlanoComplexData.h:120:5: warning: large integer implicitly truncated to unsigned type [-Woverflow] And fixed a boatload of these types of warning: src/vendorcode/amd/agesa/f12/Proc/CPU/heapManager.c: In function 'HeapGetBaseAddress': src/vendorcode/amd/agesa/f12/Proc/CPU/heapManager.c:687:17: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] src/vendorcode/amd/agesa/f12/Proc/CPU/heapManager.c:694:19: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] src/vendorcode/amd/agesa/f12/Proc/CPU/heapManager.c:701:23: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] src/vendorcode/amd/agesa/f12/Proc/CPU/heapManager.c:702:23: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] src/vendorcode/amd/agesa/f12/Proc/CPU/heapManager.c:705:23: warning: assignment makes integer from pointer without a cast [enabled by default] src/vendorcode/amd/agesa/f12/Proc/CPU/heapManager.c:709:21: warning: assignment makes integer from pointer without a cast [enabled by default] Change-Id: I97fa0b8edb453eb582e4402c66482ae9f0a8f764 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/2348 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2013-02-18AMD S3: Include the s3_resume.h only when S3 is enabled.Zheng Bao
Change-Id: I9a6c4f61e5dda6665f92c8526bb26a458ee2b739 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/2384 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
2013-02-16libpayload: only compile drivers/serial.c on machines that use it.Ronald G. Minnich
Create a new serial console variable, X86_SERIAL_CONSOLE which is only enabled when SERIAL_CONSOLE and ARCH_X86 are defined. Builds for x86 and ARM. Change-Id: I607253c418de015975a839e3c33577842885ec0c Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2412 Tested-by: build bot (Jenkins) Reviewed-by: Gabe Black <gabeblack@chromium.org>
2013-02-16exynos5250: clean out some stale IRAM-related config variablesDavid Hendricks
This cleans out some obsolete Kconfig variables pertaining to IRAM usage. Change-Id: Ie53f5f7204eadc3a3dddc739d2b4b6237242b198 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2417 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2013-02-16armv7/exynos5250: fix usage of _stack and _estackDavid Hendricks
This patch fixes up the usage of stack pointer and regions. The current approach only works by coincidence, so this fixes a few things at once to get it into a working state and allow us to use checkstack() again: - Add a STACK_SIZE Kconfig variable. Earlier on it was evaluated to 0. - Assign _stack and _estack using CPU-specific Kconfig variables since it may reside elsewhere in memory (not necessarily DRAM). - Make the existing IRAM stack variables more useful in this context. Change-Id: I4ca5b5680c9ea7e26b1b2b6b3890e028188b51c2 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2416 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2013-02-15ARMv7: Drop u-boot type remainsStefan Reinauer
Just a mechanical cleanup. Change-Id: I0815625e629ab0b7ae6c948144085f1bd8cabfb5 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2408 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2013-02-15Exynos5250: Drop unused file ehci-s5p.hStefan Reinauer
Change-Id: I39014377af718766ef86c149e2d2da3d97eaa728 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2407 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-02-15OT200: add CMOS supportChristian Gmeiner
nvramtool works as expected. root@CHGM-DEV-OT200:~# /home/vis/nvramtool -a baud_rate = 19200 debug_level = Emergency Change-Id: Ia25dc5b4f0ed3a2dd7cc67b7d3174db3a6eff70e Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Reviewed-on: http://review.coreboot.org/2382 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2013-02-15libpayload: Use the same type for 32 bit data in readl as in uint32_t.Ronald G. Minnich
The compiler gets mad when the types are equivalent size but not necessarily interchangeable because of strict aliasing checks. Since uint32_t is likely to be used when trying to read 32 bit data, it makes sense for them to be the compatible. Signed-off-by: Gabe Black <gabeblack@google.com> Change-Id: If73d794866055dc026fc06d6268e692adac0f835 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2411 Tested-by: build bot (Jenkins) Reviewed-by: Gabe Black <gabeblack@chromium.org>
2013-02-15libpayload: fix compiler flagsRonald G. Minnich
lpgcc was unconditionally setting -m32. Most of the flags it sets in the common case are right, however: no need to duplicate them everywhere, and we only want to change the common ones in one place, so it would be a shame to duplicate _CFLAGS all over the place. So add another variable, _ARCHEXTRA, which can be used to add special flags to _CFLAGS. We onlu use it at present for the x86; this may change. This allows us to get through compiling on arm and x86. Change-Id: I12f1620982c4ee10f76b3953e4225f13db31531e Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2399 Tested-by: build bot (Jenkins) Reviewed-by: Gabe Black <gabeblack@chromium.org>
2013-02-15libpayload: get time to compile cross-archRonald G. Minnich
Get rid of the nest of includes, and make separate sections for each architecture. Also gets rid of the "there's X86 and there's everything else" structure of this file. Change-Id: I4232f50f048fa05e911e5de3aa9ec1530931b461 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2397 Tested-by: build bot (Jenkins) Reviewed-by: Gabe Black <gabeblack@chromium.org>
2013-02-15libpayload: make functions static that are unused outside memory.cRonald G. Minnich
The default_ functions in memory.c are only used to initialize a weak variable. They should not be used outside memory.c. Make them invisible. Remove the declaration from libpayload.h. For real this time. Change-Id: Id54c1fd172c78748f01a958ce4065dd0eb53bbc3 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2394 Tested-by: build bot (Jenkins) Reviewed-by: Gabe Black <gabeblack@chromium.org>
2013-02-15libpayload: Use an appropriate range of memory when looking for cb tables.Ronald G. Minnich
These live at the bottom of memory on x86, but that's IO mapped on the exynos. The particular range used will likely need to be configurable, but this will make it work in one more case than it used to. Change-Id: I4d4963b9732cf538d00f8effb4398f30cbbde6aa Signed-off-by: Gabe Black <gabeblack@google.com> Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2410 Tested-by: build bot (Jenkins) Reviewed-by: Gabe Black <gabeblack@chromium.org> Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-02-15Exynos: Drop dead code in cpu.hStefan Reinauer
Change-Id: Ibb5fa27a0d45ddd8f57e8e8c28961d204e2ef1e3 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2409 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-15ARMv7: straighten out reset codeStefan Reinauer
We don't need three different implementations. Change-Id: Ie7b5fa90794676ea38838454a33e8e9188428eb7 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2406 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-15Exynos5: Drop S5P directory and merge filesStefan Reinauer
s5p-common mostly contained duplicate files, drop the whole directory and merge the few pieces that we are using into exynos5-common. Change-Id: I5f18e8a6d2379d719ab6bbbf817fe15bda70d17f Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2405 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-02-15ARMv7: Drop sr32, and wait_on_valueStefan Reinauer
They're unused. Also drop some unused defines in system.h Change-Id: Ia5afc3a676a4a94787041430f05d08f333033c73 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2404 Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: build bot (Jenkins)
2013-02-15ARMv7: Fix include file names in memset & memcpyStefan Reinauer
We don't have asm/ Change-Id: I7f80f47e9d7f457b7a5a64603c59b14d3b536a8c Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2403 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-02-15ARMv7: Drop more unused filesStefan Reinauer
Change-Id: I0dd83f96d2a9598e9677d1b0b114229de6724287 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2401 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-15libpayload: add a ldscript for armRonald G. Minnich
I think this needs to be its own ldscript. I'm pretty sure this one is going to need some work however. Is libpayload PIC? That would be best if so. Change-Id: I44578d70dfa72de527af8901a86583c2a60130ec Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2398 Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: build bot (Jenkins)
2013-02-15Drop include/arch-generic/div64.hStefan Reinauer
It's unused. Change-Id: Id67ca754ff7ad148ff1ecd4f1e5c986a4e7585a8 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2400 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-02-15Exynos: Drop unused include filesStefan Reinauer
Change-Id: Ib533938446a289167725f5beda77c2ee5236e8a5 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2395 Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: build bot (Jenkins)
2013-02-14ARMv7: drop multiboot supportStefan Reinauer
Multiboot is an x86 only thing. Drop support on ARM. Change-Id: I13fafa464a794206d5450b4a1f23a187967a8338 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2392 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-14Exynos: Drop duplicate copy of watchdog.hStefan Reinauer
Change-Id: I4c9bfa9eb7708420dc42c16bc152d761d2bdfee3 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2391 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-14ARMv7: Drop SKIP_LOWLEVEL_INITStefan Reinauer
It's not used. Change-Id: I713d60209815f0aad93f5d4d3afef9f825db427e Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2393 Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: build bot (Jenkins)
2013-02-14Exynos5250: Drop SHA implementationStefan Reinauer
We don't need SHA in coreboot. Change-Id: I1985d5e2c74fac39ff9dcdba4c23bb34fa857ec7 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2390 Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: build bot (Jenkins)
2013-02-14libpayload; put the ldscript into an arch-dependent directory pathRonald G. Minnich
Since it's utterly architecture-dependent, put it in arch/x86. Avoid the temptation to make yet another directory with just one file in it. Fix the makefile to pick up the proper arch-dependent script. Change-Id: I21ea02551a97bdcbc38419714f3b38cf8335c178 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2389 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-02-14Chromebooks: mainboard.c: Do not spell Chromebook in CamelCasePaul Menzel
»Chromebook« is the official spelling [1]. So correct that with the following command. $ git grep -l ChromeBook | xargs sed -i s,ChromeBook,Chromebook, The incorrect spelling was only used for the chip name. [1] http://www.google.com/intl/en/chrome/devices/hp-pavilion-chromebook.html#hp-pav Change-Id: I9c19f399a3e3d36bd644ec375822daa384a14961 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2370 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Marc Jones <marcj303@gmail.com>
2013-02-14Google Butterfly: thermal.h: Align macro contentPaul Menzel
Change-Id: I3729f9bf66fcd72fa8870bb56a9c253a7368c774 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2371 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Marc Jones <marcj303@gmail.com>
2013-02-14sconfig: rename lapic_cluster -> cpu_clusterStefan Reinauer
The name lapic_cluster is a bit misleading, since the construct is not local APIC specific by concept. As implementations and hardware change, be more generic about our naming. This will allow us to support non-x86 systems without adding new keywords. Change-Id: Icd7f5fcf6f54d242eabb5e14ee151eec8d6cceb1 Signed-off-by: Stefan Reinauer <reinauer@google.com> Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2377 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-14armv7: don't write a forward entry in coreboot tablesDavid Hendricks
We don't seem to need it, and it currently confuses the payload. (credit to Gabe Black for this, I'm just uploading it) Change-Id: I4e3a60eceb9b24e3bc8e50db431c1a731d1cdbae Signed-off-by: David Hendricks <dhendrix@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/2385 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-14snow: Set up MMU after DRAM is workingDavid Hendricks
This was omitted earlier while we were debugging DRAM code (0a5bc7f). It was likely broken due to inconsistent units earlier on. Now that things are cleaned up and working, let's add it back in. Change-Id: I2f356355c98b2896e2371fa63b9c9f20ae76d634 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2379 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-14snow: remove superfluous printk's from romstage mainDavid Hendricks
These were left over from earlier debugging and are no longer needed. They don't indicate any status or useful info (other than which line of code has been executed). Error messages are available in case something needs attention. Change-Id: Ie09fac29c42908cb8924169e56d8927fb76f02da Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2386 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-14sconfig: rename pci_domain -> domainStefan Reinauer
The name pci_domain was a bit misleading, since the construct is only PCI specific in a particular (northbridge/cpu) implementation, but not by concept. As implementations and hardware change, be more generic about our naming. This will allow us to support non-PCI systems without adding new keywords. Change-Id: Ide885a1d5e15d37560c79b936a39252150560e85 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2376 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-13armv7/exynos: remove some stale files leftover from initial importDavid Hendricks
This removes some files leftover from the initial port. Some are leftover from U-Boot and some were leftover from the skeleton code derived from x86. There's a bit more that we'll get in another sweep. Change-Id: I325793ecb902b3b9430dcf531714ce025d201de6 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2380 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-13armv7: use start and size parameters in mmu_setup()David Hendricks
mmu_setup() was originally written in U-Boot to utilize board-specific global data. Since we're trying to avoid that, we added start and size parameters so that board-specific info can be passed in via mainboard code. Let's start using it that way. Change-Id: I7d7de0e42bd918c9f9f0c177acaf56c110bf8353 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2378 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2013-02-12armv7: stages.c: Fix grammar: s,The is to,This is to,Paul Menzel
The comment introduced in commit 50c0a50ac6a3fa54ed1286e8b76f933701b6d053 Author: David Hendricks <dhendrix@chromium.org> Date: Thu Jan 31 17:05:50 2013 -0800 armv7: unify stage hand-off routines Reviewed-on: http://review.coreboot.org/2254 contained a typo, which is corrected now. Change-Id: I87f7cfa82fcd12b6961d3329e634b4c201cc047e Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2372 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-12Google Butterfly: acpi/thermal.asl: Fix typo »The*re* is no …«Paul Menzel
The commit introducing support for the Google Butterfly Chromebook commit d7bd4eb003f5b6a13943418ae0ac53248a2e34d2 Author: Stefan Reinauer <reinauer@chromium.org> Date: Mon Feb 11 11:11:36 2013 -0800 Add support for "Butterfly" Chromebook Reviewed-on: http://review.coreboot.org/2359 contains the typo, which is corrected now. Change-Id: I932f4cd248cac71c3ede39a7da97162e791827cb Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2373 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Peter Stuge <peter@stuge.se>
2013-02-12Google Butterfly: gpio.h: Correct whitespace errorsPaul Menzel
Correct some whitespace inconsistencies introduced in the following commit. commit d7bd4eb003f5b6a13943418ae0ac53248a2e34d2 Author: Stefan Reinauer <reinauer@chromium.org> Date: Mon Feb 11 11:11:36 2013 -0800 Add support for "Butterfly" Chromebook Reviewed-on: http://review.coreboot.org/2359 Change-Id: Ifeda7eb29ddf855cdfea41ddbd685441ede55756 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2374 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2013-02-12Google Parrot/Butterfly: fadt.c: Align macros correctlyPaul Menzel
The commits adding support for the Google Parrot Chromebook commit a7198b34ccf120df2a9e5b9f104812e96916ad08 Author: Stefan Reinauer <reinauer@chromium.org> Date: Tue Dec 11 16:00:47 2012 -0800 Add support for Google Parrot Chromebook Reviewed-on: http://review.coreboot.org/2026 and the Google Butterfly Chromebook commit d7bd4eb003f5b6a13943418ae0ac53248a2e34d2 Author: Stefan Reinauer <reinauer@chromium.org> Date: Mon Feb 11 11:11:36 2013 -0800 Add support for "Butterfly" Chromebook Reviewed-on: http://review.coreboot.org/2359 had macros in `fadt.c` which were not aligned correctly and did not adhere to the coding style which uses just one space after `#define`. Fix this and use tabs instead of spaces everywhere. Change-Id: I1422c57a3bdc2faa29d2a6e2064e4d3aeed0f1cb Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2375 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2013-02-12libpayload: New CBFS to support multiple firmware media sources.Hung-Te Lin
Upgrade CBFS in libpayload to use new media-based implementation from coreboot ( http://review.coreboot.org/#/c/2182/ ). Old CBFS functions (cbfs_find, cbfs_find_file, get_cbfs_header) are still supported, although the recommended way is to use new CBFS API. To migrate your existing x86 payload source: - Change cbfs_find to cbfs_get_file - Change cbfs_find_file to cbfs_get_file_content - Prefix every CBFS call with a CBFS_DEFAULT_MEDIA argument. Ex, char *jpeg_data = cbfs_find_file("splash.jpg", CBFS_TYPE_BOOTSPLASH); => char *jpeg_data = cbfs_get_file_content( CBFS_DEFAULT_MEDIA, "splash.jpg", CBFS_TYPE_BOOTSPLASH); The legacy setup_cbfs_from_{ram,flash} is also supported, although the better equivalent is to make a new media instance: struct cbfs_media ram_media; init_cbfs_ram_media(&ram_media, start, size); char *data = cbfs_get_file_content(&ram_media, "myfile", my_type); Verified by being successfully linked with filo. Change-Id: If797bc7e3ba975d7e3be905c59424f7a93b8ce11 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/2191 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2013-02-12build system: Don't run the full build system on "make clean"Patrick Georgi
When running "make clean" the build system used to parse the entire build system. Besides costing time, it prevents cleaning the tree if a blobs-board is selected but blobs are not enabled. Instead, clean always removes all of $(obj) and .xcompile, while distclean additionally removes .config and the like. Besides cleaning up more completely (eg. dependency files), a side effect is that this also removes $(obj)/util, if it exists (default location for build tools). Change-Id: Ief6362460d4eb7edcb4b0a47ec76cb9a61bf3b86 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/2338 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-12fix an error message in checkstack()David Hendricks
The order of some printk arguments were reversed. Change-Id: I5e8f70b79050b92ebe8cfa5aae94b6cd1a5fd547 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2364 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-12armv7: jump to ELF image using stage_exit()David Hendricks
This is just to get us to the payload. TODO: Do we want to implement any of the stuff from the x86 version, such as copying coreboot to a new location? Change-Id: Ia0544f111d7a1189ebd92d0ba3e11448eabd6252 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2363 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2013-02-12armv7: Add emulation/qemu-armv7 board.Hung-Te Lin
To simplify testing ARM implementation, we need a QEMU configuration for ARM. The qemu-armv7 provides serial output, CBFS simulation, and full boot path (bootblock, romstage, ramstage) to verify the boot loader functionality. To run with QEMU: export QEMU_AUDIO_DRV=none qemu-system-arm -M vexpress-a9 -m 1024M -nographic -kernel build/coreboot.rom Verified to boot until ramstage loaded successfully by QEMU v1.0.50. Change-Id: I1f23ffaf408199811a0756236821c7e0f2a85004 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/2354 Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-11spi-generic.h: Adapt include guardPatrick Georgi
Rename _SPI_H_ to _SPI_GENERIC_H_ to match recent file rename. Change-Id: I8b75e2e0a515fb540587630163ad289d0a6a0b22 Reported-by: Peter Stuge <peter@stuge.se> Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/2360 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2013-02-11Add support for "Butterfly" ChromebookStefan Reinauer
We're happy to announce coreboot support for the "Butterfly" Chromebook, a.k.a HP Pavilion Chromebook. More information at: http://www.google.com/intl/en/chrome/devices/hp-pavilion-chromebook.html This commit also includes support for the ENE KB3940Q embedded controller running on Quanta's firmware. Change-Id: I194f847a94005218ec04eeba091c3257ac459510 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2359 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins)
2013-02-11build system: Mark clean-for-update phonyPatrick Georgi
build system hygiene, not known if this actually matters. Change-Id: Ic800a2acecff123fc2055047fab67df107ac43ab Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/2356 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2013-02-11Update 3rdparty mark to latest repositoryStefan Reinauer
Change-Id: Iad3ee8eae9c3551a4078bd48c3f187e694ba6837 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2358 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-11snow: fix high_tables_base calculationDavid Hendricks
It was off by a few orders of magnitude. D'oh. Change-Id: I9c8a3d5bd9ce261f914cfc7d05d86a1c61519b81 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2355 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-11spi.h: Rename the spi.h to spi-generic.hZheng Bao
Since there are and will be other files in nb/sb folders, we change the general spi.h to a file name which is not easy to be duplicated. Change-Id: I6548a81206caa608369be044747bde31e2b08d1a Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/2309 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-02-11Intel: Replace MSR 0xcd with MSR_FSB_FREQPatrick Georgi
And move the corresponding #define to speedstep.h Change-Id: I8c884b8ab9ba54e01cfed7647a59deafeac94f2d Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/2339 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-11AMD/Persimmon: Enable the 2nd COM portDave Frodin
The hardware is there, so turn it on. Change-Id: I40aff1e84a22a05599c62b9f0b20397df0a40b15 Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/2353 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-02-11crossgcc: Support hosts using non-GNU make as default make.Hung-Te Lin
On hosts using non-GNU make as default make program (ex, FreeBSD's default is BSD make and having GNU make as "gmake"), building acpica will fail. We should use the correct path of make $(MAKE). Verified to build on FreeBSD 9.0 with gcc 4.7 from ports. Note, the shipped gcc in FreeBSD 9.0 is 4.2.1 and needs more patches to remove -Wbad-function-case and -Wempty-body. That should be fixed in a future patch. Change-Id: Iacbf5a05e84a8a53d9d3e783a10131de603282c9 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/2333 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-02-11Supermicro H8QGI: Substract 1 from MMCONF range limitKonstantin Aladyshev
MMCONF space is defined by two config parameters: MMCONF_BASE_ADDRESS (0xF800 0000) MMCONF_BUS_NUMBER (64) Coreboot allocates 1MB per bus, so MMCONF limit should be: 0xF800 0000 + 64*(0x0010 0000) - 1 = 0xFBFF FFFF Current code does not have (-1) component, this makes MMCONF limit equal 0xFC00 FFFF. Not 0xFC00 0000, because according to BKDG lower two bytes of MMIO limit always equal 0xFFFF: MMIOLimit = {MMIOLimitRegister[47:16], FFFFh}. Add (-1) to correct this issue. No functionality change has been experienced. The five times slower RAM speed compared to the proprietary vendor BIOS still remains. Change-Id: I2c6494c28bb8d36e54ceb2aa7d8d965b0103cbe9 Signed-off-by: Konstantin Aladyshev <aladyshev@nicevt.ru> Reviewed-on: http://review.coreboot.org/2193 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-02-11AMD SB900: fix warningsMartin Roth
Add a prototype to a .h file Remove an unused file (GppHp.c) from the build by deleting it from the makefile. I left the file since this is vendorcode. This is the code for PCIe hotplug. Inside GppHp.c, make functions not called from outside static. This obviously isn't important since the file isn't used, but for the sake of the cleanup I thought I'd go ahead with it... This was tested with the torpedo build. This fixes these warnings: src/vendorcode/amd/cimx/sb900/Dispatcher.c: In function 'LocateImage': src/vendorcode/amd/cimx/sb900/Dispatcher.c:193:38: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] src/vendorcode/amd/cimx/sb900/Usb.c:740:1: warning: no previous prototype for 'XhciA12Fix' [-Wmissing-prototypes] src/vendorcode/amd/cimx/sb900/GppHp.c:65:1: warning: no previous prototype for 'sbGppHotPlugSmiProcess' [-Wmissing-prototypes] src/vendorcode/amd/cimx/sb900/GppHp.c: In function 'sbGppHotPlugSmiProcess': src/vendorcode/amd/cimx/sb900/GppHp.c:76:5: warning: implicit declaration of function 'SbStall' [-Wimplicit-function-declaration] src/vendorcode/amd/cimx/sb900/GppHp.c: At top level: src/vendorcode/amd/cimx/sb900/GppHp.c:101:1: warning: no previous prototype for 'sbGppHotUnplugSmiProcess' [-Wmissing-prototypes] src/vendorcode/amd/cimx/sb900/GppHp.c:134:1: warning: no previous prototype for 'sbGppHotplugSmiCallback' [-Wmissing-prototypes] src/vendorcode/amd/cimx/sb900/GppHp.c: In function 'sbGppHotplugSmiCallback': src/vendorcode/amd/cimx/sb900/GppHp.c:158:5: warning: implicit declaration of function 'outPort80' [-Wimplicit-function-declaration] Change-Id: I5a1a20eeb81e1f4d59e3e3192f081e11d8506f56 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/2349 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-02-11AMD S3: Add missing erasing flash sector for saving MTRR registerZheng Bao
It has worked up to now because the region is already erased the first time the board boots, and every additional boot the same data is being written over the old data.(by Dave Frodin) Change-Id: Id334c60668e31d23c1d552d0ace8eb6ae5513e6b Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/2304 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-02-11AMD S3: Change the hardcoded data size to macros.Zheng Bao
Change-Id: Ieefc4213a6dee9c399826b1daa98bbf4bc10d881 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/2303 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-02-11snow: make build script erase 192KB instead of 128KBDavid Hendricks
This will make the build script wipe out more flash memory content. Our image is a bit bigger now that we're testing with payloads, so this is just added paranoia to prevent weird surprises caused by not flashing the full image. Change-Id: I31969922079e96886573d9d802266eb0052277cd Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2352 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-11armv7/exynos5250/snow: deprecate CONFIG_{RAMBASE,RAMTOP}David Hendricks
RAMBASE and RAMTOP are leftovers from the x86 port and do not apply the same way on ARM platforms. On x86 they refer to the low memory region where coreboot tables reside. However on ARM we don't have such a region which is architecturally defined. So instead we'll use the CPU-defined DRAM base address and the mainboard-defined DRAM size. This also has the pleasant side-effect of fixing the coreboot tables to not clobber ramstage code... Change-Id: I5548ecf05e82f9d9ecec8548fabdd99cc1e39c3b Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2351 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-10armv7/snow: Remove unused modules in bootblock and romstage.Hung-Te Lin
For Exynos/snow, cpu_info and power modules and also some parts of the GPIO API (which require timer and pwm modules) are not used in the current bootblock. Clock init only needs to be used if early console is enabled. Now our bootblock is 22420 bytes with early serial console and 11192 bytes without. Those include the 8KB BL1 region. Change-Id: I9c958dafb9cf522df0dcfbef373ce741aa162544 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2322 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-10exynos/snow: move SPI GPIO setup to mainboard bootblock codeDavid Hendricks
This moves GPIO setup from chip-specific SPI code to mainboard- specific bootblock code. This makes exynos_spi_open a bit more generic so it can eventually be used for any SPI channel. This also benefits CBFS since the user can set media->context to to any set of SPI registers. Change-Id: I2bcb9de370df0a79353c14b4d021b471ddebfacd Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2347 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-10exynos/snow: set SPI clock rate in romstage mainDavid Hendricks
This moves the setting of SPI clock rate into romstage's main, which allows us to eliminate a bunch of dependencies from the bootblock (about 7KB worth). Change-Id: I371499bb4af6a6aa838294bc56f9dbc21864957a Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2346 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-10armv7/exynos5250: place .id between .start and bootblock mainDavid Hendricks
This places the .id section toward the lower region of the coreboot image, before the bootblock. It's easier for humans to find by dumping the image and it also eliminates ID_SECTION_OFFSET which is currently the upper bound on our image size. Change-Id: I7d737b901dac659ddf9aa437cee5dc32f1080546 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2345 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-10armv7: make bootblock linker script more explicitDavid Hendricks
This adds a .bl1 and .start symbol that is placed at the beginning of the .rom section. The goal is to move the .id section in between the reset vector and bootblock_main. Change-Id: Ie732ce656d697c059cc0fa40c844b39f53fc214c Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2344 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-09armv7/exynos: make BL1_SIZE_KB consistent with numbers used...David Hendricks
The Kconfig variable indicates KB, but the number used was bytes. Let's just assume KB is correct for now. Change-Id: I910c126104f0222fc48b70a18df943f2afddeca3 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2341 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-09speedstep: Deduplicate some MSR identifiersPatrick Georgi
In particular: MSR_PMG_CST_CONFIG_CONTROL MSR_PMG_IO_BASE_ADDR MSR_PMG_IO_CAPTURE_ADDR Change-Id: Ief2697312f0edf8c45f7d3550a7bedaff1b69dc6 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/2337 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-09romcc: Use default romcc flags for most boardsPatrick Georgi
Except for one board, the flags can be derived from CONFIG_MMX and CONFIG_SSE. Change-Id: I64a11135ee7ce8676f3422b2377069a3fa78e24d Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/2336 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-09romcc: Don't use user overridable romcc flags for bootblockPatrick Georgi
The bootblock is typically run before fpu/mmx/sse setup, so we can't rely on -mcpu=p4 and the like to increase the register space. bootblock_romccflags does that for SSE, but they're controlled separately. Change-Id: I2b0609ac18b2394a319bf9bbbee1f77d2e758127 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/2335 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-09cbfstool: Handle alignment in UEFI payloadsPatrick Georgi
Tiano for X64 is much cleaner to start up when using higher alignments in firmware volumes. These are implemented using padding files and sections that cbfstool knew nothing about. Skip these. Change-Id: Ibc433070ae6f822d00af2f187018ed8b358e2018 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/2334 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-09cbfstool: Fix crash on image without bootblock in end of ROM.Hung-Te Lin
On platforms with CBFS data filling end of ROM image without bootblock in the end (ex, ARM), calculation of "next valid entry" may exceed ROM image buffer in memory and raise segmentation fault when we try to compare its magic value. To fix this, always check if the entry address is inside ROM image buffer. Verified to build and boot successfully on qemu/x86 and armv7/snow. Change-Id: I117d6767a5403be636eea2b23be1dcf2e1c88839 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/2330 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-02-09armv7: update coreboot tables for armv7David Hendricks
This is a first-pass attempt at cleaning up the coreboot tables for ARM. The most noticable difference is that there is no longer both a high and a low table. Change-Id: I5ba87ad57bf9a697b733511182c0326825071617 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2329 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-09snow: do something useful in ramstage()David Hendricks
This cleans up Snow's trivial ramstage, gives it a coreboot table address and calls hardwaremain(). Change-Id: I84c904bcfd57a5f9eb3969de8a496f01e43bc2f6 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2328 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-09armv7/snow: add BL1_SIZE_KB and get rid of magic constantsDavid Hendricks
This adds a BL1_SIZE_KB config variable so that we can get rid of some magic constants. Change-Id: I9dbcfb407d3f8e367be5d943e95b032ce88b0ad0 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2332 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-09armv7: include $(obj)/config.h when building bootblockDavid Hendricks
Explicitly including it allows us to get rid of some magic constants in the bootblock linker script. Change-Id: I095899babc997addce6b383f00e5ebf135e99d5e Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2331 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-09DEBUG_CBFS should not depend on TPMDavid Hendricks
This seemed to have been introduced in fe422184. Change-Id: I4f9ecfbec42aa8c0bb8887675a3add8951645b98 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2327 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-09document Intel VMX locking behaviorMike Frysinger
Add a comment explaining that the existing lock bit logic is correct and "as designed" even though the manual states otherwise. This way people don't have to "just know" what is going on. Change-Id: I14e6763abfe339e034037b73db01d4ee634bb34d Signed-off-by: Mike Frysinger <vapier@chromium.org> Reviewed-on: http://review.coreboot.org/2326 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2013-02-08VBE: Skip graphics mode setting for non-VGA devicesStefan Reinauer
This hit me when running the latest Qemu with coreboot: First the graphics OPROM is running, then an iPXE OPROM. The iPXE OPROM has no int10 support (obviously) so calling vbe_set_graphics() wipes the framebuffer information from the coreboot table. Change-Id: Ie0453c4a908ea4a6216158f663407a3e72ce4d34 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2325 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-02-08console: Fix using CMOS for optionsPatrick Georgi
Just a tiny mistake, but it made the console driver assume that CMOS data isn't available. Change-Id: I4e6f53e9ed59024de7b09333f82f0ce3235ef8f6 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/2323 Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2013-02-08oprom: fix compilation for Qemu target (and possibly others)Stefan Reinauer
Not sure why this didn't bite us earlier.. src/device/oprom/realmode/x86.c: In function 'fill_lb_framebuffer': src/device/oprom/realmode/x86.c:272:13: error: dereferencing pointer to incomplete type src/device/oprom/realmode/x86.c:274:13: error: dereferencing pointer to incomplete type src/device/oprom/realmode/x86.c:275:13: error: dereferencing pointer to incomplete type src/device/oprom/realmode/x86.c:276:13: error: dereferencing pointer to incomplete type src/device/oprom/realmode/x86.c:278:13: error: dereferencing pointer to incomplete type src/device/oprom/realmode/x86.c:280:13: error: dereferencing pointer to incomplete type src/device/oprom/realmode/x86.c:281:13: error: dereferencing pointer to incomplete type src/device/oprom/realmode/x86.c:283:13: error: dereferencing pointer to incomplete type src/device/oprom/realmode/x86.c:284:13: error: dereferencing pointer to incomplete type src/device/oprom/realmode/x86.c:286:13: error: dereferencing pointer to incomplete type src/device/oprom/realmode/x86.c:287:13: error: dereferencing pointer to incomplete type src/device/oprom/realmode/x86.c:289:13: error: dereferencing pointer to incomplete type src/device/oprom/realmode/x86.c:290:13: error: dereferencing pointer to incomplete type Change-Id: Ie3b0f731a7b995e954a26e745b07fc122088ca9f Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2321 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-02-08armv7/snow: Move clock initialization from bootblock to romstage.Hung-Te Lin
Exynos system clock can be initialized before RAM init, not necessary to be in the very beginning (boot block). This helps reducing bootblock dependency. Verified to boot on armv7/snow. Note: this patch was originally introduced in 2308, but there were some ordering issues so it was reverted. Change-Id: Ibc91c0e26ea8881751fc088754f5c6161d011b68 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2320 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-08armv7: Use same console initialization procedure for all ARM stagesHung-Te Lin
Use same console initialization procedure for all ARM stages (bootblock, romstage, and ramstage): #include <console/console.h> ... console_init() ... printk(level, format, ...) Verified to boot on armv7/snow with console messages in all stages. Change-Id: Idd689219035e67450ea133838a2ca02f8d74557e Signed-off-by: Hung-Te Lin <hungte@chromium.org> Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2301 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-08console: Only print romstage messages with EARLY_CONSOLE enabled.Hung-Te Lin
Revise console source file dependency (especially for EARLY_CONSOLE) and interpret printk/console_init according to EARLY_CONSOLE setting (no-ops if EARLY_CONSOLE is not defined). Verified to boot on x86/qemu and armv7/snow. Disabling EARLY_CONSOLE correctly stops romstage messages on x86/qemu (armv7/snow needs more changes to work). Change-Id: Idbbd3a26bc1135c9d3ae282aad486961fb60e0ea Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/2300 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-02-08console: Always allow setting "EARLY_CONSOLE" configuration.Hung-Te Lin
Early console should always be allowed to be turned on / off (for generating production and debug versions), and should not be enforced by "select" Kconfig rule. A new "DEFAULT_EARLY_CONSOLE" is introduced for devices to select if they prefer early console output by default. Verified Kconfig value on qemu/x86 (default y by CACHE_AS_RAM), snow/x86 (default y by EXYNOS5 config), and intel/jarrell (default n). Change-Id: Ib1cc76d4ec115a302b95e7317224f1a40d1ab035 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/2307 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-02-08exynos/snow: Configure UART peripheral during console initialization.Hung-Te Lin
For Exynos platforms, the UART component on pinmux must be first selected and configured. This should be done as part of UART console initialization. Note, that the current implementation hard-codes the device index as UART3, while the base port can be assigned to different device in Kconfig. This will be fixed later. Verified to work on armv7/snow. Change-Id: Ie63e76e2dac09fec1132573d1b0027fce55333a1 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/2315 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-02-08console: Revise serial console configuration names.Hung-Te Lin
The console drivers (especially serial drivers) in Kconfig were named in different styles. This change will rename configuration names to a better naming style. - EARLY_CONSOLE: Enable output in pre-ram stage. (Renamed from EARLY_SERIAL_CONSOLE because it also supports non-serial) - CONSOLE_SERIAL: Enable serial output console, from one of the serial drivers. (Renamed from SERIAL_CONSOLE because other non-serial drivers are named as CONSOLE_XXX like CONSOLE_CBMEM) - CONSOLE_SERIAL_UART: Device-specific UART driver. (Renamed from CONSOLE_SERIAL_NONSTANDARD_MEM because it may be not memory-mapped) - HAVE_UART_SPECIAL: A dependency for CONSOLE_SERIAL_UART. Verified to boot on x86/qemu and armv7/snow, and still seeing console messages in romstage for both platforms. Change-Id: I4bea3c8fea05bbb7d78df6bc22f82414ac66f973 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/2299 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-02-08Revert "armv7/snow: Move clock initialization from bootblock to romstage."David Hendricks
This reverts commit 9029f4b63f6d0e29bf1608e666cdb025de45ca24 This patch needs to go at the end of the UART patch set. Sorry 'bout the confusion! Change-Id: I5702c7d6130daf95776f2c15d24e5d253691cefd Reviewed-on: http://review.coreboot.org/2319 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-29 21:39:29 +0000