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2021-06-07payloads/tianocore: Restrict bootsplash option to UEFIPAYLOADMatt DeVillier
The custom bootsplash option only functions when using the UEFIPAYLOAD payload option, so restrict visibility to when that option is selected. Change-Id: If5fe46b629e5275da54a5e86465a68271110397b Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55145 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-07payloads/tianocore: Add Kconfig option to enable cbmem loggingMatt DeVillier
Logging to coreboot cbmem, instead of a serial console, was added to MrChromebox's uefipayloadpkg branch. Add a Kconfig option to enable this, and restrict it to the UEFIPAYLOAD payload option, since this feature does not exist in upstream edk2. Change-Id: Idef125235dc7ba885eb22ac69c6f752588a9e295 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55144 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com>
2021-06-07cpu/intel/model_206ax/acpi.c: Do not report P_BLKAngel Pons
IO MWAIT redirection is disabled, which means reads to the P_LVL2 and P_LVL3 "registers" will never produce any C-state transition requests. Moreover, the register resource descriptors for all reported C-states use the FFixedHW address space, not I/O. Change-Id: I026835dd24d7ac1e1bae2d851e011e1670abaad4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55215 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-06-07cpu/intel/haswell/acpi.c: Do not report P_BLKAngel Pons
Even if IO MWAIT redirection were enabled, the base address is wrong. Moreover, the register resource descriptors for all reported C-states use the FFixedHW address space, not I/O. Change-Id: Ic2faaafbe4928994aeeab8098d8e0fb6703d203d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55214 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-06-07cpu/intel/model_206ax: Do not set PMG_IO_CAPTURE_ADDR MSRAngel Pons
The MSR only needs to be set when IO MWAIT redirection is to be enabled. Change-Id: Ie856086babe4dadc690f701bd90a7bbac88cb4ad Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55213 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-06-07mb/google/dedede/var/sasukette: Update DPTF parametersTao Xia
Update DPTF parameters from internal thermal team. BUG=b:180875580 BRANCH=dedede TEST=emerge-dedede coreboot Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com> Change-Id: Id18a38cddbcacbafbe2c54d94dbda5e00de02b3b Reviewed-on: https://review.coreboot.org/c/coreboot/+/55208 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Evan Green <evgreen@chromium.org>
2021-06-07bd82x6x boards: Drop redundant `c2_latency`Angel Pons
If unspecified, chipset code already uses 101, and 0x65 == 101. Change-Id: I524ca492fa577003df23017756f74a455582132f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55212 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-06-06mb/lenovo/t410: Enable WLAN and WUSB PCIe portsAngel Pons
These PCH PCIe ports are used and should be enabled. Resolves: https://ticket.coreboot.org/issues/311 Change-Id: I26ace6e043c7c66f8944f0986923014703423b8c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55169 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Swift Geek (Sebastian Grzywna) <swiftgeek@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-06-06mb/lenovo/t410: Update PCH PCIe RP commentsAngel Pons
Looks like the comments were derived from a preproduction board's schematics. Production boards use a different port mapping. Change-Id: I40c267ff048959b131c22c07695212e8bd90c3f4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55171 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Swift Geek (Sebastian Grzywna) <swiftgeek@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-06-06util/crossgcc: Avoid complex filename setsPatrick Georgi
bin/{foo,bar,baz} can fail if one of the files doesn't exist (depending on the shell in use). Instead, cd into the directory and list the files individually. Change-Id: I042b2e45fded1b63551d8e65ead2a7bbbf96b1e7 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54060 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-06util/crossgcc: Update to clang 12Patrick Georgi
Change-Id: I38fc64fa872e2ecb0a10fb5378b3ce0d6a02443c Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55157 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-05mb/intel/sm: Use device aliasesSubrata Banik
Use the device aliases provided by alderlake chipset.cb instead of the raw pci device+function. Take advantage of the default states in chipset.cb and only list the devices that are enabled for all shadowmountain board variants. TEST=Dump devicetree device enable list without and with this CL, no difference observed. Change-Id: I2b769d653ad8ad8ff069a0787d00ff33ead5c912 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55206 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-05mb/intel/adlrvp: Use device aliasesSubrata Banik
Use the device aliases provided by alderlake chipset.cb instead of the raw pci device+function. Take advantage of the default states in chipset.cb and only list the devices that are enabled for all different adlrvp boards. TEST=Dump devicetree device enable list without and with this CL, no difference observed. Change-Id: Ib9e82d953416c076588974f3167d00ae96f01bb5 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55205 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-05mb/intel/{adlrvp, sm}: Remove ADL-S devices from ADL-P/M devicetree.cbSubrata Banik
Change-Id: I095394d9a79506346b8464c850d03cbd8ce2b812 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55221 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-05soc/intel/alderlake: Add IDE-R and KT device into chipset.cbSubrata Banik
Add IDE-R and KT device to chipset.cb and leave it off by default. Change-Id: Iaa51e3dc107eb3f06ad7b2aad72a6bc112999d98 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55209 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-05soc/mediatek/mt8195: fix GPIO register offsetsZhiqiang Ma
Correct the offsets by MT8195 Register Map V0.2-1 chapter: 3.2 GPIO Controller (page 3272) Control register names: PUPD_CFG0 PU_CFG0 Signed-off-by: Zhiqiang Ma <zhiqiang.ma@mediatek.com> Change-Id: I9b0f8a24756092a97933cc9d4ba13a9e79c73e91 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55163 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-05mb/google/cherry: Get RAM code from ADCRex-BC Chen
On Chromebooks the RAM code is implemented by the resistor straps that we can read and decode from ADC. For Cherry the RAM code can be read from ADC channel 2 and 3. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I4f28bc1c567cb886bd90d930219981a6206b9bb9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55156 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-06-05soc/mediatek/mt8195: Enable mt8195 auxadcZhiqiang Ma
Enable auxadc on MediaTek mt8195 platform. Signed-off-by: Zhiqiang Ma <zhiqiang.ma@mediatek.com> Change-Id: Ie79420e20c9ed6155791b490e1b5e4b44a579a49 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55155 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-06-05mb/google/cherry: Initialize SPMRex-BC Chen
This patch adds support for SPM. This adds 43ms to the boot time. TEST=program counter of SPM is correct value after booting up. Signed-off-by: Dawei Chien <dawei.chien@mediatek.com> Signed-off-by: Edward-JW Yang <edward-jw.yang@mediatek.corp-partner.google.com> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I5f17f6d51fc9ad2d23c71c3c5cd29fdc777dc071 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55154 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-04Revert "src/mainboard: Add Star Labs labtop series"Tim Wawrzynczak
This reverts commit 2e665eb8daa2963c52092e694a5316dc544a23f5. Reason for revert: Was submitted too early and out-of-order. Change-Id: I119b7a81b849bbe3424d73d5fdf9b55481444686 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54971 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-04vboot: Add VB2_CONTEXT_EC_TRUSTEDDaisuke Nojiri
This patch makes coreboot set VB2_CONTEXT_EC_TRUSTED based on the EC"s boot mode. Vboot will check VB2_CONTEXT_EC_TRUSTED to determine whether it can enter recovery mode or not. BUG=b:180927027, b:187871195 BRANCH=none TEST=build Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Change-Id: I9fa09dd7ae5baa1efb4e1ed4f0fe9a6803167c93 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54099 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-06-04mb/google/brya: Remove I2C4 usage in devicetree.cbSubrata Banik
I2C4 is not used pn Brya hence make below changes: 1. Disable it in SerialIoI2cMode. 2. Remove I2C4 config in common_soc_config. TEST=Make sure FSP is not programming I2C4. Change-Id: I94c72b7fac9d8a001913b5faa2c0c8a3e8b701e9 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55170 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-06-04src/mainboard: Add Star Labs labtop seriesSean Rhodes
Add support for LabTop Mk III (kblr) and LabTop Mk IV (cml) Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Iffa6061b0e600880b0c93746f35b1731e4841e31 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55128 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-04ec: Add Star Labs ITE 8987E supportSean Rhodes
Support for Star Labs labtop series EC Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I1967f7c4a7e3cab714f22844bf36749e0c9652b6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52797 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-04soc/intel/alderlake: Add PMC ACPI interfaceTim Wawrzynczak
This ACPI interface is required by e.g., the intel/common/pcie/rtd3 driver, which is used by some alderlake boards. BUG=b:190080798 TEST=disassemble SSDT and find \_SB.PCI0.PMC.IPCS Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I59eae47e623587d35e394c9bff21481fcad2d6b0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55172 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-04soc: common: gpio: Add support for common GPIO driverTaniya Das
Add common gpio functionalities across qualcomm soc targets. This common gpio driver would allow the consumers to be able to configure gpio function, set/get gpio direction as input/output, configure the gpio as pull-up/pull-down, configure the gpio as an IRQ and also query the gpio irq status. The GPIO pin definition would be SoC specific. BUG=b:182963902 TEST=Validated on qualcomm sc7180 and sc7280 development board Signed-off-by: Taniya Das <tdas@codeaurora.org> Change-Id: Ia672130c6ca938d9284cae5071307637709480d1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55076 Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-04sc7280: Reserve wlan & wpss dram regions index order correctedRavi Kumar Bokka
BUG=b:182963902 TEST=Validated on qualcomm sc7280 developement board Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org> Change-Id: I8501e9ce52bb296bb42797d8b43fd38174b80550 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55102 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-06-04mb/siemens/mc_apl2: Disable unused I2C controllersWerner Zeh
Only I2C controller 3 is used on this mainboard. Disable all other controllers. Change-Id: Id06d98787a0574a5b3a8dc2e86858dfcc7154606 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55090 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-06-04mb/siemens/mc_apl{1,2,3,5,6}: Provide I2C timings for 400 kHzWerner Zeh
The I2C bus at which the external RTC is attached to is operated at standard speed (100 kHz) at coreboot runtime. The OS can choose to run it at fast speed since it uses its own driver and controller setup. Report additional bus timings for fast mode so that OS can do it right. Change-Id: I82e11e5dde8ad1047713f105c5a6d020eebf1ffd Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55089 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-04drivers/i2c/designware: Report I2C timings for additional bus speedsWerner Zeh
Since the OS provides its own driver for the I2C controller it can choose to use a bus speed other than the one used at coreboot runtime. In this case it would be good to provide a way how the needed bus timings are communicated to the OS, since these are very board-specific and there is no way that the OS can know them other than read the appropriate ACPI reported timings. This patch adds some code to report additional bus speed timings if there are some defined in the devicetree. Change-Id: If921e0613864660dc1bb8d7c1b30fb9db8ac655d Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55088 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-06-04mb/google/dedede/var/cret: Add new Goodix touchscreenDtrain Hsu
Add Goodix GT7996F touchscreen into devicetree for cret. BUG=b:180547935, b:188501391 BRANCH=dedede TEST=Built cret firmware and verified touchscreen function. Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I2a6f7c1e9900492937202c0bc6595674f1e79e5b Reviewed-on: https://review.coreboot.org/c/coreboot/+/54872 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-06-04src/intel/xeon_sp: add hardware error support (HEST)Rocky Phagura
This patch adds the ACPI hardware error source table (HEST) support. This involves a few different parts: (1) The ACPI HEST table which is filled with the appropriate fields (2) Reserved memory which is used by runtime SW to provide error information. OS will not accept a HEST table with this memory set to 0. The ASL code to enable APEI bit will be submitted in a separate patch. Tested on DeltaLake mainboard with following options enabled SOC_INTEL_XEON_RAS After boot to Linux, the following will show in dmesg: HEST: Table parsing has been initialized Change-Id: If76b2af153616182cc053ca878f30fe056e9c8bd Signed-off-by: Rocky Phagura <rphagura@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52090 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-06-04mb/google/brya: Add firmware configuration probing for audioSugnan Prabhu S
For all of the audio devices in overridetree.cb add the probe matches that will determine if the device should be enabled or not based on the selected audio daughter board type. AUDIO=MAX98357_ALC5682I_I2S: enable max98357, dmic1 and alc5682i AUDIO=MAX98373_ALC5682_SNDW: enable max98373, dmic2 and alc5682 BUG=b:188696010 TEST=test different audio devices based on fw_config value: > AUDIO=UNKNOWN ectool cbi set 6 0x00000000 4 2 > AUDIO=MAX98357_ALC5682I_I2S ectool cbi set 6 0x00000100 4 2 > AUDIO=MAX98373_ALC5682_SNDW ectool cbi set 6 0x00000200 4 2 Change-Id: I6f159442516830f9d304d78c83f070e4fcff4a37 Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54716 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-04mb/google/guybrush/var/guybrush: Reconfigure left speaker amplifierKarthikeyan Ramasubramanian
In order to resolve the I2C address conflict with another peripheral in the upcoming hardware build, left speaker amplifier I2C address is reconfigured. BUG=b:188539052 TEST=Build Guybrush mainboard. On Guybrush board ID 1, all the 3 speaker amplifiers are added to the ACPI table. \_SB.I2C2.D028: Realtek SPK AMP L at I2C: 03:28 \_SB.I2C2.D029: Realtek SPK AMP R at I2C: 03:29 \_SB.I2C2.D02A: Realtek SPK AMP L1 at I2C: 03:2a At the OS side, the concerned speaker amplifiers are probed and enumerated. localhost ~ # i2cdetect -y -r 2 0 1 2 3 4 5 6 7 8 9 a b c d e f 00: -- -- -- -- -- -- -- -- -- -- -- -- -- 10: -- -- -- -- -- -- -- -- -- -- UU -- -- -- -- -- 20: -- -- -- -- -- -- -- -- UU UU -- -- -- -- -- -- 30: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 40: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 50: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 60: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 70: -- -- -- -- -- -- -- -- Change-Id: I69a7e7dd65a459c2e5629ada1dea1f1660dd9990 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55028 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-06-04mb/google/dedede/var/blipper: Configure I2C times for touchpad/touchpanel/codecTao Xia
Configure I2C rise/fall time in device tree to ensure I2C CLK runs accurately at I2C_SPEED_FAST (<400 kHz). Measured I2C frequency changes are just as below after tuning: touchpad: 434kHz ---> 391kHz touchpanel: 439kHz ---> 382kHz audio codec RT5682: 445kHz ---> 385kHz BUG=b:187555396 BRANCH=dedede TEST=Build and check after tuning I2C clock is under 400 kHz Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com> Change-Id: I8438e37be49f8a74f53fd8460110dac1a3f06993 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54249 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-06-04mb/google/brya/brya0: Fix irq and CS lines for FPMCUTim Wawrzynczak
The entries in the ACPI tables for the fingerprint module's SPI configuration were incorrect. 1) The GPIO is routed to IOAPIC (and SCI), therefore in ACPI, it must be described by Interrupt(), not GpioInt() 2) The chip-select signal was selected as 1, not 0 `device spi 0/1 on` BUG=b:181635081 TEST=verified in kernel logs: localhost # ~ dmesg|egrep 'cros-ec-dev|cros-ec-spi' [ 4.569412] cros-ec-dev cros-ec-dev.1.auto: CrOS Fingerprint MCU detected [ 4.575303] cros-ec-spi spi-PRP0001:00: Chrome EC device registered Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I9ef6c99f011969fc444e0c12b806529cb82bba3d Reviewed-on: https://review.coreboot.org/c/coreboot/+/55147 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-04intel/common/block: Move mainboard api to tcss common blockDeepti Deshatty
As per the comments in CB:54090 mainboard api mainboard_tcss_get_port_info() is simplified and moved to tcss common block code. Signed-off-by: Deepti Deshatty <deepti.deshatty@intel.com> Change-Id: I7894363df4862f7cfe733d93e6160677fb8a9e31 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54733 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-06-04Revert "util/vboot_lib: Add description.md"Angel Pons
This reverts commit 255b6f8646903594fb728f8228908792bad766f0. No longer needed after commit dd01e0131a8ba901bedec48844502fe85663390a (Revert "util/lint: Add test for documentation in util dirs") has been submitted. Plus, `util/vboot_lib/description.md` gets deleted whenever one runs `make -C util/cbfstool clean`, which is rather annoying. Change-Id: Ic93da096b6186d1d2af12243a74ec597694960c4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55162 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-04util/cbfstool/linux_trampoline.h: Fix typo in commentAngel Pons
inlucde ---> include Change-Id: I38987119ddabb08c457c9a7c8aecb8025fe2d9d3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55161 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-04soc/mediatek/mt8195: add SPM loaderDawei Chien
This patch adds support for loading SPM firmware from CBFS to SPM SRAM. SPM needs its own firmware to enable SPM suspend/resume function which turns off several resources such as DRAM/mainpll/26M clk when linux system suspend. TEST=program counter of SPM is correct value after booting up. Change-Id: Ia0f9b9f86e44b293c1cc47213946304c64aea75e Signed-off-by: Dawei Chien <dawei.chien@mediatek.com> Signed-off-by: Edward-JW Yang <edward-jw.yang@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55140 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-04soc/mediatek: Extract spm_parse_firmware to commonRex-BC Chen
spm_parse_firmware can be shared by MT8192 and MT8195. TEST=emerge-asurada coreboot; Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I54d9672aa9ee9078ec9fe3fa4f2e9fe860a50636 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55139 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-04soc/intel/elkhartlake: Update FSP-S storage related configsLean Sheng Tan
Further add initial Silicon UPD storage settings: - SATA - SD card - eMMC Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: Id4145fcf156756a610b8a9a705d4ab99fe7b0bf8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55082 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2021-06-04soc/intel/elkhartlake: Update FSP-S UPD RP & USB related configsLean Sheng Tan
Further add initial Silicon UPD settings for: - PCIe root ports - USB Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: I60afb78a7997b8465dd6318f3abee28f95a65100 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55034 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-04mb/google/dedede/var/cret: Add new Elan touchscreenDtrain Hsu
Add Elan eKTH7D18 touchscreen into devicetree for cret. BUG=b:180547935, b:187484857 BRANCH=dedede TEST=Built cret firmware and verified touchscreen function. Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: Iab87ddfc7b46420439efa3e7e55c88ad4c27155d Reviewed-on: https://review.coreboot.org/c/coreboot/+/54868 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-06-04soc/intel/elkhartlake: Update FSP-S UPD configs for graphic & chipsetLean Sheng Tan
Further add initial silicon UPD settings for: - graphics & display - chipset lockdown - PAVP - legacy timer - PCH master gating control - HECI This CL also enables HECI 1 in devicetree.cb. Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: I657f44f8506640c23049614b2db9d1837e6d44ed Reviewed-on: https://review.coreboot.org/c/coreboot/+/54960 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2021-06-04mb/google/dedede/var/storo: Modify I2C times for touchpadZanxi Chen
Configure I2C rise/fall time in device tree to ensure I2C CLK runs accurately (380<frequency<400 kHz). Measured touchpad I2C frequency is 394 kHz BUG=b:189740533 BRANCH=dedede TEST=Build bios and make sure frequency meets specification. Change-Id: Ibc0504a5be6fe9237b8b30783c659a761d10561a Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55109 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-06-03mb/google/dedede/var/sasukette: Modify the touch pad I2C addressTao Xia
There are two touch pads that Sasukette used have the same I2C address. It will show "/dev/input/event4: SPPT2600:00 06CB:CE9D Touchpad" when the Synaptics touch pad is connected after running evtest under VT2. BUG=b:189520603 BRANCH=dedede TEST=It will show "/dev/input/event4: SYNA0A00:00 06CB:CE9D Touchpad" when the Synaptics touch pad is connected after running evtest under VT2. Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com> Change-Id: If0bd80baa27dfeb7bcb43f0ca4b02e1228e372a6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55035 Reviewed-by: zanxi chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-03mb/google/brya: Create primus variantScott Chao
Create the primus variant of the brya0 reference board by copying the template files to a new directory named for the variant. (Auto-generated by create_coreboot_variant.sh version 4.5.0) BUG=b:188272162 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_PRIMUS Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com> Change-Id: I26787f296793b281b7f1ee1a7d240006163c6015 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55132 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-03mb/google/brya: Add support for 2 new DRAM partsAmanda Huang
1) Hynix H9HCNNNCPMMLXR-NEE 2) Micron MT53E1G32D2NP-046 WT:B BUG=b:186616388, b:181736400 Change-Id: I56bfe8aa4f8d8aab2011fa8d17b3b2c8659658e3 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54951 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-03soc/intel/alderlake: Add new memory parts for ADL boardsAmanda Huang
Use currently global_lp4x_mem_parts.json.txt to regenerate SPD files for LP4x memory parts that can be used with ADL-based mainboards. BUG=b:186616388 Change-Id: I5e76a887f81d432adbcfc2f8956b44f4343db5c2 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54950 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-06-03util/spd_tools: Modify MT53E1G32D2NP-046 WT:B LPDDR4 configAmanda Huang
CB:52586 ("util/spd_tools: Add MT53E1G32D2NP-046 WT:B LPDDR4 config") incorrectly set ranks per channel to 1. However, MT53E1G32D2NP-046 WT:B part has 2 channels per die and 2 physical dies. Each channel in each die shares DQ-DQS lines with the channel in other die and uses separate CS lines. Thus, number of ranks per channel is 2. This change fixes the attribute ranksPerChannel for MT53E1G32D2NP-046 WT:B in LP4x global config by setting it to 2. BUG=b:186616388 Change-Id: Iba87754ca04c2e026a9cbc8ef07412b467140cba Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55000 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-06-03mb/google/brya: move MIPI camera setting into overridetreeScott Chao
In order to support no MIPI camera variant, move related configuration into variant folder. BUG=b:188272162 BRANCH=none TEST=build no MIPI camera variant without error Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com> Change-Id: I4e64d078a8e39732ad29443c3b09ca008a7e902f Reviewed-on: https://review.coreboot.org/c/coreboot/+/55134 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-06-03soc/mediatek: Initialize SSPMRex-BC Chen
Load SSPM firmware and boot up SSPM in ramstage. This adds 23ms to the boot time. TEST=Load SSPM blob ok, and we can see some logs of SSPM from AP. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Ia227ea9f7d58129068cb36ec2de7d9feb677006b Reviewed-on: https://review.coreboot.org/c/coreboot/+/55051 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-06-02soc/amd/picasso: remove warm reset flag codeFelix Held
Since the MCA(X) registers have defined values on the cold boot path, the is_warm_reset check can be dropped. Also the warm reset bit in the NCP_ERR register doesn't behave as the PPR [1] suggested; no matter if something was written to the register or the machine went through a warm reset cycle, the NCP_WARM_BOOT bit never got set. [1] checked with PPR for AMD Family 17h Models 11h,18h B1 (RV,PCO) #55570 Rev 3.15 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4e6df98ffd5d15ca204c9847a76c19c753726737 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55059 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-06-02cbfstool/linux_trampoline.S: Fix up the e820 tableArthur Heymans
The e820 type don't fully match the LB_TAG_MEMORY types, so change all unknown types to e820 to '2', reserved memory. TESTED with Linuxboot: e820 now shows the CBMEM region as reserved. Change-Id: Ie0e41c66e002919e41590327afe0f543e0037369 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55074 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Rocky Phagura Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-02mb/google/volteer/var/volet: Update gpio and devicetree settingsSheng-Liang Pan
Based on schematic and gpio table of volet, update gpio and devicetree settings for volet Proto. BUG=b:186334008 TEST=FW_NAME=volet emerge-volteer coreboot chromeos-bootimage Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: Ia0e9557e01ce1e7a49a3dddf6da3e4a29587a8b7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55113 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-02mb/google/volteer/var/volet: add volet memory configuration.Sheng-Liang Pan
volet use same memory configuration from Voxel, copy voxel setting to volet. BUG=b:186334008 TEST=FW_NAME=volet emerge-volteer coreboot chromeos-bootimage Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: I7e65b18f2ddae3d1ce02d9006153269697188f61 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55096 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-01mb/intel/adlrvp_m: Enable LTR for PCIEBernardo Perez Priego
BUG=none TEST=Use command $ lspci -vv LTR+ is listed on DevCtl2 Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com> Change-Id: If65d08a46b9e7304fbe4b92b7f1e6d4e08c599e7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54492 Reviewed-by: Ryan A Albazzaz <ryan.a.albazzaz@intel.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-01mb/google/brya: Enable WFCMeera Ravindranath
1. Add 1 port and 1 endpoint 2. Add support for OVTI8856 WFC is on I2C0 BUG=None BRANCH=None TEST=Build and boot brya Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com> Change-Id: Ic5e9c28f255bdf86a68ce80a4f853be4e7c7ccfe Reviewed-on: https://review.coreboot.org/c/coreboot/+/52013 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-01drivers/intel/mipi_camera: Add macros to increase code readabilityVarshit B Pandya
This will be used to pass information to driver through ACPI in devicetree. Example https://review.coreboot.org/c/coreboot/+/52013 register "clk_panel.clks[0].clknum" = "IMGCLKOUT_3" register "clk_panel.clks[0].freq" = "FREQ_19_2_MHZ" TEST=Add these macros in devicetree, build and check static.c for consistency Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.corp-partner.google.com> Change-Id: Ia4137e09c934bf06857ceedb933e616bed5070dd Reviewed-on: https://review.coreboot.org/c/coreboot/+/55097 Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-01soc/amd/cezanne/include/iomap: properly align definesFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I14647b3d88146602b96fc1dff2347a293bab0c26 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55100 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-06-01mainboards using soc/amd/picasso: use aliases for remaining PCIe devicesFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id2bdce5871f57e9edb17f89cba61b5c5ae018566 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55104 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-06-01mainboards using soc/amd/picasso: use aliases for PCIe devices on bus 0Felix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia6199c70163d32467abe5ba5da55c73ff62ba10f Reviewed-on: https://review.coreboot.org/c/coreboot/+/55103 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-06-01soc/amd/picasso: introduce and use chipset device treeFelix Held
The chipset devicetree only has the essential PCIe devices enabled that are needed for the SoC code to work. It also defines aliases for all PCIe devices that can be used to reference the devices in the mainboard- specific devicetrees and devicetree overrides. To make the change easier to review that part will be done in a follow-up patch. Despite missing in the PPR, device pci 18.7 exists on Picasso. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6b7c3fd32579a23539594672593a243172c161c7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50626 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-06-01tests: Add lib/cbmem_stage_cache-test test caseJakub Czapiga
Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: Ie6851b9473b225beb5ba51e26f44e21ea5919a64 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54916 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2021-06-01acpi: drop unused parameter from acpi_soc_fill_bertFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic354824468f016a7857c6990024ae87db6fd00bf Reviewed-on: https://review.coreboot.org/c/coreboot/+/55052 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Lance Zhao
2021-06-01util/cbfstool/Makefile: Check out vboot before trying to use itPatrick Georgi
Change-Id: Ie2044d73b97663f7816964c4d908a46570aafdbc Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55072 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Idwer Vollering <vidwer@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-06-01soc/mediatek: Move the SSPM driver to commonRex-BC Chen
The SSPM driver can be shared by MT8183, MT8192 and MT8195. TEST=emerge-{asurada, kukui} coreboot; Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: If9779853becb298eeeabb3dc6096bc474baae202 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55050 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-01Documentation/community: Add link to the OSF SlackArthur Heymans
We are also present on Slack so advertise that. Change-Id: I7d9887e524e47e6f42a5013e9f696881ef54a631 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55036 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-06-01Documentation/community: Add Discord to forumsPatrick Georgi
Change-Id: Ib1d866ecf041ddc4aaf508d290a3e31b9a108cf2 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55018 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2021-06-01configs: Update configs for OCP Delta Lake LinuxBoot payloadJohnny Lin
OCP Delta Lake is developed and validated against LinuxBoot payload. Need to put the respective binary blobs in site-local/deltalake to build the final coreboot image. Add LINUX_COMMAND_LINE for LinuxBoot payload kernel cmdline, CPU_UCODE_BINARIES for CPU microcode binary, CONSOLE_SERIAL_57600 is the serial baud rate used by OCP Delta Lake, DEFAULT_CONSOLE_LOGLEVEL_4 is for a faster boot time. Tested=On OCP Delta Lake it can boot up target CentOS 8 GNU/Linux OS. Change-Id: Ib494e4170a7ebb445d9e11df83c370b40a9e5194 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55058 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-01soc/intel/elkhartlake: Update FSP-S UPD LPSS related configsTan, Lean Sheng
Add Silicon upd settings for LPSS (GSPI/UART/I2C). Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: Ib0c3cd1d37ff9892d09d6d86ac50e230549c7e53 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54959 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2021-06-01cpu/intel/car/romstage.c: Drop unused function argumentArthur Heymans
This is a leftover when migrating to C_ENV_BOOTBLOCK Change-Id: Ibc610cd15448632dc13d87094853d9b981e2679b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55062 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-05-31soc/amd/cezanne: Add pre-FSPM call to the mainboardMartin Roth
The Guybrush platform needs to set up some GPIOs immediately before the FSP-M runs. Add a platform specific call. This will be used in a follow-on commit. BUG=b:184796302, b:184598323 TEST=Build Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I37d2625ff426347852e98a9a50f15368e0213449 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54638 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-30soc/amd/common/block/espi: Explicitly assert PLTRST#Raul E Rangel
PLTRST# is currently asserted and latched when eSPI_RST# gets asserted. If eSPI_RST# isn't used on a platform or it doesn't properly assert in all cases, then PLTRST# will never be asserted. This could result in the AP and EC being out of sync. BUG=b:188188172, b:188935533 TEST=Warm reset guybrush with partial #22 rework. Verify that peripheral channel is correctly reset. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I20d12edf3efc6100096e24aa8d1aec76bbde264f Reviewed-on: https://review.coreboot.org/c/coreboot/+/54884 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-05-30tests/Makefile.inc: Move generated headers to corresponding build dirJakub Czapiga
Test-local config override headers were generated to paths missing /tests/ infix, thus creating divergent tree in build output directory. This patch fixes it moving generated config headers to the test-local build directory. Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: Ic5f3ba287ba3e9f5897cbaac64e88c2809f52d73 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54917 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2021-05-30drivers/pc80/mc146818rtc: Check date and time for sanityWerner Zeh
There are cases where the RTC_VRT bit in register D stays set after a power failure while the real date and time registers can contain rubbish values (can happen when RTC is not buffered). If we do not detect this invalid date and/or time here and keep it, Linux will use these bad values for the initial timekeeper init. This in turn can lead to dates before 1970 in user land which can break a lot assumptions. To fix this, check date and time sanity when the RTC is initialized and reset the values if needed. Change-Id: I5bc600c78bab50c70372600347f63156df127012 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54914 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-30lib/rtc: Add sanity check for time and dateWerner Zeh
Add a function to check sanity of a given RTC date and time. Invalid values in terms of overrun ranges of the registers can lead to strange issues in the OS. Change-Id: I0a381d445c894eee4f82b50fe86dad22cc587605 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54913 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-05-30mb/siemens/mc_apl{1,2,3,5,6}: Disable ACPI-support for RX6110Werner Zeh
Already released Linux versions did not have the needed ACPI-extension in the RTC driver. If the ACPI-Support is enabled for the RTC, this older Linux will not be able to use this device as it will be claimed by the PNP-drivers. As there is no way to avoid that an older Linux kernel meets a newer coreboot in the field, we need to disable the ACPI support for the RTC for the mc_apl-based mainboards. Change-Id: I9f9939ba3234dc3654a4ef8a498649453941ebdf Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55004 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-30drivers/i2c/rx6110sa: Add a Kconfig switch to disable ACPI supportWerner Zeh
In commit b64db833d6 a basic ACPI support was added to the driver. With this support an SSDT-entry is created for this RTC and it is now visible to the OS via ACPI. In Linux the PNP-devices, which are reported over ACPI, are scanned rather early and if the entry is found, the device is claimed even if there is no driver available yet. In this case, when the native RTC-driver without ACPI-support is loaded and tries to register this device, the RTC is already blocked by the PNP-drivers and cannot be used anymore. This leads to a non-usable RTC on kernels where the needed ACPI-extension is not yet merged into the RTC driver. This patch provides a way to disable the ACPI-support for the RTC if needed. Change-Id: Ic65794d409d13a78d17275c86ec14ee6f04cd2a6 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55003 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-30cpu/x86/smm: Fix u32 type mismatch in print statementPaul Menzel
The 64-bit compiler x86_64-linux-gnu-gcc-10 aborts the build with the format warning below: CC ramstage/cpu/x86/smm/smm_module_loader.o src/cpu/x86/smm/smm_module_loader.c:415:42: error: format '%lx' expects argument of type 'long unsigned int', but argument 4 has type 'u32' {aka 'unsigned int'} [-Werror=format=] 415 | printk(BIOS_DEBUG, "%s: stack_end = 0x%lx\n", | ~~^ | | | long unsigned int | %x 416 | __func__, stub_params->stack_top - total_stack_size); | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | | | u32 {aka unsigned int} The size of `size_t` differs between i386-elf (32-bit) and x86_64-elf/x86_64-linux-gnu (64-bit). Unfortunately, coreboot hardcodes src/include/inttypes.h:#define PRIx32 "x" so `PRIx32` cannot be used. There use `z` as length modifier, as size_t should be always big enough to hold the value. Found-by: x86_64-linux-gnu-gcc-10 (Debian 10.2.1-6) 10.2.1 20210110 Fixes: afb7a814 ("cpu/x86/smm: Introduce SMM module loader version 2") Change-Id: Ib504bc5e5b19f62d4702b7f485522a2ee3d26685 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54343 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-05-30cpu/x86/smm: Fix size_t type mismatch in print statementPaul Menzel
The 64-bit compiler x86_64-linux-gnu-gcc-10 aborts the build with the format warning below: CC ramstage/cpu/x86/smm/smm_module_loader.o src/cpu/x86/smm/smm_module_loader.c: In function 'smm_module_setup_stub': src/cpu/x86/smm/smm_module_loader.c:360:70: error: format '%lx' expects argument of type 'long unsigned int', but argument 5 has type 'unsigned int' [-Werror=format=] 360 | printk(BIOS_ERR, "%s: state save size: %zx : smm_entry_offset -> %lx\n", | ~~^ | | | long unsigned int | %x As `size_t` is defined as `long unsigned int` in i386-elf (32-bit), the length modifier `l` matches there. With x86_64-elf/x86_64-linux-gnu (64-bit) and `-m32` `size_t` is defined as `unsigned int` resulting in a type mismatch. So, use the correct length modifier `z` for the type `size_t`. Found-by: x86_64-linux-gnu-gcc-10 (Debian 10.2.1-6) 10.2.1 20210110 Fixes: afb7a814 ("cpu/x86/smm: Introduce SMM module loader version 2") Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Change-Id: I4172e0f4dc40437250da89b7720a5c1e5fbab709 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54342 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2021-05-30cpu/x86/smm: Fix uintptr_t type mismatches in print statementsPaul Menzel
The 64-bit compiler x86_64-linux-gnu-gcc-10 aborts the build with the format warning below: CC ramstage/cpu/x86/smm/smm_module_loader.o src/cpu/x86/smm/smm_module_loader.c: In function 'smm_create_map': src/cpu/x86/smm/smm_module_loader.c:146:19: error: format '%zx' expects argument of type 'size_t', but argument 3 has type 'uintptr_t' {aka 'long unsigned int'} [-Werror=format=] 146 | " smbase %zx entry %zx\n", | ~~^ | | | unsigned int | %lx 147 | cpus[i].smbase, cpus[i].entry); | ~~~~~~~~~~~~~~ | | | uintptr_t {aka long unsigned int} In coreboot `uintptr_t` is defined in `src/include/stdint.h`: typedef unsigned long uintptr_t; As `size_t` is defined as `long unsigned int` in i386-elf (32-bit), the length modifier `z` matches there. With x86_64-elf/x86_64-linux-gnu (64-bit) and `-m32` `size_t` is defined as `unsigned int` resulting in a type mismatch. Normally, `PRIxPTR` would need to be used as a length modifier, but as coreboot always defines `uintptr_t` to `unsigned long` (and in `src/include/inttypes.h` also defines `PRIxPTR` as `"lx"`), use the length modifier `l` to make the code more readable. Found-by: x86_64-linux-gnu-gcc-10 (Debian 10.2.1-6) 10.2.1 20210110 Fixes: afb7a814 ("cpu/x86/smm: Introduce SMM module loader version 2") Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Change-Id: I32bff397c8a033fe34390e6c1a7dfe773707a4e8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54341 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2021-05-30mb/intel/adlrvp_m: add ec device entry to devicetreeBora Guvendik
TEST=Boot to OS and verify acpi tables. Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: I3c78ac44afa3515acef9ea2d59f22f95e6b45e90 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54490 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: John Zhao <john.zhao@intel.corp-partner.google.com> Reviewed-by: John Zhao <john.zhao@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-30soc/intel/alderlake: Add placeholder SPD fileTim Wawrzynczak
Change-Id: I38eb4bb684c511fff5ae148091c066682e9c35cb Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55021 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-05-30Update vboot submodule to upstream mainDaisuke Nojiri
Updating from commit id e681c37: change node locked version expectations to commit id b38e3a63: cros_ec: Use boot mode to check if EC can be trusted Change-Id: Id6de185af85a61a3843b302fef6fa0d4d3c17aef Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55026 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-30mb/siemens/mc_apl1: Move gpio.c from baseboard to mc_apl1Mario Scheithauer
Variant mc_apl1 is the only one that uses gpio.c from baseboard. For this reason, gpio.c is moved from baseboard to mc_apl1. Change-Id: Ie2ba8181dfe887df9abbbd648f2cbdc6ffc65530 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54945 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-05-30mb/siemens/{mc_apl2,...,mc_apl6}: Do early UART pad configurationMario Scheithauer
With commit 405f229689 (soc/intel/*: drop UART pad configuration from common code) the UART pad configuration was dropped from common SoC code. Through a second commit 5ff17ed393 (mb/siemens/mc_apl1: do UART pad configuration at board-level) the UART pad configuration was made for mc_apl1 baseboard. This change is also needed for all other mc_apl boards. Change-Id: If78726d9b141e4e7580cca3267f49c1a5b95d7fa Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54911 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-05-30arch/x86/acpi_bert_storage: change return type of bert_errors_presentFelix Held
The return value is a boolean, so use the bool type. Also add the types.h header to have the bool type defined. Also change type of bert_region_broken static variable to bool. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I13d6472deeb26ba92d257761df069e32d9b2e5d4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55023 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-05-30soc/intel/elkhartlake: Update FADT tableTan, Lean Sheng
Update FADT table per relevant PM settings: Fix PM Timer block access size and disable C2 and C3 states for the CPU. Further on, set the century byte offset in FADT to point to the common location in CMOS. Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: I72a57bf8ec61c3eabc4522c2695ae4b16979f188 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54958 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-30soc/intel/elkhartlake: Update FSP-M UPD related configsTan, Lean Sheng
Upload the FSP-M UPD configs. This CL also updated the chip.h and devicetree.cb with the relevant variables and configs. This CL also updated the GPIO related settings (PMC & SD card) in devicetree.cb. Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: If6321064b37535b390cf3dd7c41a719c598a0cd7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54892 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2021-05-30Apply more uses for Kconfig TPMKyösti Mälkki
Change-Id: I54b296563940cd46fe9da9fe789b746f2fc1987d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55016 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-05-29drivers/intel/fsp2_0: Make fsp_temp_ram_exit() function staticSubrata Banik
fsp_temp_ram_exit() function is only getting called by late_car_teardown() function inside temp_ram_exit.c file. Hence, make function as static and removed from include/fsp/api.h. Change-Id: I2239400e475482bc21f771d41a5ac524222d40fc Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55025 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-05-28mb/kontron/mal10: Use mainboard_ops driver for GPIO configurationFelix Singer
`mainboard_silicon_init_params()` should *only* be used for configuring FSP options which can not be configured anywhere else. Therefore, use the init phase from the mainboard_ops driver for configuring the GPIOs. Signed-off-by: Felix Singer <felixsinger@posteo.net> Change-Id: Ia01091938ac113cb5cf95f046609a1ebf3620806 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48143 Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-28vendorcode/intel/fsp: Update to include post PRQ UPDs for Tiger LakeSrinidhi N Kaushik
Update FSP headers for Tiger Lake platform generated based on FSP version 4133 to include post PRQ UPDs. BUG=b:188452018 BRANCH=none TEST=build voxel Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: I493391294391c1222a1aa5fdb86baad968abf7a6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54811 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-28arch/x86/timestamp.inc: Remove unused fileArthur Heymans
This is a romcc compiled bootblock leftover. Change-Id: I8d4f8bcdac7e15d60540157e9d2ac98603320977 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55007 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-28mb/google/volteer/var/collis: Update DPTF parametersFrankChu
Update the first version DPTF parameters received from the thermal team. BUG=b:188936764 TEST=emerge-volteer coreboot chromeos-bootimage Cq-Depend: chrome-internal:3851737 Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com> Change-Id: Id14b1d0bdd48c65eafbdd2e80b4611c86781be00 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54858 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-05-28mb/google/dedede: Update Storo setting for PEN detection.Zanxi Chen
Update devicetree and gpio driving of storo that enable stylus Updates the GPIO configuration for GPP_C12 to PAD_CFG_GPI_GPIO_DRIVER and device tree entry for PENH device to use WAKEUP_ROUTE_GPIO_IRQ. BUG=b:188519508,b:188365033 BRANCH=dedede TEST=build bios and the pen behavior can be detected. Change-Id: I2ffc969569b3ca29ba76326140f958a9707199f7 Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54762 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-28mb/amd/bilby,cereme,mandolin: change PSPP policy to balancedFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I7571ed92b3c3fa79581e2c7342960ca31451af1f Reviewed-on: https://review.coreboot.org/c/coreboot/+/54935 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-05-28Documentation: Fix up toctreePatrick Georgi
Some files weren't properly hooked up, making Sphinx complain. Change-Id: If959fa63d4ddbc3916c49c5ad6602e76b12a7e60 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55020 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-14 09:34:05 +0000