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Put the FMAP FMAP region right above the coreboot CBFS region.
The other regions like RW_MRC_CACHE and CONSOLE often have alignment
requirements so it makes sense to put those on top. This also
simplifies the code the generate the default fmap a little.
Change-Id: I24fa6c89ecf85fb9002c0357f14aa970ee51b1df
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30419
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change enables I2C bus 2, 3 and 4 in devicetree and configures
GPIO pads for the same. It also configures pads for I2C5 as
no-connect.
BUG=b:123711244
TEST=Verified that i2c shows up in "i2cdetect -l" after booting to OS.
Change-Id: Ib4714a670d73228332115415e4393f82802c6475
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/31237
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Current coreboot size is not adequate for adding new features.
Note for cros: This change is for merge to ToT only and should not be
cherry-picked into reef's firmware branch.
BUG=chromium:903833
TEST=emerge-reef coreboot
Change-Id: Ie7a25c4638c474e81fb34b57de0dfc1bf393ea67
Signed-off-by: Mathew King <mathewk@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31230
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Add maximum width and height options and set the default to 2560x1600
(WQXGA). The framebuffer will be scaled up to the displays' native
resolutions. So this should help with tiny fonts on high-DPI displays.
For laptops, reasonable defaults can be set at the mainboard level.
Change-Id: I47fba063629260c3a2854caf7a73f1a1e933d063
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/30585
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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We generate a $(obj)/cb-config.ads once and copy it per stage that uses
it to $(obj)/<stage>/cb-config.ads (to simplify the gnat-bind step). The
Ada package is called `CB.Config`. As there was no `CB` package yet, add
that too.
Change-Id: I963a6517ef4bcf84f2c8e9ae8d24a0d6b971d2b0
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/30584
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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- improve descriptions of Purism and ChromeOS hardware
- add entry for Libretrend Librebox
- improve description of Mr Chromebox and John Lewis'
3rd party ChromeOS firmware offerings
Change-Id: I66bd1a3701091e499d88738a7c06126de66e58ff
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31252
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
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This moves a lot of the common romstage boilerplate code to a common
location, while adding a few mainboard specific hooks.
Another difference is that the settings for enable_igd and enable_peg
are now based on the static devicetree settings.
Change-Id: I30ef7f6962aabde78b5c40e0b53bb85e01c254c1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/31190
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Some settings don't make sense like specifying input/output on native
ports or high/low on input ports.
Change-Id: Ib37837b9cdb8bb05e2523e0c43cc71fe4fbf243b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/31187
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I2057bf66435fd9113cdb1eef4c273f66b07a5a79
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/31186
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: I1e9a165b722006557557058a14e9f5dac78d4538
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/31189
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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his either sets unwanted or unnecessary settings.
Also this RCBA replay did not even originate from the T400 as this
code was copied from the Thinkpad x200 code on which this replay was
already removed in 7bcd062 'mb/lenovo/x200: Remove RCBA replay'
Change-Id: Iac6846d43395e342897e03c1ad31387638bcac64
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/31188
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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We already had such a page on the wiki, but it's outdated and the wiki
is supposed to go the way of the dodo anyway.
This is a fresh start to make sure that all ideas we're coming up with
are still current and that there are mentors willing to support them.
Change-Id: Idd68f845930bd37a2293969b9a153cf584d6d15f
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/30972
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch ensures to select chromeos kconfig only for required
CFL-U and WHL-U RVPs supported by Intel client team.
TEST=Ensure CONFIG_GBB_FLAG_FORCE_MANUAL_RECOVERY is only selected
for CFL-U and WHL-U boards.
Change-Id: Ib61409402a948f8d5f91130e200c45320ea13d3d
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/31214
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Get some content on the documentation site's front page.
Change-Id: I7f36234ef783e041a44590858bb75a69b96ee668
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/31127
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Neither payloads nor distributors are an integral part of the coreboot
source tree, but they're very important parts of the coreboot
ecosystems, so add some descriptions.
Change-Id: Id64744c252b6b78c4811fbded48c441ef486ad94
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/31180
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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It's what the doc.coreboot.org docker container is running and when
using its livehtml feature, it listens at localhost, which isn't always
desirable.
With `docker run -e SPHINXOPTS="-H $localip" ...` it now listens at
localip, which is more flexible.
Change-Id: Ia0614e57458c32169f6d614783366025e9c814b3
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/31128
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Select the appropriate system type for the different variants of
the Sarien board.
This will allow the Arcada variant to use the tablet mode feature
of the Intel Virtual Button driver.
Change-Id: I8a829aab012256ec196c8ec0fa298fd2bc77f2e1
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/31207
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Add an ACPI device that is compatible with the Intel Virtual
Button kernel driver for reporting tablet mode state and various
virtual button events that may come from the EC.
This driver is used in Windows and in the Linux kernel at
drivers/platform/x86/intel-vbtn.c
Because of a check in the kernel driver it expects the board to
define the SMBIOS enclosure type as convertible for the check at
driver load time for tablet/laptop and dock/undock to work.
The virtual tablet mode button will proxy the tablet mode state
sent from the Sensor Hub to a SW_TABLET_MODE event in the kernel.
The virtual power button is used during S0ix for the EC to wake
the system with an SCI. There are separate press and release
events which are sent for completeness, although the kernel driver
will ignore the release event.
BUG=b:73137291
TEST=Test that the power button can wake the system from S0ix.
Also verify that the device is reported as laptop mode at boot.
Change-Id: I0d5dc985a3cfb1d01ff164c4e67f17e6b1cdd619
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/31208
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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These are more common system types and in some cases it is important
to know when a device is a convertible or a tablet or detachable
instead of just a laptop.
This change will select the appropriate SMBIOS enclosure type based
on the selected system type.
This is important for the Intel Virtual Button driver as it does a
check on the SMBIOS enclosure type and only enables the tablet mode
events if it is set to convertible:
https://patchwork.kernel.org/patch/10236253/
Change-Id: I148ec2329a1dd38ad55c60ba277a514c66376fcc
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/31206
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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After CL:31122, we can finally define a memory type specific for BL31,
to make sure BL31 is not loaded on other reserved area.
Change-Id: Idbd9a7fe4b12af23de1519892936d8d88a000e2c
Signed-off-by: Ting Shen <phoenixshen@google.com>
Reviewed-on: https://review.coreboot.org/c/31123
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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The ACPI spec has an asl example for _PLD in the form:
Name (_PLD, Package (0x01) { ToPLD (PLD_Revision = 0x2) })
When I ported this to acpigen and diffed the results I noticed that
the binary blob was no longer provided within a package. The ACPI
spec (section 6.1.8 in version 6.2) defines _PLD as "a variable-length
Package containing a list of Buffers". This commit changes
acpigen_write_pld to use a package (the one existing caller I found
isn't wrapping the result in a package so it doesn't look like
it was intended for the callers of acpigen_write_pld to be responsible
for using a package.
BUG=none
BRANCH=none
TEST=Verified that after this change a package is use and the result
of acpigen matches what was used in the original asl.
Change-Id: Ie2db63c976100109bfe976553e52565fb2d2d9df
Signed-off-by: Matt Delco <delco@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31162
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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If an acpi_dp table has children but no properties then acpi_dp_write()
will write out a properties UUID and package that contains no properties.
The existing function will avoid writing out a UUID and empty package
when no children exist, but it seems to assume that properties will
always be used. With this change properties are handled in a manner
akin to children so that a UUID and package are only written if
properties exist.
BUG=none
BRANCH=none
TEST=Confirmed that prior to this change a UUID and empty package was
present for a device that had children but no properties. Verified that
after this change the UUID and empty package are no longer present but
the child UUID and package are still present.
Change-Id: I6f5597713a1e91ca26b409f36b3ff9eb90a010af
Signed-off-by: Matt Delco <delco@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31161
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This change adds keyboard backlight feature for Hatch platform.
BUG=b:122799544
BRANCH=none
TEST=keyboard backlight works when EC reports correct info.
Change-Id: I29273122f061e0e442f6629351ef3670535c0507
Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/31175
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The allocation is not required before romstage,
so it can be just another CAR_GLOBAL instead of
polluting the linker script.
Change-Id: I0738a655f6cc924fbed92ea630f85406e3f58c0b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31191
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The default state of the HOSTSW_OWN register in the PCH is zero, which
configures GPIO pins for ACPI ownership. The board variabt GPIO tables
can request specific pins to be configured for GPIO driver ownership.
This change sets the HOSTSW_OWN ownership bit when requested and
explicitly clears the ownership bit if not requested.
BUG=b:120884290
BRANCH=none
TEST=Build coreboot on sarien. Verified UEFI to coreboot transition
boots successfully.
Change-Id: Ia82539dbbbc7cf5dfb9223902d563cafec1a73e5
Signed-off-by: Keith Short <keithshort@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31209
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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By APL BIOS Spec, we must not do this on warm boots.
The TODO comment seems stale and copied over. So the actual
requirements for SGX are unknown and we add a guard for that
case.
Change-Id: I09b4a2fe22267d7318951aac20a3ea566403492e
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/31200
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Idfe93e454cc0ce0d8e06e23beaddee2f11f5eedd
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/31199
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This reconfigures the GPP_D1 GPIO pin as a no-connect. It really
doesn't go anywhere today or on previous revs of the board.
BUG=b:110614620
BRANCH=none
TEST=atlas still boots
Change-Id: Iea53cf909f8f060c4e0f14e8b4ad579b838b7caa
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31210
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This reverts commit 7696290004b6490c7ef8027d7ddf67b163e7dad8.
We're seeing trackpad problems on some units with the I2C bus running
at 1MHz but not at 400KHz. So, revert back to 400KHz until we
understand how to make 1MHz operation more robust.
BUG=b:123650686
Change-Id: Ifb06afece9eee0c153240d35e6c3001f5b74f310
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31212
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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The default value for Chrome OS HWID should be different.
Calculated as HWID v1.
BUG=b:123336677
BRANCH=kukui
TEST=build and boots properly.
Change-Id: I39c640562c1c3b117292b8abacd36a4a9c2fa6c6
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31088
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: You-Cheng Syu <youcheng@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Use unsigned long to prevent sign overflow.
Fixes wrong MTRRs settings on x86_64 romstage.
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Change-Id: I71b61a45becc17bf60a619e4131864c82a16b0d1
Reviewed-on: https://review.coreboot.org/c/30502
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Use memory map from fw_cfg e820 map to find cbmem_top in romstage to
avoid conflicts with CMOS option table. Keep qemu_gwt_memory_size() as
fallback.
Change-Id: I6465085020125fc790257f09eb157030c6ceabcb
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/30850
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Change-Id: I98f1c97e3ca33a12620cdd073c76fd4e271f1fcc
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/30849
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Qemu provides e820 table at fw_cfg interface. Add functions to access it.
Change-Id: I547bc7fef09999baa28149a6325cbca91e31e99b
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/30848
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Remove memory mapped copy of the file list to use it also in romstage.
fw_cfg_find_file searches directly for the file on data port.
Change-Id: Ie97ed3f0c98a5bb18a35ab0eaf8c4777a53e5779
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/30847
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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These boards need a working VTD therefore enable this feature.
Change-Id: I74c64bf1bd66188c4c32b85c66683dafd0e1fd38
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/31195
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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The FSP has a parameter to enable or disable the VTD feature
(Intel's Virtualization Technology for Directed I/O). In current header
files for FSP-S (Apollo Lake and Gemini Lake) this parameter is set to
disabled per default. Therefore, if the FSP was not modified via BCT,
this feature is most likely disabled on all mainboards.
Add a chip parameter so that VTD can be enabled on mainboard level in
devicetree and therefore this feature can be activated if needed.
Change-Id: Ic0bfcf1719e1ccc678a932bf3d38c6dbce3556bc
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/31194
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change enables exporting the reset GPIO for CNVi Bluetooth module to
the kernel for use in an rf-kill operation.
BUG=b:123296264
BRANCH=octopus
TEST=Boots to ChromeOS. Checked the SSDT table to ensure that the reset
gpio is exported under the device \_SB_.PCI0.XHCI.RHUB.HS09. Ensured
that the kernel btusb driver is able to find the exported GPIO in the
devices with CNVi BT module.
Change-Id: I10f28bfe705da5104d709ae2ed91a8ae003fa639
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/31183
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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GLK has a dedicated USB2 port that is used specifically for CNVi
BT. This requires that the ACPI tables define an additional USB 2 port
which results in _ADR for USB 3 ports being different for GLK than
APL.
This change splits the ports in xhci.asl into APL and GLK specific
ports.asl and selects the appropriate file based on
CONFIG_SOC_INTEL_GLK. It also adds support for returning HS09 for GLK
if ACPI name is requested for that port.
BUG=b:123670712
BRANCH=octopus
TEST=Verified that generated DSDT for octopus (GLK) includes HS09 and
for reef (APL) does not include HS09 definition.
Change-Id: I2d3d3690ec9ea1f6e35c38c3b3cbb82e961b7950
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/31172
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This implementation adds support to create ACPI package for USB port
capability (_UPC) and physical location of device (_PLD) for USB2 port 10.
BUG:b:123375275
TEST:Verify _UPC and _PLD ACPI packages gets published for USB2 Port 10
in SSDT and BT is functional in discrete and integrated mode.
Change-Id: Ifeab24505a700e8e4677be20074c7d0400769cec
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/31197
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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AGESA doesn't detect invalid NV data during AmdInitResume(). In
cases where the data has been erased, or cannot be found, reboot
the system. Otherwise the user will experience a hang when cbmem
isn't recovered and the postcar frame cannot be initialized.
BUG=b:122725586
TEST=Write S3 NV save data with 0xff and force reboot
Change-Id: Ib3cf2515f300decd3de198f7741660d95ee4c744
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31160
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Add a separate ACPI device for the Wilco EC event interface so that the
OS drivers can bind to it separately. Since the event handling is all
done with ACPI and not mailbox calls this will be implemented as a
standard acpi_driver in the kernel.
BUG=b:119046283
TEST=veriy device exists in DSDT
Change-Id: I5259a926fb6d5faea835bcdefa12f0184c5adf4a
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/31204
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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1) In the EC _REG method set the flag indicating S0ix support in the OS.
2) Add a function that can be called by the LPI _DSM method to indicate
to the EC that the OS is entering or exiting S0ix.
BUG=b:73137291
Change-Id: Iddc33a08542a6657694c47a9fda1b02dd39d89f7
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/31094
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Shaunak Saha <shaunak.saha@intel.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Disable xHCI by default if USE_BLOBS option has not been selected.
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: I1c3f0ff49fbe3db3ef095d99055f75d65cd6f661
Reviewed-on: https://review.coreboot.org/c/31216
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Register 0x2a [Bit 1] is a PIN89, PIN90 function select for i2c
Change-Id: I9231a68ec7e9a3130a6b6975544bf89ab09cb3e6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/31185
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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This patch removes duplicate selects of same SOC_INTEL_CANNONLAKE_MEMCFG_INIT
from various CFL/WHL SoC based boards to include cnl_memcfg_init.c file
and include the cnl_memcfg_init.c file by default in CNL SoC Makefile.inc.
Change-Id: Ib21ea305871dc859e7db0720c18a9479100346c3
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/31134
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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The structure is placed inside CBMEM, one should
use types with fixed size. Seems we prefer to
prepare for 64-bit builds even for MMIO pointers.
Change-Id: I60382664a53650b225abc1f77c87ed4e121d429e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31182
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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We need sizeof(struct ehci_dbg_info) of 88 but only
reserved 64 bytes. If usbdebug_hw_init() was called
late in romstage, for some builds it would corrupt
CAR_GLOBALs like console_inited variable and stop
logging anything.
Also change pointer initialisation such that
glob_dbg_info will hit garbage collection for
PRE_RAM stages.
Change-Id: Ib49fca781e55619179aa8888e2d859560e050876
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Also show hart id in trap information for easier debugging.
Change-Id: I20acf86e1af111600c158295ae03b2167838d127
Signed-off-by: Philipp Hug <philipp@hug.cx>
Reviewed-on: https://review.coreboot.org/c/31201
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: ron minnich <rminnich@gmail.com>
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1. Simplify payload code and convert it to C
2. Save the FDT pointer to HLS (hart-local storage).
3. Don't use mscratch to pass FDT pointer as it is used for exception handling.
Change-Id: I32bf2a99e07a65358a7f19b899259f0816eb45e8
Signed-off-by: Xiang Wang <wxjstz@126.com>
Signed-off-by: Philipp Hug <philipp@hug.cx>
Reviewed-on: https://review.coreboot.org/c/31179
Reviewed-by: ron minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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It has 2x 10GbE XGMII and 1x i210IT on PCIe, but no GBE.
Change-Id: I641c336350a0b05f3db7603cc7f6281ff3b0c388
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/31198
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
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This patch ensures to enable IFD GBE region only for required
CFL RVP8 and 11 supported by Intel IOTG team.
TEST=Ensure CONFIG_MAINBOARD_USES_IFD_GBE_REGION is not selected
for CFL-U and WHL-U boards
Change-Id: If3fcd23c32f9afd2004fb176c0324f089f2ee412
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/31192
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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Have the generated Chrome OS ACPI GPIO table provide the ACPI GPIO
pin number instead of the raw GPIO number when possible.
This is necessary if the OS uses a different numbering for GPIOs
that are reported in ACPI than the actual underlying GPIO number.
For example, if the SOC OS driver declares more pins in an ACPI GPIO
bank than there are actual pins in the hardware it will have gaps in
the number space.
This is a reworked version of 6217e9beff16d805ca833e79a2931bcdb3d02a44
which does not try to convert CROS_GPIO_VIRTUAL.
BUG=b:120686247
TEST=pass firmware_WriteProtect test on Sarien
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Change-Id: I3ad5099b7f2f871c7e516988f60a54eb2a75bef7
Reviewed-on: https://review.coreboot.org/c/31080
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Datasheets describe the used command as 'I2C Read' but adding the
word 'eeprom' in between should avoid further confusion with other
block commands.
Followups will add a symmetrical pair of commands i2c_block_read()
and i2c_block_write() that operate via I2C_EN bit and have a 32
byte size restriction on block transfers. For some hardware revision
these block commands are available, while 'I2C Read' was not.
Change-Id: I4494ab2985afc7f737ddacc8d706a5d5395e35cf
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31151
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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BUG=b:123540469
BRANCH=None
TEST=None
Change-Id: I713e6ad70efdd152895afa45aee44a5b53a8136b
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/31157
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Convert vboot_platform_prepare_reboot() to call a function in
soc//stoneyridge. A subsequent patch will add another call to
the new function, and this change removes any inference of a
dependency on vboot.
BUG=b:122725586
Change-Id: I634fcd030e206c790bda697a3dbef4e8cc21b3a8
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31159
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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The coreboot table entry containing the memory entries can have
fields unnaturally aligned in memory. Therefore one needs to perform
an aligned_memcpy() so that it doesn't cause faults on certain
architectures that assume naturally aligned accesses.
BUG=chromium:925961
Change-Id: I28365b204962ac89d65d046076d862b6f9374c06
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31181
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Manoj Gupta <manojgupta@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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TEST=Dump SSDT entries to verify _CST between S0ix enable and disable.
>> iasl -d SSDT # to generate SSDT.dsl
Change-Id: I82d8bf9d143263a80a544f6e11186a3bc9c41052
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/31153
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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TEST=Dump SSDT entries to verify _CST between S0ix enable and disable.
Change-Id: I25e8f8c13bb91c2645e8e9fdfdf9ba4d7022f1b1
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/31154
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
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Enable ASPM L1.2 support for embedded realtek card reader, after change
the power consumption for SD controller from 5mW to less than 2mW.
BUG=N/A
TEST=Build and boot up on Arcada platform, check the PCI configuration
on pcie root port offset 0x208 is 0x0f, and offset 0x168 on card reader
is also 0x0f.
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I08d85ee332ceee8ed85cd816bc3e6c895528fdb0
Reviewed-on: https://review.coreboot.org/c/31145
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Roy Mingi Park <roy.mingi.park@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Enable USB ACPI driver for octopus boards and add bluetooth USB ACPI
configuration in devicetree. This change enables exporting the bluetooth
reset GPIO to the kernel for use in an rf-kill operation.
BUG=b:123296264
BRANCH=octopus
TEST=Boots to ChromeOS
Change-Id: Ie40f1ad70f21a6fd398ce23d060e0c588ba6ce41
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/31130
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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XHCI is currently named as XHC1. This leads to namespace lookup error in
the kernel when children USB ACPI devices are added under the scope of
XHCI device.
BUG=b:123296264
BRANCH=octopus
TEST=Boot to ChromeOS; Ensure that the below error is resolved in the
kernel dmesg
[ 0.001000] ACPI Error: [\_SB_.PCI0.XHCI.RHUB.HS03] Namespace lookup
failure, AE_NOT_FOUND (20170728/dswload-210)
Change-Id: Ia4921547fee6fb51333319b9e881501a7e75ebce
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/31147
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
|
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Add separate functions for selecting the port and reading the port.
Romstage can now read incremental from the data port.
Change-Id: I0ffde3bc2a4415a8af99af2275d16f6609099e37
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/30846
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
|
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Reduce the number of fw_find_file calls by returning the file structure
at fw_cfg_check_file. The file structure can then be used to allocate memory
and access the file content directly without recurrence searching.
Remove now unnecessary function fw_cfg_load_file.
Fixed breaking function calls and add include guard at fw_cfg_if.h.
Change-Id: I48cc943aaa999e4323e9d7e5dd666c5316533dcc
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/30845
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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In payloads, we didn't set GPIO modes. We have to set up GPIO mode in
coreboot for payloads.
BUG=b:80501386
BRANCH=none
TEST=HW reboot works in depthcharge
Change-Id: Ibd2c6c071871edc59497fbb245cdbec6a814f621
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/31148
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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CB:31139 fixs few ACPI type error. Here is few more typo mistake.
Change-Id: Ieecf0ba8fe09ed5003d5ae766079b8f83cc891b9
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/31152
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Change-Id: Iede98359c22aefbfd5725a5e7cd661ef18d7284e
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/31146
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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FSP 2.0.9 provides UPD interface to adjust integrated filter
value, usb3 LDO and pmic vdd2 voltage. Change coreboot upd
structure to sync with fsp 2.0.9 release.
BUG=b:123398358
CQ-DEPEND=CL:*817128
TEST=Verified yorp boots to kernel.
Change-Id: I3d17dfbe58bdc5222378459723da8e9ac0573510
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/31131
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This is the old wiki page https://www.coreboot.org/Coding_Style
coverted from mediawiki to markdown.
Change-Id: Id56a8b7500121c4d9c18bc0b6bbc2c05402268dc
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30834
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
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This patch enables SaGv on Intel CNL-Y and CNL-U RVP board
Change-Id: I8a4b8a2a365caed304935bf0d66db9a92d10c23f
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/31132
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Move functions not available in PRE_RAM into seperate file.
Makes it easier to share code between rom and ramstage.
Change-Id: I0b9833fbf6742d110ee4bfc00cd650f219aebb2c
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/31141
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Currently, selflock_check() verifies that the binary is loaded in an
usable RAM area.
Extend its functionality so we can also check that BL31 is loaded in
a manually reserved area, and fail early if the range is not protected.
Change-Id: Iecdeedd9e8da67f73ac47d2a82e85b306469a626
Signed-off-by: Ting Shen <phoenixshen@google.com>
Reviewed-on: https://review.coreboot.org/c/31122
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Remove hard coding for SaGv config in devicetree.cb and apply macro for
SaGv config for CNL variants boards
Change-Id: If007589d5c1368602928b1550ec8788e65f70c05
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/31120
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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After adjustment on Arcada EVT
TouchScreen: 390 KHz
TouchPad: 389 KHz
H1: 389 KHz
BUG=b:120584026, b:120584561
BRANCH=master
TEST=emerge-sarien coreboot chromeos-bootimage
measure by scope
Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com>
Change-Id: Ia6eb332e7a664b211a5025ad07e0d01bf7f8d5bb
Reviewed-on: https://review.coreboot.org/c/31124
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
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Modifiy Makefile so that we can get board ID in verstage.
BRANCH=none
BUG=b:117916698
TEST=manually
Change-Id: Idcdb6e07f565c937185cab811abac0ce47e5e3a7
Signed-off-by: You-Cheng Syu <youcheng@google.com>
Reviewed-on: https://review.coreboot.org/c/31006
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
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Currently SMBUS registers are accessed through IO, but with stoneyridge
they can be accessed through MMIO. This reduces the time of execution by
a tiny amount (MMIO write is faster than IO write, though MMIO read is about
as fast as IO read) as most of the time consumed is actually transaction
time. Convert code to MMIO access.
BUG=b:117754784
TEST=Used IO to write and MMIO to read, to confirm a one to one relationship
between IO and MMIO. Then build and boot grunt.
Change-Id: Ibe1471d1d578611e7d666f70bc97de4c3b74d7f8
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/c/29258
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Because of Intel's faulty LPC clock, the SERIRQ mode must be corrected.
By removing this entry from devicetree, the default value (quiet mode)
is used. The problem is described in Intel document 334820-007 under
point APL47.
Change-Id: I7a45e0e5fcde17a20abd19a33282b8a9215b1480
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/31138
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: Ie0e11b1ce6c6acb1b74ce1196304f7e6ac4664d9
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/31137
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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The TPM chip is connected to the SPI interface of APL. The proper chip
select pin needs to be used in order to access the TPM in the memory
mapped space. This needed chip select is internally (inside APL)
routable to GPIO 106. Therefore the change of GPIO 106 mode is needed to
make the TPM work on SPI bus.
TEST=Build coreboot for mc_apl2 board and check the TPM console output.
In addition the TPM was correctly verified by our Linux driver.
Change-Id: I2b0d5a6f2c230187857c2428a70de61f21da6724
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/31125
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Real unused GPIO pad is GPIO_123, but GPIO_122 is configured as unused pad.
This patch corrects the configuration.
BUG=NONE
BRANCH=octopus
TEST=emerge-octopus coreboot
Change-Id: I4473bd66a4162f5aee3b998aacba906824728fc8
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/c/31135
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Initialize EC_PCH_WAKE_ODL GPIO to make sure that ec events will wake
the AP from suspend. Also create a task to initialize the hostevent
wake mask properly.
BUG=b:123325238,b:123325720
BRANCH=None
TEST=from AP console: powerd_dbus_suspend
from EC console: hostevent (make sure wake mask set)
from EC console: gpioset PCH_WAKE_L 0
Make sure device wakes up
Also, checked to make sure keyboard press wakes up
device from S3.
Change-Id: I53d5291a6b9ab9a21e89ccd21f172180ce473bd5
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/31100
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Unless things changed considerably, this file doesn't contain any
firmware. It is merely replacing a configuration EEPROM for the MAC
address etc. So don't call it firmware.
Change-Id: Ife6190639e7f05da2cb6eddeb1b0db0e8ffc8e6e
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/31108
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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Change-Id: I51493203b82868d221806c2e22b0c4b62e9fac97
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/31139
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Now running 1.8.3, with a fix to the theme so search still works, and
a recommonmark version that properly rewrites links to .md files.
Change-Id: Ice25554c77a398a71782c8d1cb9e205debd80d67
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/31129
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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List Raydium touchscreen in the devicetree so that the correct ACPI device
are created.
BUG=b:121105424
BRANCH=octopus
TEST=emerge-octopus coreboot chromeos-bootimage
reflash the coreboot to DUT, make sure the Raydium touchscreen can work.
Change-Id: I9ffb2a858f31a8b003086806de07f4079870cddf
Signed-off-by: Hao He <hao.he@bitland.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/31116
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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MT8183 only allows booting from eMMC, so we have to do eMMC emulation
from an external source, for example EC, which makes the size of
bootblock very important.
This CL moves some initialization steps from bootblock to verstage. This
will save us about 2700 bytes (before compression) / 1024 bytes (after
LZ4 compression) in bootblock. In case of CONFIG_VBOOT is disabled,
these initialization steps will be done in romstage.
BRANCH=none
BUG=b:120588396
TEST=manually boot into kernel
Change-Id: I9968d88c54283ef334d1ab975086d4adb3363bd6
Signed-off-by: You-Cheng Syu <youcheng@google.com>
Reviewed-on: https://review.coreboot.org/c/30331
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Now we have usb2eye configuration register in FSPUPD, so we need
to add an interface to override usb2eye setting.
BRANCH=octopus
BUG=NONE
TEST=Verified usb2eye custom setting works
Change-Id: I5c500964658072eaaf59364242aa928df25d99d1
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/c/31060
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Asserting GPIO PERIPHERAL_EN8 will send a signal to EC to trigger a HW
reset for SoC and H1.
BUG=b:80501386
BRANCH=none
TEST=emerge-kukui coreboot; manually verified the do_board_reset() on
Kukui P1
Change-Id: I9afad84af2031a766bc08fc76c8b5f55588c453a
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/31118
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Separate WDT reset function from WDT driver, then we can use the common
WDT driver and have a board-specific reset function on different boards.
In Kukui, we plan to use GPIO HW reset, instead of WDT reset. Add config
"MISSING_BOARD_RESET" in Kukui to pass the build for now.
BUG=b:80501386
BRANCH=none
TEST=emerge-elm coreboot; emerge-kukui coreboot;
Change-Id: Ica07fe3a027cd7e9eb6d10202c3ef3ed7bea00c2
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/31121
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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* Check if microcode is really updated.
* Enable more verbose output.
Change-Id: I534aa790c8d37b5f1603e1715635446835513a65
Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/29864
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
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Version 2 IFD will have flmstr5 as EC region access control, consider it
during descriptor lock/unlock process.
BUG=N/A
TEST=Build coreboot with CONFIG_LOCK_MANAGEMENT_ENGINE set, and check
flmstr5 value by hexdump the SPI image at offset FMBA+0x90.
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I970064dcf6114a15f054ab7c44349841deb99dc8
Reviewed-on: https://review.coreboot.org/c/31111
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Cannonlake and Icelake have same read/write region permission settings
with skylake and kabylake, so add it here as well.
BUG=b:123199222
TEST=Turn on CONFIG_LOCK_MANAGEMENT_ENGINE and build image, check the
setting matches 0x0D for read and 0x04 for write.
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I71d8b815c7dff7dcbcff2bf77c85ebf80b8df6d2
Reviewed-on: https://review.coreboot.org/c/31104
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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This board has almost the same schematics as [xt]60 so this should work.
See also commit 7971582e with Change-Id
Iff6dac5a5f61af49456bc6312e7a376def02ab00.
Change-Id: I8dc9b122eb64b5c1dcd0dbc99ac41aa0f8dd9766
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31115
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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This patch enables SaGv on Intel ICL-Y RVP board.
TEST=Able to build and boot to Chrome OS.
Change-Id: Ic3ed94d47ddc7fd70bf3de1db15fe574029df856
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/31119
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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This patch removes stale ASL entries added in past due to chromeos
requirement.
BUG=115755982
TEST=Build and boot ICL platform without any problem.
Change-Id: I18b57822ce3198fb96aae977f0b552ff2d4a14ee
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/31117
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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4.9 was still marked as "upcoming" and 4.10 was missing altogether,
leading to a sphinx warning.
Change-Id: I008d546715b7841eb9f325a6f698380dd4c1a7c2
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/31126
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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The SoC has an Image Processing Unit which is located on PCI 00:03.0.
There is a corresponding parameter for FSP which handles
enabling/disabling of this functionality (IpuEn). Add this device to
the disable_dev() function of the chip so that if this device is
disabled in devicetree the matching FSP parameter will be disabled as
well. As this parameter is only valid for Apollo Lake, use the config
switch CONFIG_SOC_INTEL_GLK to disable this code if compiled not for
Apollo Lake. As this issue is regarding a missing structure member,
this check needs to be done on preprocessor level and not at runtime.
Test=Verified this function on mc_apl2.
Change-Id: I75444bf483de32ba641f76ca50e9744fdce2e726
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/30992
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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If the VTd feature is enabled, there will be up to two fixed resources
which are set up by the FSP. Add these resources to the list of system
resources so that the PCI enumerator will know them.
Change-Id: If96fc1c93746e3c7f510e5b3095ea3090e1b8807
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/30991
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Generate DMAR table if VTd feature is enabled.
Test=Booted into Linux on mc_apl2 and verified the DMAR table contents.
In addition turned off Vtd and verified that no DMAR table is generated
at all.
Change-Id: Ie3683a2f3578c141c691b2268e32f27ba2e772fa
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/30990
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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In preparation of generating DMAR tables, provide the hook in SoC scope
for the systemagent to write ACPI tables. The complete functionality is
SoC-specific. Therefore the entry hook is defined as a weak function which
can be overridden by SoC code. If the SoC does not have support for
generating DMAR tables this hook will do no harm.
Change-Id: I1333ae2b79f1a855e6f3bb39bf534da170ddc9e1
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/30989
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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