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While debugging lack of battery status under Windows, it was discovered
that the read/write flags in the args to the EC RAM 'ECRW' method were
not being correctly identified. Force set them from the R() and W()
methods which call ECRW() so those calls are processed properly.
TEST=build/boot Windows on google/drallion, verify battery status,
charging, etc are all reported properly.
Change-Id: I2a40b8d50ba65213813c781e53b56cc1a8b8debf
Signed-off-by: Coolstar <coolstarorganization@gmail.com>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72472
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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IOE_PMC support was not enabled on Meteor Lake platforms. This patch
adds the bare minimum hooks to initialize and allocate a memory region
for IOE operations. Additionally, this patch moves those IOE operations
to a newly included IOE-specific file, Previously, PMC was responsible
for these operations.
BUG=b:287419766
TEST=build and verified on google/rex.
Change-Id: I8bbc0b8a3e32dad5404c80bc7717ef07e3ec60b9
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77261
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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C1-state auto demotion feature allows hardware to determine C1-state
as per platform policy. Since platform sets performance policy to
balanced from hardware, auto demotion can be disabled without
performance impact.
Also, disabling this feature results soc to enter PC2 and lower
state in camera preview case and save platform power.
Note: C1 demotion heuristics used EPB parameter to balance between power
and performance, i.e. low threshold when EPB is low in-order to get C1
demotion faster and vice-versa. ChromeOS operates at default EPB=0x7
(low EPB) in both AC/DC, so in DC mode it gets more C1 demotion hits
than expected (similar to AC mode) and losing power respectively.
ref. https://review.coreboot.org/c/coreboot/+/76827
BUG=b:286328295
TEST=Code compiles and correct value of c1-state auto demotion is
passed to FSP. Also verified PC residency improvement ~10% in
camera preview case.
Change-Id: I1b2db634176f0072c535608c5600846a9086fef1
Signed-off-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77067
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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Change-Id: Ic7d51037d527f95e8664ad04e328fc27901cacde
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71993
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Existing code did not include the HID over SPI for rex4es.
This CL corrects this issue.
BUG=None
TEST=Tested on Rex
Signed-off-by: Eran Mitrani <mitrani@google.com>
Change-Id: I02f7c4b68cfee2ebb202581c9f031af99ab4b6f9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77245
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Allow users of Alderlake N processors to use the microcode repository
and also add their related microcode blob to the list of microcodes
which should be included in the coreboot rom.
Change-Id: I11c9cb13fa81118bfcb819bad5fb39731c7e3e76
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75632
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
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Newer versions of Sphinx complain about the language being set to None,
so explicitly set it to 'en'. The syntax that is currently used to
enable custom CSS styling for tables [1] also no longer works, resulting
in the docs rendering without CSS. Fix this using the html_css_files
option instead.
TEST: The documentation builds and renders correctly with both Sphinx
1.8.3 in from the doc.coreboot.org Docker container and Sphinx 7.2.2
from distro packages.
[1] Commit a78e66e5f4: Documentation: Add static CSS file to fix tables
Change-Id: I036b1cad3cfa533c0c3a037bac649caa2d968d4b
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75466
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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Fix the issue by adding the "ifeq" keyword which makes the extraneous
text a correct conditional directive.
Change-Id: Id8a8aa7acfdaeb0549f417fb013b2535a7298045
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77286
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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Change-Id: I551d71d968abb6a9cadbc0f87bc9258768db1fca
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77275
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I7ed982c9dcf755c97f26cc43b3dc05b898e4150a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77274
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add data.vbt files for all variants supported by current brya, brask,
and nissa recovery images. Select INTEL_GMA_HAVE_VBT for all variants
which currently have a VBT file.
TEST=build/boot various brya variants (banshee, osiris, redrix)
Change-Id: Ic66f91e264d37c3742cb17994f637604d77a1576
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77144
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch removes unused CBMEM ID named
`CBMEM_ID_CSE_PARTITION_VERSION`.
BUG=b:285405031
TEST=Able to build and boot google/rex w/o any compilation error.
Change-Id: I83f53b7f64bdef62a8ee2061d5a9c9e22bc4b8a4
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77179
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch selects `SOC_INTEL_STORE_ISH_FW_VERSION` config to dump
the ISH version as part of the .final hook.
BUG=b:285405031
TEST=Able to build and boot google/rex_ec_ish. Verify the ISH version
is same as MFIT ISH version section.
> cbmem -c | grep "ISH"
[DEBUG] ISH version: 5.6.0.28821
Change-Id: I052af85ad836ab81ff6c510bb74e042b11940a65
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77178
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch implements `soc_is_ish_partition_enabled()` override to
uniquely identify the SKU type between ISH and non-ISH to conclude
if ISH partition is enabled and need to retrieve the ISH version from
CSE FPT by sending a HECI command.
BUG=b:285405031
TEST=Able to uniquely identify the ISH SKUs while booting
to google/rex_ec_ish to dump the ISH version.
Change-Id: I48358ad9e2e582e8b2274cbf4655de01f8792e6c
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77177
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch uses the CSE firmware specific data to store Intel
ISH firmware related information. Sending an ISH partition version
information command on every boot cycle would impact the overall boot
performance.
This information is used by the auto-test framework to ensure the ISH
firmware update is proper for in-field devices.
BUG=b:285405031
TEST=Able to build and boot google/rex. Verified ISH FW version is
getting displayed across warm resets without impacting the boot time.
Change-Id: I0242c26dd90d834815799f54740d8147ff9d45b7
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77176
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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This patch selects SOC_INTEL_STORE_CSE_FW_VERSION config by default
for CSE LITE SKU. It helps to dump the CSE RW firmware version which
further consumed by auto-test infrastructure to ensure CSE RW firmware
update is successful.
BUG=b:285405031
TEST=Able to build and boot google/rex.
Verified CSE RW FW version (for LITE SKU) is getting displayed without
impacting the boot time.
Change-Id: Iba5903c73c0a45b01e6473714e0d5f759c061825
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77175
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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This patch introduces a CSE firmware specific data in order
to store Intel CSE and associated firmware related information which
requires a sync between Pre-RAM and Post-RAM phase.
This information will be used further to retrieve currently running
CSE RW firmware instead of fetching the version information by sending
a HECI cmd (which consumes 7ms-15ms depending upon the CSE operational
state).
Current implementation attempts to simply the CSE RW FW version store
and retrieval operations as below
* CSE sync in romstage (aka Pre-RAM) - Relying on .bss segment to store
the CSE info data in absence of real physical memory and sync back into
the CBMEM once available (after FSP-M exits).
* CSE sync in ramstage (aka Post-RAM) - Directly stored the CSE RW
version into the CBMEM (as CBMEM is online).
BUG=b:285405031
TEST=Able to build and boot google/rex. Verified CSE RW FW version
(for LITE SKU) is getting displayed without impacting the boot time.
w/o this patch:
10:start of ramstage 722,257 (43)
17:starting LZ4 decompress (ignore for x86) 723,777 (1,520)
w/ this patch:
10:start of ramstage 722,257 (43)
17:starting LZ4 decompress (ignore for x86) 723,777 (1,520)
Change-Id: Ia873af512851a682cf1fac0e128d842562a316ab
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77174
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
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Disable TPM support for CR50 TPM when using MrChromebox repo, since
it's not currently supported in edk2, and causes some boards (eg AMD
Zen-based) to failed to boot.
TEST=build/boot on google/frostflow
Change-Id: I64b5eb09d64eafd2bed400b7a7c97750cc368aed
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77270
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add Kconfig for passing a VBT file and GOP driver to edk2, and pass a
build param to use them along with the platform GOP driver. This allows
edk2 to initialize the display and change display modes, instead of
being limited to the single mode set by whatever display init method
coreboot might use (libgfxinit, FSP/GOP, VBIOS, etc).
TEST=build/boot multiple google boards spanning several platforms using
the edk2 GOP driver for display init.
Change-Id: I63a49df2411fe44b06eaee6d0fb9aab42ac8aedb
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77269
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
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When cbfs_map()/cbfs_ro_map() fails, the caller may still want to know
the decompressed size of the CBFS file, for example, to print an error
message. Move the assignment earlier in the flow. Note that coreboot's
cbfs_map() is already doing the same.
BUG=none
TEST=emerge-geralt libpayload
BRANCH=none
Change-Id: I82c6b7e69c95bf597fa3c7d37dd11252893c01af
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77193
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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CPU replacement check should only be done on cold boots.
Original-Change-Id: I98efa105f4df755b23febe12dd7b356787847852
Original-Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Change-Id: I3c79f4e55e23c0b98da7661988e3ff8b50d6300d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77048
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add libgfxinit support for Nami, Nautilus, and Soraka. Panel timing
values taken from default panel selection extracted from the
respective VBTs.
TEST=build/boot nami w/edk2 payload and libgfxinit selected
Change-Id: If0ca389487338c47f9d8de990acf591c6907eaa9
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77268
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Add support for ACPI display brightness controls, so that panel
adjustment is available under Windows.
TEST=build/boot Win11 on google/magpie, verify panel brightness
controls available and functional.
Change-Id: I66daa6bbca15046994dff83bee6e7cf99aae0b33
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77271
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Update VBT with file extracted from FW_MAIN_A region of firmware file
bios-endeavour.ro-13259-80-0.rw-13259-144-0.bin
TEST=build/boot endeavour
Change-Id: Ibf7b35c4e59c6fe816cf036e637483de75d6ecd4
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77267
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Update header files for FSP for Meteor Lake platform to version 3292.83,
previous version being 3223.80.
The patch doesn't include any function changes, only a few comments and
headers have been changed.
BUG=b:295126631
TEST=Able to build and boot google/rex to ChromeOS.
Change-Id: I27f88732bfafd4732ea39bf9c54e18341dd26cf9
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77247
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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update DTT settings for thermal control
BUG=b:291217859
TEST=emerge-rex coreboot
Change-Id: I6e6ad653157dc87a7d87b5ffc4f9590991a7c284
Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76678
Reviewed-by: Simon Zhou <zhouguohui@huaqin.corp-partner.google.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The site-local directory is not checked into the coreboot tree, so this
change excludes it by default. By adding the site-local directory,
an issue could be missed in the rest of the coreboot tree.
This change also adds a new command-line argument of -S or --site_local
that re-enables the site-local checking.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I95efa3e7b2cbb84e5c84d263222d8e914626d314
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77138
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Add support for ACPI display brightness controls, so that panel
adjustment is available under Windows.
TEST=build/boot Win11 on google/drobit, verify panel brightness
controls available and functional.
Change-Id: Ic0c026ae09b3fde648db4bdeb4971423953c96a1
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77143
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Configures ISH related GPIO's based on FW_CONFIG obtained from CBI.
BUG=b:280329972,b:283023296
TEST= Set bit 21 of FW_CONFIG with CBI
Boot rex board
Check that ISH is enabled, loaded, and functional
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Change-Id: I778251aadef4499427fc9855adfdd9cade3a3e70
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77235
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add the builtin to copy variadic lists/arguments.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I4507b901bdce052c5d1701fdf825eb8a96a5b55a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77097
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This UPD does exist for Alder Lake, so set it there also.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: If2f405804ab675aaf6dbf8b12d149566055b9eef
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77125
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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For Thunderbolt to be disabled, `UsbTcPortEn` and `TcssXhciEn`
also need to be disabled.
Change-Id: Ie02c1e0ea7583bbd78e25c8184e2cdf2b6281741
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77200
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Ie4032048f5f53b25c46f00b3b48eb5f986a5d0b3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77045
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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This patch chooses to show the early splash screen which is an
OEM feature. The current implementation is relying on the Intel
FSP GFX PEIM to perform the display initialization.
Having this feature allows the platform to show the user notification
with 500ms since boot compared to traditional scenarios where first
user notification is coming from kernel (typically ~3sec+ after cpu
reset). Eventually this feature will help to improve the user
experience while booting Intel SoC platform based chromeos devices.
BUG=b:284799726
TEST=Able to see the early splash screen on google/marasov.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I2449bf97d6c82cb08f603b29643cc261738b5379
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77234
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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This patch adds the ability to show a pre-boot splash screen on
Meteor Lake systems using FSP-S.
The patch calls into `fsp_convert_bmp_to_gop_blt()` when the
`BMP_LOGO` config is enabled. This function converts a BMP
file to a BLT buffer, which is then used by FSP-S to render the splash
screen.
Additionally, increase the heap size (malloc'able size) upto 512KB
(when BMP_LOGO config is enabled) to accommodate high
resolution logo file.
BUG=b:284799726
TEST=Able to see splash screen while booting google/marasov
with BMP_LOGO config enable.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I9f4d1bc0aa991e784624ca19ba96a259ab8ddfa6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77233
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Fix regression introduced in I25e757108e0dd473969fe5a192ad0733f1fe6286
"payloads/external/LinuxBoot: Clean up".
Add creation of the build folder as necessary dependency.
Change-Id: Ie76c914f6a705de0c275a05b5af82ac21243d522
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77202
Reviewed-by: Marvin Drees <marvin.drees@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
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Disable pins for SD card based on fw_config.
BUG=b:294456574
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot
Change-Id: I0b383d1b00056a69ba925bb5203dc4ca026b9d8e
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77105
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Backport commit cf544ac (broadwell: Remove XHCI workarounds on WPT).
Newer Lynxpoint reference code shows LPT-H also uses these workarounds.
Also, add the `ISWP` object (Name or Method) to test for WildcatPoint.
Change-Id: I76bc07e585e8af292c7316442760d1cfabf1e9c9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46960
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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BUG=b:294155897
TEST=emerge-rex coreboot
Change-Id: Ia4bd6fe02ffa62ed8aeffb188de5c4c4b64900ff
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77106
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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BUG=b:294155897
TEST=emerge-rex coreboot
Change-Id: I1575ee1d7e4c834ad15f60a3b7d63c041a8d4890
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77007
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Follow schematic, modify SSD related settings.
BUG=b:294155897, b:289880020
TEST=emerge-rex coreboot
Change-Id: Ie9c228ed7ccc83afaa8365f89c1d5cdedc4f0c8c
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77006
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add initial devicetree config for karis.
It's copied from rex0 and only for initial settings, will update more
settings afterward.
BUG=b:294155897
TEST=emerge-rex coreboot
Change-Id: I89585a86e8afe636d3927a21a64451b59591acda
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77203
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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Add initial Kconfig settings for karis. Copied from rex for support
audio codec, SD card and ISH. It's only for initial settings, will
update more settings afterward.
BUG=b:294155897
TEST=emerge-rex coreboot
Change-Id: I4bcea7f5e678f2862b3477206838786ff5bad173
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77182
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=b:294155897
TEST=emerge-rex coreboot
Change-Id: I4076ee4a16b7260db464760d5a19e1144081bab8
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77181
Reviewed-by: Eran Mitrani <mitrani@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add initial GPIO settings for karis.
It's copied from rex0 and only for initial settings, will update more
settings afterward.
BUG=b:294155897
TEST=emerge-rex coreboot
Change-Id: Ic1e52a1eaca0aa5f68661826a70ccb89d6e302dc
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77003
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Bluetooth was missing USB configuration, so add it according
to the schematics.
BUG=b:290111789
TEST=Boot on Ovis and list bluetooth with `hciconfig`
Change-Id: Iee8a3368bbad6c5b49f09ec7335d77ed63ecc784
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77146
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch selects LZ4 decompression for logo CBFS file. Able to save
2ms of the boot time when HAVE_FSP_LOGO_SUPPORT config is enabled.
However, the compressed BMP logo size is increased by ~2KB.
Raw BMP Image size is ~97KB.
BUG=b:284799726
TEST=Able to see pre-boot splash screen while booting google/rex
with 32MB (W25Q256JWEIM) SPI-Flash.
w/o this patch:
sudo cbfstool image-screebo4es.bin print -r FW_MAIN_A
FMAP REGION: FW_MAIN_A
Name Offset Type Size Comp
...
...
logo.bmp 0x167480 raw 6172 LZMA (97078 decompressed)
...
15:starting LZMA decompress (ignore for x86) 849,090 (1,022)
16:finished LZMA decompress (ignore for x86) 851,207 (2,116)
w/ this patch:
sudo cbfstool image-screebo4es.bin print -r FW_MAIN_A
FMAP REGION: FW_MAIN_A
Name Offset Type Size Comp
...
...
logo.bmp 0x167480 raw 8568 LZ4 (97078 decompressed)
...
17:starting LZ4 decompress (ignore for x86) 849,419 (1,279)
18:finished LZ4 decompress (ignore for x86) 849,559 (140)
Change-Id: I856c39146a5ec0faf44c1cd37fa7c0d7296bf673
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76930
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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This patch adds a new configuration option to allow the compression
algorithm for the logo cbfs file to be specified. By default, the logo
cbfs file is compressed using LZMA. However, enabling LZ4 compression
can save ~2ms of boot time when the BMP_LOGO config is enabled.
This patch verified that the logo cbfs file can be booted using either
LZMA or LZ4 compression.
BUG=b:284799726
TEST=Able to boot google/rex and verified firmware splash screen using
either LZMA or LZ4 compression.
Change-Id: Ib0aa5320632ae3f734004d2b1d495af11c2e1928
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76927
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Intel has rebranded ESE as ISSE (Intel Silicon Security Engine),so all
references to ESE is updated to ISSE in the current coreboot code.
BUG=None
TEST=Build all the variants based on Intel Meteor Lake SoC
Signed-off-by: Usha P <usha.p@intel.com>
Change-Id: I1f8785704706d56a35e94a0f3386bc551cd1f263
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77241
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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Enable Crystaldrift platform to send the fuse SPL (security patch level)
command to the PSP.
BUG=b:279499517
BRANCH=none
TEST=emerge-skyrim coreboot chromeos-bootimage
Then get "PSP: SPL Fusing Update Requested." in the firmware log.
Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com>
Change-Id: I1d41505e64bf54ad911ad7d287263013a9c458db
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77190
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Change-Id: If26184058536590b70bbb03209913118307ff6c5
Signed-off-by: Michael Strosche <michael.strosche@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76830
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I8a04068dd986f2d5dbebecd0bff08cc0189a34d6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74605
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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Change the order of enabling EC and GPE wake sources, so it comes more
obvious we can use existing chromeec handlers without changes.
Change-Id: I5a10afa2b816dc8c01074be68a63114ee027c1e2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74604
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I752d5644d6140e5a6d6f53543bbbc5ef7281f3b4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74824
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I9ac7293e03bba773753f48163aca9385f819a71b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74822
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I6b67358431d8c2b9f88b4e8948baf3497b902fed
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74821
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Early Chromebook generations stored the information about
USB port power control for S3/S5 sleepstates in GNVS, although
the configuration is static.
Reduce code duplication and react to ACPI S4 as if it was ACPI
S5 request.
Change-Id: I7e6f37a023b0e9317dcf0355dfa70e28d51cdad9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74524
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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Add support MIPI driver and DA7219 driver for pirrha.
BUG=b:292134655
BRANCH=nissa
TEST=FW_NAME=pirrha emerge-nissa coreboot
Change-Id: I6a8f0f942a54909627aad3bf447dc7225f57cef2
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77165
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
|
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Correct TPM I2C BUS number for pirrha
BUG=b:292134655
BRANCH=nissa
TEST=FW_NAME=pirrha emerge-nissa coreboot
Change-Id: I9fa0b46db752d02368f19ce8c58a4122b371c100
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77164
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Increase VBT_DATA_SIZE_KB to 10 since pirrha uses bigger VBT file.
It includes MIPI power sequence data for panel.
BUG=b:295112773
BRANCH=nissa
TEST=FW_NAME=pirrha emerge-nissa coreboot
Change-Id: Ib6c293ccb4a8df3ebbd2271e7db2de4e7bd9cc3e
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77163
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Add a limited config for starbook/adl so that Jenkins will build
test it, and specifically, ramtop.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Idcfa45532835a6d89b167fa498b5023b62db0f0a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75386
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ic559b78e6444acec36d437fe3c139b692a3f4d0a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77126
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
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BUG=b:292134655
BRANCH=nissa
TEST=Boot to OS on pirrha ADV board
Change-Id: I65429ec8d30b4458511f7c0138652528aadfde25
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76892
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
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Implement support for elan i2c touchscreen and use fw_config
to pick between i2c or HID-over-i2c touchscreen.
BUG=b:294456574
BRANCH=firmware-nissa-15217.B
TEST=build and verified touchscreen work
Change-Id: I32ba97f5e5f6d280d1ae47da22360fde421a26c0
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77104
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
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Change-Id: Iadd8a0f3bae07918990cba8f33eb1e65f4e1977a
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77188
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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The docker-shell target was originally intended to point at the
docker-jenkins-node image, and was documented as such. It was actually
split into two targets - docker-shell and docker-jenkins-shell.
This fixes the documentation for docker-shell and adds new help
for docker-jenkins-shell. The docker-jenkins-shell target is also
noted as phoney now.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ib3ce82f6a73a2f81e5ae51ce8063ae4e59ef67db
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76854
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
|
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Now that all of the makefiles under the src tree have SPDX headers,
add that expectation to the license header lint tool by removing
the exception for Makefile.inc.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Iab9d3262621af09a1c625378ae2e61e8a736cdf8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76952
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
|
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This makefile had a 3-clause BSD license. Swap the full license text with an SPDX header.
Looking through the history determined that it had copyright lines,
so those were added back as the license required.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I53a746de6d2e6b60c41415531b7f261e02908b28
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77151
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
|
|
Update DPTF thermal settings from thermal team suggestion:
1. Modify CPU passive policy to 95.
2. Modify TS0/TS1/TS2 passive policy to 90 for CPU.
3. Modify TS1 passtve policy watt to 6w.
4. Modify TS0/TS1/TS2 critical policy to 100.
BUG=b:294479707
TEST=Build and verify DPTF value by thermal team on Boxy system
Change-Id: Ic34e44f218ff980c54bf93841880fab5e21b3fca
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77108
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Instead of open coding this, use the mmio_range helper function to tell
the resource allocator about the northbridge's IOAPIC's MMIO. This
change sets the IORESOURCE_RESERVE and IORESOURCE_STORED bits in the
resource flags that weren't set before, but mmio_range is already used
elsewhere for similar purposes.
TEST=None
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id66a73cdb22fd551e4359914ba5513313dcc3193
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77173
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
|
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Disable NULL breakpoints in setup_realmode_idt before calling
write_idt_stub in a loop.
TEST=No more spurious Null dereference errors in the console output.
Before Mandolin showed these two errors before running the VBIOS:
[ERROR] Null dereference at eip: 0x4e6f1a35
[ERROR] Null dereference at eip: 0x4e6f1a4f
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I2255d85030e41192ae8a3a7f0f6576c0d373eead
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77172
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
|
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Instead of open coding the same functionality, use fixed_io_range_flags
to tell the resource allocator about the FCH subtractively decoding the
first 0x1000 bytes of I/O space. Also update the comment to match the
code.
TEST=On Mandolin the flags of this resource stay the same (0xc0040100).
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia30a87a4e37c98248568476b74af2730a3c0e88d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77170
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The resource allocator's setup_resource_ranges will make sure that the
memory resources are 4KiB-aligned. The resource allocator doesn't
enforce any alignment requirements on IO regions.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3c148ce2acbe284b40126e331d8f372839817e73
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77167
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Use get_iohc_fabric_id() to translate the coreboot domain's number into
the destination data fabric ID of the PCI root. This allows using the
coreboot domain 0 as primary domain of the SoC in all cases, so it's
still possible to use config_of_soc(). This allows dropping the
SOC_AMD_COMMON_BLOCK_DATA_FABRIC_DOMAIN_MULTI_PCI_ROOT Kconfig option
and do the check if the destination fabric ID in the PCI bus number,
MMIO, and IO decode registers is the correct one for the domain without
the need to use a non-zero number for the primary PCI root domain.
TEST=Mandolin still boots and the PCI bus, IO and MMIO resources still
get reported correctly.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I880ee0bf5c185cfe4af7de0d39581eb951ee603a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77169
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Implement get_iohc_fabric_id for each SoC that translates the coreboot
domain number to the fabric ID of the corresponding PCI root. This
allows the primary domain to have the number 0 even though the
destination data fabric ID will be non-zero. Keeping the primary domain
number 0 allows to use config_of_soc() which can be resolved at link
time and not need to dynamically find the SoC device to get the config.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6538a777619eed974b449fc70d3fe3084ba447dd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77168
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
|
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Change-Id: Ie766807ae1538b21acf471cfacbfe75cfeead921
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77187
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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Change-Id: I107e2952bcca864a1cacf240cca301011df44719
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77158
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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Change-Id: Iab1ac1609f117a1a80bc025bcbe4659189bdb676
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77159
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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Change-Id: I88668d8c69da68cc28bae287f573f650f28da32e
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77157
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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To help identify the licenses of the various files contained in the
coreboot source, we've added SPDX headers to the top of all of the
.c and .h files. This extends that practice to Makefiles.
Any file in the coreboot project without a specific license is bound
to the license of the overall coreboot project, GPL Version 2.
This patch adds the GPL V2 license identifier to the top of all
makefiles in the commonlib, console, northbridge, security, and
southbridge directories that don't already have an SPDX license line
at the top.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I02804a10d0b0355e41271a035613d9f3dfb122f8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68985
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
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Rewrite them to more accurately describe what they are about.
Change-Id: Icb0ac1e592b662bbb81da431ff97af1a00f952c0
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47429
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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In the case of SoCs hat have more than one PCI root, we need to check to
which PCI root the PCI bus number, IO and MMIO regions configured in the
data fabric registers get routed to and only tell the resource allocator
about the resources that get routed to the current PCI root domain. For
this the numbers of the domains need to match the PCI root's destination
data fabric ID.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib6a6412f733d321044678d2b064c33418a53861c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77113
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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Intel Platform Service Record (PSR) provides on-platform persistent and
tamper resistant ledgers and counters.
Key events captured within the Intel PSR Event Ledger, e.g., Chassis
Intrusion Detection, can be observed over the life cycle of the platform
to help assess confidence.
Counters for platform S0 operational use and power state transitions can
be assessed to aid in the determination of general wear or correlations
of other platform events when determining platform decommission plans
(repurpose, resell, recycle).
PSR data is created and stored in CSE data partition. In platforms that
employ CSE Lite SKU firmware, a firmware downgrade involves clearing of
CSE data partition which results in PSR data being lost.
CSE Lite SKU firmware supports a command to backup PSR data before
initiating a firmware downgrade. Add a config to support this PSR data
backup flow.
BRANCH=None
BUG=b:273207144
Change-Id: Iad1ce2906177081c103ef4d4bcef78fa2c95026f
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77068
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
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With this change TPERST_HIGH could met spec.
Before
160ms
After
460ms(met spec min=400ms)
BUG=b:295277868
TEST=emerge coreboot
EE measured power sequence met spec
boot to system and check wifi connection is fine
Change-Id: Ifb909a55b36f2366132c3e20021c4bde4bc87a05
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77117
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
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Add GPIO table for pirrha based on pirrha ADV board schematics.
BUG=b:292134655
TEST=FW_NAME=pirrha emerge-nissa coreboot
Change-Id: I1f45365665b200fa97766344df2f9e06bc6dfb3d
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76882
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I5174e0457489c29be6a2b2b882de2db4255bbca0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77145
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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This adds a missing prerequisite, because otherwise it can happen that
curl tries to put the downloaded kernel in a non existing build
directory
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I459172f794ab9c1010cebcff5e28f1454e136fba
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76914
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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Allows cbmem console log and timestamps to be read from Windows.
TEST=build/boot Win11 on google/eve, read cbmem log
Change-Id: I545ce43d4337dd71afedda6bc9208a8c3bf158ee
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77139
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Move specific selections to {cpx,skx,spr} and remove
dummy SOC_SPECIFIC_OPTIONS
Change-Id: I71e41deb0478bf4d04395c88fc7b68df1ea83ac0
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76939
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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Based on contents from coreboot wiki[1], this patch adds much needed
documentation for the very important abuild utility.
On top of what was there:
- Mainboard targets have been updated
- Added example for building one variant of one board
- Added example for building boards selectively and/or with custom
configurations using --skip_set/--skip_unset, -K, and config files
[1] https://www.coreboot.org/Abuild
Change-Id: I69701eaeef616828bc30736aba2f617e844a3148
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76775
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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The data fabric also controls which PCI bus numbers get decoded to the
PCI root. In order for the resource allocator to know how the hardware
is configured, read the corresponding data fabric registers to get the
information that then gets passed to the allocator.
Picasso, Cezanne, Mendocino and Rembrandt only support one PCI segment
with 256 buses while the Phoenix and Glinda data fabric hardware has
support for more PCI segments. Due to this change, the register layout
is different and incompatible between those two, so introduce the
SOC_AMD_COMMON_BLOCK_DATA_FABRIC_MULTI_PCI_SEGMENT Kconfig option for a
SoC to specify which implementation is needed. At the moment, coreboot
doesn't have support for multiple PCI segments and the code doesn't
support PCI segments other than segment 0.
On Picasso the PCI bus number limit read back from the data fabric
register is 255 even though CONFIG_ECAM_MMCONF_BUS_NUMBER is set to 64,
so also make sure that the bus and limit returned by
data_fabric_get_pci_bus_numbers is within the expected limits.
TEST=PCI bus allocation still works on Mandolin (Picasso) and Birman
(Phoenix). Picasso has 64 PCI buses. coreboot puts this info into the
resource producer in _SB\PCI0\_CRS which the Linux kernel reads:
* coreboot: PCI0 _CRS: adding busses [0-3f]
* Linux: pci_bus 0000:00: root bus resource [bus 00-3f]
This matches the information in the ACPI MCFG table.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ide5fa9b3e95cfd59232048910cc8feacb6dbdb94
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77080
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The fixed I/O resource descriptor macro implies that the device will
only decode 10 of the 16 IO port bits causing aliasing. Use an I/O port
descriptor instead and use Decode16 to tell the OS that this I/O
resource will decode all I/O address bits.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I2df260cea6f12f5a3a6cbae3c7b99bab244a556b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77066
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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The fixed I/O resource descriptor macro implies that the device will
only decode 10 of the 16 IO port bits causing aliasing. Use an I/O port
descriptor instead and use Decode16 to tell the OS that this I/O
resource will decode all I/O address bits.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6183d625fb7968fb33caf396f19feef8917ba4fe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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The SOC_AMD_REMBRANDT_BASE comment at the end of Glinda's Kconfig is
probably a leftover from the Mendocino/Rembrandt SoC this file was
copied from. Change it to SOC_AMD_GLINDA to match the corresponding
'if SOC_AMD_GLINDA' in the file.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I85132e4840c1bc713cfc2f3493f800d66edd10ff
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77121
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Tested using `edk2` from
`github.com/starlabsltd/edk2/tree/uefipayload_vs`:
* Windows 11
* Ubuntu 22.04
* Manjaro 22
No known issues.
https://starlabs.systems/pages/starbook-specification
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I7c92bf92ab4de546c3633fae7e19a302409508ce
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74444
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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Neither Windows nor mainline Linux make use of IOSF on the Braswell
platform, so adjust the ACPI status return value based on
CONFIG(CHROMEOS) to prevent an unknown device being listed in Windows
device manager.
TEST=build/boot Win11, Linux 6.2 on google/edgar
Change-Id: Ic51624ffd816d48c007c13d510601cf8cbf1edc4
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77142
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
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Neither Windows nor mainline Linux make use of IOSF on the Baytrail
platform, so adjust the ACPI status return value based on
CONFIG(CHROMEOS) to prevent an unknown device being listed in Windows
device manager.
TEST=build/boot Win11, Linux 6.2 on google/swanky
Change-Id: I249028c57cc704955cf5a11e2088780ef58e16cf
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77141
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Neither Windows nor mainline Linux make use of DPTF on the Baytrail
platform, so guard its inclusion with CONFIG(CHROMEOS) to prevent an
unknown device being listed in Windows device manager.
TEST=build/boot Win11, Linux 6.2 on google/swanky
Change-Id: Ifc4d349691b647fe2d70c92bd20d1b1128b1e10a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77140
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I83574032ef506a411571e8363f476f322ac13e5e
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76686
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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VBOOT_CBFS_INTEGRATION needs board_reset in its logic. Otherwise, it
will cause a build failure.
BUG=b:294643742
TEST=build coreboot
Change-Id: Ia4b81d8add71e62707f6b5a747d270caba502174
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77118
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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