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2021-04-07mb/amd/majolica: add PCIe devices to devicetreeFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I838aeda2e6c403eaa3388a6b934e7ab6b4e918e3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52045 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-07mb/google/guybrush: add DXIO and DDI descriptorsFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com> Change-Id: Ic8a4349315f8759c79dc6b087b2a933c307cd573 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51957 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-04-07soc/amd/cezanne: Pass DXIO and DDI Descriptors to FSPMatt Papageorge
This patch adds the functionality to write the DXIO and DDI descriptors to the UPD data structure to the SoC code and adds the mainboard_get_dxio_ddi_descriptors function to each mainboard using the Cezanne SoC that gets called to get the descriptors from the board code. Change-Id: I1cb36addcf0202cd56ce99e610a13d6d230bc981 Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51948 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-04-07vc/amd/fsp/cezanne/FspmUpd: use arrays for DXIO/DDI descriptorsFelix Held
This allows coreboot to easily iterate over the descriptors. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I2ecb3b543f90b8c6a957794f0c55b0ba5c72d59d Reviewed-on: https://review.coreboot.org/c/coreboot/+/51955 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-04-07vc/amd/fsp/cezanne: update UPD headersMatt Papageorge
The UPD header files get generated as part of the FSP build process. For the initial Cezanne development we took the Picasso UPD data structures as a starting point. This patch replaces it with the first version of the Cezanne-specific UPD data structures that is present in version 12 of the internal work-in-progress FSP binary drops. The serial_port_stride UPD-M field is removed, since the information is already given by serial_port_use_mmio. The stride is 4 bytes for the MMIO UART case and 1 byte for the legacy I/O case. BUG=b:182524631 TEST=NVMe works on google/guybrush when the rest of the patch train is applied as well. Change-Id: Idca235029bf2e68d403230d55308820cab61a6c0 Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51806 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-04-07vc/amd/fsp/cezanne: add platform_descriptors.hFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib16f133b270c99c6e060e5bd0c156cbb03293474 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51197 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-04-07mb/google/mancomb: Enable USB ports in devicetreeEric Lai
BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I375ad38da14189de2ae2713082a80e8cdb2fe5f3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52119 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-04-07mb/google/mancomb: Enable PCIe devices in devicetreeEric Lai
BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Id6c20b32ddafe415132ce70abf5381ff3aad13f7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52118 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-07mb/google/mancomb: Add initial fch irq routingEric Lai
BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I850a3ecc8776593d97f4162e812a39991caa30ef Reviewed-on: https://review.coreboot.org/c/coreboot/+/52117 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-07mb/google/mancomb: Add eSPI GPIO back to init tableEric Lai
GPIOs should be configured in ramstage even if they are configured in an earlier stage. BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I07d5c46d6ea6dc2bc9ab265d0c01772d653884cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/52123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-07mb/google/mancomb: Configure UART0 gpio in early stageEric Lai
BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I2d4ec1556ac7136c454eb025ff99aafbf49b8982 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52122 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-07mb/google/mancomb: Enable DISABLE_SPI_FLASH_ROM_SHARINGEric Lai
BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I1d28c2335b095a77285dcb261a0dffe96d129c46 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52125 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-07mb/google/mancomb: Enable early EC Software SyncEric Lai
BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I9768feaadf2423acd50a71e9a2310b4ab2d1a2a8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52124 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-07libpayload/storage: Add NVMe driverThomas Heijligen
Tested with qemu virtual NVMe and Intel hardware. Works with FILO. Change-Id: Ie75b1dc743dac3426c230c57ee23b771ba3a6e0c Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33582 Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-073rdparty/blobs: Update blobs pointer to f388b6794e6fRaul E Rangel
mb/google/guybrush: Update APCB - disable debug mb/google/guybrush: Add APCB to get through memory training soc/mediatek/mt8192: Add EMI Settings of 8GB Normal Mode soc/mediatek/mt8192: Update MCUPM firmware soc/mediatek/mt8192: Add version info for SSPM TEST=Boot guybrush to OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I445d753c712670fe80efcdf29459736df2b76666 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52112 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-04-07util/bincfg/Makefile: change ./bincfg to $(abspath $(TARGET))Martin Roth
This change was promised as a follow-up in change ID: Ic0302f663cbc931325334d0cce93d3b0bf937cc6 Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I9a41b46cc90684746e2b240c8ee442df1b3d7cf5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52111 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-04-07mb/sapphire/pureplatinum/cmos.default: Remove `volume` entryNicola Corna
Following commit de50d39, remove the `volume` entry from cmos.default. Change-Id: Ieebafffa0d2fbf6cdd24cff4ddefe090a727cbfa Signed-off-by: Nicola Corna <nicola@corna.info> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52027 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-06intel/tigerlake: Add Acoustic featuresShaunak Saha
On VCCin there was an oscillation which occurred just as the kernel started (kernel starting... message). On some devices, this behavior seems even worse. In previous platforms VCCin toggled for a few ms and then was stable. For volteer, this happens at the same point in time for around 40ms. However, it starts oscillating again later in the boot sequence. Once at the root shell, it seems to oscillate indefinitely at around 100-200Hz (very variable though). To fix this we need to control the deep C-state voltage slew rate.We have options for controlling the deep C-state voltage slew rate through FSP UPDs. This patch expose the following FSP UPD interface into coreboot: - AcousticNoiseMitigation - FastPkgCRampDisable - SlowSlewRate We are setting SlowSlewRate for all volteer boards to 2 which is Fast/8. TGL has a single VR domain(Vccin). Hence, the chip config is updated to allow mainboards to set a single value instead of an array and FSP UPDs are accordingly set. BUG=b:153015585 BRANCH=firmware-volteer-13672.B TEST= Measure the change in noise level by changing the UPD values. Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Change-Id: Ica7f1f29995df33bdebb1fd55169cdb36f329ff8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50870 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-04-06soc/intel/common: Prevent SMI storm when setting SPI WPD bitAngel Pons
From Skylake/Sunrise Point onwards, there are two BIOS_CNTL registers: one on the LPC/eSPI PCI device, and another on the SPI PCI device. When the WPD bit changes from 0 to 1 and the LE bit is set, the PCH raises a TCO SMI with the BIOSWR_STS bit set. However, the BIOSWR_STS bit is not set when the TCO SMI comes from the SPI or eSPI controller instead, but a status bit in the BIOS_CNTL register gets set. If the SMI cause is not handled, another SMI will happen immediately after returning from the SMI handler, which results in a deadlock. Prevent deadlocks by clearing the SPI synchronous SMI status bit in the SMI handler. When SPI raises a synchronous SMI, the TCO_STS bit in the SMI_STS register is continously set until the SPI synchronous SMI status bit is cleared. To not risk missing any other TCO SMIs, do not clear the TCO_STS bit again in the same SMI handler invocation. If the TCO_STS bit remains set when returning from SMM, another SMI immediately happens and clears the TCO_STS bit, handling any pending events. SPI can also generate asynchronous SMIs when the WPD bit is cleared and one attempts to write to flash using SPI hardware sequencing. This patch does not account for SPI asynchronous SMIs, because they are disabled by default and cannot be enabled once the BIOS Interface Lock-Down bit in the BIOS_CNTL register has been set, which coreboot already does. These asynchronous SMIs set the SPI_STS bit of the SMI_STS register. Clearing the SPI asynchronous SMI source should be done inside the SPI_STS SMI handler, which is currently not implemented. All of this goes out of the scope of this patch, and is currently not necessary anyway. This patch does not handle eSPI because I cannot test it, and knowing if a board uses LPC or eSPI from common code is currently not possible, and this is beyond the scope of what this commit tries to achieve (fix SPI). Tested on HP 280 G2, no longer deadlocks when SMM BIOS write protection is on. Write protection will be enforced in a follow-up. Change-Id: Iec498674ae70f6590c33a6bf4967876268f2b0c8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50754 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-06Revert "mb/google/guybrush: Disable GFX"Raul Rangel
This reverts commit 52e61945588bc327844acc4658426861d63ad189. Reason for revert: Graphics actually works now. I should have abandoned this CL. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I83aac3a2c616bb434706f23e36549760bc764080 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51985 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-04-06lint: checkpatch: Only exclude specific src/vendorcode/ subdirectoriesJulius Werner
Some of the src/vendorcode/ directories are used to import a whole codebase from somewhere else which uses a completely different coding style. For those directories, excluding them from checkpatch makes sense. However, other directories are simply implementing vendor-specific extensions that were written by coreboot developers specifically for coreboot in coreboot's coding style. Those directories should be covered by checkpatch. This patch narrows the existing blanket exception of src/vendorcode/ to the amd, cavium, intel and mediatek directories (which actually include large amounts of foreign source). The eltan, google and siemens directories (which seem to contain code specifically written for coreboot) will now be covered by checkpatch. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I1feaba37c469714217fff4d160e595849e0230b9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51827 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-06lint: checkpatch: Ignore ASSIGN_IN_IF and UNNECESSARY_ELSE errorsJulius Werner
This patch disables checkpatch warnings about two style constructs that are not illegal in coreboot style and can in my opinion be useful in certain situations. The first is an assignment in if conditions like this: if ((ret = func())) return ret; This can save a line compared to the alternative construct which may help readability, especially in functions that need to do a lot of these. More importantly, the while-equivalent of this construct is not forbidden (and a lot more useful, because certain things become very complicated to write without it), and it seems weird to forbid one but not the other. We already have GCC warnings that enforce an extra set of parenthesis to highlight that this is an assignment instead of a comparison, so the risk of typos or confusion between those two is already mitigated anyway. The second is the use of `else` after return like this: if (CONFIG(TYPE_A)) return response_for_type_a; else return response_for_type_b; While the else is redundant in this case, it serves to highlight the symmetry and equivalence in importance of the two paths. There are certainly other situations where the construct of if (something_went_wrong) return error; if (something_else_went_wrong) return other_error; if (...) is more useful, but this usually suggests an "either abort here or continue on the main path" style flow, whereas the code with `else` is more suitable to highlight an "either one or the other" flow with two equal-weighted options. I think the programmer should pick which style best represents the intentions of their code in these cases, and don't understand why one of the two should be categorically forbidden. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I130598057c1800277a129ae6b927e961d6e26e42 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51551 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-06util/crossgcc: Add date to the toolchain revisionMartin Roth
With the current version method, it's not possible to determine if a different version is older or newer than the current version without digging into the repository and finding the dates for the version numbers. This change adds the commit date to the start of the toolchain version which will let us tell at a glance how old or new the toolchain is. It's not perfect because multiple toolchain commits can go in on the same day, but adding the time made the string even longer, and really doesn't help that much. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I9c6d27667b922dc15e7a6e132e1beff69eed839c Reviewed-on: https://review.coreboot.org/c/coreboot/+/48901 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-04-06mb/facebook/monolith: Allow TPM initializationWim Vervoorn
TPM_INIT is disabled by default. This prevents TPM to be operational when VBOOT is disabled. Remove the TPM_INIT disable. BUG=N/A TEST=tested on facebook monolith with VBOOT disabled. Change-Id: I84d525a18c84643903922fef0a11dcf98abbbe4d Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52052 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2021-04-06mb/facebook/monolith: Update VBOOT settingsWim Vervoorn
Make sure the standard for the board options are set when VBOOT is enabled. BUG=N/A TEST=tested on facebook monolith Change-Id: I9749eeeffbd26e7c5caaeb7c0407a765cf093337 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52053 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2021-04-06soc/intel/alderlake: Add LPC and IGD device Ids for Alderlake MMaulik V Vaghela
Added new LPC and IGD device IDs for Alderlake M. Also, added entry for CPUID_ALDERLAKE_M_A0 in report_platform.c TEST=Check if platform information print is coming properly in coreboot Change-Id: If33c43da8cbd786261b00742e342f0f01622c607 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50138 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-06mb/google/volteer/var/lindar: Increase Goodix touchscreen reset delay to 180 msKevin Chang
1. Follow GT7375P Programming Guide_Rev.0.6 to increase reset delay to 180ms. BUG=b:181711141 TEST=Build and boot lindar to OS. Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Change-Id: I82222ca094eead7e9e691857e128243cfe7c310e Reviewed-on: https://review.coreboot.org/c/coreboot/+/51739 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-04-06Lindar/Lillipup: Enable Bayhub SD card reader power-saving modeKevin Chang
Enable Bayhub SD card reader power-saving mode for Lindar and Lillipup. BUG=b:173676531 TEST=Boot to OS and test with SD card function. Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Change-Id: I923d6e1beacd007c0e501f39c1f434c3e1085b9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/51623 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-04-06mem_pool: Track the last two allocations (not just one)Julius Werner
This patch changes the mem_pool implementation to track the last two allocations (instead of just the last) and allow them both to be freed if the mem_pool_free() calls come in in reverse order. This is intended as a specific optimization for the CBFS cache case when a compressed file is mapped on a platform that doesn't natively support memory-mapping flash. In this case, cbfs_map() (chaining through to _cbfs_alloc() with allocator == NULL) will call mem_pool_alloc(&cbfs_cache) to allocate space for the uncompressed file data. It will then call cbfs_load_and_decompress() to fill that allocation, which will notice the compression and in turn call rdev_mmap_full() to map the compressed data (which on platforms without memory-mapped flash usually results in a second call to mem_pool_alloc(&cbfs_cache)). It then runs the decompression algorithm and calls rdev_munmap() on the compressed data buffer (the latter one in the allocation sequence), leading to a mem_pool_free(). The remaining buffer with the uncompressed data is returned out of cbfs_map() to the caller, which should eventually call cbfs_unmap() to mem_pool_free() that as well. This patch allows this simple case to succeed without leaking any permanent allocations on the cache. (More complicated cases where the caller maps other files before cbfs_unmap()ing the first one may still lead to leaks, but those are very rare in practice.) Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Ic5c4c56a8482752ed65e10cf35565f9b2d3e4b17 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52087 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2021-04-06verstage: Add debug print when returning from verstageJulius Werner
RETURN_FROM_VERSTAGE is a somewhat tricky construct that we don't normally do otherwise in coreboot. While it works remarkably well in general, new development can lead to unintentional interactions with confusing results. This patch adds a debug print to the verstage right before returning to the bootblock so that it's obvious this happens, because otherwise in some cases the last printout in the verstage is about some TPM commands which can be misleading when execution hangs after that point. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I9ca68a32d7a50c95d9a6948d35816fee583611bc Reviewed-on: https://review.coreboot.org/c/coreboot/+/52086 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-06decompressor: Add CBFS_VERIFICATION supportJulius Werner
CBFS_VERIFICATION requires the CBFS metadata hash anchor to be linked into an uncompressed stage, but for platforms using COMPRESS_BOOTBLOCK, this is only the decompressor stage. The first CBFS accesses are made in the bootblock stage after decompression, so if we want to make CBFS_VERIFICATION work on those platforms, we have to pass the metadata hash anchor from the decompressor into the bootblock. This patch does just that. (Note that this relies on the decompressor data remaining valid in memory for as long as the metadata hash anchor is needed. This is always true even for OVERLAP_DECOMPRESSOR_ROMSTAGE() situations because the FMAP and CBFS metadata necessarily need to have finished verification before a new stage could be loaded.) Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I2e6d7384cfb8339a24369eb6c01fc12f911c974e Reviewed-on: https://review.coreboot.org/c/coreboot/+/52085 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-06cbfs: Add file data hashing for CONFIG_CBFS_VERIFICATIONJulius Werner
This patch adds file data hashing for CONFIG_CBFS_VERIFICATION. With this, all CBFS accesses using the new CBFS APIs (cbfs_load/_map/_alloc and variants) will be fully verified when verification is enabled. (Note that some use of legacy APIs remains and thus the CBFS_VERIFICATION feature is not fully finished.) Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Ic9fff279f69cf3b7c38a0dc2ff3c970eaa756aa8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52084 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2021-04-06cbfs: Simplify cbfs_load_and_decompress() and stop exporting itJulius Werner
With the last external user to cbfs_load_and_decompress() gone, we can stop exporting this function to the rest of coreboot and make it local to cbfs.c. Also remove a couple of arguments that no longer really make a difference and fold the stage-specific code for in-place LZ4 decompression into cbfs_prog_stage_load(). Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I4b459650a28e020c4342a66090f55264fbd26363 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52083 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-04-06mb/intel/adlrvp: Update iDisp Link UPD settingsFrancois Toguo
This changes updates the iDisp-Link T-mode to 8T required for ADL-M. The update is made because the HW on ADL now supports 8T mode. BUG=None TEST= build and boot ADL-M RVP and verify HDMI/DP audio playback. Signed-off-by: Francois Toguo <francois.toguo.fotso@intel.com> Change-Id: I9d0bf7dc76348f7e184e8496f042badc30bf3211 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51353 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-06mb/intel/adlrvp: Enable Camera in ADL-M RVPVarshit Pandya
1. Configure Power Enable, Reset and Clock GPIO for both camera 2. Use same ASL code as ADL-P RVP Configure RST, PWR_EN and IMGCLKOUT signals for WFC and UFC TEST=Build, Boot and Verify streaming in both Camera Signed-off-by: Varshit Pandya <varshit.b.pandya@intel.com> Change-Id: I70636eaa8d9bdf23d649e811b3ff4f33b1bc604e Reviewed-on: https://review.coreboot.org/c/coreboot/+/50265 Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-06mb/google/kukui: Add flag for MIPI_DSI_MODE_LINE_END ANX7625Jitao Shi
Config ANX7625 line data end same time on all line. BUG=b:173603645 BRANCH=kukui TEST=Display is normal on Kukui Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> Change-Id: Ia1dc217138a98a79ef2f31225b52ba2b1aaf8672 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51435 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2021-04-06nb/intel/i440bx: Enable bootblock consoleKeith Hui
Change-Id: Ie59593d3e3e0c455ffd3813980d1c2fe801c3c18 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41461 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-04-06mb/asus/p2b: Add option table supportKeith Hui
Just do it already. The two SCSI-specific options for p2b-{ls,ds} will be wired up in a followup. They will be ignored by boards without the hardware. Change-Id: Ia43d502219d7c23d21f49d651113e3d653c6e9f4 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41560 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-04-06arch/x86: Provide readXp/writeXp helpers in arch/mmio.hAngel Pons
These p-suffixed helpers allow dropping pointer casts in call-sites, which is particularly useful when accessing registers at an offset from a base address. Move existing helpers in chipset code to arch/mmio.h and create the rest accordingly. Change-Id: I36a015456f7b0af1f1bf2fdff9e1ccd1e3b11747 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51862 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-06sb/intel/i82371eb: Do not read PM/SMBus I/O ports at runtimeKeith Hui
Commit 023fdaffd1 (mb/asus/p2b: Refactor southbridge ACPI stuff) moved the southbridge ACPI stuff to its own file. It also (prematurely) listed PM and SMBus I/O port ranges as a #defined fixed value. Since these two ranges are not expected to change at runtime anyway, we can simply drop the ASL code doing the read. Change-Id: Id5adb37d047621d7c8faf81607ceea4cbcac3d34 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41093 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-06nb/intel/haswell: Ensure MCH has acked raminitAngel Pons
Haswell MRC.bin can return zero even when raminit did not complete successfully. When this happens, the memory controller will not have acknowledged raminit: the mc_init_done_ack bit in the MC_INIT_STATE_G register will be zero, and memory accesses will lock up the system. To handle this situation more gracefully, check the mc_init_done_ack bit after running MRC. If the bit is not set, log a fatal error and halt. Tested on Asrock B85M Pro4: - With badly-seated DIMMs, MRC raminit fails and coreboot dies. - After reseating the DIMMs, the board still boots successfully. Change-Id: I144bf827f65cd0be319c44bf3d407ddc116b129d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51940 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-04-06sb/intel/*/smihandler.c: Correct BIOS_CNTL access widthAngel Pons
The BIOS_CNTL register is 8 bits wide on all affected platforms. Change-Id: Iaf9267cf27847d54ed50e1f9ae29011d0e99cf8e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51939 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-06mb/google/guybrush: Disable GFXRaul E Rangel
This is locking up the OS. For now this will unblock booting. BUG=b:183971103 TEST=Boot guybrush to OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Id2b96eedf38c9038169407418c6d36f13299fb62 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51928 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2021-04-06drivers/i2c/nau8825: Support nau8825 for ACPI GPIO descriptorsSeven Lee
Add definitions to describe GPIOs in generated ACPI objects. The method allow either write a GpioInt() or Interrupt() descriptor. Signed-off-by: Seven Lee <wtli@nuvoton.com> Change-Id: I37fec7b0b9324dbfb61b7a8bea80f45026c54409 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51922 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-06security/intel/cbnt: Fix ibbhash command lineChristian Walter
Using brackets here seems to break the build for _some_ environments. Removing the brackets fixes it and works just fine. Change-Id: I965b0356337fe74281e7f410fd2bf95c9d96ea93 Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51974 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Deomid "rojer" Ryabkov <rojer9@fb.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-04-06mb/google/dedede/var/cret: Support LTE moduleDtrain Hsu
Add LTE module support into devicetree and associated GPIO configuration. BUG=b:183774169 BRANCH=dedede TEST=Build the cret board. Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I14684bb30e46bf845a401649f56b16b60db379e8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51844 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-04-06mb/google/dedede/var/cret: Add audio supportDtrain Hsu
Select the drivers for DA7219 codec and MAX98360A spk amp BUG=b:183771323 BRANCH=dedede TEST=emerge-dedede coreboot chromeos-bootimage Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I3fd7c374fc8214e25a28fb9ba62a9c8473d3f755 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51841 Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-06mb/purism/librem_14: acpi: Remove unused EC defineTim Crawford
The define for color keyboard setting has never been used, as it was added as a Kconfig selection when ec/system76/ec was introduced. Change-Id: Iec9134e226382d32783342ef1d37c6f6f6caeb6e Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51946 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2021-04-06mb/clevo/cml-u: acpi: Remove unused EC defineTim Crawford
The define for color keyboard setting has never been used, as it was added as a Kconfig selection when ec/system76/ec was introduced. Change-Id: I6c8f17b398fb4645feb830c2ad28ac98fb744280 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51945 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2021-04-06mb/system76: acpi: Remove unused EC defineTim Crawford
The define for color keyboard setting has never been used, as it was added as a Kconfig selection when ec/system76/ec was introduced. Change-Id: Ib83d4510c14ddf083660e42175ab093403792cac Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51944 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2021-04-06soc/intel/alderlake: Update variable SD3C to only track enabled devicesJohn Zhao
Each TCSS DMA is grouped together with two PCIe RPs in terms of PM flow. This change ensures that SD3C is updated for the TCSS DMA devices corresponding to the TBT RP ports. If TBT port is 0 or 1, SD3C for DMA0 is updated, else for DMA1. BUG=None TEST=Built Alderlake image successfully. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: Ia3462dfbb287a374960a57bb4c3541db2a435611 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51965 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-06soc/intel/alderlake: Remove TCSS DMA _DSM methodJohn Zhao
The kernel does not need TCSS DMA's _DSM method. This change simply removes this method. BUG=None TEST=Built Alderlake image successfully. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I313f9c8913bb8cf54581c5460ac3fb1597291ad5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51964 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-04-06mb/google/kukui: fix the issue of getting error panel_idxuxinxiong
Current get panel_id is over sku_id() >> 4, but sku_id is combined with wfc_id/lcm_id/sku_id, so the panel_id value is wfc_id << 4 | lcm_id() in fact. When wfc_id is not 0, the panel_id will be wrong. So only get the low 4 bits for the panel_id. BUG=b:183779755 BRANCH=kukui TEST=emerge-kukui Change-Id: I63e0c8a2719462a9b979afe52a27c78b9fc804e8 Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51853 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-04-06src/drivers/generic/nau8315: Add nau8315 supportSeven Lee
Configure and enable GPIO for speaker amp nau8315. change return acpi string name directly. Signed-off-by: Seven Lee <wtli@nuvoton.com> Change-Id: Ie883d65ced3cd95fe318ba0914ed806ff592258d Reviewed-on: https://review.coreboot.org/c/coreboot/+/51971 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-04-06mb/google/kukui: katsu: update the EDID and initial codeSunway
The EDID and initial code are provided by STA (the vendor). BUG=b:183969078 TEST=Boots on Chromebook Katsu and displayed developer firmware screen successfully. Signed-off-by: Sunway <lisunwei@huaqin.corp-partner.google.com> Change-Id: I54e72c072b47d2be264ed7f0700812a6c704a104 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51918 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-06device/i2c_bus.c: Correct code styleFrans Hendriks
device: Correct code style Revise the following aspects to follow coreboot's coding style: - Drop braces for single-statement condition. - Remove unnecessary newlines. BUG = N/A TEST = Build Compulab Intense-PC with secure oprom enabled Change-Id: I78ce97b0ce1587119a71893c867c2dd062552a31 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50190 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
2021-04-06vendorcode/intel/FSP2_0/CPX-SP: Declare struct RC_VERSION non-packedDeomid "rojer" Ryabkov
It is a bug acknowledged by Intel (IPS case 00600003) that has been fixed for SRP but won't be fixed for CPX. This fixes field offsets for fields that follow SYSTEM_STATUS.RcVersion Change-Id: I5248734e2f086d39bb75b7b1359e60dfd8704200 Signed-off-by: Deomid "rojer" Ryabkov <rojer9@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51545 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-06vc/eltan/security/mboot/Kconfig: Add dependency of VBOOTFrans Hendriks
VENDORCODE_ELTAN_MBOOT should not be used when VBOOT is enabled. Hide VENDOCODE_ELTAN_MBOOT when VBOOT is enabled. BUG = N/A TEST = run `make menuconfig` and boot Facebook FBG1701 Change-Id: Iac57103431cc7efac5b6019f180572d255e683ab Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52021 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
2021-04-06mb/facebook/monolith: Remove disabled devices from devicetreeWim Vervoorn
All known on-chip PCI devices are disabled in the chipset devicetree. So they are removed from the mainboard devicetree. BUG=N/A TEST=tested on facebook monolith Change-Id: Ie67cd8afc9ea92e9fd7caed4338cb25a68d94cb1 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52018 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2021-04-06mb/facebook/fbg1701/vboot-rw.fmd: Expand RO_SECTIONFrans Hendriks
The romstage does not fit in RO_SECTION. Increase the CBFS size in RO_SECTION. BUG = N/A TEST = Boot Facebook FBG1701 with VBOOT enabled. Change-Id: I2f1020acb3ec99d4cddbaa05b0998fe32b470d3e Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52026 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-04-06include/rules.h: Add ENV_TEST definitionJakub Czapiga
Some functions/macros like assert() require redefinition for testing purposes. ENV_TEST is introduced to make it possible without using bypass hacks. This patch also adds a global __TEST__ define to TEST_CFLAGS for all test targets in order to enable ENV_TEST. Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: Ib8f2932902a73a7dbe181adc82cc18437abb48e8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51803 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-04-06tests: Add lib/uuid-test test caseJakub Czapiga
Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: I7f8498ad3d9d0d68b34aa0b48daca60545ec3f4e Reviewed-on: https://review.coreboot.org/c/coreboot/+/51976 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2021-04-06mb/ocp/tiogapass: use IPMI driver functionality for "POST complete"Michael Niewöhner
Replace the mainboard-specific code for "POST complete" signalling with devicetree entries for using the newly introduced IPMI driver functionality. Test: Boot the machine via the BMC web interface and check that sensors get read correctly by the IPMI firmware when the payload starts. Change-Id: I7503dec4e72810db8dfe74f72638b466a3d66748 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48671 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-06mb/ocp/tiogapass: correct "POST complete" pad initial valueMichael Niewöhner
On OCP Tioga Pass the pad GPP_B20 is used as output for signalling "POST complete" to the BMC. According to the schematics and the code in `ramstage.c`, the signal is active-low. There is an external pull-up resistor. To make the signalling work as it should, set the initial output value to `high`. Change-Id: I82fbda1caba9163ba3b2e38f494a0cefa27e657f Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48670 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-06drivers/tpm/Kconfig: TPM_INIT for measured boot onlyFrans Hendriks
TPM_INIT depends on VBOOT but should also depend on VENDORCODE_ELTAN_xBOOT. Add dependency. TPM_INIT will be enable for measured boot only. BUG = NA TEST = Boot Facebook FB1701 with possible combinaties of VBOOT, measured boot and eltan security. Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Change-Id: I03f8457731c73c653bd82b1042bda3fc2d797feb Reviewed-on: https://review.coreboot.org/c/coreboot/+/52050 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
2021-04-06include/cbfsglue.h: Use BIOS_INFO for LOG macroWim Vervoorn
The ERROR() and LOG() macros both used BIOS_ERR as the error level. The messages generated by the LOG() macro are informational items. Change to BIOS_INFO to reflect that. BUG=N/A TEST=tested on facebook monolith Change-Id: I3827a7d65a9d70045a36fb8db4b2c129e1045122 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52019 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2021-04-06mb/intel/shadowmountain: Add Cr50 supportAamir Bohra
This patch includes changes to add Cr50 support over GSPI0. BUG=b:175579964 TEST=Verify TPM init is done and boots to kernel Change-Id: I33f7427d1675190f65acf14679be93546e6db69a Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51086 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-06util/kconfig_lint: Drop exception for paths without quotesNico Huber
The tree is clean at the moment. Change-Id: I1be3b6c2f3b54b5c10ad3d5c6f0a6fd7e490c6bc Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52066 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-06mb/msi/h81m-p33: Put MAINBOARD_DIR in double quotesNico Huber
Change-Id: I73160985c025cb0945a4ac16c8c3ebb988d3858f Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52065 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-06mb/google/brya: Move early GPIO config earlierTim Wawrzynczak
The recent refactor of console UART GPIOs to mainboard's bootblock caused brya boards to lose the first ~5 lines of the logs from bootblock. Rename bootblock_mainboard_init to bootblock_mainboard_early_init so that the UART pads will be ready by the time the console is initialized. BUG=b:184319828 TEST=First lines from report_platform.c are now seen in UART output Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I4a4fadcc091bf9b1c9894f9afaf42baff63c73a3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52062 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-04-06lib: Add obvious definition for `calloc`Tim Wawrzynczak
The calloc() function is useful in addition to malloc and friends, so add the obvious definition. Change-Id: I57a568e323344a97b35014b7b8bec16adc2fd720 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51949 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-06mb/prodrive/hermes: Properly pack EEPROM structuresAngel Pons
To pack a struct, the `__packed` attribute must come after the `struct` keyword. Moreover, unions cannot be packed (structs inside unions can, though). Correct uses of `__packed` so that EEPROM structs get packed. Change-Id: I39d2c9ebc370605d5623b134189aa95a074ec7c3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51980 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: <wouter.eckhardt@prodrive-technologies.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-04-06Docs/mb/lenovo/t420: List working, tested and non-working featuresPiotr Szymaniak
Signed-off-by: Piotr Szymaniak <szarpaj@grubelek.pl> Change-Id: I6fb4a8da44125b4280d37d0cf7c372f8024fb2d1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51952 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-06mb/lenovo/t420: Copy HDA verbs from vendor firmwarePiotr Szymaniak
Background story (I think that's what great in opensource - ppl leave there part of their lives): ;-) While trying to fix audio jack not working with coreboot and Windows 10 with some help from hell__ and nico_h on IRC nico_h discovered that t420 and t430 hda_verb.c are the same: <nico_h> oddly, in coreboot source T420 and T430 have the same numbers for very different codecs... I suspect copy-pasta Difference between /sys/class/sound/cardX/hwCXDY/init_pin_config in vendor BIOS helped with the updated config. Connecting audio jack now works flawless both in Linux and Windows. Audio-related keyboard buttons: volup, voldown, mute works fine both in Linux (Debian-based) and Windows 10. mutemic button works (tested ie. with xev) but both in Linux and Windows 10 wont light up or makes any effect. +-----------------------------------+ | init_pin_config dump from: | +----= VENDOR =---+---= coreboot =--+ | 0x19 0x04211040 | 0x19 0x04211040 | | 0x1a 0x61a19050 | 0x1a 0x61a19050 | | 0x1b 0x04a11060 | 0x1b 0x04a11060 | | 0x1c 0x6121401f | 0x1c 0x6121401f | | 0x1d 0x40f001f0 | 0x1d 0x40f001f0 | | 0x1e 0x40f001f0 | 0x1e 0x40f001f0 | | 0x1f 0x90170110 | 0x1f 0x90170110 | | 0x20 0x40f001f0 | 0x20 0x40f001f0 | | 0x22 0x40f001f0 | 0x22 0x40f001f0 | | 0x23 0x90a60170 | 0x23 0x90a60170 | +-----------------+-----------------+ Tested-by: Piotr Szymaniak Signed-off-by: Piotr Szymaniak <szarpaj@grubelek.pl> Change-Id: Ie5eba84e5ea590b7db00e189cd68e714bee7e410 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51612 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-06drivers/intel/fsp1_1: Drop dead MMA codeAngel Pons
The only FSP 1.1 platform with MMA support is Skylake. As it now uses Kaby Lake FSP 2.0, this code is no longer useful. Drop it. Change-Id: I819c3152bdea0fdad629793d96136ef134429fbd Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51951 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-04-06mb/google/zork: update DRAM table for morphiusKevin Chiu
Add Micron DDR4 memory part MT40A1G16RC-062E-B 16Gb index was generated by gen_part_id BUG=b:184024142 BRANCH=zork TEST=emerge-zork coreboot Change-Id: I890a2da38c8cd1963e9ee7c5df9410b2b2538e9f Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51947 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-04-06util: Add DDR4 generic SPD for Micron MT40A1G16RC-062E-B 16GbKevin Chiu
Add SPD support for Micron DDR4 memory part MT40A1G16RC-062E-B 16Gb BUG=b:184024142 TEST=none Change-Id: I438310fb74d96953bc83374df3109e4c56192a5f Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44861 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-04-06mb/google/zork/var/vilboz: Update WiFi SAR for Vilboz/Vilboz360 LTEFrank Wu
Loading wifi_sar-vilboz-2.hex for vilboz LTE sku. Loading wifi_sar-vilboz-3.hex for vilboz360 LTE sku. BUG=b:183902165, b:176211194, b:183913210 BRANCH=firmware-zork-13434.B TEST=Build coreboot and load the wifi sar table by fw_config Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: I37a40456970e3f1dc8b2eed26aa23e3d75748222 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51935 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-04-05fsp2_0: Replace fspld->get_destination() callback with CBFS allocatorJulius Werner
The Intel FSP 2.0 driver contains a custom construct that basically serves the same purpose as the new CBFS allocator concept: a callback function to customize placement of a loaded CBFS file whose size is initially unknown. This patch removes the existing implementation and replaces it with a CBFS allocator. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I0b7b446a0d2af87ec337fb80ad54f2d404e69668 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52082 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-04-05cbfs: Make `mdata` argument to cbfs_allocator_t constJulius Werner
Right before CB:49334 was submitted, I changed the signature of cbfs_allocator_t function pointers to include another argument passing in the already loaded CBFS metadata (to allow for the rare edge case of allocators needing to read CBFS attributes). This interface is not meant to be able to modify the passed-in metadata, so to clarify that and prevent potential errors, we should declare the argument const. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I7e3756490b9ad7ded91268c61797cef36c4118ee Reviewed-on: https://review.coreboot.org/c/coreboot/+/52081 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-04-05vc/amd/fsp/picasso/platform_descriptors: fix typos in enum element namesFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5cad6a6a585320b33bfab7b3950888241f7c179c Reviewed-on: https://review.coreboot.org/c/coreboot/+/52028 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-05mb/google/guybrush/var/guybrush: Add Codec and Speaker configrationKarthikeyan Ramasubramanian
Enable I2C2 in devicetree and fill ACPI information for Codec and Speaker amplifiers. Pass correct IRQ GPIO for headset jack. BUG=None BRANCH=None TEST=Ensure that the Codec and Speaker Amplifiers are detected in i2cdetect. Change-Id: I1ae52a8bbaa0181c906cd14a94de22e0250ed4c1 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52046 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-05mb/google/guybrush: Add Bluetooth configurationKarthikeyan Ramasubramanian
Configure the BT disable GPIO to logic low in order to enable Bluetooth. Add USB ACPI configuration for BT device. BUG=b:182201890 TEST=Build and boot to OS. Change-Id: I647c301e2db6d4a7c5c8cb31cbc47a44cba5e734 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51963 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-04-05soc/amd/cezanne: Add soc/msr.hRaul E Rangel
This is a copy of picasso. BUG=b:184151560 TEST=Compared with the cezanne PPR. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ia4bc40daa971c126c2596837155312d411b91a06 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51983 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-04-05mb/google/guybrush: Enable camera power GPIOIvy Jian
Configure camera power GPIO to high BUG=b:182207799 TEST=Build and boot to OS then checked camera device existence with lsusb Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Change-Id: Ie894167e3c4f8efdb3710599c6ff3a9fc975adb6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52017 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bhanu Prakash Maiya <bhanumaiya@google.com> Reviewed-by: Martin Roth <martinroth@google.com>
2021-04-05mb/google/guybrush: Update GPIO configurationMartin Roth
Initialize all eSPI signals including PCIE_RST0_L early for EC communication. - Set PCIE_RST0_L to a GPIO and set it high to release the bus. This is a temporary workaround until PCIE_RST_L comes up on its own. - Make sure all GPIO muxes initialized early are re-initialized. BUG=b:183340503 TEST=Boot Guybrush Change-Id: I512cb8b435dc8412cd46189e741ad94e5a24699e Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51675 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-05soc/amd/common: Add some ESPI register definitionsMartin Roth
Use definitions instead of magic numbers clean up some whitespace while I'm here. BUG=b:183207262 TEST=Build Change-Id: Ieae53b12e5303641fb3f180c47468aaa6906e9af Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51747 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-04-05util/bincfg: Clean up MakefileMartin Roth
- Enable warnings - Enable warnings as errors - Remove debug flag -g - Add targets for all, distclean, and help - Add dependency of the bincfg file for output targets - Add all phony targets to .PHONY BUG=None TEST=Build all targets Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Ic0302f663cbc931325334d0cce93d3b0bf937cc6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50654 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-05mb/google/mancomb: Add ACPI support for Chrome ECEric Lai
BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ibce15d2e4340515353a33c593d065df50a15286a Reviewed-on: https://review.coreboot.org/c/coreboot/+/51628 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2021-04-05mb/google/mancomb: Enable eSPI VW SCI eventsEric Lai
Mancomb does not have a dedicated SCI pin so it uses VW. BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Id315ab448209d9c93494f7689361e45f8a6ed001 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51627 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2021-04-05mb/google/mancomb: Enable Chrome EC SKUID and BOARDIDEric Lai
BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I70283c8d93b5cbabdaf5a8ab947d5f8444940dff Reviewed-on: https://review.coreboot.org/c/coreboot/+/51626 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2021-04-05mb/google/mancomb: Add smihandlerEric Lai
BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I52411917d9e7e8f8d9ac5d1c9b426a58ba09f5ae Reviewed-on: https://review.coreboot.org/c/coreboot/+/51625 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2021-04-05mb/google/mancomb: Enable Chrome ECEric Lai
BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Id1617be67bfc5d2f142358ae8a70c3e575a94c6d Reviewed-on: https://review.coreboot.org/c/coreboot/+/51489 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2021-04-05soc/amd: Make espi_clear_decodes privateRaul E Rangel
espi_setup already clears most of the controller registers. So this change consolidates the clear logic into one spot. This shouldn't result in a behavior change on Picasso. Picasso already has the eSPI decodes clear on boot, so this change is a nop. BUG=b:183524609 TEST=Boot guybrush to the OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ic57689e50febd29796d8ac8d99c81e41fee5b41c Reviewed-on: https://review.coreboot.org/c/coreboot/+/52064 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-04-05soc/amd: Make espi_configure_decodes privateRaul E Rangel
This is only ever called after espi_setup. 55861 - AMD System Peripheral Bus Overview also says that io ranges should be configured before enabling the BUS_MASTER bit. BUG=b:183524609 TEST=Boot guybrush to OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I074e487d8768a578ee889a125b9948e3aa6c7269 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52059 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-04-05mb/google/dedede/var/sasuke: Update DPTF parametersSeunghwan Kim
Remove TSR2, use DPTF parameters from internal thermal team. BUG=b:183749595 BRANCH=dedede TEST=emerge-dedede coreboot Change-Id: I3182b96bf36c8d07299fe435a29e6b8c0b8a6927 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51970 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2021-04-05mb/google/dedede/var/sasuke: Configure I2C times for touchpad/audioSeunghwan Kim
Configure I2C rise/fall time in device tree to ensure I2C CLK runs accurately at I2C_SPEED_FAST (< 400 kHz). Measured I2C frequency just as below after tuning: I2C0(touchpad): 385 kHz I2C4(audio): 380 kHz BUG=b:180335053 BRANCH=dedede TEST=Build and check after tuning I2C clock is under 400kHz Change-Id: Ic92ee0379456e80260a8026bc38ee41325dad6d2 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51335 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-04-05soc/amd/common/espi: Clear DNCMD_COMPLETE on completionRaul E Rangel
Tidy up the interrupt status. This will leave SLAVE0_INT_STS = 0. BUG=b:183524609 TEST=Boot guybrush to OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I950cfb81521e35758c120a482670cfdb924201d2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52056 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-05soc/amd/common/espi: Reset eSPI registers to known stateRaul E Rangel
This sets the eSPI registers to the reset values specified in the PPR. On Cezanne, the PSP modifies these registers such that the eSPI peripheral cannot send DEFER packets. This causes random bus errors. These reset values are identical to what is currently used on Zork. I didn't clear out ESPI_DECODE because it's currently being done by cb:51749. BUG=b:183524609 TEST=Boot guybrush to the OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ic3a9860747aac78121358b4499d8a38052236c0c Reviewed-on: https://review.coreboot.org/c/coreboot/+/52058 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-04-05soc/amd/common/espi: Add missing eSPI register definitionsRaul E Rangel
These are defined in the public Picasso PPR - 55570-B1 Rev 3.15. BUG=b:183524609 TEST=Build guybrush Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I7e601f767327e0a24a086146623af039388b2e7b Reviewed-on: https://review.coreboot.org/c/coreboot/+/52057 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Rob Barnes <robbarnes@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>