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AgeCommit message (Expand)Author
2015-04-13vbnv flash: use proper SPI flash offset for NVRAMVadim Bendebury
2015-04-13chromeos: Move common VBNV offsets to a headerDavid Hendricks
2015-04-13vboot1: Set BEFORE_OPROM_LOAD flag for VbInit()Duncan Laurie
2015-04-13elog: Fix regression that caused elog to omit "System boot" eventJulius Werner
2015-04-13elog: Correct behavior when FMAP section doesn't exist on ChromeOSJulius Werner
2015-04-13urara: add support for DMA coherent memory areaIonela Voinescu
2015-04-13t132: add RAM repair to cluster 1Yen Lin
2015-04-13vboot1: Fix compilation error with CONFIG_ARCH_ROMSTAGE_ARM64 enabledYidi Lin
2015-04-13broadwell: Enable double self refresh by defaultDuncan Laurie
2015-04-13pistachio: increase the size of romstage to 36KIonela Voinescu
2015-04-13vboot2: use offset to vboot2 work buffer instead of absolute addressDaisuke Nojiri
2015-04-13arch: armv7: Fix cache sync instructions.Deepa Dinamani
2015-04-11hp/pavilion_m6_1035dx/cmos.layout: Remove unused optionsAlexandru Gagniuc
2015-04-10fmap: allocate memory as much as discovered fmap sizeDaisuke Nojiri
2015-04-10rk3288: reset edp after edp clock source selecthuang lin
2015-04-10Add google/veyron_mighty boardKatie Roberts-Hoffman
2015-04-10rockchip: support displayhuang lin
2015-04-10veyron*: select VIRTUAL_DEV_SWITCHDavid Hendricks
2015-04-10veyron: Adapt to new board revisionsJulius Werner
2015-04-10veyron_jerry: Port CPU overshoot preventionJulius Werner
2015-04-10veyron*: sdram_get_ram_code() -> ram_code()David Hendricks
2015-04-10veyron*: use gpio_base2_value() in board_id()David Hendricks
2015-04-10veyron: Change VCC10_LCD_PWREN_H to allowed maximum of 2.5VJulius Werner
2015-04-10veyron_jerry: Remove board ID based assumptionsJulius Werner
2015-04-10veyron: Change eMMC enable pin to be pulled (not driven) highDoug Anderson
2015-04-10Add google/veyron_jerry boardKatie Roberts-Hoffman
2015-04-10storm: copy WiFi calibration data in the CBMEMVadim Bendebury
2015-04-10tegra132: psci: add cpu_on/off supportJoseph Lo
2015-04-10arm64: No need of invalidating cache line for secondary CPU stackFurquan Shaikh
2015-04-10arm64: Add support for save/restore registers for CPU startup.Furquan Shaikh
2015-04-10arm64: Add macro to invalidate stage 1 TLB entries at current ELFurquan Shaikh
2015-04-10arm64: Add conditional read/write from/to EL3 assembly macros.Furquan Shaikh
2015-04-10arm64: Add function for reading TCR register at current ELFurquan Shaikh
2015-04-10tegra132: Make non-vboot2 memlayout more usefulFurquan Shaikh
2015-04-10tegra132: Change memlayout to have PRERAM and POSTRAM CBFS CacheFurquan Shaikh
2015-04-10tegra132: Bump up ramstage to 256KFurquan Shaikh
2015-04-10google/rush_ryu: Add speaker amp config for AD4567 on P0/P1Tom Warren
2015-04-10tegra132: prepare cpu startup in psciAaron Durbin
2015-04-10arm64: psci: actually inform SoC layer of CPU_ON entryAaron Durbin
2015-04-10google/rush_ryu: Remove long delay when turning on AVDD_DSI_CSIJimmy Zhang
2015-04-10tegra132: Increase size of bootblock due to overflowTom Warren
2015-04-10arm64: ensure secondary CPU's stack tops are not in the cacheAaron Durbin
2015-04-10arm64: add timeout waiting for CPUs to come onlineAaron Durbin
2015-04-10tegra132: always bring up PLLDAaron Durbin
2015-04-10tegra132: rename clock_display() to clock_configure_plld()Aaron Durbin
2015-04-10google/rush_ryu: audio: Setup clocks for AHUB, I2S1, codec, etc.Tom Warren
2015-04-10tegra132: Set dc to resize the difference between framebuffer and panelJimmy Zhang
2015-04-10google/rush_ryu: devicetree: Add framebuffer resolution settingsJimmy Zhang
2015-04-10tegra132: Add framebuffer parametersJimmy Zhang
2015-04-10tegra132: Pass panel spec to lib_sysinfoJimmy Zhang
2015-04-10tegra132: Expand ramstage size to 208k (from 192k)Jimmy Zhang
2015-04-10tegra132: Add dsi driverJimmy Zhang
2015-04-10google/rush_ryu: devicetree: Add dsi panel mode settingsJimmy Zhang
2015-04-10tegra132: Add panel mode specJimmy Zhang
2015-04-10google/rush_ryu: dsi: Enable panel related vdd and clocksJimmy Zhang
2015-04-10google/rush_ryu: Disable EC SW sync for proto boards before proto3Furquan Shaikh
2015-04-10tegra132: Increase space for romstage in memlayoutFurquan Shaikh
2015-04-10urara: support building with CHROMEOS enabledVadim Bendebury
2015-04-10baytrail: correct NC pin to GPO pin according to BYT platform design guideKane Chen
2015-04-10samus: Log EC panics to eventlogShawn Nematbakhsh
2015-04-10cros_ec: Retry failed VBNV transactionsJulius Werner
2015-04-10samus: Enable vr_slow_rampShawn Nematbakhsh
2015-04-10x86: Support reset routines in bootblockLee Leahy
2015-04-10broadwell: Correct XHCI offset for USB 3.0 portsJulius Werner
2015-04-10broadwell: Set PCIe replay timeout to 0xDDuncan Laurie
2015-04-10samus: Use codec internal 1.8V as DACREF sourceBen Zhang
2015-04-10samus: Set MICBIAS1 to 2.970VBen Zhang
2015-04-10baytrail: add code for supporting 2x ddr refresh rateKane Chen
2015-04-10broadwell: Add configuration for tuning VR for C-state operationsDuncan Laurie
2015-04-10samus: Adjust SATA Gen3 TX voltage amplitudeDuncan Laurie
2015-04-10broadwell: Preserve VbNv around cmos_initDuncan Laurie
2015-04-10broadwell: Add function to apply PRR to a range of SPI flashDuncan Laurie
2015-04-10samus: Add clear_recovery_mode_switch functionDuncan Laurie
2015-04-10samus: Set current backlight PWM valueDuncan Laurie
2015-04-10broadwell: Turn off panel backlight in S5 SMI handlerDuncan Laurie
2015-04-10broadwell: Skip steps when disabling PCIe portDuncan Laurie
2015-04-10broadwell: Remove XHCI workarounds on WPTDuncan Laurie
2015-04-10broadwell: Only do pre-graphics delay when running option romDuncan Laurie
2015-04-10PCI - Add interrupt disable bit definitionLee Leahy
2015-04-10samus: Add ACPI binding for rt5677 codec SPIBen Zhang
2015-04-10broadwell: Fix PCIe ports programming sequences to enable HSIOPCWenkai Du
2015-04-10samus: Add RT5677 ACPI/DT bindings with _DSDDuncan Laurie
2015-04-10broadwell: Update SATA Gen3 TX adjustment registersDuncan Laurie
2015-04-10broadwell: Add a few bits to finalize stepDuncan Laurie
2015-04-10baytrail: fix the coding error on PCIe L1 exit latencyKevin L Lee
2015-04-10TPM: Reduce buffer size to fix stack overflowJulius Werner
2015-04-10Baytrail: Prior to PCI scan, wait for LCTL to be active in 50 msKevin Hsieh
2015-04-10tpm: Remove error message for unknown resource typeDuncan Laurie
2015-04-10Broadwell: Set boot_mode of pei_data before running reference codeKenji Chen
2015-04-10samus: Move board version to a separate fileDuncan Laurie
2015-04-10tpm: Add ramstage driver and interrupt configurationDuncan Laurie
2015-04-10tpm: Move the LPC TPM driver to a subdirectoryDuncan Laurie
2015-04-10broadwell: Increase I2C SDA hold timing to 300nsChiranjeevi Rapolu
2015-04-10broadwell: add RCBA posting read after writingWenkai Du
2015-04-10Broadwell: Synchronization with FRC for Root Port Power ManagementKenji Chen
2015-04-10broadwell: Skip DDI-A enable in S3 resumeDuncan Laurie
2015-04-10broadwell: Add support for ACPI \_GPE._SWSDuncan Laurie
2015-04-10baytrail: Switch from ACPI mode to PCI mode for legacy supportMarc Jones
2015-04-10southbridge/intel/fsp_rangeley/ : Spellcheck + Formattingnicky sielicki
2015-04-10vboot: Remove unused 2lib header pathRandall Spangler
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