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2022-08-12mb/google/rex: Update mainboard properties for BB retimerSubrata Banik
This patch backport commit 9e23d017f555bad (mb/google/brya: Update mainboard properties for BB retimer upgrade) for Google/Rex. BUG=b:224325352 TEST=Able to build and boot MTLRVP. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I508858683cf3cdb0cab5a564fef4a242f8a6679e Reviewed-on: https://review.coreboot.org/c/coreboot/+/66541 Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-12mb/google/rex: Describe TCSS USB ports in devicetreeSubrata Banik
This patch describes the TCSS USB ports in devicetree to generate ACPI code at runtime. The ACPI code includes the port definition, location, type information. BUG=b:224325352 TEST=Able to build and boot MTLRVP. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I08613b31aad47cbf573ed1b5fc68c91cf973e190 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66540 Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-08-12mb/google/rex: Add OC pin programming for USB2 Port 8Subrata Banik
This patch adds OC pin programming for USB2 Port 8. BUG=b:224325352 TEST=Able to build and boot MTLRVP. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ic9dcaef5972d6c0e9fe264445ea10fcd9a82619f Reviewed-on: https://review.coreboot.org/c/coreboot/+/66543 Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-08-12soc/intel/meteorlake: Have non prefetchable MMIO for IGD BAR0Wonkyu Kim
Enable SOC_INTEL_GFX_NON_PREFETCHABLE_MMIO for MTL to fix guc driver failure. BUG=b:241746156 TEST=boot to OS and check guc driver loading successful Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: Ifc20935bccdda55db3e57eecd37a4260b3f1a2d1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66613 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-12soc/intel/common: Ignore prefetch PCI attribute for IGD BAR0Wonkyu Kim
From Meteorlake, IGD BAR0(GTTMMADR) is changed to 64bit prefetchable. Due to the prefetchable attribute, resource allocation for IGD BAR0 is assigned WC memory and it causes kernel driver failure. For avoiding kernel driver failure, ignore prefetch PCI attribute for IGD BAR0 to assign UC memory. We're working on publishing below information. - IGD BAR0(GTTMMADR) is changed to 64bit prefetchable BAR - GTTMMADDR BAR should be always mapped as UC memory although marked Pre-fetchable. BUG=b:241746156 TEST=boot to OS and check guc driver loading successful Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: I76d816d51f32f99c5ebcca54f13ec6d4ba77bba5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66403 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-08-11util/amdfwtool: Rename Sabrina to MendocinoJon Murphy
'Mendocino' was an embargoed name and could previously not be used. Update amdfwtool for consistency with the correct naming convention. BUG=b:239072117 TEST=Builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I673a9b99d207603b605756fc7d277c54c5d0f311 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66467 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-08-11treewide: Rename Sabrina to MendocinoJon Murphy
'Mendocino' was an embargoed name and could previously not be used in references to Skyrim. coreboot has references to sabrina both in directory structure and in files. This will make life difficult for people looking for Mendocino support in the long term. The code name should be replaced with "mendocino". BUG=b:239072117 TEST=Builds Cq-Depend: chromium:3764023 Cq-Depend: chromium:3763392 Cq-Depend: chrome-internal:4876777 Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I2d0f76fde07a209a79f7e1596cc8064e53f06ada Reviewed-on: https://review.coreboot.org/c/coreboot/+/65861 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-08-11util/lint: Add .gitignore files to list that don't need a licenseMartin Roth
Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Change-Id: I568a357b40e8bb69b2b26752d241f06adfbe029e Reviewed-on: https://review.coreboot.org/c/coreboot/+/66503 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2022-08-11lib: Add SPDX identifiers to files missing themMartin Roth
This adds SPDX identifiers to the remaining source files in the lib directory that don't already have them. A note on gcov-iov.h - As machine generated content, this file is believed to be uncopyrightable, and therefore in the public domain, so gets the CC-PDDC license even though there is code in the file. Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Change-Id: Ifcb584d78a55e56c1b5c02d424a7e950a7f115dc Reviewed-on: https://review.coreboot.org/c/coreboot/+/66502 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2022-08-11include: Add SPDX identifiers to files missing themMartin Roth
This adds SPDX identifiers to the remaining source files in the include directory that don't already have them. Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Change-Id: I0dbf4c839eacf957eb6f272aa8bfa1eeedc0886f Reviewed-on: https://review.coreboot.org/c/coreboot/+/66501 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-11southbridge: Add SPDX identifiers to files missing themMartin Roth
This adds SPDX identifiers to the remaining source files in the southbridge directory that don't already have them. Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Change-Id: If74aa82a7c40293198e07e81ceac52bd8ca8ad27 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66500 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-11drivers: Add SPDX identifiers to files missing themMartin Roth
This adds SPDX identifiers to the remaining source files in the drivers directory that don't already have them. Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Change-Id: I97f96de857515214069c3b77f3c781f7f0555c6e Reviewed-on: https://review.coreboot.org/c/coreboot/+/66499 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-11src/mb: Add SPDX identifiers to files missing themMartin Roth
This adds SPDX identifiers to the remaining source files in the mainboard directory that don't already have them. Change-Id: I1adc204624f3ab6fcafd8fbb239e6d69e057973a Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66498 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2022-08-11src/soc/intel/mtl: Add VPU supportSrinidhi N Kaushik
This change adds support for enabling VPU on MTL SoC. BUG=b:240665069 TEST=build coreboot mtlrvp Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: Ie79b45f34a669b9ff777599cb85217abac6cb74e Reviewed-on: https://review.coreboot.org/c/coreboot/+/66566 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2022-08-10mb/google/nissa/var/joxer: Add WiFi SAR tableMark Hsieh
Add WiFi SAR table for joxer. BUG=b:239788985 TEST=build FW and checked SAR table can load by WiFi driver. Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: Ia8dddf454e441840233fa4405704ee1f0a8ed86c Reviewed-on: https://review.coreboot.org/c/coreboot/+/66522 Reviewed-by: Reka Norman <rekanorman@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-10docs/utils/ifdtool: Fix waning of malformed tableLance Zhao
Signed-off-by: Lance Zhao <lance.zhao@gmail.com> Change-Id: Idc90c6e8186320979a72563fb5dcdc8fce760e72 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66562 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-10soc/intel/tigerlake: Add USBOTG and CrashLog to irq tableFrans Hendriks
FSP reports missing IRQ for devices. Add USBOTG (D20:F1) and CrashLog & Telemetry (D10:F0) to irq_constrain. Bug = N/A TEST = Build and boot Siemens AS-TGL1 Change-Id: Ic02d33045a07a6888ba97d8f2c6fa71bc7e363e8 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66390 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-08-10util/lint & LICENSES: Add PDDC as a "license" for corebootMartin Roth
The Creative Commons Public Domain Dedication and Certification is not a license in the common sense in that it's stating that the associated file is already in the public domain (having no copyright), and is not actually putting it in the public domain like the CC-C0 license does. The use for this in coreboot is for unlicensable files - either blank files or files with no creative content. This allows these files to have the SPDX identifier to identify them as having no known copyright for open source license compliance. If CC-PDM-1.0 is ever included in the list of SPDX licenses, that would probably fit better, but because the public domain mark isn't actually a license, and because "public domain" isn't well defined, CC-PDM was rejected as a SPDX identifier. For further information: https://web.archive.org/web/20201018194411/https://github.com/spdx/license-list-XML/issues/988 Change-Id: Ibb300ecd066cde2a016195c2beca76a460c588e3 Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66496 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2022-08-10util/lint & LICENSES: Add GCC-exception-3.1 to license exceptionsMartin Roth
The gcov files in the lib directory are licensed GPL 3.0 with the GCC runtime library exception. Add this as a valid license so that the files can get a correct SPDX identifier. Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Change-Id: I1cf9c3125592741923c9b4481038055f24fe6ab1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66495 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2022-08-10LICENSES: Add missing licenses and exceptionsMartin Roth
These licenses and exceptions are allowed by coreboot's license checker, but the copies of the licenses were missing from the LICENSES directory. Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Change-Id: Ic4233e556de08275fe50f1ec83828f9470b4b566 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66494 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2022-08-10mb/google/zork: Set vw_irq_polarity from low to highRaul E Rangel
The EC used on zork uses a level high interrupt. This change configures the polarity correctly. The eSPI config is baked into RO verstage. The zork ToT build doesn't use signed verstage since it's incompatible with the ToT version of vboot. This means we can safely switch the keyboard IRQ polarity. NOTE: Do not cherry pick this into the Zork firmware branch! BUG=b:160595155 TEST=On morphius verify keyboard works as correctly and no spurious interrupts are thrown on S0i3 resume. Also verified keyboard and mouse work correctly in windows. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I8d3195522f3bd5e477635494c7156683aae0ff0a Reviewed-on: https://review.coreboot.org/c/coreboot/+/66291 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-08-10mb/google/{zork,guybrush,skyrim},soc/amd/espi: Fix vw_irq_polarityRaul E Rangel
The default state for the IRQ lines when the eSPI controller comes out of reset is high. This is because the IRQ lines are shared with the other IRQ sources using AND gates. This means that in order to not cause any spurious interrupts or miss any interrupts, the IO-APIC must use a low polarity trigger. On zork/guybrush/skyrim the eSPI IRQs are currently working as follows: * On power on/resume the eSPI controller drives IRQ 1 high. * eSPI controller gets configured to not invert IRQ 1. * OS configures IO-APIC IRQ 1 as Edge/High. * EC writes to HIKDO (Keyboard Data Out) which causes the EC to set IRQ1 high. * eSPI controller receives IRQ 1 high, doesn't invert it, and leaves IRQ 1 as high. This results in missing the first interrupt. * When the x86 reads from HIKDO, the EC deasserts IRQ1. This causes the eSPI controller to set IRQ1 to low. We are now primed to catch the next edge high interrupt. This is generally not a problem since the linux driver will probe the 8042 with interrupts off. On S3/S0i3 resume since the eSPI controller comes out of reset driving the IRQ lines high, we trigger a spurious IRQ since the IO-APIC is configured to trigger on edge high. This results in the 8042 controller getting incorrectly marked as a wake trigger. By configuring the IO-APIC to use low polarity interrupts, we no longer lose the first interrupt. This also means we can use a level interrupt to match what the EC actually asserts. We use the `Interrupt` keyword instead of the `IRQ` keyword in the ACPI because the linux kernel will ignore the level/polarity parameters for the `IRQ` keyword and default to `edge/high. `Interrupt` doesn't have this problem. The PIC is not currently configured anywhere and it defaults to an edge/high trigger. We could add some code to configure the PICs trigger register, but I don't think we need the functionality right now. For zork and guybrush, this change is a no-op. eSPI is configured in verstage which is located in RO, and we have already locked RO for these devices. We will need to figure out how to properly set the `vw_irq_polarity` for these devices. BUG=b:218874489, b:160595155, b:184752352, b:157984427, b:238818104 TEST=On zork, guybrush and skyrim $ suspend_stress_test --post_resume_command 'cat /sys/devices/platform/i8042/serio0/wakeup/wakeup35/active_count' Verify keyboard works as expected and no interrupt storms are observed. On morphius I verified keyboard and mouse work on windows as well. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I4608a7684e34ebb389e0e55ceba7e7441939afe7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54924 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-08-09MAINTAINERS: Add lists for soc/intel/meteorlake and mb/google/rexKapil Porwal
Change-Id: Ia5def4cf86b47ac96ba5fc6ec86a139d5ad2765e Signed-off-by: Kapil Porwal <kapilporwal@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66533 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-08-09mb/google/nissa/var/pujjo: Enable USB3.0 port 3 for WWANStanley Wu
Pujjo support WWAN device, enable USB3.0 port 3 for WWAN device BUG=b:241322361 TEST=Build and boot on pujjo Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com> Change-Id: Iafe2ea18663794138e0a27879fc108d23eb81456 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66457 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-08-09utils: Add initial version of "remove_unused_code" scriptMartin Roth
This script creates a patch to remove all of the coreboot code that a platform doesn't use. This is useful for auditing the codebase for an individual platform or releasing a platform's code. Unlike the script that Sage used that did something similar, this keeps the entire Kconfig tree (Though in a single file), all makefiles that are required to build, and the standard build tools can still be used. This will allow for much easier re-integration back into the coreboot codebase if code is released after running this. This is just the initial version and more features needed to be added to make it fully functional. - It should be able to build multiple configurations to retain the code for all of those configurations. - Flag to remove submodules files as well - Additional variable flags to replace hardcoded values. - The list of makefiles that need to be kept is pretty long, and could be updated so that they aren't needed by the top level makefiles. - Add flag to show changed files - Show number of files before and after script is run Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Iec69db2ad1358846d649db627b6d60ac8c2204e4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59169 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-08-09mb/google/brya/var/ghost: update arbitrage gpio.c headerKevin Chowski
This update follows suggestions from Martin Roth about the contents of the comment. Change-Id: Ic296bcd6a0fb250426f5d75aac69a3fa0f2aaf32 Signed-off-by: Kevin Chowski <chowski@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66555 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-08-09util/amdfwtool: Fix ISH_B directory offsetKarthikeyan Ramasubramanian
On boards which use both PSP recovery A/B layout as well as VBOOT A/B layout, ISH_B directory entry is pointing directly to PSP Level2 directory. This is not correct and either ISH_B should be marked as not present or it should point to the ISH_A directory itself which in turn point to PSP L2 directory. Fix it by choosing the latter option. BUG=None TEST=Build and boot to OS in Skyrim with PSP verstage. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I0a7a56e98de3f85669ff8ec2fcd1687aa33576a9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66445 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-08-08mb/google/brya: Select SOC_INTEL_COMMON_UFS_SUPPORT for NissaMeera Ravindranath
BUG=b:238262674 TEST=Build and check ufs.c file gets compiled for Nissa boards Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Change-Id: Idc5ad922b97bd1e65e5023f9126c43e42cfc38a5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66064 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Reka Norman <rekanorman@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-08soc/amd/sabrina: Rename PSP SPL defaultMarshall Dawson
Change the SPL file from the 'cezanne' placeholder to a mendocino filename. Also, move the default location to blobs/mainboard since it's not board-agnostic. BUG=b:241543152 BUILD=Enable feature and build amd/chausie Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I47647c5d926484e25e3f893e72c671554e277a56 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66465 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-08-08soc/amd/sabrina: Rename PSP whitelist defaultMarshall Dawson
Change the name of the whitelist file from the 'cezanne' placeholder to a mendocino path/to/file. Also, as whitelist files won't be pushed into a public repo, modify the path to point to site-local. Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I49bbf1335606567735e36ed9bda1314bfc6247d6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66464 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-08-07soc/amd/sabrina: Use new mendocino amd_blobsMarshall Dawson
Modify sabrina's fw.cfg to point to the proper directory and use the standard names, as released by AMD. The name 'sabrina' was an alias used for the Mendocino product. The public-facing builds have been using Cezanne blobs, renamed as Sabrina or SBR, but can now take advantage of the appropriate blobs. BUG=b:239072117 TEST=Build amd/chausie Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: Id646844e41980802be1e39dce96e5adaace4311d Reviewed-on: https://review.coreboot.org/c/coreboot/+/66463 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-08-073rdparty/amd_blobs: Advance submodule pointerMarshall Dawson
This picks up the following changes 83c44ad mendocino: Add additional SPI configs 5141d91 mendocino: Add all blobs from PI 1.0.0.1 3b29a7d cezanne: Upgrade microcode patch to 00A50F00h BUG=239072117 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I1060dc7bec8f436dccf270bc3abde75cb09bb591 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66462 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-08-07mb/google/skyrim: Resolve boot behaviorJon Murphy
Move GPIO init for SSD_AUX_RESET_L to ensure that eMMC devices will be initialized in time for the nominal boot flow. BUG=b:237701972 TEST=Boots to OS BRANCH=none Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I610966fd9d31581f15d8bcd51f8a116c27fd6311 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66461 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-07mb/google/brya/var/ghost: Pull EN_PP3300_TCHSCR highJack Rosenthal
This gets the display working. BUG=b:240884260 BRANCH=firmware-brya-14505.B TEST=display works in both depthcharge and linux Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: I03edac865d68ef48e86d47a04f27ed84894f2f7f Reviewed-on: https://review.coreboot.org/c/coreboot/+/66395 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2022-08-07superio/ite/common/early_serial.c: ite_kill_watchdog: set timeout to 0Michał Kopeć
Set the watchdog timeout to 0 in ite_kill_watchdog, as in some ITE models it is set to non-zero by default, activating the watchdog despite us setting the control register to 0. Based on: - "ITE IT8786E-I Preliminary Specification V0.4.1 (For D Version)" - Linux it87_wdt driver Change-Id: I1e78e2acc96e9dd0f283c5c674d3277d26cdee26 Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66189 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-08-07mb/amd/chausie: Add Kconfig prompts to EC stringsMarshall Dawson
Make the default Microchip EC firmware path/to/file values overridable by adding prompts to the strings. Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I300f78a11960dbe193165fcb379b7190e3de4545 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66446 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-08-07pciexp_device: Handle unsupported requests in pciexp_get_ext_cap_offset()Bill XIE
Looking into pciexp_get_ext_cap_offset() it seems a little hackish and prone to endless loops. Either it should limit the loop or bail out when pci_read_config32() returns 0xffffffff, meaning "Unsupported Requests". This commit fixes an endless loop when the queried PCIe device is downstream of a legacy PCI bus which doesn't support extended config space, thus pci_read_config32() will return 0xffffffff, for example, the combination below with CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS enabled. TEST=Build and boot to OS in ASUS P8C WS with the following peripherals and CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS enabled: 00:1c.4 PCI bridge [0604]: Intel Corporation 7 Series/C210 Series Chipset Family PCI Express Root Port 5 [8086:1e18] (rev c4) 00:1c.4/00.0 SATA controller [0106]: Marvell Technology Group Ltd. 88SE9170 PCIe 2.0 x1 2-port SATA 6 Gb/s Controller [1b4b:9170] (rev 13) 00:1e.0 PCI bridge [0604]: Intel Corporation 82801 PCI Bridge [8086:244e] (rev a4) 00:1e.0/00.0 PCI bridge [0604]: PLX Technology, Inc. PEX 8111 PCI Express-to-PCI Bridge [10b5:8111] (rev 21) 00:1e.0/03.0 FireWire (IEEE 1394) [0c00]: VIA Technologies, Inc. VT6306/7/8 [Fire II(M)] IEEE 1394 OHCI Controller [1106:3044] (rev c0) 00:1e.0/00.0/00.0 Network controller [0280]: Qualcomm Atheros AR93xx Wireless Network Adapter [168c:0030] (rev 01) with 00:1c.4/00.0 being successfully tuned with pciexp_tune_dev(), and 00: 1e.0/00.0/00.0 not tuned as expected. Change-Id: Ibb92548c47288b40e851fcc0a8a37937e8bdbf3c Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66439 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-08-07payloads/tianocore: Remove the option for CorebootPayloadPkgSean Rhodes
Recent changes to both coreboot and edk2 means that UefiPayloadPkg seems to work on all hardware. It has been tested on: * Intel Core 2nd, 3rd, 4th, 5th, 6th, 8th, 8th, 9th, 10th, 11th and 12th generation processors * Intel Small Core BYT, BSW, APL, GLK and GLK-R processors * AMD Stoney Ridge and Picasso This includes the problematic Lenovo X230s. The most likely fixes are: * Configuring the PCI Base and Length in edk2 * Fixes to the HostBridgeLib in edk2 * Adjustment to the SD/eMMC initialisation timeout This means we can now remove the already deprecated option for CorebootPayloadPkg and the legacy 8254 timer build option. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ice7b7576eb3d32ea46e5138266b7df3fbcdcf7ea Reviewed-on: https://review.coreboot.org/c/coreboot/+/65721 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-08-07soc/intel/alderlake: Fix RPL-P 282 15W GT ICC MAXJeremy Compostella
The software used to read the document listing the VR settings turns out to not be perfectly compatible. Indeed, it displays a value of 55A for RPL-P 282 15W GT ICC MAX while the correct value actually is 40A. After a thorough review using the software used to create the document, it is the only value presenting a discrepancy. BRANCH=firmware-brya-14505.B BUG=b:239797178 TEST=build and boot Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Change-Id: Iee293c87a66f0cd32714766e3ad81eee1a411723 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66057 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Anil Kumar K <anil.kumar.k@intel.corp-partner.google.com> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2022-08-07soc/amd/sabrina: Enable PSP Crypto Co-Processor (CCP) DMAKarthikeyan Ramasubramanian
Boot issue while using FW slot A has been root-caused to the usage of same TLB to map HW Crypto engines and SPI flash. With upcoming PSP release, this TLB usage conflict has been resolved. Hence enable CCP DMA. BUG=b:240175446 TEST=Build and boot to OS in Skyrim with PSP verstage using CCP DMA. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I2b12adb7e94e489bf07963a6f9a829cf4b36ad5c Reviewed-on: https://review.coreboot.org/c/coreboot/+/66444 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-08-07soc/amd/sabrina: Re-init eSPI in bootblockKarthikeyan Ramasubramanian
Currently bootblock does not initialize eSPI if it is already done in PSP verstage. But some other component is clobbering the eSPI configuration causing timeouts in EC communication after the boot flow hits x86. To workaround this issue, re-initialize eSPI in bootblock. BUG=b:217414563 TEST=Build and boot to OS in Skyrim with PSP verstage. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I41c0b2816a106a6a547f3cb372693e1bb7f23734 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66443 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-08-07mb/google/rex: Remove depedency on board id for early GPIO configTarun Tuli
This adds a default early GPIO table in the case of us not being able to identify a valid board ID. Primarily, this is useful in the case of EC issues to ensure that debug interfaces (e.g. UART) are always up and available. BUG=b:238165977 TEST=Boots and no errors on simics Signed-off-by: Tarun Tuli <taruntuli@google.com> Change-Id: I135dc6c29bc23195afe5c78eb79992691652d9e4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66394 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-08-07pci_device: Add a function to find PCI capability ID recursivelyBill XIE
Some PCI capabilities should only be enabled if it is available not only on a device, but also all bridge upstream of it. Checking only the device and the bridge just above it may not be enough. Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Change-Id: I1237d3b4b86dd0ae5eb586e3c3c407362e6ca291 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66383 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-07pciexp_device: Fix a bug in pciexp_enable_ltr()Bill XIE
'parent_cap' should be found from 'parent' instead of 'dev'. Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Change-Id: I99dab83d90287ca924d30dc4aeac0ff96e877e5c Reviewed-on: https://review.coreboot.org/c/coreboot/+/66385 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-08-07vc/intel/fsp: Update ADL N FSP headers from v3222.03 to v3267.01Saurabh Mishra
Update generated FSP headers for Alder Lake N from v3222.03 to v3267.01. Changes include: - Add UPD Lp5BankMode - Update UPD Offset in FspmUpd.h BUG=b:240373012 BRANCH=None TEST=Build using "emerge-nissa intel-adlnfsp"and boot Nissa. Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com> Change-Id: I7b921e2aa467593a1c764fc554e2e83e8bb522e8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66222 Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-07mb/google/brya/variants/agah: update dptf settingTony Huang
1. Add active policy 2. Set critical policy trigger point to 105C 3. Correct TSR location BUG=b:240634844 TEST=emerge-draco coreboot values provided and verified by thermal team Change-Id: I0d91bad03cbdeea5c84b533580ac98072ce0110b Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66351 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2022-08-07mb/google/brya/acpi: Fix PERST# handling in GC6 exitTim Wawrzynczak
PERST# is supposed to be de-asserted in GC6 exit, but the original patch used the CTXS Method, which drives a GPIO low, instead of STXS, because PERST# is active-low. This patch fixes that. BUG=b:214581763 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ib0adb8efe5e2cc733ae2228614c58c124ba3f11b Reviewed-on: https://review.coreboot.org/c/coreboot/+/66402 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-08-07mb/google/brya/var/ghost: Disable LID_SHUTDOWNCaveh Jalali
The lid sensor is on a daughterboard which can cause unintended shutdowns when not connected. Disable lid sensor based shutdown behavior in depthcharge until we have a better solution. BUG=b:240005819 BRANCH=firmware-brya-14505.B TEST=booted ghost, no longer shuts down due to missing lid sensor Change-Id: I69f70255dee1b69e05b112c0174f5f52d1368837 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66295 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-08-07soc/intel/tigerlake: Expose In-Band ECC config to mainboardFrans Hendriks
Support for feature "In-Band ECC" not available for Tiger Lake Similar to Elkhart Lake, Tiger Lake also provides this feature. Ported from Elkhart Lake (CB:55668) Bug = N/A TEST = Build and boot Siemens AS-TGL1 Change-Id: Ie54d5f6a9747fad0105d0f8bf725be611bb8cf60 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66372 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-08-07mb/google/brya/acpi: Fix NVJT subfunction IDsTim Wawrzynczak
The POWERCONTROL and PLATPOLICY NVJT subfunctions were incorrectly set to 2 and 3, respectively. While looking at the ACPI code, Nvidia noticed these are supposed to be 3 and 4, also respectively, so this patch fixes that. BUG=b:214581763 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I0f808aba7072b943ee2fad20e06ff39a9b54903d Reviewed-on: https://review.coreboot.org/c/coreboot/+/66374 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-08-07commonlib/timestamp_serialized: Add comment explaining "ignore for x86"Reka Norman
BUG=b:240624460 TEST=None Signed-off-by: Reka Norman <rekanorman@chromium.org> Change-Id: I8542c9bb624a366bc1bb01f6eae66ba97520d19c Reviewed-on: https://review.coreboot.org/c/coreboot/+/66381 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-06mb/google/rex: Add memory config for rexTarun Tuli
Configure the rcomp, dqs and dq tables based on the schematic dated July 17/2022 and Intel Kit #573387. TEST=Built successfully Signed-off-by: Tarun Tuli <taruntuli@google.com> Change-Id: I092f42db252052382d377a4ae48dc25f73080a3b Reviewed-on: https://review.coreboot.org/c/coreboot/+/66202 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-06util/elogtool: Mark redundant boot mode event type as `deprecated`Subrata Banik
This patch adds `_DEPRECATED_` tag to ChromeOS boot mode related event logging types as below: * ELOG_TYPE_CROS_RECOVERY_MODE <---- to record recovery boot reason while booting into recovery mode * ELOG_TYPE_CROS_DEVELOPER_MODE <--- if the platform is booted into developer mode. * ELOG_TYPE_CROS_DIAGNOSTICS <---- if the platform is booted into diagnostic mode. Drop static structure `cros_deprecated_recovery_reasons` as it has been replaced by vb2_get_recovery_reason_string() function. ELOG_TYPE_FW_BOOT_INFO event type is now used to record all those related fw boot info along with ChromeOS boot mode/reason etc. BUG=b:215615970 TEST=Build and boot google/kano to ChromeOS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I932952ce32337e2d54473667ce17582a90882da8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65802 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-08-05mb/google/brya/var/vell: Set GPP_B2 NC for RGB keybaordRobert Chen
When GPP_B2 output high, there is a leakage path. This patch fix it by setting the pin NC. BUG=b:233959105 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot Change-Id: I3c833d5d62c715960dcb27494a0b9b93c91e8f2f Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66382 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-08-05vc/intel/fsp/mtl: Update header files from 2253_00 to 2304_01Srinidhi N Kaushik
Update header files for FSP for Meteor Lake platform to version 2304_01, previous version being 2253_00. FSPM: 1. Removed CpuCrashLogDevice 2. Address offset changes FSPS: Includes below new UPDs 1. VpuEnable 2. SerialIoI3cMode 3. ThcAssignment 4. PchIshI3cEnable BUG=b:240665069 TEST=emerge-rex intel-mtlfsp Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: I9740e5877af745124d573425da623e814d8df5d7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66289 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-05soc/intel/mtl: Remove deprecated FSP optionSrinidhi N Kaushik
Remove the reference to `CpuCrashLogDevice` UPD since FSP v2304.01 has deprecated this UPD. BUG=b:240665069 TEST=build rex coreboot Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: I23223fd7936a60d974229b553de255a7dcf4416b Reviewed-on: https://review.coreboot.org/c/coreboot/+/66357 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-08-04mb/intel/adlrvp: shorten MAINBOARD_PART_NUMBER to fix buildNick Vaccaro
Building firmware for Brya is currently broken due to the RO_FWID region for adlrvp_m_ext_ec bloating past 64 characters. The CONFIG_MAINBOARD_PART_NUMBER is catenated onto the CONFIG_MAINBOARD_VENDOR string, which for Intel, makes for a very long trunk string that the kernel version will then be added to form the RO_FWID string. For Intel, that trunk string is already pretty long at : "Intel Corporation_Alder Lake Client Platform". Shortening the CONFIG_MAINBOARD_PART_NUMBER should address this issue for now. BUG=b:241273391 TEST="emerge-brya coreboot chromeos-bootimage" and verify it builds successfully Change-Id: Ie862c87dd9a24743f249f1b10862ca6f3295db23 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66397 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2022-08-04soc/amd/cezanne/cppc: drop duplicate newlineFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I774be6d80e0aae725ecb1027501c8d66e0bf5a08 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66399 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2022-08-04soc/amd/cezanne/cppc: reduce visibility of cpu_init_cppc_configFelix Held
This function is only called from the same compilation unit, so turn it into a static function. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5c2deaa46f69c763df9612e39415b37c60d631be Reviewed-on: https://review.coreboot.org/c/coreboot/+/66398 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2022-08-04MAINTAINERS: Update maintainer for Purism mainboardsJonathon Hall
Change-Id: Ie5c2d01e13cafdbfd629ebe52af8b1f0cc8f20be Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66378 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-08-03util/cbfstool: Fix truncate command error handling and cbfs_image_from_buffer()Jakub Czapiga
Check return value of cbfs_truncate_space() in cbfs_truncate(). Remove return from cbfs_image_from_buffer() to inform about invalid image region when incorrect offset header was provided. Also change header offset provided to mentioned function in cbfs_expand_to_region() and cbfs_truncate_space() from zero to HEADER_OFFSET_UNKNOWN, as they do not support images with cbfs master header. Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: Ib009212692fb3594a826436df765860f54837154 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66334 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-08-03mb/google/skyrim: Enable PSP verstageKarthikeyan Ramasubramanian
Enabling required config items to execute verstage in PSP. BUG=b:217414563 TEST=Build and boot to OS in Skyrim with PSP verstage. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: Iee14dc80cb6691acb5cb59a21da5a3dff69f7dd2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66135 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-03device: Fix 64Bit Device Resource Info PrintGang Chen
Use 0x016llx to print device resource info so that both 64bit and 32bit resources could be displayed correctly. Signed-off-by: Gang Chen <gang.c.chen@intel.com> Change-Id: I0ec4c47cca4a09ceb7dc929efaa5630b1f9df81c Reviewed-on: https://review.coreboot.org/c/coreboot/+/66324 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-08-03drivers/i2c/dw_i2c: Re-add check for empty i2c transfer listNico Huber
The check was recently removed to allow callers to pass `count == 0`. Dereferencing the `msg` array is invalid in that case, though. Linux, where we borrowed the i2c interface from, also treats this with -EINVAL. Change-Id: I1eec02dd3a3fcf2d477a62cc65292fca40e469d3 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66341 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Tim Crawford <tcrawford@system76.com>
2022-08-03dev/i2c_bus: Fix `count` argument in i2c_dev_detect()Nico Huber
We actually want the bus driver to process the 1 zero-length write we are passing. So set the count to 1. Change-Id: I5a41abb68c27a83715b6baec91ece9fa90b66a8c Signed-off-by: Nico Huber <nico.h@gmx.de> Tested-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66337 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Crawford <tcrawford@system76.com>
2022-08-03soc/mediatek: Move common definitions to dramc_soc_common.hRex-BC Chen
Some definitions are the same in dramc_soc.h for MT8192, MT8195 and MT8186, so we move them to dramc_soc_common.h TEST=build pass BUG=b:236331724 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I3095333e62abf98de1f2d27033baeeba7a4cad79 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66276 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-03mb/google/geralt: Implement SKU ID and RAM codeRex-BC Chen
- Retrieve the SKU ID for Geralt via CBI interface. If that failed (or no data found), fall back to ADC channels for SKU ID. - The RAM code is implemented by the resistor straps that we can read and decode from ADC. TEST=build pass BUG=b:236331724 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I31626e44bd873a3866c9bd1d511b476737f15a20 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66275 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-03mb/google/geralt: Configure GPIOsRex-BC Chen
Configure ChromeOS specific GPIOs: - Open-drain pins to high-z mode: GPIO_EC_AP_INT_ODL, GPIO_GSC_AP_INT_ODL and GPIO_WP_ODL. - GPO mode: GPIO_AP_EC_WARM_RST_REQ, GPIO_EN_SPKR and GPIO_XHCI_INIT_DONE. This patch is based on MT8188G_GPIO_Formal_Application_Spec_V0.3. TEST=build pass BUG=b:236331724 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I84d3f62ec8a3966fe1982d5d4cf6ff270450d4bf Reviewed-on: https://review.coreboot.org/c/coreboot/+/66274 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-03mb/google/geralt: Configure TPMRex-BC Chen
Initialize I2C bus 1 for TPM control. TEST=build pass BUG=b:236331724 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: If5807c9bb39260315ecbc55305def483bd2b8c51 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66273 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-03mb/google/dedede/var/beadrix: Update SoC gpio pin of DMICTeddy Shih
Update SoC GPIO setting of unused DMIC channel according to beadrix schematics. GPP_S2 : NF2 -> NC (DMIC1_CLK) GPP_S3 : NF2 -> NC (DMIC1_DATA) BUG=b:203113413, b:237224862 BRANCH=None TEST=on beadrix, validated by beadrix's DMIC working properly. Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com> Change-Id: Ibe2f432cd74b546218ff4ee6e428e9eed9ac611f Reviewed-on: https://review.coreboot.org/c/coreboot/+/65381 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivan Chen <yulunchen@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-08-03mb/google/dedede/var/drawcia: Add Wifi SAR for oscinoShon Wang
Add wifi sar for oscino BUG=b:240373077 BRANCH=dedede TEST=enable CHROMEOS_WIFI_SAR in config of coreboot, emerge-dedede coreboot-private-files-baseboard-dedede coreboot chromeos-bootimage. Cq-Depend: chrome-internal:4893022 Change-Id: I44cbe8ee08d6136ed116623046893c9749795e50 Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66176 Reviewed-by: Ivan Chen <yulunchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-08-03mb/google/dedede/var/beadrix: Update SoC gpio pin of BC1.2Teddy Shih
Update SoC GPIO setting of adding BC1.2 SLGC55545 according to beadrix schematics. GPP_A18 : NC -> NF1 (USB_OC0_N) BUG=b:214393595, b:226294980 BRANCH=None TEST=on beadrix, validated by beadrix's Type A working properly. Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com> Change-Id: I746931582cc12f49f7f1c667563350ebac8ddfa1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65377 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Super Ni <super.ni@intel.corp-partner.google.com> Reviewed-by: Ivan Chen <yulunchen@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-08-03mb/prodrive/atlas: Select FSP_TYPE_IOTLean Sheng Tan
Atlas uses IoT FSP. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I4c20600e0b62367e6e58908cf9cf916f309e6362 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66368 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Christian Walter <christian.walter@9elements.com>
2022-08-03soc/intel/alderlake: Add config for IoT FSP supportLean Sheng Tan
Add new config FSP_TYPE_IOT to add the IoT FSP option so that respective mainboard Kconfig can use IoT FSP if needed. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I01d891348c039269138e64290ae3d6ec75d3c687 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66367 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-08-033rdparty/fsp: Update submodule pointer to latest masterLean Sheng Tan
The latest master adds the missing MemInfoHob.h to IOT ADL-P & ADL-S folders. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I8ef998b2e414d3d63494e6177b4fde2dc26e9d55 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66366 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Christian Walter <christian.walter@9elements.com>
2022-08-03mb/google/brya: Enable DRIVERS_GENESYSLOGIC_GL9755 for kuldaxDavid Wu
Enable DRIVERS_GENESYSLOGIC_GL9755 support for kuldax. BUG=b:232858957 TEST=build pass Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I1b2c0bff8497d727c697ea6287078055a39bd1f3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66332 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
2022-08-03mb/google/brya/variants/agah: set tcc_offset to 3Tony Huang
Set tcc_offset value to 3 in devicetree for Thermal Control Circuit (TCC) activation feature. This value is suggested by Thermal team. BUG=b:240600260 TEST=emerge-draco coreboot verified by thermal team Change-Id: I3044643d52f1d6e883beb3ec87a77f32d086f46c Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66252 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2022-08-03soc/soc/intel: Add UFS device with ref-clk-freq propertyMeera Ravindranath
UFS storage devices require the bRefClkFreq attribute to be set to operate correctly in high speed mode. The correct value is determined by what the SoC / board supports. For the ADL UFS controller, it is 19.2 MHz. a) Introduce a new ACPI property "ref-clk-freq". b) Add support to configure this property using an SoC Kconfig. Kernel patch: https://web.archive.org/web/20220801060732/https://lore.kernel.org/all/ 20220715210230.1.I365d113d275117dee8fd055ce4fc7e6aebd0bce9@changeid/ BUG=b:238262674 TEST=Build,boot Nirwen and dump SSDT entries and check that the kernel correctly parses ref-clk-freq as 19.2 MHz. Scope (\_SB.PCI0) { Device (UFS) { Name (_ADR, 0x0000000000120007) // _ADR: Address Name (_DDN, "UFS Controller") // _DDN: DOS Device Name Name (_DSD, Package (0x02) // _DSD: Device-Specific Data { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */, Package (0x01) { Package (0x02) { "ref-clk-freq", 0x0124F800 } } }) } } Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Signed-off-by: Reka Norman <rekanorman@chromium.org> Change-Id: I80c338a8a61f161b0feb6c5a3ca00cf5e0cfb36c Reviewed-on: https://review.coreboot.org/c/coreboot/+/66051 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-08-03soc/amd/sabrina/fch: enable XTAL pad disabling in S0i3Felix Held
Switching off the pads of the internal crystal oscillator that connect to the crystal on the board in S0i3 saves a little power, so enable it. No measurements to quantify the power savings have been made. PPR #57243 revision 1.59 was used as a reference. BUG=b:237647468 TEST=None Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I52f14ae5c614ad8ff0479b619de7164afa1e7648 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66336 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2022-08-03mb/google/herobrine: Add support to enable displayVinod Polimera
This change adds support to enable edp gpios, display init for herobrine. BUG=b:182963902,b:216687885 TEST=Validated on qualcomm sc7280 development board. Monitor name: LQ140M1JW49 Change-Id: I01dbe23afbb3d41d87f24cb7dcfa456cb7f133fb Signed-off-by: Vinod Polimera <quic_vpolimer@quicinc.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64885 Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-03qualcomm/sc7280: Add support for edp and mdp driverVinod Polimera
- Add support for edp aux read and write. - Update edp panel properties based on edid read. - Configure edp controller and edp phy. Panel details: Manufacturer: SHP Model 1523 Serial Number 0 Made week 53 of 2020 EDID version: 1.4 Digital display 8 bits per primary color channel DisplayPort interface Maximum image size: 31 cm x 17 cm Gamma: 220% Check DPMS levels Supported color formats: RGB 4:4:4 Default (sRGB) color space is primary color space First detailed timing is preferred timing Supports GTF timings within operating range Established timings supported: Standard timings supported: Detailed timings Hex of detail: 5a8780a070384d403020350035ae10000018 Detailed mode (IN HEX): Clock 346500 KHz, 135 mm x ae mm 0780 07b0 07d0 0820 hborder 0 0438 043b 0440 0485 vborder 0 -hsync -vsync Did detailed timing Hex of detail: 653880a070384d403020350035ae10000018 Detailed mode (IN HEX): Clock 144370 KHz, 135 mm x ae mm 0780 07b0 07d0 0820 hborder 0 0438 043b 0440 0485 vborder 0 -hsync -vsync Hex of detail: 000000fd003090a7a7230100000000000000 Monitor ranges (bare limits): 48-144Hz V, 167-167kHz H, max dotclock 350MHz Hex of detail: 000000fc004c513134304d314a5734390a20 Monitor name: LQ140M1JW49 Changes in V2: - Remove Misc delays in edp code. - Move mdss soc code to disp.c - Update EDID read using I2C write & read. Changes in V3: - Remove unrelated delays. - Misc changes. BUG=b:182963902,b:216687885 TEST=Validated on qualcomm sc7280 development board. Monitor name: LQ140M1JW49 Signed-off-by: Vinod Polimera <quic_vpolimer@quicinc.com> Change-Id: If89abb76028766b19450e756889a5d7776106f95 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61342 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2022-08-03commonlib: Add support for rational number approximationVinod Polimera
This patch adds a function to calculate best rational approximation for a given fraction and unit tests for it. Change-Id: I2272d9bb31cde54e65721f95662b80754eee50c2 Signed-off-by: Vinod Polimera <quic_vpolimer@quicinc.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66010 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-02Makefile.inc: Disable compiler warning array-compare for GCCPaul Menzel
gcc 12 fails the build with the warning below: CC romstage/lib/cbfs.o src/lib/cbfs.c: In function 'switch_to_postram_cache': src/lib/cbfs.c:31:32: error: comparison between two arrays [-Werror=array-compare] 31 | if (_preram_cbfs_cache != _postram_cbfs_cache) | ^~ src/lib/cbfs.c:31:32: note: use '&_preram_cbfs_cache[0] != &_postram_cbfs_cache[0]' to compare the addresses Instead of following gcc’s suggestion, disable the warning for gcc as requested by Julius [1]: > Can we just set -Wno-array-compare instead? There's nothing illegal > about that expression and as we can see in this case, there are > perfectly reasonable cases where you might want to do something like > that. On the other hand, I don't really see a realistic scenario where > this warning could prevent a real problem (anyone who doesn't know > that array1 == array2 doesn't compare the array elements in C > shouldn't have any business submitting code to coreboot). [1]: https://review.coreboot.org/c/coreboot/+/62827/1 Found-by: gcc-12 (Debian 12-20220313-1) 12.0.1 20220314 (experimental) [master r12-7638-g823b3b79cd2] Found-by: gcc (Debian 12.1.0-7) 12.1.0 Change-Id: I322f7cc57dcca713141bddaaaed9ec034898754d Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66105 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-08-02soc/intel/alderlake: Configure DDR5 Physical channel width to 64Meera Ravindranath
A DDR5 DIMM internally has two channels each of width 32 bit. But the total physical channel width is 64 bit. BUG=b:180458099 TEST=Boot DDR5 to kernel Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Change-Id: Ic5e9c58f255bdf86a68ce90a4f853bf4e7c7ccfe Reviewed-on: https://review.coreboot.org/c/coreboot/+/52730 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-08-02mb/google/dedede/var/pirika: Add Elan touchscreen supportFrankChu
Enable I2C2 and register touchscreen ACPI device for pirika. BUG=b:236564261 TEST=touch screen is functional. Signed-off-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Change-Id: Id2fd5606b7126eabc1c88bf516198ff00b5d75dd Reviewed-on: https://review.coreboot.org/c/coreboot/+/65967 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-08-02mb/google/brya/var/ghost: Enable AMP powerEric Lai
Follow latest schematic, GPP_A17 is used to enable AMP power. BUG=b:240006200 BRANCH=firmware-brya-14505.B TEST=Check I2C scan can see the AMP return ACK. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: Ia6c52302a12ddec68303714ac07e96a65a8f8fb8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66325 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2022-08-02mb/system76: Change touchpad detection methodTim Crawford
Use the new "detect" method instead of "probed". Fixes an uncommon issue where i2c-hid fails to initialize the device on Linux. Tested on: gaze15, gaze16-3060, lemp10, oryp8 Tested: - Linux: Touchpad works across 50 reboots - Windows: Touchpad is still detected as an I2C HID device - Windows: Extra I2C HID devices are not shown in Device Manager Change-Id: I6a899c64a6d77b65a2ae57ab8df81cd84b568184 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66129 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-08-02mb/google/geralt: Enable Chrome ECRex-BC Chen
Initialize SPI bus 0 for Chrome EC control. TEST=build pass BUG=b:236331724 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I6de5ea8a0273a3b0c725e4cdbcf69f4db74c5db7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66272 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-08-02payloads/tianocore/Makefile: Fix restoring default boot logoMatt DeVillier
the missing `; \` at the end of the line meant subsequent lines were no longer run from $project_dir, so Logo.bmp was silently failing to restore. This led to the working dir being dirty, and on subsequent runs, any change to a different branch in the same repo would fail. Change-Id: I17a323bc2dda19b69d809e398b273f24e14b43af Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66321 Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-02soc/intel/alderlake: Add IRQ constraints for CPU PCIe portsTim Crawford
Copy the constraint from ADL-S to ADL-P. Fixes the following warning in Linux on System76 oryp9, which has an NVIDIA GPU on the bridge. pcieport 0000:00:01.0: can't derive routing for PCI INT A This, in turn, resolves an IRQ conflict with the PCH HDA device that would cause a stack track on every boot. irq 10: nobody cared (try booting with the "irqpoll" option) <snip> [<00000000bf549647>] azx_interrupt [snd_hda_codec] Disabling IRQ #10 Change-Id: I550c80105ff861d051170ed748149aeb25a545db Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66285 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-02mb/google/nissa/craask: Add eMMC DLL tuning valueSimon Yang
Configure eMMC DLL tuning values for Craask board. BUG=b:238985924 TEST="Use the value to boot on Nivviks and Craask successfully." Change-Id: I14f3e2329404cca94e14034d1fb52fcb99a2ddc9 Signed-off-by: Simon Yang <simon1.yang@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66218 Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-08-02mb/google/rex: Enable CSE Lite SKUSubrata Banik
The first CSE Lite SKU is available, therefore enable the Kconfig option to have the CSE reboot the system into its RW FW during a cold boot. BUG=b:240228892 TEST=TBD Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I00ef4176cf08cbeed06e446cfe68f06cb1ea27b4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66287 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-02util/cbfstool/elogtool: Support logging FW vboot info in elogSubrata Banik
List of changes: 1. Add support for new elog event type to log vboot info (type 0xB7). 2. Add support string for fw_slot name, boot status and boot mode. 3. Print fw slot information like FW try count, FW current slot, previous FW slot, previous FW boot result and boot mode. BUG=b:215615970 TEST=Able to build and boot google/kano to OS. localhost # elogtool list 0 | 2022-07-01 11:10:27 | Log area cleared | 4088 1 | 2022-07-01 11:10:27 | Memory Cache Update | Normal | Success 2 | 2022-07-01 11:10:42 | System boot | 360 3 | 2022-07-01 11:10:42 | Power Fail 4 | 2022-07-01 11:10:42 | SUS Power Fail 5 | 2022-07-01 11:10:42 | ACPI Wake | S5 6 | 2022-07-01 11:10:42 | Wake Source | Power Button | 0 7 | 2022-07-01 11:10:42 | Chrome OS Developer Mode 8 | 2022-07-01 11:10:42 | Firmware vboot info | boot_mode=Developer | fw_tried=B | fw_try_count=0 | fw_prev_tried=B | fw_prev_result=Unknown 9 | 2022-07-01 11:11:42 | System boot | 361 10 | 2022-07-01 11:11:42 | System Reset 11 | 2022-07-01 11:11:42 | Firmware vboot info | boot_mode=Developer | fw_tried=B | fw_try_count=0 | fw_prev_tried=B | fw_prev_result=Success localhost # crossystem recovery_request=1 localhost # elogtool list 41 | 2022-07-13 12:13:48 | Firmware vboot info | boot_mode=Manual recovery boot | recovery_reason: 0x1/0 (Recovery requested from legacy utility) | fw_tried=A | fw_try_count=0 | fw_prev_tried=A | fw_prev_result=Unknown Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I48b5d54723683cef51e416fc6f58da000507fbcc Reviewed-on: https://review.coreboot.org/c/coreboot/+/65562 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-02vc/google/elog: Record vboot FW boot information into elogSubrata Banik
This patch calls into vboot API (vb2api_get_fw_boot_info) to retrieve FW slot boot information like (tries count, current boot slot, previous boot slot, previous boot status and boot mode). Upon retrieval of the vboot information, elog callback from ramstage records the info into the eventlog. Additionally, this patch refactors the existing event logging mechanism to add newer APIs to record vboot firmware boot related information. BUG=b:215615970 TEST=Build and boot google/kano to ChromeOS and run below command to check the cbmem log: Scenario 1: localhost ~ # cbmem -c | grep VB2 [INFO ] VB2:vb2_check_recovery() Recovery reason from previous boot: 0x0 / 0x0 [INFO ] VB2:vb2api_fill_boot_config() boot_mode=`Developer boot` VB2:vb2api_get_fw_boot_info() fw_tried=`A` fw_try_count=0 fw_prev_tried=`A` fw_prev_result=`Success`. .... Scenario 2: localhost ~ # crossystem recovery_request=1 localhost ~ # cbmem -c | grep VB2 [INFO ] VB2:vb2api_fill_boot_config() boot_mode=`Manual recovery boot` VB2:vb2api_fill_boot_config() recovery_reason=0x13 / 0x00 VB2:vb2api_get_fw_boot_info() fw_tried=`A` fw_try_count=0 fw_prev_tried=`A` fw_prev_result=`Unknown`. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I6882cd1c4dbe5e24f6460388cd1af4e4a05fc4da Reviewed-on: https://review.coreboot.org/c/coreboot/+/65561 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-02Update vboot submodule to upstream mainSubrata Banik
Updating from commit id a975eed306: 2kernel.c: check display request in vb2api_kernel_phase2 to commit id 18cb85b52d: 2load_kernel.c: Expose load kernel as vb2_api Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I58c5d54723683cef51e416fc6f58da000507fbcc Reviewed-on: https://review.coreboot.org/c/coreboot/+/66269 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-01soc/amd/common/block/apob/apob_cache.c: Add assert for APOB DRAM sizeFred Reitberger
Add static check to ensure the reserved APOB DRAM space is the same size as the MRC_CACHE region specified in the fmap. Update sabrina APOB DRAM size to match the fmap. TEST: Timeless builds identical. Test build with a larger MRC_CACHE than APOB DRAM failed the assert as expected. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Ia14f6ef94b9062df0612fe96098b1012085ccf9c Reviewed-on: https://review.coreboot.org/c/coreboot/+/65878 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-01util/spd_tools/spd_gen/lp5: Remove maxSpeed for SabrinaKarthikeyan Ramasubramanian
Firmware component that does memory training already limits the memory controller to train at 5500 Mbps for all memory parts in Sabrina. Hence removing this interim SPD change to limit the speed. BUG=b:238074863 TEST=Build and boot to OS in Skyrim. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I2bc82c7407a97aac282708c3e0bd56ae99a8fc31 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66290 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-01soc/qualcomm: Fill coreboot table with PCIe infoVeerabhadrarao Badiganti
In order to pass PCIe base address to payloads, implement pcie_fill_lb() to fill coreboot table with PCIe info. BUG=b:182963902,b:216686574,b:181098581 TEST=Verified on Qualcomm sc7280 development board with NVMe endpoint (Koixa NVMe, Model-KBG40ZPZ256G with FW AEGA0102). Confirmed NVMe is getting detected in response to 'storage init' command in depthcharge CLI prompt. Output logs: ->dpch: storage init Initializing NVMe controller 1e0f:0001 Identified NVMe model KBG40ZPZ256G TOSHIBA MEMORY Added NVMe drive "NVMe Namespace 1" lbasize:512, count:0x1dcf32b0 * 0: NVMe Namespace 1 1 devices total Also verified NVMe boot path that is depthcharge is able to load the kernel image from NVMe storage. Change-Id: I1ca2be55b98c8d1b86576072078cdda02ac55940 Signed-off-by: Veerabhadrarao Badiganti <quic_vbadigan@quicinc.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57614 Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-08-01libpayload: Enable PCIe driver for sc7280Veerabhadrarao Badiganti
Enable PCIe driver for herobrine board. BUG=b:182963902,b:216686574,b:181098581 TEST=Verified on Qualcomm sc7280 development board with NVMe card (Koixa NVMe, Model-KBG40ZPZ256G with FW AEGA0102). Confirmed NVMe is getting detected in response to 'storage init' command in depthcharge CLI prompt. Output logs: ->dpch: storage init Initializing NVMe controller 1e0f:0001 Identified NVMe model KBG40ZPZ256G TOSHIBA MEMORY Added NVMe drive "NVMe Namespace 1" lbasize:512, count:0x1dcf32b0 * 0: NVMe Namespace 1 1 devices total Also verified NVMe boot path, that is depthcharge is able to load the kernel image from NVMe storage. Change-Id: Idb693ca219ba1e5dfc8aec34027085b53af49a2c Signed-off-by: Veerabhadrarao Badiganti <quic_vbadigan@quicinc.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65661 Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-01libpayload/pci: Add pci_map_bus function for Qualcomm platformPrasad Malisetty
Add 'pci_map_bus' function and PCIE_QCOM config for Qualcomm platform. BUG=b:182963902,b:216686574,b:181098581 TEST=Verified on Qualcomm sc7280 development board with NVMe endpoint (Koixa NVMe, Model-KBG40ZPZ256G with FW AEGA0102). Confirmed NVMe is getting detected in response to 'storage init' command in depthcharge CLI prompt. Output logs: ->dpch: storage init Initializing NVMe controller 1e0f:0001 Identified NVMe model KBG40ZPZ256G TOSHIBA MEMORY Added NVMe drive "NVMe Namespace 1" lbasize:512, count:0x1dcf32b0 * 0: NVMe Namespace 1 1 devices total Also verified NVMe boot path that is depthcharge is able to load the kernel image from NVMe storage. Change-Id: I7d1217502cbd7d4d0cdd298919ae82435630d61c Signed-off-by: Prasad Malisetty <quic_pmaliset@quicinc.com> Signed-off-by: Veerabhadrarao Badiganti <quic_vbadigan@quicinc.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57615 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-27 09:31:02 +0000