| Age | Commit message (Collapse) | Author |
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Remove chromeos_dsdt_generator() calls under mainboard, it
is possible to make the single call to fill \CNVS and
\OIPG without leveraging device operations.
Change-Id: Id79af96bb6c038d273ac9c4afc723437fc1f3fc9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55502
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Support GL9763E as a eMMC boot disk
BUG=b:210089379
TEST=enable DRIVERS_GENESYSLOGIC_GL9763E and check eMMC on taniks.
Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Change-Id: Iab0fd88ac88e07a8580426234adc9c21df6c11d6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60023
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Add Kconfig item RT8168_SET_LED_MODE to enable LED customization.
Update the LED settings in devicetree.
BUG=b:193750191
TEST=Try different register values to verify LED feature.
Signed-off-by: Rory Liu <rory.liu@quanta.corp-partner.google.com>
Change-Id: If80ace497c7481ce40b55af7e17e12a286aa9164
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60298
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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The Realtek RTL8125 has four registers for four leds
and a feature config register.
We use led0 and led2 in brask, so modify ethernet driver.
Those registers' IO address are based on RTL8125 datasheet.
BUG=b:193750191
TEST=Modify overridetree.cb to verify LEDs' settings.
Signed-off-by: Rory Liu <rory.liu@quanta.corp-partner.google.com>
Change-Id: I4b05a859dc0a0d2b8d6b35d6491fc88f7077cb92
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59531
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Add Hynix H9JCNNNCP3MLYR-N6E LP5 DRAM part for vell:
DRAM Part Name ID to assign
H9JCNNNCP3MLYR-N6E 1 (0001)
BUG=b:204284866
TEST=emerge-brya coreboot
Change-Id: I1ec2985fa1f1c488ee3a9c5e34f7b370d16cf98e
Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60288
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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The board ID check for audio codec is no longer required, therefore
remove it.
BUG=b:210705216
TEST=emerge-brya coreboot chromeos-bootimage and check audio function
Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com>
Change-Id: Ifbe838186da2e64737a9ffb557cf324124e79a9d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60128
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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- Enable Acoustic noise mitigation
- Copied from gimble set slow slew rate VCCIA and VCCGT to 8
BUG=b:206704930
TEST=USE="project_gimble emerge-brya coreboot" and verify it builds
without error.
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: I156859ce6894a6ed5270fe0242de4aef9656bbeb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59949
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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The patch add timestamp around cse_fw_sync().
TEST=Verified on Brya, cbmem -t:
948:starting CSE firmware sync 1,381,577 (45,227)
949:finished CSE firmware sync 1,459,513 (77,936)
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: Idba11417e0fc7c18d0d938a4293ec3aff1537fb4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60135
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
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Add the stylus field in fw_config.
Update devicetree and gpio to handle stylus pen detection.
BUG=b:167983049
TEST=Build firmware and check behavior as following:
1) Set the fw_config "bit4=1" for pen present:
Wake up from suspend when pen is removed from the garage.
Present the stylus menu when pen is removed from the garage.
2) Set the fw_config "bit4=0" for pen absent:
Wake up and present menu will not work when pen is removed
form the garage.
Change-Id: I62489bb289b18f9aa0823005224eda3ef5218e03
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60185
Reviewed-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This adds a new port for the ASRock H77 Pro4-M motherboard. It is
microATX-sized with an LGA1155 socket and four DIMM sockets for DDR3
SDRAM.
The port was initially done with autoport. It is quite similar to the
ASRock B75 Pro3-M which is already supported by coreboot.
Working:
- Sandy Bridge and Ivy Bridge CPUs (tested: i5-2500, Pentium G2120)
- Native RAM initialization with four DIMMs of two different types
- PS/2 combined port (mouse or keyboard)
- Integrated GPU by libgfxinit on all monitor ports (DVI-D, HDMI, D-Sub)
- PCIe graphics in the PEG slot
- All three additional PCIe slots
- All rear and internal USB2 ports
- All rear and internal USB3 ports with reasonable transfer rates
- All six SATA ports from the PCH (two 6 Gb/s, four 3 Gb/s)
- All two SATA ports from the ASM1061 PCIe-to-SATA bridge (6 Gb/s)
- Rear eSATA connector (multiplexed with one ASM1061 port)
- Console output on the serial port of the Super I/O
- SeaBIOS 1.15.0 to boot slackware64
- SeaBIOS 1.15.0 to boot Windows 10 (needs VGA BIOS)
- Internal flashing with flashrom-1.2 (needs `--ifd -i bios --noverify-all`)
- External flashing with flashrom-1.2 and a Raspberry Pi 1
- S3 suspend/resume from either Linux or Windows 10
Not working:
- Booting from the two SATA ports provided by the ASM1061
- Automatic fan control with the NCT6776D Super I/O
Untested:
- VBT (it is included, though)
- Infrared header
Change-Id: Ic2c51bf7babd9dfcbaf69a5019b2a034762052f2
Signed-off-by: Michael Büchler <michael.buechler@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45317
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Writing a coreboot image without a payload to a board's flash chip will
result in a non-bootable system, so warn the user if this is the case.
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Change-Id: I15ae9548a45e9f566c84db41e8e171c6bc179057
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60025
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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1. Samsung LPDDR4X 4266 4G K4UBE3D4AB-MGCL
2. Hynix LPDDR4X 4266 4G H54G56CYRBX247 (already used by other variants)
BUG=b:203014978
BRANCH=guybrush
TEST=emerge-guybrush coreboot chromeos-bootimage
Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Change-Id: Ie5ece849a86c75be5af9bc0393090b5f1e33bfed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60090
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
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Update the two load line slope settings for the SVID3 telemetry.
AGESA sends these values to the SMU, which accepts them as units
of current. Proper calibration is determined by the AMD SDLE tool
and the Stardust test.
vdd scale: 73457 -> 73331
vdd offset: 291 -> 1893
soc scale: 30761 -> 31955
soc offset: 834 -> 852
BUG=b:207299255
BRANCH=guybrush
TEST=1. emerge-guybrush coreboot
2. pass AMD SDLE/Stardust test
Change-Id: I9c9dd4883fd21a70a1e7a50f25a4f76df1e56bc6
Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60243
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
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Add support for Alder lake N LP5 RVP with board ID 0x7.
Since SPD index 7 is unused earlier, ADL-N will use it.
Change-Id: Ib2f53e65f75e23793d8c85ee924827446fd9fea7
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60193
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
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This patch introduces new FlashMap API, the fmap_locate_area().
It works on cached FlashMap provided in lib_sysinfo.fmap_cache.
Change-Id: Idbf9016ce73aa58e17f3ee19920ab83dc6c25abb
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59494
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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coreinfo and nvramcui are using libpayload/bin/lpgcc and libpayload
build directory as a base, instead of installing it first. This caused
include errors, because commonlib/bsd is not present there. This patch
introduces comonlib/bsd include path to lpgcc CFLAGS if it is being
built using libpayload build directory as a base.
Change-Id: I7d1fe9e5dc3e7c1c1ba825a1bf19972722b42778
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60171
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Remove SD controller configurations based on the beadrix's schematic.
BUG=b:204882915
BRANCH=None
TEST=Built test coreboot image
Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com>
Change-Id: Iba6f5cbbe90d9307e5e8080d7063a1881acd7ed9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60266
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change adds internal USB camera into devicetree for beadrix.
BUG=b:204882915, b:210772511
BRANCH=None
TEST=Built and checked camera device existence with lsusb
Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com>
Change-Id: Iddc58c0d27d5da0fa4652f503f15ebb308be18c7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60252
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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This change adds ALC5682I audio codec and MAX98360A amplifier for beadrix.
BUG=b:204882915, b:210756131
BRANCH=None
TEST=Built and heared speaker sound on OS
Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com>
Change-Id: I6f12f71ec66acd420471ab9a7612b1821650ad54
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60250
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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This change adds PIXA touchpad into devicetree for beadrix.
BUG=b:204882915, b:203113111
TEST=Built and verified touchpad function
Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com>
Change-Id: I0b551554c69d52f0559ace4ad9c1335270dacea9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60246
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Using Vbt.bin version 244, with the following changes:
* Add 200ms delay to sink (T3) to avoid no response to AUX Channel
transaction, which manifests as a repeating, colourful flicker.
* Increase maximum supported refresh rate to 120Hz
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ifc03b8f5d45cbbf90fb61d8b08148ed402dd85ec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59727
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Andy Pont <andy.pont@sdcsystems.com>
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Add new memory parts in the mem_parts_used.txt and generate the
SPD ID for the parts. The memory parts being added are:
1. Samsung K4U6E3S4AB-MGCL
2. Hynix H54G46CYRBX267
BUG=b:203837656
BRANCH=dedede
TEST=FW_NAME=cret emerge-dedede coreboot chromeos-bootimage
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I03980858f89e56320ddff3a808110a5f1dd57784
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58412
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Enable SaGv support for anahera/anahera4es.
BUG=b:211362081
TEST=FW_NAME=anahera emerge-brya coreboot
Change-Id: I68c916dbc570759dba3a4c32fbb8ebfc6e387be4
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60249
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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In commit 667471b8d8 (ec/google/chromeec: Add PLD to EC conn in ACPI
table), PLD is added to ACPI table. It causes the DUT to not boot into
the OS. So fix the USB3/USB2 Type-C Port C2 PLD group order from 3 to 2
to solve this issue.
Fixes: 667471b8d8 ("ec/google/chromeec: Add PLD to EC conn in ACPI table")
BUG=b:209723556
BRANCH=none
TEST=build coreboot and boot into OS.
Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Change-Id: Iff1302fa758bcde1ce8b03c16f7cc6eac807e5c9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60187
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Building an image for the Lenovo T60 with `x86_64-linux-gnu-gcc-11`
fails with the format warning below.
CC ramstage/southbridge/intel/common/rcba_pirq.o
src/southbridge/intel/common/rcba_pirq.c: In function 'intel_acpi_gen_def_acpi_pirq':
src/southbridge/intel/common/rcba_pirq.c:86:69: error: format '%ld' expects argument of type 'long int', but argument 5 has type 'size_t' {aka 'unsigned int'} [-Werror=format=]
86 | printk(BIOS_SPEW, "ACPI_PIRQ_GEN: %s: pin=%d pirq=%ld\n",
| ~~^
| |
| long int
| %d
87 | dev_path(dev), int_pin - PCI_INT_A,
88 | pirq_idx(pin_irq_map[map_count].pic_pirq));
| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
| |
| size_t {aka unsigned int}
The return value of `pirq_idx()` is of type `size_t`, so use the
appropriate length modifier `z`.
Change-Id: I7af24cee536b81e4825b77942bcac75afeb9f476
Found-by: gcc (Debian 11.2.0-13) 11.2.0
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60194
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Currently, the pmc_mux/conn driver uses integer fields to store the
USB-2 and USB-3 port numbers from the SoC's point of view. Specifying
these as integers in the devicetree is error-prone, and this
information can instead be represented using pointers to the USB-2 and
USB-3 devices. The port numbers can then be obtained from the paths of
the linked devices, i.e. dev->path.usb.port_id.
Modify the driver to store device pointers instead of integer port
numbers, and update all devicetrees using the driver. These are the
mainboards affected (all are Intel TGL or ADL based):
google/brya
google/volteer
intel/adlrvp
intel/shadowmountain
intel/tglrvp
system76/darp7
system76/galp5
system76/lemp10
Command used to update the devicetrees:
git grep -l "usb._port_number" src/mainboard/ | \
xargs sed -i \
-e 's/register "usb2_port_number" = "\(.*\)"/use usb2_port\1 as usb2_port/g' \
-e 's/register "usb3_port_number" = "\(.*\)"/use tcss_usb3_port\1 as usb3_port/g'
BUG=b:208502191
TEST=Build test all affected boards. On brya0, boot device and check
that the ACPI tables generated with and without the change are the same.
Change-Id: I5045b8ea57e8ca6f9ebd7d68a19486736b7e2809
Signed-off-by: Reka Norman <rekanorman@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60143
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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USB ports
Tune the USB phy settings to update txpreempamptune to 3 and txvreftune to 6 for passing USB 2.0 SI Eye diagram measurement (port 0/1/4).
BUG=b:199468920
TEST= emerge-guybrush coreboot; pass USB 2.0 SI Eye diagram measurement.
Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Change-Id: Ie46c9019186f1893d736fc2806ab74a4f1171be7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60239
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
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Change-Id: I3f4dc26699e3618740af5a0ade1a19599d5a2cc7
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60225
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Change CLKSRC#3 to CLKSRC#1 in override devicetree based on schematics
BUG=b:208756696
TEST=emerge-brya coreboot
Change-Id: I4d452eaa690a91814739cc1b80966fc3a9f1be37
Signed-off-by: = <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60099
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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update override devicetree for touchpad based on schematics
BUG=b:209554950
TEST=emerge-brya coreboot
Change-Id: I835958349537ed490191db7c8e35847630de64ed
Signed-off-by: = <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60098
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Because of a typo, `bootblcok-y += rtc.c` does nothing. Drop it.
Change-Id: Ife2ee152ab32ef23df5986c47bec490db592ab60
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56216
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch removes unused header inclusion as <commonlib/helpers.h>
from several mainboard gpio definition files.
Change-Id: I36758089a4981bba916f4d9cf485f64fca2f81ae
Signed-off-by: subratabanik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60305
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
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Some SKUs of google/taeko have a Bayhub LV2 card reader chip,
therefore enable the corresponding driver for the mainboard.
BUG=b:204343849
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I738af7e77a3c076742a3d6c6f48fad29dfc978ac
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60017
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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The Bayhub LV2 has a known errata wherein PCI config registers at
offsets 0x234, 0x238, and 0x24C will only correctly accept writes
when they are addressed via a DWORD (32-bit) wide write operation
on the PCIe bus. Offset 0x234 is the LTR max snoop and max no-snoop
latency register, therefore add a finalize callback to this driver
which will program the LTR max-snoop/no-snoop register with a 32-bit
write using the values from pciexp_get_ltr_max_latencies().
BUG=b:204343849
TEST=verified the PCI config space writes took effect on google/taeko
Change-Id: I1813f798faa534fb212cb1a074bc7bcadd17a517
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60016
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Some device drivers may need to get access to the LTR values for their
respective devices, therefore export this function instead of marking it
static.
BUG=b:204343849
Change-Id: Id372600e8adec0d55d3483726bb9353139685774
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60015
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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This change in power sequencing appears to fix issues with power
consumption of the SD card controller. Possibly this change
ensures the device has enough time to properly initialize itself
after reset is deasserted but before it is accessed.
BUG=b:206014046
TEST=USE="project_gimble emerge-brya coreboot" and verify it builds
without error.
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: I90e5dd074ceda365283fe7e1f43dfd8c692d7338
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60279
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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This causes the I2C touchpad device to stop working after warm reboot.
BUG=b:210701402
BRANCH=none
TEST=after warm reboot, the touchpad still works.
Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com>
Change-Id: I106ddc96c3185656d3f1fbcd45f198d2d46f3f4d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60126
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Based on schematic G570_MB_CHROME_1207_1630_ADC and gpio table of
taniks, generate overridetree.cb settings for taniks.
BUG=b:209926534
TEST=FW_NAME=taniks emerge-brya coreboot chromeos-bootimage
Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Change-Id: Ib333150117832480f70fbe13bdbdf2982a7f70e6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59998
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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According to util/kbc1126/README.md, for these ECs to work, the
address and size of their two firmware should be written to $s-0x100`
(`$s` means the image size, done with kbc1126_ec_insert), which means
that every existing section (especially those used to store code)
should not overlap this address, otherwise the bootblock will get
damaged when inserting firmwares of the EC.
In this commit, ecfw_ptr is a structure initialized at build time
according to CONFIG_KBC1126_FW1_OFFSET and CONFIG_KBC1126_FW2_OFFSET
(to do so, they should be redefined as hex), and linked to
CONFIG_ECFW_PTR_ADDR within bootblock, so kbc1126_ec_insert is not
needed at build time any more.
Test passed on Elitebook Folio 9470m.
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Change-Id: I4f0de0c4d7283e630242fbe84a46e0547783c49e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51671
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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This reverts commit ae0ea32c52905d6bcb527b04727463bc2d1b9e09.
This change should not have merged until the 2471_02 FSP change is ready
for merge.
BUG=b:211481222
TEST='emerge-brya coreboot chromeos-bootimage', flash and boot brya0
to kernel.
Change-Id: Iae5b0c53ace196053e1e155efd2e08f438979ba7
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60262
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
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Move selects from Kconfig.name to Kconfig so that the configuration is
at one place and not distributed over two files.
Change-Id: Id71c63556da73a09c5a6d3e844686ddc3e113ea7
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60148
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Change-Id: I9578dd7cd4766b4b2ce8fb14992b1ef4701d9878
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60147
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
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Move board-specific selects out of common configuration and add them to
each board where necessary.
Change-Id: I5bda94b20da4c9184cef2a39598e25a214c044b1
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60146
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
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These variant-specific options are only selected by their board options
and are not used for anything else. Thus, merge their selects into the
board options and drop them.
Change-Id: I0eb3fdc4fd7306e76d5479494e3ab80bbdb984fe
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60189
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
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Move selects from Kconfig.name to Kconfig so that the configuration is
at one place and not distributed over two files.
Change-Id: I462426f2ef4a0ff62c0a7c1eb2a4946fba68c4a9
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60188
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Change-Id: If5cb98712767e2acab8955931d4f342c8f3d7824
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60144
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
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Enable PSP_S0I3_RESUME_VERSTAGE for all guybrush based boards. This will
cause verstage to run during s0i3 resume. The TPM will be reinitialized
in verstage during s0i3 resume. This is necessary on guybrush boards
because the TPM_RST_L pin is asserted by the SOC in S0i3.
BUG=b:200578885
BRANCH=None
TEST=TPM initialized after s0i3
Change-Id: I9d64fe92ffc67a421be6d5e013e636332ce86dd5
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60139
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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PSP_S0I3_RESUME_VERSTAGE softfuse bit is 58, not 40.
BUG=b:202397678
BRANCH=None
TEST=Boot guybrush, ensure S0i3 verstage runs with latest PSP.
Change-Id: Ia27f6e48e345aac0d5f6579d663a6b655688239a
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60214
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
|
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Build-test the configuration Prodrive uses to build coreboot for their
Hermes mainboard.
Change-Id: I62e79d3143851bf14dfdbe70e60c60f13dd06c3f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57168
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Justin van Son <justin.van.son@prodrive-technologies.com>
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The patch defines new TS for CSE firmware synchronization.
Also, removes unused TS_FIT_UCODE_LOADED TS.
TEST=Build the code for Brya
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I9ed82c5358eb94b5e7c91b9fd783c5e09189b77a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59668
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Add a wake-on-lan GPIO in devicetree for RTL8125.
Modify GPIO A7 for wake-on-lan.
BUG=b:204289108
TEST=emerge-brask coreboot chromeos-bootimage
Signed-off-by: Rory Liu <rory.liu@quanta.corp-partner.google.com>
Change-Id: Ic40301888a138df4a67398485f2a484d69b83fc9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60132
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
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Crashlog has error records and PMC reset records two parts. When we
send ipc cmd "PMC_IPC_CMD_ID_CRASHLOG_ON_RESET", PMC reset record is
enabled. At each warm/cold/global reset, crashlog would be triggered.
The cause of this crash would be "TRIGGER_ON_ALL_RESETS", it is used to
catch unknown reset reason. At the same time, we would see [Hardware
Error] in the kernel log.
If we default enable TRIGGER_ON_ALL_RESETS, we would have too many false
alarm. Now we disable PMC reset records part by default. And we could
enable it when we need it for the debug purpose.
The generated bert dump is under /var/spool/crash/, we could check this
path to verify this CONFIG disable/enable status.
BUG=b:202737385
TEST=No new bert dump after a warm reset.
Signed-off-by: Curtis Chen <curtis.chen@intel.com>
Change-Id: I3ec4ff3c8a3799156de030f4556fe6ce61305139
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59951
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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|
DQ/DQS info from Intel_Platform_DQ_DQS_RCOMP_Info_Utility
GPIO_MEN_CONFIG_0 GPP_E11 to GPP_E3
GPIO_MEN_CONFIG_3 GPP_E12 to GPP_E7
GPIO_MEM_CH_SEL_GPP_E5 GPP_E13 to GPP_E5
BUG=b:205908918
TEST=emerge-brya coreboot
Change-Id: Ic0bbac5eaebc77639be6c1bc399658ac90e72fbb
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59334
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
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Configure GPIOs according to schematics
BUG=b:205908918
TEST=emerge-brya coreboot
Change-Id: Icc91866f7555c294af7eed9e5d1550e73d8059d0
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59305
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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When compiling libpayload using x86_64 toolchain for ARCH_MOCK compiler
reports an error about gerring address of packed member. Until now it
had to be disabled by passing -Wno-address-of-packed-member to
EXTRA_CFLAGS. This patch disables this warning.
Change-Id: I9a948fabe66f7297632ecaca8ec1bfa5c842b750
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60169
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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None of the touchscreens used in the brya program (any brya board)
should require exporting of GPIOs in the ACPI _CRS method for any i2c
device. This can cause i2c devices to malfunction or cause timing
sequence violations if:
1) ACPI exports a PowerResource for the device that uses GPIOs that are
also exported in _CRS
2) The kernel driver for the device uses the GPIOs exported in _CRS for
its own purposes. This means the state of the pin is out of sync
between platform firmware and the kernel. The Linux ELAN I2C
touchcsreen driver (https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/third_party/kernel/upstream/drivers/input/touchscreen/elants_i2c.c;l=1429)
is one example of this.
Therefore, add disable_gpio_export_in_crs to all brya variants that use
the drivers/i2c/generic or drivers/i2c/hid chip drivers.
Change-Id: Ib4475bd0dc885e230911de6298fd95baa868ef29
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60175
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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- Because primus have five sensors,we need to define 5 sensors.
BUG=b:200836803
TEST=USE="project_primus emerge-brya coreboot" and verify it builds
without error.
Signed-off-by: Ariel_Fang <ariel_fang@wistron.corp-partner.google.com>
Change-Id: I02fb8eee644f9999d9c5d48e3a056499d968f85d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60101
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
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We experienced the `Cr50 i2c TPM IRQ timeout!` error when the device
executed the reboot test even though we have updated the Cr50 firmware
to the latest version 0.6.70. Besides, we also experienced the device
failed with the IRQ timeout when using the 0.3.22 Cr50 firmware in the
factory. In order to fix these issues, we disable the gpio power
management from the devicetree.
BUG=b:210540890
TEST=reboot 100 cycles without the error message.
Change-Id: I5f18fea5bc28493107c6d4951805de640a0b8ae5
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60100
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
|
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Use enum cb_err as return type of all remaining functions that only
return success or failure.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6cff8480d99641fdfb613bb3e4edc4055ad5efc6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60208
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
|
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Use enum cb_err as return type of all functions that aren't exposed
outside of this compilation unit. The checks if a function has returned
a failure are replaced with checks if the return value isn't CB_SUCCESS
which is equivalent if only those two values are used, but also detects
a failure if any unexpected value would be returned.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If8c703f62babac31948d0878e91bd31b31bebc01
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60207
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
|
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The intermediate ret variable isn't needed. espi_open_generic_io_window
only returns 0 or -1, so if ret is != 0, it has to be -1. This is a
preparation to use the enum cb_err type for the return values.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia6c7f4cedf8c2defadcf4c4da1697a97c7b401f2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60206
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
|
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The intermediate ret variable isn't needed.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I4e6747cf468c5ba8da6c1a3b20022851e32ad951
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60205
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
|
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S0i3 is a low power state which reduces the power consumption to about
the level of the S3 suspend state where the DRAM is kept in a self-
refresh state and most of the rest of the system is powered down. So
everything that can be switched off in the S0i3 state should be switched
off in order to maximize the standby time.
BUG=b:210722314
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If445f5825dc7b795c95d73c061156cc485421ada
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60125
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
|
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The AOAC device states shouldn't be stored in GNVS, but be read from the
AOAC registers during runtime. Same for the EHCI controller's BAR0. The
location and size of the XHCI firmware can either be statically
determined at build-time or have coreboot generate ACPI objects that
contain the needed addresses. Since I can't easily test changes that
require booting to a desktop on Stoneyridge at the moment, only add
TODOs for now.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Suggested-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Change-Id: I3691b05606b9430cb60923780a6131993a9887d4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60196
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
|
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Split the southbridge code into a bootblock and a ramstage part to align
it more with Picasso and Cezanne. Also move the implementation of
fch_clk_output_48Mhz to the end of early_fch.c since it's not really
related to the functions that were previously around it.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib660fbef8dc25ba0fab803ccd82b3408878d1588
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60142
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
|
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Split the code that gets called from the AGESA wrapper from the rest of
the FCH/southbridge code that directly interacts with the hardware.
Since the remaining parts of southbridge.c aren't used in romstage,
drop it from the list of build targets for romstage.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6197add0e1396a82545735653110e1e17bf9c303
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60141
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
|
|
Factor out enable_aoac_devices out of southbridge.c to aoac.c to align
Stoneyridge more with Picasso and Cezanne.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ied4d821138507639cad1794f6c5017b5873b761f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60140
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
|
|
Introduce and use an enum for the `power_profile` CMOS option. Add a
helper function that converts CMOS values into enum values. Using an
enum allows GCC to warn about switch statements using enum types for
their control expressions not handling all possible enum values, and
also improves readability.
Change-Id: I47a453ea12d164d26908a9944a89a481757e753c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60212
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <admin@starlabs.systems>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Rename `mainboard.c` to `smbios.c` as it only contains SMBIOS functions.
Rename `ramstage.c` to `mainboard.c` as it contains the mainboard chip
operations struct.
Change-Id: I9548ca72a7583de98f5b154e3381825bba00d5cf
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60211
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <admin@starlabs.systems>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
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We shouldn't be providing -I include paths to the root of the soc
specific directory. It allows for lazy includes that can collide,
but there's no way of knowing the winning path since the winning
path is determined by Makefile.inc parsing order.
This is taken from CB:41355
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I45ed219e4e0cccf3d4f04cc70dc1ef77c518afff
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60201
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I50d8c45e711dc62afe6f80e0f66422bcc9924dfd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60202
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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This is taken from CB:41355
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iba1948ae2332788b7e0ec9b4e3cea35c6608b152
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60200
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I9b37efc89e505c2de99536b59e7d7e2bb1d54bff
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60199
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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This is taken from CB:41355
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I10a18efb92ac0c3cad31044156e32aa6afe1d4d1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60198
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie716633bd7602d5e4a7e186aa9e444b7f70dab56
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60197
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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These boards program the early GPIO table in bootblock, not romstage.
Change-Id: Iae9353d106483f30cefa2d035d96e63e4c127261
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60210
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Sean Rhodes <admin@starlabs.systems>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
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Reuse the options from Kconfig.name for variant-specific selects.
Change-Id: I35f51756180882d019a3ea8c555ccd18cd588f44
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57761
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Reuse the options from Kconfig.name for variant-specific selects.
Change-Id: I29ce7ef6f5137c1cf43726faed6081a04c83dea6
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57760
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Update the parameter types of `intel_me_status()` to not be pointers.
Change-Id: I0fd577c49bec7a581c340fc2fcadcadd50b1a638
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59625
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Change the signature of MEI CSR functions to reduce pointer usage.
Change-Id: I1e4885daf8b3e11056421e663e67c8f360699a98
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59624
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Wrap bitfield structs in unions to reduce pointer usage. This adds more
uses of the `mei_dump()` function, only used for debugging. Refactoring
the MEI CSR functions to not use pointers is done in a follow-up.
Change-Id: I4defbb8c0e7812bf95c672ce529959f67c34537a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59623
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Wrap bitfield structs in unions to reduce pointer usage.
Change-Id: I8ac901211beb0ef24dff926b1a06004a99e68bda
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59622
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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There's no need to use typedefs for enum types. Get rid of it.
Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical.
Change-Id: I830d95018b33fe6ab7e2c37ebf15bb1df6ceec38
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59620
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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There's no need to use typedefs for struct types. Get rid of them.
Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical.
Change-Id: I109bd690500a9f03b9da0fd72044be79abf660d3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59619
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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The RTC on Cezanne is an unstable wake source when the system is in
S0i3. We instead need to use an internal timer that triggers a GPIO that
acts as a wake source. This change provides the ACPI necessary to allow
the OS to manage the wake source.
BUG=b:209705576
TEST=Boot guybrush with this patch and several OS patches. Verified the
OS sets the correct wake bit, the system correctly suspends
and resumes, and the wake source is correctly accounted for.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I1f14d14df5d30d48d244416f2ec8c10ac5c8040e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60172
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Limonciello <mario.limonciello@amd.corp-partner.google.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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We want ACPI to own the GPIOs. This will stop the GPIOs from being
exposed to the OS driver.
BUG=b:209705576, b:210694108
TEST=Dump ACPI table and verify GPIO are no longer in _CRS.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I8d2af41e1d04b98f0e3e19a95d7b91d08ecdf17b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60173
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
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Both the Picasso PPR #55570 Rev 3.18 and the Cezanne PPR #56569 Rev 3.03
define bit 9 of the PM_RST_STATUS register as internal Thermal Trip
reset status bit.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ida8b13fe62b16c18fc9924520b83220e73eca624
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60184
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
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Use the `popcnt()` helper instead of manually counting the number of set
bits in the first `CONFIG_MAX_CPUS` bits with a loop. Also, use unsigned
types to store the number of active/total cores.
Change-Id: Iae6b16991fcf07c9ad67d2b737e490212b8deedd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58912
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Setup eSPI to dedicated alert per the latest schematic changes.
DUT won't hang up at power on boot due to eSPI alert is triggerred
unexpectedly.
BUG=b:199458949,b:203446084
BRANCH=guybrush
TEST=emerge-guybrush coreboot chromeos-bootimage
test power on/reboot on DUT (6 units) each 10 loops->pass
Change-Id: I55cda7a1af22e555a4f55285cb7e337a69e6c234
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60082
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
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BRANCH=none
BUG=b:201478528
TEST=build and boot
Change-Id: I6130ee00a0e6f469142f5416627e38c7b5076071
Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60130
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Change-Id: I09aca01d9bb2624983e0d62628aef617c10eba9c
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60138
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Felwinter has non-stylus sku. Add a FW_CONFIG field to indicate
stylus presence and add a probe statement to the devicetree for the
corresponding device.
BUG=b:208937710
TEST=non-stylus doesn't register garage driver.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I06a2c125f2b5a73f9f7c27bf1b20ff8712664809
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60073
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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This reverts commit 7dce19080889955576f8fd197658077aced96a96.
Reason for revert: Unable to boot in factory mode
Change-Id: I1b51010080164c6e28d77a932f77c10006fd4153
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60030
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Address Mode 0: Physical Address, bit 63~56: 0x00
Address Mode 1: Relative Address to entire BIOS image, bit 63~56: 0x40
Address Mode 2: Relative Address to PSP/BIOS directory, bit 63~56: 0x80
Address Mode 3: Relative Address to slot N, bit 63~56: 0xC0
It is the expanding mode for simple relative address mode, for which
address_mode equals 1.
Only mode 2 is added. We need to record current table base address and
calculate the offset. The ctx.current_table is zero outside the
table. When it goes into the function to integrate the table, it
should backup the old value and get current table base. Before it goes
out the function, it should restore the value.
If the table address mode is 2, the address in each entry should be
also add address mode information. If not, the address mode in entry
is meanless.
The old mode 0,1 should be back compatible.
Change-Id: I29a03f4381cd0507e2b2e3b359111e3375a73de1
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59308
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Add ALC5682I-VD and ALC1019 for dewatt.
BUG=b:208172493
TEST=emerge-guybrush coreboot chromeos-bootimage; Tested with proto build.
Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Change-Id: Ie4d21a11377c73b913a8f79a92d5869ea70f4394
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60021
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
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Init basic override devicetree based on initial schematics
BUG=b:205908918
TEST=emerge-brya coreboot
Change-Id: Ibaa910eb1c5584197907963781258035c668298e
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59304
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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1. Fix typo in *based*
2. Use official spelling for Alder Lake
3. Mention *Converged Security*
4. Capitalize CMOS
Change-Id: I36eac6f017229a3e9261e0eb84371421927e1cae
Fixes: 941239d54d (Documentation/releases: Update 4.16 release notes)
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60133
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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See for example Intel document *Secure the Network Infrastructure –
Secure Boot Methodologies* [1].
Change all occurrences with the command below:
$ git grep -l BootGuard | xargs sed -i 's/BootGuard/Boot Guard/g'
[1]: https://builders.intel.com/docs/networkbuilders/secure-the-network-infrastructure-secure-boot-methodologies.pdf
Change-Id: I69fb64b525fb4799bcb9d75624003c0d59b885b5
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60136
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Preloading files before vboot runs and using them after vboot has
finished will result in the wrong files getting used. Disable
cbfs_preload to avoid this behavior.
BUG=b:179699789
TEST=none
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I7698b481a73fb24eecf4c810ff8be8b6826528ca
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59876
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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This change consolidates the COOP rules. Co-op in theory works in all
x86 stages now, but it hasn't been enabled yet.
BUG=b:179699789
TEST=Boot guybrush to OS and verify preloads still work
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I1197406d1d36391998b08e3076146bb2fff59d00
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59550
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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