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2018-05-15msrtool: use a bit more clever cpuid vendor matchLubomir Rintel
Not everything non-intel is AMD. Change-Id: I06d6fbaa0b4f2c9e61d9b3b4aeeb349a91aa090e Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-on: https://review.coreboot.org/18255 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-14sb/intel/i82371eb: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: Ie366a49045940747eb5cc1e38316cce31c5774cb Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26251 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-05-14nb/intel/fsp_sandybridge: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: Id3289c891e8a81c750fc3f5fad0fd16c0f2702fe Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26195 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-05-14nb/intel/i945/raminit.c: Remove not necessary braces {}Elyes HAOUAS
Braces {} are not necessary for single statement blocks. Change-Id: I2a2d8672fe3f53450dcfa53dc127b89b4aa6b75e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26201 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-05-14cbfs_locate: Optionally return file typeRonald G. Minnich
In some cases callers want to know if a file exists and, if so, what its type is. Modify cbfs_locate so that if the pointer is non-NULL, but has the value 0, the type of the file that matches the name will be returned. Change-Id: Ic1349d358c3054207ccbccf3825db56784327ad0 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: https://review.coreboot.org/26279 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-14soc/intel/denverton_ns: Enable common code for CPUJulien Viard de Galbert
Change-Id: Ib215aa17dd20112946b74a1b63ce8a735388873c Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/24927 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-14mb/scaleway/tagada: Update gpio configuration to use intelblockJulien Viard de Galbert
Update the gpio configuration structure to the intelblock format. The resulting configuration is functionally similar (even if some bits are not identical). Change-Id: Ide515424c6e1b0cb560b52a7f12909f23fd41e06 Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/25424 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-14soc/intel/denverton_ns: port gpio to intelblockJulien Viard de Galbert
The intelblock code is common code already used by appololake and cannonlake platform. The denverton platform also use a similar gpio controller so the intelblock code can be used as well. Change-Id: I7ecfb5a3527e9c893930149f7b847a41c5dd9374 Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/24928 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-14soc/intel/denverton_ns + mb: Rename gpio configurationJulien Viard de Galbert
In order to use the shared code in intelblock, this patch renames the denverton specific implementation to not use the same names (for files and types). - rename pad_config to remove conflict with soc/.../intelblocks/gpio.h - rename gpio.c, soc/gpio.h to not conflict with intelblock Note: There is no functional change in this patch. Change-Id: Id3f4e2dc0a118e8c864a96a435fa22e32bbe684f Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/24926 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-14Documentation: Add static CSS file to fix tablesPatrick Rudolph
Add a static CSS file to remove annoying scrollbars on rst code tables. Change-Id: I436b36fb7ee9856c7d6ad8534cd0610b7f071b17 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/26263 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-05-14security/vboot: Remove redundent _verstage/_everstage/_verstage_size symbolsSubrata Banik
All those symbols are part of /include/symbols.h file hence removing from /security/vboot/symbols.h Change-Id: Id968186e28d6b772a1a6bca200a852407324d6e3 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/26274 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-14pci: Fix compilation on non x86Patrick Rudolph
* Introduce pci_devfn_t on all arch * Add PCI function prototypes in arch/pci_ops.h * Remove unused pci_config_default() Change-Id: I71d6f82367e907732944ac5dfaabfa77181c5f20 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25723 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-14superio/nuvoton: Add support for NPCD378Patrick Rudolph
The NPCD378 can be found on at least: * HP Compaq 8200 * HP Compaq 8300 The datasheet is not publicly available, as HP implements lots of custom hardware. Add basic support for it, based on HP Compaq 8200. The first eight LDNs seem to be standard nuvoton compatible, except for LDN4, which is used to control front LED and power in ACPI S3. LDN8 provides access to HP's proprietary HWM which is accessiable at the LDN's IOBASE with a size of 0x100 bytes. The HWM consists of 16 pages with each holding 0xff bytes. The pages can be selected by writing the page index to IOBASE + 0xff. TODO: Reverse engineer the HWM to support fan control. WARNING: The remaining LDNs have been guessed and might be wrong! The serial has been tested and is working. Change-Id: Ib497fd41b88e9c159eeeffa69bc2bfdccee9cb38 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/25384 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-14cpu/x86: Add support to run function with argument over APsSubrata Banik
This patch ensures that user can pass a function with given argument list to execute over APs. BUG=b:74436746 BRANCH=none TEST=Able to run functions over APs with argument. Change-Id: I668b36752f6b21cb99cd1416c385d53e96117213 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/25725 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-05-14cpu/x86/mp: pass pointers to structures for AP callbacksAaron Durbin
In order to extend the MP callback infrastructure prepare for easier changes by making the AP callback get signalled by a single pointer to a local variable on the signaller's stack. When the APs see the callback they will copy the structure to a local variable and then set the acknowledgement by clearing out the slot. The reading and writing to the slots were implemented using inline assembly which forces a memory access and a compiler barrier. BUG=b:74436746 Change-Id: Ia46133a49c03ce3ce0e73ae3d30547316c7ec43c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/26043 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-14nb/intel/x4x/raminit: DDR3 specific ODTArthur Heymans
Change-Id: Ie32a008ce636b8eee6ed90c364978f7d37f4bfb2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19876 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-14nb/intel/x4x: Add DDR3 rcompArthur Heymans
Change-Id: Ifef905f5115ffc826b1a355e54c4b1ca818e56fa Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19875 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-14nb/intel/x4x/raminit: Support programming initials DD3 DLL settingArthur Heymans
Adapt the programming of initial DLL values for DDR3. Change-Id: I67e48b4ae6f2076399133ba7b98ab1dfc0e0ab08 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/22993 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-05-14nb/intel/x4x/raminit: Support programming DDR3 timingsArthur Heymans
Also throws in some minor fixes like the wrong conditional for bankmod and using real CAS when programming MCHBAR(0x248). Change-Id: Ia2494684ec66d84d4dc27c6a6b425a33ace6e827 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19873 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-05-14nb/intel/x4x/raminit: Make programming launch ddr3 specificArthur Heymans
Adds nmode to the sysinfo struct as it is needed later on. Change-Id: Ia2ca4a200a1c813b2133eb1004fbe248fa3de9ce Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19872 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-14nb/intel/x4x/raminit: Make programming crossclock support DDR3Arthur Heymans
A few values were wrong, but it does not seem to matter all that much. Change-Id: I86b70e06c81817854994b7feddf9f3638fd16198 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19871 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-14nb/intel/x4x: Rename a things that are not specific to DDR2Arthur Heymans
This memory controller supports both DDR2 and DDR3 memory, yet many functions have ddr2 in their name while not being ddr2 specific. This patch renames those to avoid confusion. Change-Id: Ib3d10014f530905155e56fc52706edb4ab9f5630 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19870 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-05-14nb/x4x/raminit: Decode ddr3 dimmsArthur Heymans
Since this memory controller supports both DDR2 and DDR3 allow it to decode both while making the dram type mutually exclusive. Change-Id: I8dba19ca1e6e6b0a03b56c8de9633f9c1a2eb7d7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19869 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-05-14nb/intel/x4x/raminit: Fix programming dual channel registersArthur Heymans
Some things in programming registers related to dual channel interleaved operation were wrong. This also adds some code that could in the future be used when me is active and claims some memory for its UMA. This also uses some more sensible variable names to clarify at least some of the magic. This fixes memtest86+ failing with some assymetric DIMM configuration. TESTED on DG43GT: memtest86+ now succeeds on many more different DIMM configuration setups (would instantly fail at addresses above 4G on many configurations). Change-Id: If84099d27100e57437bf214dc4cf975f67c2ea1f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/22914 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-05-14agesa/hudson/southbridge: add acpi name reporting for lpcKevin Cody-Little
Add an lpc_acpi_name function to report its namespace as "LIBR" rather than some fallback value which seems to vary. This repair is required for the LPC TPM device to register its presence without blowing up the table and preventing the payload from seeing the SATA device. Before change (but after other similar change to PCI0), the TPM device reported itself as: \_SB.PCI0.LPC0.TPM After change, the TPM device reports as: \_SB.PCI0.LIBR.TPM which is consistent with the tables AGESA generates. Change-Id: Ifa3a0e386cc00062855331e5f9d1c00d6541c238 Signed-off-by: Kevin Cody-Little <kcodyjr@gmail.com> Reviewed-on: https://review.coreboot.org/26205 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-05-14agesa/family16kb/northbridge: report acpi namespaceKevin Cody-Little
Add a function domain_acpi_name to return "PCI0", rather than falling back to the parent' device's "\_SB" label. This repair is required for the LPC TPM device to register its presence without blowing up the table and preventing the payload from finding SATA. Before change, the TPM device reported as: \_SB.\_SB.LPC0.TPM After change, the TPM device reports as: \_SB.PCI0.LPC0.TPM A separate change submission will correct "LPC0" as well. Change-Id: I5e8d4715c9b42f50c84dd65818e4b0fdfc9d54f9 Signed-off-by: Kevin Cody-Little <kcodyjr@gmail.com> Reviewed-on: https://review.coreboot.org/26204 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-05-14timestamp: Increase max number of timestampsRaul E Rangel
I'm increasing the max because when AGESA tracing is enabled it will use over 120 entries. I added some padding to the number incase more probes are added. This only affects ramstage so the extra ram shouldn't matter. BUG=b:64549506 TEST=boot on grunt and ran cbmem -t Change-Id: I7a3d2d09c91c9e302d139e7f65fa9c85c4594de4 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/26234 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-14grunt: use stage cache when waking from S3Raul E Rangel
BUG=b:79154155 TEST=built and tested on grunt 31 entries total: 0:1st timestamp 20,917 900:calling AmdInitReset 87,525 (66,608) 901:back from AmdInitReset 98,318 (10,793) 902:calling AmdInitEarly 99,165 (847) 903:back from AmdInitEarly 139,619 (40,454) 5:start of verified boot 156,301 (16,682) 503:starting to initialize TPM 156,697 (396) 504:finished TPM initialization 186,107 (29,410) 505:starting to verify keyblock/preamble (RSA) 187,316 (1,209) 506:finished verifying keyblock/preamble (RSA) 208,000 (20,684) 507:starting to verify body (load+SHA2+RSA) 208,108 (108) 508:finished loading body (ignore for x86) 273,238 (65,130) 509:finished calculating body hash (SHA2) 290,364 (17,126) 510:finished verifying body signature (RSA) 294,236 (3,872) 511:starting TPM PCR extend 295,071 (835) 512:finished TPM PCR extend 320,512 (25,441) 513:starting locking TPM 320,514 (2) 514:finished locking TPM 332,081 (11,567) 6:end of verified boot 332,083 (2) 13:starting to load romstage 332,187 (104) 4:end of romstage 395,559 (63,372) 10:start of ramstage 395,999 (440) 916:calling AmdS3LateRestore 396,135 (136) 917:back from AmdS3LateRestore 428,066 (31,931) 30:device enumeration 428,087 (21) 40:device configuration 434,640 (6,553) 50:device enable 438,185 (3,545) 60:device initialization 439,565 (1,380) 70:device setup done 453,326 (13,761) 918:calling AmdS3FinalRestore 454,363 (1,037) 919:back from AmdS3FinalRestore 455,520 (1,157) 98:ACPI wake jump 467,541 (12,021) Total Time: 446,624 Change-Id: I326e81d3c987130e258c616c7c66dd82ddc0d942 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/26219 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-14program_loading: make types a mask, make unknown type a non-zeroRonald G. Minnich
This will allow loading of programs that are more than one type, e.g. ramstage type might now be a stage or payload. Further, unknown types of 0 are dangerous, make it a real value. Change-Id: Ieb4eeb7c5934bddd9046ece8326342db0d76363c Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: https://review.coreboot.org/26242 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-05-13drivers/pc80/tpm: get ioport from pnp recordsKevin Cody-Little
Had 0x2e hardcoded, which is often the SuperIO chip. Instead, pull the port from the PNP tree generated from devicetree.cb, where either 0x4e or 0x2e will be specified. Change-Id: I4a92693f8acd3a1618cefcdf6b25eb22a727e20f Signed-off-by: Kevin Cody-Little <kcodyjr@gmail.com> Reviewed-on: https://review.coreboot.org/26203 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-05-13cbmem: Sort timestamp entriesRaul E Rangel
If the timestamp entries are added out of order, the duration calculation will be wrong. AGESA collects timestamp data through all the stages. Then in AmdInitPost it asks for a buffer to write TP_Perf_STRUCT into. agesawrapper will then take the data and call timestamp_add on each entry. This results in the entries being out of order. TEST=Built firmware for grunt that manually added entries and then ran cbmem -t/-T to verify the entries were in the correct order. Change-Id: I6946a844b71d714141b3372e4c43807cfe3528ad Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/26168 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-13mainboard/asus: Add license headersNoah Glovsky
Change-Id: I71e461b91f981368d4bd13631b868430d1fc5774 Signed-off-by: Noah Glovsky <noah.glovsky@watershedschool.org> Reviewed-on: https://review.coreboot.org/14530 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-05-13mainboard/hp: Add HP Elitebook 8770wxiinc37
This is based on the code from the 8470p port. Tested on the quad core/quad SODIMM version. This laptop uses discrete MXM 3.0b graphics cards. Tested working with both Quadro K3000M and GTX 980M 8GB. The laptop must be completely disassembled down to the motherboard to perform the initial flash, subsequent flashes can be done internally via flashrom. There is a simple mod that can be performed to make subsequent external flashes easier in case of a brick, I'll put more information on this on the wiki later. The lack of an MXM structure built in to the firmware causes the GPU to enter a mode with nerfed performance, there is a workaround though, I'll add this to the wiki as well. I have no info on EHCI debugging. Tested and working: - memory: 4G+4G, 4G+4G+4G+4G - Linux (Debian Stretch with kernel 4.9.0) booted from SeaBIOS payload with graphics init disabled in coreboot. I allowed SeaBIOS to load the VBIOS from the MXM. - WLAN - keyboard, trackpoint and touchpad - USB - serial port on dock - fan control - VGA - DisplayPort - Audio - Both HDD SATA ports, ODD SATA, eSATA - S3 with SeaBIOS 1.11, SERCON must be disabled - Brightness and volume FN keys - Mute and calculator hotkeys - Status LEDs - Bluetooth Not working: - GRUB2 as payload will freeze. Has something to do with at_keyboard module. The built in keyboard requires this module to function though. - Sleep FN key - WiFi toggle and internet browser hotkeys - S3 fails to resume (restarts) if the laptop is removed from AC power, or gets unplugged and then plugged back in while suspended. Sleep status LEDs remain normal during this process. Change-Id: Ic4ff64e9cf0c7a51ac48ca2fe6fe8beab02e9f9a Signed-off-by: Robert Reeves <xiinc37@gmail.com> Reviewed-on: https://review.coreboot.org/23651 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-05-13timestamp: Add timestamps for TPM communicationRaul E Rangel
On grunt these operations combined take a little over 37ms. BUG=b:64549506 TEST=built on grunt 511:starting TPM PCR extend 301,268 (598) 512:finished TPM PCR extend 326,710 (25,442) 513:starting locking TPM 326,716 (6) 514:finished locking TPM 339,517 (12,801) Change-Id: I05cfb3d0f8463f073e329a035484a340546649e1 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/26218 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-13msrtool: add support for printing string valuesLubomir Rintel
The VIA CPUs allow setting the CPUID vendor, which is best read as a character string. Change-Id: I67f77ca75f7d77e47b3ba09bad904df5805e373a Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-on: https://review.coreboot.org/18257 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-05-13mstrool: only use intel targets for actual intel CPUsLubomir Rintel
VIA c3 & C7 use the the family of 0x6 and model 10, but are not quite Pentium III. Change-Id: I85e9853b42cfd20db46db0bd244620d6813bc826 Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-on: https://review.coreboot.org/18256 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-12superio/ite/it8623e: initialize the PWM fan controllerKevin Cody-Little
Copies the common/env_ctrl support code from the it8728f driver. Tested on an ASUS AM1I-A using Linux 4.16.7-gentoo as payload, and booting userspace without a kexec call. Prior to this change, an error was given during boot: it87 it87.656: Detected broken BIOS defaults, disabling PWM interface After this change, the message is gone, and PWM fan control works through the /sys/class/hwmon interface. Change-Id: Id97c4ec19562e7c78308c5afe6ff7c938922c9e7 Signed-off-by: Kevin Cody-Little <kcodyjr@gmail.com> Reviewed-on: https://review.coreboot.org/26224 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-12Revert "3rdparty/blobs: Update submodule marker for Intel microcode updates"Nico Huber
This reverts commit 0ff9daac45d604fa4864394616e335e20af26c3e. It points to a stale commit under review; i.e. not to a commit on blob.git's master branch like it's supposed to. Change-Id: I19cb8a32b3971c3104e381673ca08ae4d3979128 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/26241 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-05-12mb/google/poppy/variants/nami: Provide implementation of mainboard_vbt_filenameFurquan Shaikh
This change adds board-specific implementation of mainboard_vbt_filename which returns "vbt.bin" by default. This is in preparation to allow multiple vbt binaries to be added to single image. More sku_id specific names will be added in follow-up CLs. BUG=b:79396300 Change-Id: I3821d55bfbe9e5773bd2eb0b0003045a80158d8c Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/26227 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-11purism/librem_bdw: Rename Broadwell baseboard from BDL to BDWYouness Alaoui
My bad, it seems the acronym for Broadwell is BDW, and not BDL, so I'm renaming librem_bdl into librem_bdw and changing the KConfig options accordingly. Change-Id: I8e992aa3474863236adf8893fcbe37c1b801fa25 Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Reviewed-on: https://review.coreboot.org/26237 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-11drivers/intel/gma: honor vbt_size parameter to locate_vbt()Aaron Durbin
In 4a3956d7 (drivers/intel/gma, soc/intel/common: improve cooperation) the vbt_size parameter was not honored leading to the use of unitialized variables from the caller. Instead, keep track of if the vbt is already loaded by using the size returned from the load. If it's non-zero the vbt has been loaded. BUG=b:79562868 Change-Id: Ia1c47f0d982fae74e0223922f83943c68a846aa9 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/26236 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-11mainboard/google/coral: Override VBT selection for epauletteren kuo
Current VBT setting for T8 is only 1ms which is under Innolux N116BCA-EA1 panel's spec. Modify T8 to 100ms. (Innolux's panel's spec requires T8 needs to be greater than 80ms BUG=b:78541692 BRANCH=master TEST=emerge-coral depthcharge coreboot chromeos-bootimage Run on DUT and check panel sequence meets spec. Change-Id: I5f9103aca7871095a828a74cd6a97e1951adb81f Signed-off-by: Ren Kuo <Ren.Kuo@quantatw.com> Reviewed-on: https://review.coreboot.org/26214 Reviewed-by: Ren Kuo <ren.kuo@quantatw.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-11mb/google/reef/variants/: Add new memory IDren kuo
Add a new RAM ID of memrory PN:MT53E512M32D2NP BUG=b:78491470 TEST= emerge-coral coreboot chromeos-bootimage. Signed-off-by: Ren Kuo <Ren.Kuo@quantatw.com> Change-Id: I855702c2850887df74941e00da69322124557498 Reviewed-on: https://review.coreboot.org/26213 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Ren Kuo <ren.kuo@quantatw.com>
2018-05-11asrock/b75pro3-m: Add superio ACPI declarationsIru Cai
Without it the PS/2 keyboard doesn't work after booting into the OS. Change-Id: Idcb0ea0779fcd5dfd6e0fbf33a532ecf0caec420 Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/26131 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-11purism/librem_bdl: Add support for Librem 15 v2Youness Alaoui
Adding new librem_bdl variant for the Librem 15 v2, which is very similar to Librem 13 v1, with the following differences: - SATA ports 0 and 1 instead of 0 and 3 - SATA DTLE IOBP value is 7 instead of 9 for port 0 - There is no LAN device - There are two SODIMM slots, and DQs are interleaved - USB ports are different Change-Id: Ifaca382a540d085e6c919daa992a0fbd52643a5b Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Reviewed-on: https://review.coreboot.org/26184 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-11purism/librem_bdl: Convert to variant setupYouness Alaoui
Convert the purism/librem13v1 to a variant setup, in preparation for adding the librem15v2 board as a new variant. The Librem 13 v1 and Librem 15 v2 are nearly identical, so this minimizes new code to add support for the latter. Also update the URL in board_info to an archive.org link. Change-Id: I00bb82b9e895e2464ddaa92915c01ce0e35933a2 Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Reviewed-on: https://review.coreboot.org/26183 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-11nb/intel/i945/bootblock.c: Correct commentElyes HAOUAS
Change-Id: Ic28ff80eb1dae6d0a307e2a1b73e8129fffbac13 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26207 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-11nb/intel/i440bx: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: I69c8b95ff1937c0b08147d9e26a3118c58129cf5 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26197 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-05-11acpi: Add support for writing ACPI _PLD structuresDuncan Laurie
This commit adds support for writing ACPI _PLD structures that describe the physical location of a device to the OS. This can be used by any device with a physical connector, but is required when defining USB ports for the OS. A simple function is provided that generates a generic _PLD structure for USB ports based on the USB port type. Change-Id: Ic9cf1fd158eca80ead21b4725b37ab3c36b000f3 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/26171 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-05-11acpi: Add support for generating ACPI _UPCDuncan Laurie
This commit adds support for writing ACPI _UPC structures that help describe USB ports for the OS. This is a simple structure format which indicates what type of port it is and whether it is connectable. It should be paired with an ACPI _PLD structure to define USB ports for the OS. Change-Id: Ide3768f60f96e9ad7f919ad3fb11d91045dc174a Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/26170 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-11devicetree: Add USB device typeDuncan Laurie
This commit adds support for describing USB ports in devicetree.cb. It allows a USB port location to be described in the tree with configuration information, and ACPI code to be generated that provides this information to the OS. A new scan_usb_bus() is added that will scan bridges for devices so a tree of ports and hubs can be created. The device address is computed with a 'port type' and a 'port id' which is flexible for SOC to handle depending on their specific USB setup and allows USB2 and USB3 ports to be described separately. For example a board may have devices on two ports, one with a USB2 device and one with a USB3 device, both of which are connected to an xHCI controller with a root hub: xHCI | RootHub | | USB2[0] USB3[2] device pci 14.0 on chip drivers/usb/acpi register "name" = ""Root Hub"" device usb 0.0 on chip drivers/usb/acpi register "name" = ""USB 2.0 Port 0"" device usb 2.0 on end end chip drivers/usb/acpi register "name" = ""USB 3.0 Port 2"" device usb 3.2 on end end end end end Change-Id: I64e6eba503cdab49be393465b535e139a8c90ef4 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/26169 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-11Dokumentation: Sphinx add RST in markdown supportPhilipp Deppenwiese
* This feature embedds RST into markdown for table generation. For more information, see http://recommonmark.readthedocs.io/en/latest/index.html#autostructify Change-Id: Iefebb3b7857bc98818e345f7d0e95fbf987305a8 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/26190 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-11mb/google/poppy/variants/atlas: add SPD for new samsung 4GB memoryCaveh Jalali
This adds a new SPD entry for samsung's new 4GB memory and updates atlas to use it instead of the previous gen memory. BUG=b:79444337 TEST=booted on atlas Change-Id: I19567736c45a1321586378c3d964c2cbebe24755 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/26185 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-11mb/google/octopus: Ignore standby state for DMIC pinsShamile Khan
This keeps Audio clock and data pins ON in S0ix to support Wake on Voice. BUG=b:77605180 BRANCH=none TEST=Checked that S0ix suspend/resume works. Validation of WoV was done on glkrvp previously. For Yorp, audio topology firmware updates are required for testing WoV. Change-Id: Idafe4e7d24fe16f8e8ff3dd86e299776ea860d03 Signed-off-by: Shamile Khan <shamile.khan@intel.com> Reviewed-on: https://review.coreboot.org/26202 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-113rdparty/blobs: Update submodule marker for Intel microcode updatesMartin Kepplinger
This moves the blobs submodule marker forward to include the following: b45abbd cpu/intel: microcode: add license agreement 1d37962 cpu/intel: add microcode updates 20180312 for new CPU models 8b8bbce cpu/intel: apply microcode updates 20180312 to currently tracked models in short: bump Intel's microcode updates to the latest version. This includes Spectre/Meltdown mitigations. Change-Id: I4ab74ae0bdcf2a109b0697ad233fbb812b5c4544 Signed-off-by: Martin Kepplinger <martink@posteo.de> Reviewed-on: https://review.coreboot.org/25505 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-11mb/google/poppy/variants/nami: add 2-channel LPDDR3 memoryT.H. Lin
hynix/H9CCNNNCLGALAR-NUD nayna/NT6CL256T32CM-H1 BUG=b:79443146 BRANCH=Nami TEST=emerge-nami coreboot chromeos-bootimage Change-Id: I3a362080b9e60adecbac14d5cfe193da44bf87c8 Signed-off-by: T.H. Lin <t.h_lin@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/26187 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-10AGESA f14: Remove OPTION_DDR2Kyösti Mälkki
Was never used for the boards in our tree. Change-Id: Ib9e9ab25ccb8d1d556fdeb8bb4c6558f25bb81b6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26041 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-05-10AGESA f14 vendorcode: Only have f14 Ontario configKyösti Mälkki
Change-Id: I8cf2f23d785e934371dfa687483491cd22b9863d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21306 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-05-10bootmem: Keep OS memory map separate from the startJulius Werner
The patch series ending in 64049be (lib/bootmem: Add method to walk OS POV memory tables) expanded the bootmem framework to also keep track of memory regions that are only relevant while coreboot is still executing, such as the ramstage code and data. Mixing this into the exsting bootmem ranges has already caused an issue on CONFIG_RELOCATEABLE_RAMSTAGE boards, because the ramstage code in CBMEM is marked as BM_RAMSTAGE which ends up getting translated back to LB_RAM in the OS tables. This was fixed in 1ecec5f (lib/bootmem: ensure ramstage memory isn't given to OS) for this specific case, but unfortunately Arm boards can have a similar problem where their stack space is sometimes located in an SRAM region that should not be made available as RAM to the OS. Since both the resources made available to the OS and the regions reserved for coreboot can be different for each platform, we should find a generic solution to this rather than trying to deal with each issue individually. This patch solves the problem by keeping the OS point of view and the coreboot-specific ranges separate from the start, rather than cloning it out later. Ranges only relevant to the coreboot view will never touch the OS-specific layout, to avoid the problem of losing information about the original memory type of the underlying region that needs to be restored for the OS view. This both supersedes the RELOCATABLE_RAMSTAGE fix and resolves the problems on Arm boards. Change-Id: I7bb018456b58ad9b0cfb0b8da8c26b791b487fbb Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/26182 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-09mainboard/google/.../terra: Fix ACPI external definition errorsMartin Roth
According to ACPI 6.1 spec 19.6.44, External informs compiler that object is external to this TABLE, no necessary for object in same DSDT tables. A name cannot be defined and declared external in the same table (GPID) A name cannot be defined and declared external in the same table (CTOK) Change-Id: Ica80b59ad6a8af865bf1551ac4e014ec5f4e7d08 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/26122 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-09mb/google/poppy/variants/nocturne: update Audio configurationSathyanarayana Nujella
This patch updates the below: 1) Nocturne board has only Max98373 speaker amp. Update both NHLT and DT entries to include only Max98373 and not include DA7219. 2) I2S2 is used for Boot Beep. So, update GPP_F0 ~ F2 pins accordingly. 3) Include DMIC-4ch configuration. BUG=b:79362472 TEST=None [Waiting for HW to verify] Change-Id: I0e9b3a564c22de6e84e96e5e937a3aca4ae73d75 Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-on: https://review.coreboot.org/26143 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-09lenovo: Add various data.vbtPatrick Rudolph
Add the Video Bios Table to improve user experience when running coreboot's blob free graphics init. As it's not a binary blob it should not be added to the blobs repo. This is taken from vendor BIOS and contains purely documented configuration data, so it should not be subjected to copyright. Extracted using intelvbttool with applied patch I8cbde042c7f5632f36648419becd23e248ba6f76 "util/intelvbttool: Rewrite tool" Change-Id: I15573ddd37ee9738df1f7178f967131687a50f48 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/25926 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-05-09util/lint: Ignore whitespace, newlines, and licenses in vbt filesMartin Roth
Change-Id: I84f612db058d83936ddd5a6baa32c993e5b0f594 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/26064 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-09drivers/intel/gma, soc/intel/common: improve cooperationPatrick Georgi
Instead of both featuring their own VBT loaders, use a single one. It's the compression-enabled one from soc/intel/common, but moved to drivers/intel/gma. The rationale (besides making all the Kconfig fluff easier) is that drivers/intel/gma is used in some capacity on all platforms that load a VBT, while soc/intel/common's VBT code is for use with FSP. BUG=b:79365806 TEST=GOOGLE_FALCO and GOOGLE_CHELL both build, exercising both affected code paths. Change-Id: I8d149c8b480e457a4f3e947f46d49ab45c65ccdc Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/26039 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-09mainboard/asus/am1i-a: fix interrupt routing definitions in DSDTGergely Kiss
Incorrect interrupt routing configuration prevented handling interrupts for devices behind PCIe bridges 00:02.1 and 00:02.5. With the new configuration, devices work as expected. Tested with Linux 4.10 booted with the "pci=nomsi" parameter. Change-Id: I3c95be7ba6207697afc7983d4b5f9d9a28584723 Signed-off-by: Gergely Kiss <mail.gery@gmail.com> Reviewed-on: https://review.coreboot.org/23771 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-09mb/technexion: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: I6efd1675b1124b200b5ff16fdef91c10b77b69d1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26094 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-05-09mb/avalue: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: I7f1276ee593928956913eaeecd62fd3018cc9ae2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26077 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-05-09mb/asrock: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: I4b2b8593c98791dac7a5c016e75d2c05bcfbf890 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26075 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-05-09mb/a785e-i: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: I15f160c1e30496461f7100e3bd3a2e2467c64c4a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26071 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-05-09cpu/amd/quadcore: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: I6cb8f36dea4a22fdf05c57bb3e3dcaeb2da8020f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26066 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-05-09mb/asus: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: I8fe817bb514c69a647c2208a0573a2c5fe98722d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26076 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-09mb/bap: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: I6fc056acb8ff16a943352342b99a9ede6558d438 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26078 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-09mb/amd: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: I01270248bddf07df4c959f0c632e722728d0cd03 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26072 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-09{device,drivers,lib,mb,nb}: Use only one space after 'if'Elyes HAOUAS
Change-Id: I390191fb58605d1bd6a2e5d19a9dfa7c8493e6b2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26063 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-09sdm845: Add DRAM resourcesT Michael Turney
TEST=build Change-Id: Icf934caf8b4584ef2633054a5cc7f5be7cc734ee Signed-off-by: T Michael Turney <mturney@codeaurora.org> Reviewed-on: https://review.coreboot.org/25212 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-05-09src/southbridge: Serialize methods with named objects insideMartin Roth
Change-Id: Ia9d884d7247f0cc3a175de31649d0163c69f1299 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/26152 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-09src/mainboard: Serialize methods with named objects insideMartin Roth
Change-Id: I90e1d8b9f8e37bec8fc2796637b4548ea17e076b Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/26151 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-05-09mainboard/bap/ode_e20xx: Remove commented out asl code.Martin Roth
Change-Id: I64229d12e9e7fd54eaae3425ae9546872c5bf8f3 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/26150 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-05-09vendorcode/amd/pi/00670F00: Control which procedure buildsRichard Spiegel
Vendor code is compiled as a library, thus the whole library is included into the final image. However, not all procedures are required, they are there because original AGESA code had them. We cannot remove them, in order to facilitate porting of fixed AGESA code. Therefor add #if throughout the code to allow the control if unneeded procedures will be build. BUG=b:78610011 TEST=Build and boot grunt; build kahlee and gardenia. Change-Id: I68f9e359b2331f715a3b85486c4181866985afdf Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/26135 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-09vendorcode/amd/pi/00670F00: Remove unneeded includesRichard Spiegel
Vendor code has several headers included into source code that are not needed in order to build them. Remove unneeded #include. This is part of controlling the build of unneeded procedures within vendor code. BUG=b:78610011 TEST=Build grunt. Change-Id: Id7d451b6be564632836fc64fd343131edb85183a Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/26134 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-05-09mb/gizmosphere: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: I75258ecc5f3881012c3f767c8b970a1f10c6abbd Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26085 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-05-09mb/elmex: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: If4ec2e2e7cca8d8f3e5abfd9cd204f86e367b44a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26081 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-05-09mb/esd: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: I5928e871b8e9ba5964c02fbabb7a9d8dc9ecc0a8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26082 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-05-09mainboard/google/eve: Add subsystem_idHarsha Priya
This patch adds subsystem_id for eve as 0x006B. The value is set in nhlt structure which will be used by endpoints as well. Change-Id: Id6910678c4d6e92ed45c776f174855efd26f9e27 Signed-off-by: Harsha Priya <harshapriya.n@intel.com> Reviewed-on: https://review.coreboot.org/26139 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-09lib/nhlt: add support for passing subsystem_id to endpoint's structureHarsha Priya
This patch adds subsystem_id to nhlt structure whose value is passed on to the endpoint's structure. Its default value is retained to be NHLT_SSID. Change-Id: Iad53f27e958f50e02e928cd8fa60d8397ca0eb06 Signed-off-by: Harsha Priya <harshapriya.n@intel.com> Reviewed-on: https://review.coreboot.org/26046 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-09util/xcompile: prefer riscv64 over riscvPatrick Georgi
gcc 8.1 insists. Change-Id: I8cb00fafdfff7679e38f357c6e8968da656c351d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/25995 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-09console: Skip non-BSP printk() earlierKyösti Mälkki
Fix regression after commit: 6032018 console: only allow console messages after initialization Bail out early on AP CPUs, this avoids use of CAR_GLOBAL when we have SQUELCH_EARLY_SMP=y. Change-Id: I506c5fbec43a6eb6f6d9362d62a040def9e1e7bb Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26120 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-09mb/google/poppy/variants/nami: Add support for getting OEM name from CBFSFurquan Shaikh
This change: 1. Allows mainboard to add OEM table to CBFS 2. Provides mainboard specific smbios_mainboard_manufacturer that reads OEM ID from EC using CBI and compares it against the OEM ID in CBFS table to identify the right OEM string. BUG=b:74617340 Change-Id: Iff54b12745de3efa7be0801c9a3a9f2a57767dde Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/26142 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-08amd/common/pi: Insert missing newline in printkMarshall Dawson
Add a newline to the unsupported callout message. Change-Id: I9bfff0ed920843f6c0818b51ee0046366f2a5c8d Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/26144 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-05-08mb/google: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: I8e549e4222ae2ed6b9c46f81c5b5253e8b227ee8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26086 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-08mb/aopen/dxplplusu: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: I3857d7ef4eb02974aabe3029abb49efb218cbd93 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26073 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-05-08mb/hp: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: Ib9c0d0a85a9e38cdb1bdbcfa055e597f19cf3d5c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26087 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-05-08mb/getac: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: Ie5ed621423315388e2b8eb3d5433ef2a7a47d602 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26083 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-05-08mb/biostar: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: Ifc9d82270513f4b4f34d9cf210c37029202b5a5f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26079 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-05-08mb/sapphire: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: I93b2ce6a26b3a64bd6f4e4c827e9f551b37c6dd0 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26098 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Nicola Corna <nicola@corna.info>
2018-05-08mb/broadcom: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: Icf7c99ca55d2bcbca2c974d59a63e89758ba5ea6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26080 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-05-08soc/intel/skylake: Support PCH UART 0 and 1 for consoleDuncan Laurie
The current PCH UART support for console is limited to UART2. This change adds support for specifying UART0 or UART1 to be used instead by changing CONFIG_UART_FOR_CONSOLE in the board level Kconfig. The default is still 2. This is tested with a board that uses UART0 for debug output. Change-Id: I91323ed3298f9b2558764aa4b54173833c021a7b Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/26140 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-08soc/intel/fsp_broadwell_de: Spell verb *set up* with spacePaul Menzel
Change-Id: If2e66f3531696d430b3ae133c4b7ec0d929713b7 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/26129 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-05-08mb/siemens: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: If67ea25a9e1363dde8aefe62b92ee7a61f0458b0 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26097 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2018-05-08mb/sifive: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: I8c6358d072b25ab4758637da989883daa600c8ee Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26099 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-20 00:29:39 +0000