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2018-04-27google/kahlee: Add RW_NVRAM to FMAPMarc Jones
Add RW_NVRAM area to FMAP for VBOOT_VBNV_CMOS_BACKUP_TO_FLASH support. BUG=b:77347873 TEST=Manually clear CMOS and check coreboot restores VBNV from flash. Change-Id: Id8c6f54634b94bf6ae3755a827e80d0862a42dd2 Signed-off-by: Marc Jones <marc.jones@scarletltd.com> Reviewed-on: https://review.coreboot.org/25843 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-04-27soc/amd/stoneyridge: Enable CMOS VBNV backup to flashMarc Jones
Now that we have SPI flash writes working, we can support VBOOT_VBNV_CMOS_BACKUP_TO_FLASH. This requires the mainboard to reserve the area in FMAP. BUG=b:77347873 TEST=Manually clear CMOS and check coreboot restores VBNV from flash. Change-Id: I488dbfc4c200f5100374d47feb0a0522e6a60e88 Signed-off-by: Marc Jones <marc.jones@scarletltd.com> Reviewed-on: https://review.coreboot.org/25842 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-27libpayload/include/queue.h: Remove trailing whitespaceElyes HAOUAS
Change-Id: I7ff676f51958e12c40a82f56e68a776ddf429228 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/25825 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-04-27mb/lenovo/x1_carbon_gen1/spd: remove trailing whitespaceElyes HAOUAS
Change-Id: Ic81a172cdeb6c0dca396312393897613c1c51191 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/25841 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-04-27mb/pcengines/apu2/spd: Remove unneeded whitespaceElyes HAOUAS
Change-Id: I0c59cefa4067d3fc01b8425184e10d3caf1c81ac Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/25839 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-04-27Documentation/Doxyfile.coreboot: Remove trailing whitespaceElyes HAOUAS
Change-Id: I9218766d14b971c1703ac8de9766138b71728eee Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/25836 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-04-27Documentation/COPYING: Remove trailing whitespaceElyes HAOUAS
Change-Id: I796159f055a19537247652ecb3e86a03f3104a3c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/25835 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-04-27payloads/coreinfo/README: Remove trailing whitespaceElyes HAOUAS
Change-Id: I467376bab942eac1b6f1f8544bdd96202335b75d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/25833 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-04-27payloads/external/tianocore: Remove trailing whitespaceElyes HAOUAS
Change-Id: Ibb15d370beb8ba34f24bd86eed19de38a3df3561 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/25832 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-04-27Documentation/Intel/NativeRaminit: Remove trailing whitespaceElyes HAOUAS
Change-Id: I1d38aea07e2d9ffb89115410603a5beac5e4d44d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/25831 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-04-27libpayload/curses/form: Remove trailing whitespaceElyes HAOUAS
Change-Id: I231ea26e8d8bfc53da22a440451802b425c996b0 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/25830 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-04-27payloads/libpayload/curses/menu: Remove trailing whitespaceElyes HAOUAS
Change-Id: Ia4bd5224a77914e0561fa35a18aec8db16bff320 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/25829 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-04-27RISC-V boards: Remove PAGETABLES section from memlayout.ldJonathan Neuschäfer
RISC-V doesn't set up page tables anymore, since commit b26759d703 ("arch/riscv: Don't set up virtual memory"). Change-Id: Id1e759b63fb0bc88ab256994d3849d16814affa0 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/25701 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2018-04-27drivers/uart: Allow the 8250IO driver only on x86Jonathan Neuschäfer
The driver relies on I/O space access functions (inb, etc.), which are only available on x86. Rather than explicitly disallowing it on ARM, allow it only on x86. TEST=Configure for RISC-V, and see that "Serial port on SuperIO" is not available in the "Generic Drivers" menu anymore. Change-Id: Ib8e8c402264afeba6dc098683c5464af6edb3ba3 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/25631 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2018-04-27vendorcode/intel: Update GLK FSP Header files w.r.t FSP v2.0.2Srinidhi N Kaushik
Update FSP header files to match FSP Reference Code Release v2.0.2 for Gemimilake CQ-DEPEND=CL:*594651,CL:*598345 Change-Id: I78d064db41a54d97e98d6e44e0832724127e5bfc Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Reviewed-on: https://review.coreboot.org/25757 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-27util/x86/x86_page_tables: add command line to generated filesAaron Durbin
In order to help the reader understand where things are generated from add a comment string that is composed of the command line used to generate the files. BUG=b:72728953 Change-Id: I1b93923f8b08192448ab19226fd27661cc09e853 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/25834 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-04-27mb/google/poppy,soraka,nautilus: Enable xDCIFurquan Shaikh
This change enables xDCI controller on poppy, nautilus and soraka. BUG=b:78577893 BRANCH=poppy Change-Id: I9b0f81bda889b822479ead4d1acc2b613151a304 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/25849 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-27soc/intel/common/block/xdci: Use vboot_can_enable_udc in xdci_can_enableFurquan Shaikh
This change uses the newly added vboot_can_enable_udc to decide if it is okay to enable xDCI in vboot developer mode. BUG=b:78577893 BRANCH=poppy Change-Id: Ia83b91ce17eec782faf5bb318ad8c00c09e2db05 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/25848 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-04-27security/vboot: Add function to check if UDC can be enabledFurquan Shaikh
Add a function that will check the various requirements to enable USB Device Controller (UDC): - developer mode enabled - GBB flag set or VBNV flag set If VBOOT is not enabled, then default is to allow UDC enabling. BUG=b:78577893 BRANCH=poppy Change-Id: Id146ac1065f209865372aeb423f66ae734702954 Signed-off-by: Duncan Laurie <dlaurie@google.com> Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/25847 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-27security/vboot: Add function to read UDC enable flagFurquan Shaikh
This change adds a helper function to read USB Device Controller (UDC) enable flag from VBNV. BUG=b:78577893 BRANCH=poppy Change-Id: Ifd1e9b0781ffee242d695b72287632bc944a50c7 Signed-off-by: Duncan Laurie <dlaurie@google.com> Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/25846 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-26mainboard/google/kahlee: Set SPI speed in bootblockMarc Jones
Set the SPI speed for Normal, Fast, AltIO, and TPM in bootblock. This setup is needed when moving AGESA out of the bootblock. It sets the SPI bus speed of the TPM access in verstage. BUG=b:70558952 TEST=Boot with AGESA moved out of the bootblock. Change-Id: Ida77d78eb1f290e46b57a46298400ed6c8015e2c Signed-off-by: Marc Jones <marc.jones@scarletltd.com> Reviewed-on: https://review.coreboot.org/25756 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-04-26soc/amd/common/block/include/amdblocks/psp.h: Replace todo messageRichard Spiegel
It was decided to not add the buffers definitions, so the todo message is obsolete. Replace it with minimum instructions about when a new buffer will be needed. It was also noticed a typo in one command. MBOX_BIOS_CMD_C3_DATA_INFO is about S3 transition, so it should be called MBOX_BIOS_CMD_S3_DATA_INFO. BUG=b:77940747 TEST=None. Change-Id: I6143d7e85476061395962b95ad8864ac32a1d4a3 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/25740 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-26src: Fix a typo on "mtrr"Elyes HAOUAS
Change "mttrs" to mtrrs. Change-Id: I4e5930cdcba5e8f5366bb2d4ebbcb659c0c2eb27 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/25823 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Martin Roth <martinroth@google.com>
2018-04-26device: Add flag to disable PCIe ASPMNico Huber
For broken devices that spuriously advertise ASPM, make it possible to decide ASPM activation in the device driver. Change-Id: I491aa32a3ec954be87a474478609f0f3971d0fdf Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/25617 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-26mb/google/octopus: Add dptf.asl in dsdt.aslSumeet Pawnikar
This patch enables dptf for Octopus by adding dptf.asl in dsdt.asl. BUG=b:74263914 BRANCH=None TEST=None Change-Id: I7194cdd2af88ff062ebcc92cc97b3cdc3d21ecd6 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/25809 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-04-26mb/google/grunt: Add grunt touchpad wake GPE to devicestreeDaniel Kurtz
The grunt touchpad interrupt can be used as a wake source. For grunt, the touchpad interrupt uses GPIO5 which corresponds to GEVENT7. BUG=b:77602771 TEST=In OS: # cat /proc/acpi/wakeup => D015 S3 *enabled i2c:i2c-ELAN0000:00 TEST=powerd_dbus_suspend, touching touchpad (> 1 sec) wakes from S3. Change-Id: I510642108a1257f6601f18c77cf3107573427f39 Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/25827 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-26mainboard/google/kahlee: Enable EC wake on GPIO24Daniel Kurtz
The grunt EC uses GPIO24 (EC_PCH_WAKE_L) to signal wake-up events to the AP. On Stoney, GPIO24 maps to GEVENT (GPE) 15. The kahlee EC uses GPIO2 (EC_PCH_WAKE_L) to signal wake-up events to the AP. On Stoney, GPIO2 maps to GEVENT (GPE) 8. BUG=b:78461678 TEST=powerd_dbus_suspend, tap any key on keyboard wakes from S3. TEST=sign in, EC: lidclose, EC: lidopen => system wakes from S3. Change-Id: Ib1809740837e686992ff70b81933159a5dff7595 Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/25816 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-04-26mainboard/google/kahlee: Fix EC_SMI_GPIDaniel Kurtz
On the kahlee variant, EC_SMI_ODL is connected to GPIO6, which uses GEVENT 10 (GPE10). Fix this up, and also clean up the EC_*_GPI definition format a bit to match the format in the baseboard/gpio.h. BUG=b:78461678 TEST=build coreboot for kahlee Change-Id: I9445efbc02559c2a7c90f67bcb0154b04b03a1aa Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/25826 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-04-26mb/lenovo/x200: Use acpi_s3_resume_allowed()Paul Menzel
Apply commit 12d681b2 (intel/i945 gm45: Use acpi_s3_resume_allowed()) also to the Lenovo X200. Change-Id: I4e1e0ccf2abbe175c0e5ddcbb6ee7bf6afb1ae88 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/25793 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-04-26payloads/depthcharge: Update stable version to upstream masterDuncan Laurie
From commit id 61cfcc3b: eowth: Select CONFIG_DRIVER_BUS_SPI_INTEL_GSPI_VERSION_2 To commit id 902681db: zoombini: Enable NVMe as boot source Change-Id: Iab7676dd642c13f58dde85940ac1c8b52bfce3b7 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/25840 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-04-26Update vboot submodule to upstream masterDuncan Laurie
Updating from commit id e0b38418: - image_signing: Add sha1sum of keys in keyset to VERSION.signer. To commit id 392211f0: - Update Android signing to support signature scheme v2 This fixes bulding with depthcharge master. Change-Id: I07b570f54b26a937a5a7c53ade464e0c7a550312 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/25837 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-04-26soc/intel/apollolake: enable exception handling in every stage for glkAaron Durbin
Now that an idt is available in every stage utilize it for exception processing to help catch and debug issues. BUG=b:72728953 Change-Id: I69e7f938f36f2e522b787e311fd148bb8fd41247 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/25764 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-26arch/x86: remove nop padding from exception vectorsAaron Durbin
Now that assembly code isn't processing the idt gates there's no need to ensure each vector entry is the same amount of code. BUG=b:72728953 Change-Id: I2b248b26b9df36d6543163762c74622f79278961 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/25765 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-26arch/x86: print cr2 value on every exceptionAaron Durbin
Even though most x86 systems don't run with paging on, it's helpful to always print it out for the ones that do without making a more complicated handler. New dump will look like the following: Unexpected Exception: 6 @ 10:7ab84be2 - Halting Code: 0 eflags: 00010006 cr2: 00000000 eax: 7abb80ec ebx: deadbeef ecx: 00000000 edx: 00000002 edi: 7abb3000 esi: 00000004 ebp: 7abb2fd8 esp: 7abb2fb0 7ab84ba0: 00 01 00 83 ec 0c 6a 39 7ab84ba8: e8 8a 02 01 00 e8 e1 08 7ab84bb0: 00 00 e8 4e 3d 00 00 59 7ab84bb8: 5b 52 50 e8 f5 3c 00 00 7ab84bc0: c7 04 24 0a 00 00 00 e8 7ab84bc8: 3c 3d 00 00 c7 04 24 80 7ab84bd0: 00 00 00 e8 5f 02 01 00 7ab84bd8: e8 1e 38 01 00 e8 7e 50 7ab84be0: 01 00 0f 0b bb 98 ec ba 7ab84be8: 7a 83 c4 10 8b 03 85 c0 7ab84bf0: 0f 84 be 00 00 00 83 78 7ab84bf8: 04 00 8d 50 08 75 0c 56 7ab84c00: 56 ff 30 52 e8 f8 fe ff 7ab84c08: ff eb 0a 51 51 ff 30 52 7ab84c10: e8 2e ff ff ff 83 c4 10 7ab84c18: 83 c3 04 eb cf 89 d8 e8 BUG=b:72728953 Change-Id: I0e87bbe776f77623ad8297f5d80167998daec6ed Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/25762 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-26arch/x86: allow idt to be available to link in all stagesAaron Durbin
Add Kconfig IDT_IN_EVERY_STAGE to optionally specify having the interrupt handling code available to all stages. In order to do this the idt setup is moved to a C module. The vecX entries are made global so that a table of references to all the interrupt vector entry points can be used to dynamically initialize the idt. The ramification for ramstage is that exceptions are initialized later (lib/hardwaremain.c). Not all stages initialize exceptions when this Kconfig variable is selected, but bootblock for the C, stages using assembly_entry.S, and of course ramstage do. Anything left out just needs a call to exception_init() at the right location. BUG=b:72728953 Change-Id: I4146a040e5e43bed7ccc6cb0a7dc2271f1e7b7fa Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/25761 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-04-26util/hugo: Drop support for hugo based documentationPatrick Georgi
We shouldn't have two of everything Change-Id: I9879b40e26ba5a98626bc14c3d273fb525c070f7 Signed-off-by: Patrick Georgi <patrick@georgi.software> Reviewed-on: https://review.coreboot.org/25870 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-04-26Documentation: Add support for building with SphinxJonathan Neuschäfer
This commit adds the necessary infrastructure to convert the Markdown files in the Documentation directory to HTML using Sphinx[1] and recommonmark[2]. I selected "sphinx_rtd_theme" as the theme, because it offers a useful navigation sidebar, and because it's already used for the Linux kernel[3]. Makefile.sphinx was auto-generated by sphinx-quickstart. conf.py was auto-generated and manually adjusted. [1]: http://www.sphinx-doc.org/en/stable/ [2]: https://recommonmark.readthedocs.io/en/latest/ [3]: https://www.kernel.org/doc/html/latest/index.html Change-Id: Ie4de96978e334c598cf5890775807d3e15c29c4d Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/25787 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-04-26drivers/i2c/ck505: Remove unneeded headersElyes HAOUAS
Change-Id: Ic525c92e73097752a7c690186dc2034785cac678 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/25821 Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-26Documentation: SandyBridge_registers.md: Add a titleJonathan Neuschäfer
This fixes the following error when using "make -C Documentation sphinx": /.../Documentation/Intel/NativeRaminit/Sandybridge.md:32: WARNING: toctree contains reference to document u'Intel/NativeRaminit/SandyBridge_registers' that doesn't have a title: no link will be generated Change-Id: Id273b8dbc96465833b8e2b2e78c3bac8cd217d4b Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/25788 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-04-26Documentation: Sandybridge RAM init: Fix links for Sphinx/recommonmarkJonathan Neuschäfer
Add a dash before the links to other files to mark those files as subpages, and avoid the following error: reading sources... [ 33%] Intel/NativeRaminit/Sandybridge Exception occurred: File "/usr/lib/python2.7/dist-packages/recommonmark/states.py", line 134, in run_role content=content) TypeError: 'NoneType' object is not callable While at it, also spell these filenames correctly: Only SandyBridge_registers.md is spelled in camel-case. Change-Id: If92be7d2b61229d0315e1cc5204e951171612fee Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/25786 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-04-26mb/sifive: Add HiFive Unleashed mainboardJonathan Neuschäfer
Change-Id: I52ef2da9148809923c90178a00ba94babba8d2f8 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/25790 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2018-04-26src/sifive: Add the SiFive Freedom Unleashed 540 SoCJonathan Neuschäfer
The FU540 is the first RISC-V SoC with the necessary resources to run Linux (an external memory interface, MMU, etc). More information is available on SiFive's website: https://www.sifive.com/products/hifive-unleashed/ Change-Id: Ic2a3c7b1dfa56b67cc0571969cc9cf67a770ae43 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/25789 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2018-04-26arch/riscv: Store mprv bit in size_tJonathan Neuschäfer
CSRs are XLEN bits wide (i.e. the same width as general purpose registers), so size_t seems a little more correct than int. This change doesn't affect functionality because MSTATUS_MPRV already fits in 31 bits. Change-Id: I003c1b88b4493681dc9b6178ac785be330203ef5 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/25625 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2018-04-26soc/amd/stoneyridge: Fix smi_write32 arg order in disable_all_smi_statusDaniel Kurtz
The argument order for smi_write32() is offset, value. Current code had it backwards. So, when disable_all_smi_status() was called by sb_slp_typ_handler(), instead of clearing pending flag SlpTypeEvent65 (0x2) in SMIx88 SmiStatus2 by writing 0x00000002 to 0xfed80288, it would instead write 0x00000088 to 0xfed80202 - clearing the lower 2 bytes of SMIx04 Event_Enable, which disabled the lower 16 GPEs from waking the system from S3. Thus, the EC events (Keyboard / lid switch) [GPE15] and touchpad [GPE7] did not work as wake up sources. BUG=b:78461678 TEST=powerd_dbus_suspend, tapping any key on keyboard wakes from S3. Change-Id: Ie4fbe6db1bb73f603dcf409117fcce93479a1f46 Fixes:081851a9e4 ("amd/stoneyridge: Add SlpTyp SMI handler") Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/25815 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-04-26soc/amd/stoneyridge: Static constify smi_sourcesDaniel Kurtz
smi_sources is a file local array of constants. Change-Id: I431f181449a591ccaf8395f01a84c8e006a29b52 Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/25814 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2018-04-26src/mainboard/ibase/mb899: Fix typo in commentElyes HAOUAS
CR 24h Bit 0 is PNPCVS. Change-Id: Ia79a42ed60e82a84b60f254a0895ec52c1fcda0b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/23790 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-26cpu/x86: add limited runtime identity page mappingAaron Durbin
When employing PAGING_IN_CACHE_AS_RAM more areas need to be mapped in at runtime. Therefore, paging_identity_map_addr() is added to support adding identity mappings. Because there are a fixed amount of pages in cache-as-ram paging only the existing paging structures can be used. As such that's a limitation on what regions and length one can map. Using util/x86/x86_page_tables.go to generate page tables will always populate all the page directory pages. Therefore, 2MiB mappings are easy to map in. BUG=b:72728953 Change-Id: Ibe33aa12972ff678d2e9b80874529380b4ce9fd7 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/25718 Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-26siemens/mc_apl1: Provide baseboard and variant conceptsMario Scheithauer
Siemens will provide further boards based on Apollo Lake. These differ only slightly. To avoid copying the complete directory of the reference board we simply create variants that only contain the differences, like google/reef does. To further the ability of multiple variant boards to share code provide a place to land the split-up changes. This patch provides the tooling by using a new Kconfig value, VARIANT_DIR, as well as the Make plumbing. The directory layout with a single variant mc_apl1 (which is also the baseboard) looks like this: variants/baseboard - code variants/baseboard/include/baseboard - headers variants/mc_apl1 - code variants/mc_apl1/include/variant - headers New boards would then be added under their board name within the 'variants' directory. No split has been done with providing different logic yet. This is purely an organizational change. Change-Id: Ia3c1f45daee3b9690a448b82edbeec552ee05973 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/25785 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-04-26drivers/uart: Add helper function to allow bit-bangingJulius Werner
In some cases it may be useful to be able to bitbang a UART, such as during early bring-up when a driver for the actual controller isn't available yet. On some platforms we may even want to use this permanently, such as on the SDM845 where the hardware UART controller needs to have firmware loaded and is thus unavailable for most of the bootblock. This patch adds some helper code that makes it easy to implement this on a platform, you just have to pass it a function to control the Tx pin state and it will do the rest. It relies on the mono_time API and is thus bound to microsecond timing granularity, but that seems to be barely good enough for 115200 baud if the bit times are calculated carefully. Change-Id: If7dcecc7b8a95ec15f456efd2ec1f1e0dde239b4 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/25812 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-25soc/intel/apollake: add support for tracking memory detailsAaron Durbin
It's going to be necessary to know the i/o hole size as well the amount of memory configured in the sytsem. Therefore, add two helper functions: memory_in_system_in_mib() iohole_in_mib() Both return values in units of MiB. BUG=b:72728953 Change-Id: I481ba517c37f769e76d9e12b3631f5f99b5427a9 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/25738 Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Hannah Williams <hannah.williams@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-25soc/intel/common: disable paging if PAGING_IN_CACHE_AS_RAM enabledAaron Durbin
When tearing down cache-as-ram disable paging if PAGING_IN_CACHE_AS_RAM is enabled. BUG=b:72728953 Change-Id: I86e8a57a1187876dcbedce9f4f6b05be30aea7c6 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/25732 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-04-25arch/x86: add support for cache-as-ram pagingAaron Durbin
Processors, such as glk, need to have paging enabled while in cache-as-ram mode because the front end is agressive about fetching lines into the L1I cache. If the line is dirty and in the L1D then it writes it back to "memory". However, in this case there is no backing store so the cache-as-ram data that was written back transforms to all 0xff's when read back in causing corruption. In order to mitigate the failure add x86 architecture support for enabling paging while in cache-as-ram mode. A Kconfig variable, NUM_CAR_PAGE_TABLE_PAGES, determines the number of pages to carve out for page tables within the cache-as-ram region. Additionally, the page directory pointer table is also carved out of cache-as-ram. Both areas are allocated from the persist-across-stages region of cache-as-ram so all stages utilizing cache-as-ram don't corrupt the page tables. The two paging-related areas are loaded by calling paging_enable_for_car() with the names of cbfs files to load the initial paging structures from. BUG=b:72728953 Change-Id: I7ea6e3e7be94a0ef9fd3205ce848e539bfbdcb6e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/25717 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-04-25soc/amd/stoneyridge: Add additional early LPC and SPI initMarc Jones
Additional LPC and SPI setup needed to move AGESA out of the bootblock. Setup the prefetch, sio decode, and a bugfix for SPI. BUG=b:70558952 TEST=Boots with AGESA moved out of bootblock. Change-Id: I2c0d8632b25c036ff977c21477feb4778575189c Signed-off-by: Marc Jones <marc.jones@scarletltd.com> Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/25755 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-25vendorcode/amd/pi/00670F00: Remove include headerGarrett Kirkendall
Remove Fch.h from being included in src/vendorcode/amd/pi/00670F00/agesa_headers.h. It is not needed. BUG=b:69220826 BRANCH=master TEST=build Gardenia and Grunt systems. Change-Id: Ifde58421d20c813ae5708b1d9c6ec76433051d33 Signed-off-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/25808 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-04-25cpu/via/car: drop CARTESTLubomir Rintel
It's broken for years and nobody noticed (%ei for %esi and stackerr for .Lhlt). It would also leave CAR not zeroed out. Change-Id: Ib1ca8e8e71ea8d1bf834c349fd6e2ca81538b6eb Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-on: https://review.coreboot.org/25797 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-04-25cpu/via/car: ensure CAR ends up zeroed outLubomir Rintel
We need to ensure the cache as ram area is set to all zeroes so that car_migrated works. Despite a comment claims the previous value is a test pattern it's actually not used for any testing. Drop the comment too. Change-Id: I1c91acbca8a860c2ed9c691d08d18718604682d8 Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-on: https://review.coreboot.org/25796 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-04-25mb/google/octopus: Disable PCIE NPK deviceShaunak Saha
This patch sets the NPK device off for octopus. BUG=b:76115112 TEST=Build for Octopus and check that the logs do not report "PCI: 00:00.2 not found, disabling it". Change-Id: I3ac01f90cf946b019a6604a38dd1d6782f8d5759 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/25801 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-25soc/intel/apollolake: Sync FSP PCIE NPK device as per devicetreeShaunak Saha
This patch makes our devicetree in sync with the FSP configuration. Without this we see in boot logs "PCI: 00:00.2 not found, disabling it". The reason being in FSP NPK device is disabled by default. We can enable it by enabling the UPD parameter TraceHubEn. If we enable it in FSP then the logs complain the NPK pcie device is not seen. BUG=b:76115112 TEST=Build for Octopus and check that the logs do not report "PCI: 00:00.2 not found, disabling it". Change-Id: I8fe3a36dac2eff2225dacb0e6e16500a5750261e Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/25333 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-04-25util/riscvtools: Rename to util/riscv/Jonathan Neuschäfer
There's no good reason to use the more complicated name. Change-Id: I515e2df3b87580ddd31d18fe63451a98e92ead61 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/25700 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-25vx900: Drop some unused definesLubomir Rintel
These are redundant -- the actual APIC Ids and addresses are in the devicetree. Change-Id: I895563dd574a8f4631866ceec91a20cbc3b158e4 Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-on: https://review.coreboot.org/25800 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-04-25drivers/uart: Add a driver for SiFive's UARTJonathan Neuschäfer
This UART is used in the SiFive FU540 SoC, and will probably be used in other SoCs in the future. Change-Id: I915edf39666b7a5f9550e3b7e743e97fe3cacfd3 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/25768 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-04-24soc/amd/common/block/pi/amd_late_init.c: Fix illegal memory accessRichard Spiegel
Found-by: Coverity (CID 1387031: Memory - illegal accesses (BUFFER_SIZE_WARNING)). Calling strncpy with a maximum size argument of 19 bytes on destination array "dimm->module_part_number" of size 19 bytes might leave the destination string unterminated. Fix the size parameter. BUG=b:76202696 TEST=Build and boot kahlee, using special debug code to see the output strings, which was later removed. Change-Id: I18fa5e9c73401575441b6810f1db80d11666368c Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/25419 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-04-24mb/google/kahlee/variants/baseboard/gpio.c: move all non-critical gpiosRichard Spiegel
When GPIO tables were created, there was no study on which pins had to be programmed ASAP and which could be programmed later. Execute such study and move all non-critical gpios from reset to late. BUG=b:76097508 TEST=Build and boot grunt to OS, test OS for lost functionality (WIFI, video playback, track pad, keyboard). Change-Id: Icbc9370050d619800026035caaac3e89536a460a Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/25395 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-04-24mb/google/cyan/spd/spd.c: Fix module part number transferRichard Spiegel
With the increase of dimm->module_part_number size from 19 to 21 (commit 35b273eea3) "include/memory_info.h: Change part number field from 19 bytes to 21", this code is now advancing outside DDR3 SPD designated space. The correct size is already defined as LPDDR3_SPD_PART_LEN, use it. Also make sure to 0 terminate the string. BUG=b:77943312 TEST=Build cyan. Change-Id: Iba0ef4149acfc09b7672fce079df06bf1a01dff6 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/25702 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-04-24include/memory_info.h: Change part number field from 19 bytes to 21Richard Spiegel
DDR4 reserves 20 bytes for part number without termination. Therefor coreboot buffer for part number has to be increased to 21 bytes, to account termination. BUG=b:77943312 TEST=Build kahlee. Change-Id: I57aa8e06d907a1e6b11ce88f612a0d6c14b7c65b Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/25650 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-04-24arch/x86: add ENV_CACHE_AS_RAMAaron Durbin
Add ENV_CACHE_AS_RAM to indicate to compilation units if cache-as-ram is employed for that particular stage. BUG=b:72728953 Change-Id: I06dfa7afe2d967229549090d5aa95455687b0bb9 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/25716 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-04-24lib/ext_stage_cache: include prog arg in stage cache metadataAaron Durbin
In commit d87e4b34 (stage_cache: Add rmodule params in metadata) the cbmem stage cache was updatd to keep track of the arg from struct prog in the metadata. However, external stage cache did not get the same change. Fix that. BUG=b:72728953 Change-Id: Ifdaaa255cac0f413856410ff61bfb411a9554a31 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/25794 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-04-24arch/x86/postcar: add comment clarifying reason for finalize_load()Aaron Durbin
Certain platforms need to pass different stack pointer values to postcar depending on S3 resume or not. Add comments to ease the reader in understanding the point. If different stack values weren't needed the program was already cached in stage cache with the correct value. Change-Id: I7202c62e6202a14416cb49ad5348740174747c7d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/25795 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-04-24compiler.h: add __weak macroAaron Durbin
Instead of writing out '__attribute__((weak))' use a shorter form. Change-Id: If418a1d55052780077febd2d8f2089021f414b91 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/25767 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-04-24arch/x86: align stack on entry to x86_exception()Aaron Durbin
Entry points from assembly to C need to have the stacks aligned to 16 bytes with the newer compilers. This entry point was missed. Correct it. BUG=b:72728953 Change-Id: Idb29daf830c05fd5543c2194690364ce31b6a22c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/25763 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-04-24arch/x86: prepare for having an idt in other stagesAaron Durbin
Currently the idt setup and handling is only in ramstage. In order to prepare having an exception handler in other stages move the interrupt vector entry code to its own compilation unit. vec0 and int_hand need to be global so c_start.S references will resolve at link time. BUG=b:72728953 Change-Id: I435b96d987d69fb41ea27a73e2dd634b5d6ee3d9 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/25760 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-04-24mainboard/emulation/qemu-i440fx/fw_cfg: fix checksum for ACPI tablesOleksii Kurochko
Current patch fixes problem with validation of ACPI in Linux kernel: ACPI BIOS Error (bug): A valid RSDP was not found (20180313/tbxfroot-210) 1. function acpi_checksum() returns u8, so seems that is not good idea to use write_le32(). 2. at least RSDP (https://wiki.osdev.org/RSDP#Validating_the_RSDP) has u8 checksum. Change-Id: I1fb29ef4e58982aab0c54b1f715c5658d2a663d8 Signed-off-by: Oleksii Kurochko <oleksii.kurochko@gmail.com> Reviewed-on: https://review.coreboot.org/25753 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-04-24mb/google/poppy/variants/nami: Add keyboard backlight supportZhuohao Lee
This change adds keyboard backlight feature for Nami platform BUG=b:78360907 BRANCH=none TEST=keyboard backlight works when EC reports correct info. Change-Id: I3fceb83e155032b6e9f1763c4e2a29e7521269d2 Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://review.coreboot.org/25782 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-04-23drivers/spi: reduce confusion in the APIAaron Durbin
Julius brought up confusion about the current spi api in [1]. In order alleviate the confusion stemming from supporting x86 spi flash controllers: - Remove spi_xfer_two_vectors() which was fusing transactions to accomodate the limitations of the spi controllers themselves. - Add spi_flash_vector_helper() for the x86 spi flash controllers to utilize in validating driver/controller current assumptions. - Remove the xfer() callback in the x86 spi flash drivers which will trigger an error as these controllers can't support the api. [1] https://mail.coreboot.org/pipermail/coreboot/2018-April/086561.html Change-Id: Id88adc6ad5234c29a739d43521c5f344bb7d3217 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/25745 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-04-23clang-format: Update .clang-format to be compliant with linux kernel coding ↵zaolin
style * The coreboot clang format file seems to be incomplete. * Add missing options. Change-Id: I61a32ed951d18d5865be201bb38d18e50dd76f08 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/25687 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-23device/oprom/yabel: Fix spelling of *successful*Paul Menzel
Remove one *l* at the end. Change-Id: Ife5af64b380dc5d31f22873f1639382d2bf9a5d9 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/25748 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-04-23cpu/x86: add paging_set_default_pat() functionAaron Durbin
Add paging_set_default_pat() which sets up the PAT MSR according to util/x86/x86_page_tables.go. Using page attribute types require a matching of the PAT values with the page table entries. This function is just providing the default PAT MSR value to match against the utility. BUG=b:72728953 Change-Id: I7ed34a3565647ffc359ff102d3f6a59fbc93cc22 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/25715 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-04-23cpu/x86: expose and add paging helper functionsAaron Durbin
Add the following functions for use outside of the paging module: void paging_enable_pae_cr3(uintptr_t cr3); void paging_enable_pae(void); void paging_disable_pae(void); The functions just enable and/or disable paging along with PAE. Disassembly shows equivalent output for both versions. BUG=b:72728953 Change-Id: I9665e7ec4795a5f52889791f73cf98a8f4def827 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/25714 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-04-23cpu/x86: move NXE and PAT accesses to paging moduleAaron Durbin
The EFER and PAT MSRs are x86 architecturally defined. Therefore, move the macro defintions to msr.h. Add 'paging' prefix to the PAT and NXE pae/paging functions to namespace things a little better. BUG=b:72728953 Change-Id: I1ab2c4ff827e19d5ba4e3b6eaedb3fee6aaef14d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/25713 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-04-23cpu/x86: add pae paging module to all stagesAaron Durbin
In preparation for bringing in paging early always provide the paging pae module to all stages. Since we cull unused symbols this is a no-op. Compilation testing will happen all the time since the module currently doesn't compile without <arch/cpu.h> include. The current file is completely guarded with ENV_RAMSTAGE because it's using cpu_index() which is a ramstage-only construct. BUG=b:72728953 Change-Id: Ib4310b8206e5247fa220b42203bcd18d522d51ea Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/25712 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-04-23util/x86/x86_page_tables: add license header to generated codeAaron Durbin
If one wants to check in generated page tables in C then coreboot complains about there not being a license. Therefore, add the BSD license to the generated page tables. BUG=b:72728953 Change-Id: I980d7a7c0c14c1ed5aa8ce37a1484943a6a100f2 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/25737 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-04-23util/x86/x86_page_tables: update PAT mapping to match linuxAaron Durbin
The linux kernel uses the following mapping for PAT entries: PTE encoding: PAT |PCD ||PWT PAT ||| slot 000 0 WB : _PAGE_CACHE_MODE_WB 001 1 WC : _PAGE_CACHE_MODE_WC 010 2 UC-: _PAGE_CACHE_MODE_UC_MINUS 011 3 UC : _PAGE_CACHE_MODE_UC 100 4 WB : Reserved 101 5 WP : _PAGE_CACHE_MODE_WP 110 6 UC-: Reserved 111 7 WT : _PAGE_CACHE_MODE_WT Update the page table generator to match what the linux kernel is using. This just makes things consistent with linux. BUG=b:72728953 Change-Id: Ie5ddab5c86d4e03688d7e808fcae34ce954b64f9 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/25711 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-04-23soc{broadcom,imgtec,mediatek,qualcomm}: stop using spi_xfer_two_vectorsAaron Durbin
On a second look broadcom/cygnus and imgtec/pistachio appear to support full duplex. Therefore, remove the use of spi_xfer_two_vectors(). For mediatek/mt8173 and qualcomm/ipq40xx, the driver is written in such a way that it does not support full duplex. Remove the use of spi_xfer_two_vectors() and explicitly error out when a full duplex transaction is requested. Change-Id: I8689bc9bb2b27563d25e9f165487d38881c0b059 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/25742 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-23mb/google/poppy/atlas: Enable trackpadCaveh Jalali
This enables the i2c trackpad on atlas. BUG=b:75454415 TEST=able to move pointer using trackpad Change-Id: If4a82aa605ec68fd38e52c13406eaf803f9e86cc Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/25759 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-04-21mb/google/bip: Add GPIO configuration settingsShamile Khan
These settings are identical to yorp settings except overrides are not provided for sleep_gpio[] table which is currently empty for yorp and cros_gpios[] table which is not expected to change for bip. BUG=b:77869623 BRANCH=none TEST=Build coreboot for bip. Change-Id: Icc205f576691427d78c9159dfdbced87e41a0517 Signed-off-by: Shamile Khan <shamile.khan@intel.com> Reviewed-on: https://review.coreboot.org/25741 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-04-20rules: Define SIMPLE_DEVICE on x86 onlyPatrick Rudolph
Make sure to define __SIMPLE_DEVICE__ on x86 only, as other platforms currently doesn't have support for it. Fixes static.c devicetree compilation on non x86. Change-Id: I75fb038681a8edf119415705af5da9f999fd8225 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25721 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-20pci: Move inline PCI functions to pci_ops.hPatrick Rudolph
Move inline function where they belong to. Fixes compilation on non x86 platforms. Change-Id: Ia05391c43b8d501bd68df5654bcfb587f8786f71 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25720 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-20soc/amd/stoneyridge/include/soc/southbridge.c: Rename gpio structureRichard Spiegel
The GPIO definition structure has evolved to a point where it's no longer specific to stoneyridge, though probably still specific to AMD. Therefore, rename the GPIO declaration structure removing stoneyridge from it. BUG=b:72875858 TEST=Build kahlee, grunt, gardenia. Change-Id: Ib034d3f7840c36ee8f5c5384241d7326d3fe5543 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/25726 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-20soc/intel/common: Adjust LPC Generic IO setupLijian Zhao
Check same IO ranges get programmed first, if so just skip it to avoid double programming. BUG=b:77944335 TEST=Boot up with mewoth board, and check serial log, there's no error message about "LPC: Cannot Open IO Window: ". Change-Id: I89f9bb70320f91b16c6084384c4a0a53ede3760c Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/25667 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-20device/oprom/yabel: Fix vbe-buffer index in vbe.cHal Tsai
There's a issue about {VbeSignature to "VBE2" to indicate VBE 2.0+ request}, these indexes are counted wrong. Change-Id: I8ec85df60076162518aa55a94fa7b66c0c2391ab Signed-off-by: Hal Tsai <hal_tsai@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/25736 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-04-19libpayload: Move GDB functions to stdlib.hJulius Werner
When GDB support is compiled in, halt() in libpayload will call gdb_enter(). halt() is defined in <stdlib.h> and gdb_enter() in <libpayload.h>. Usually files just include <libpayload.h> so this is not a problem, but in some situatons a payload may just include <stdlib.h> (or a file including it like <assert.h>), leading to an undeclared identifier here. Move the GDB functions to <stdlib.h> to solve this. Change-Id: I7b23b8ac9cd302aa6ef96f24565130490ac40071 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/25730 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-19ectool: Add an option to get and use EC ports from /proc/ioportsIru Cai
There are boards that don't use ports 0x62 and 0x66 for EC, e.g. Dell Latitude E6230 uses 0x930 and 0x934. Change-Id: Ie3005f5cd6e37206ef187267b0542efdeb26b3af Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/23430 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-04-19soc/amd/common/block/pi/heapmanager.c: Simplify codeRichard Spiegel
There are sections of code that are almost identical and they can be converted to auxiliary procedures. For allocating heap, 3 sizes (the buffer size of currently being examined node, the buffer size of the current best fit node and the minimum size for a buffer that will need to be split if selected as the best fit) are used often so they could be stored in temporary variables. These 2 changes will make code shorter, with less indentation problems and overall easier to read. The actual logic of the code is not changed. BUG=b:77940747 TEST=Build and boot grunt. Change-Id: Ib4c69981eab7452228ccae9ed9bc288c8baceffe Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/25703 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-19soc/intel/cannonlake: Set DISB after Dram initLijian Zhao
DRAM Initialization Scratchpad Bit needs to be set after Dram Initialization finished, according to Cannonlake PCH-LP EDS(#565870) chapter 5.3.1. BUG=None Change-Id: I16dd3787cb743bc5b7492042f3c3757534e1a51c Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/25704 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Kin Wai Ng <kin.wai.ng@intel.com>
2018-04-19soc/intel/apollolake: fix 'DENSITY' misspellingAaron Durbin
DESNITY is not DENSITY. Fix that error. BUG=b:72728953 Change-Id: I1e4ebec378a20cefc7c1e4114d39b707fc767fc1 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/25735 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-19soc/intel/cannonlake: Force LPC IO decode settingsLijian Zhao
Force PCH LPC generic IO ranges are identical between PCH LPC pci config space and DMI PCR registers. Reference documentation from 570374 chapter 2.4.1. Bug=77944335 TEST=Boot up in OS in meowth board, using iotools to read LPC pci config space offset 0x84~0x90 and compare with values read from DMI PCR private register offset 0x2730~0x273c are identical. Change-Id: I72a40360ba67f443f24468f10504d8cfd0b099ca Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/25668 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-19mb/google/octopus: Select DRIVERS_I2C_HIDFurquan Shaikh
This change selects DRIVERS_I2C_HID which is required for adding SSDT node for digitizer. BUG=b:78099046 Change-Id: I526c0ac7b88dec7b2b22d022d911840555f15cde Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/25710 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-04-18soc/amd/stoneyridge/include/soc/gpio.h: Remove vendor code referenceRichard Spiegel
With the exception of code that deals directly or indirectly with AGESA, all other code should be independent of vendor code reference. Therefore, remove vendor code reference from any GPIO code. BUG=b:77999987 TEST=Build and boot grunt. Change-Id: I9ba78767a269ad6b9b06fa11993d8a12350e4bad Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/25695 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-18mb/google/kahlee/variants/kahlee/gpio.c: Convert GPIO to new formatRichard Spiegel
As part of preparing to make GPIO code independent of vendor code references, convert GPIO table format using newly defined macros. BUG=b:77999987 TEST=Build and boot kahlee. Change-Id: I0af768bb4dbcbfef0d2d08ffe869c1dfb6827974 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/25694 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-04-18mb/google/poppy/variants: Set VmxEnable to 1Furquan Shaikh
This change sets VmxEnable to 1 to match the kernel setting. If this feature is enabled at the kernel level and not in FSP, then there is an issue where FSP expects it to be disabled so it forces a cold reboot on every warm reboot. BUG=b:78129261 BRANCH=poppy Change-Id: Idedbde1d8eb0c9e959733b7b50e5dec804d61cae Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/25698 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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