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2021-06-24mb/google/cherry: Add mt6360 driver for PMIC accessRyan Chuang
Add initialization of mt6360 drvier used by DRAM calibration test. Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com> Change-Id: Id74835d8395afac9e7e2c987a0a033f1b524fbfb Reviewed-on: https://review.coreboot.org/c/coreboot/+/55750 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-06-24soc/mediatek/mt8195: Support 4 channel DRAM in DPM init flowRyan Chuang
Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com> Change-Id: If2e9d8a4dcfad28c48a2b5fa7c92f70fae879e67 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55749 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-06-23mb/google/guybrush: Indicate the presence of ACP DMICKarthikeyan Ramasubramanian
In order to enable ACP DMIC hardware runtime detection, indicate that ACP DMIC is present. BUG=b:182960979 TEST=Build and boot to OS in guybrush. Ensure that the _WOV ACPI method is populated in the ACP device. Change-Id: I9a53d158ed08a6b46c29bcb8fe3a2a0d108bd6cd Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55030 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-23soc/amd/common/acp: Populate _WOV ACPI methodKarthikeyan Ramasubramanian
In order to support Audio Co-processor (ACP) DMIC hardware runtime detection on the platform, ACPI _WOV method is populated on the concerned ACP device. This method returns the ACPI Integer value as 1 if ACP DMIC exists on the platform. BUG=b:182960979 TEST=Build and boot to OS in guybrush. Ensure that the _WOV ACPI method is populated under the scope of ACP device. Scope (\_SB.PCI0.GP41.ACPD) { Method (_WOV, 0, NotSerialized) { Return (One) } } Change-Id: Ide84f45f5ea2ae42d5efe71ac6d1595886157045 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55029 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-23soc/amd/cezanne: Init eSPI early if requiredMartin Roth
If the NO_EARLY_BOOTBLOCK_POSTCODES config option is enabled, configure eSPI as early as possible in the x86 boot sequence. We found that there are situations that can cause the system to hang if there are any port80h postcodes sent out before eSPI is initialized. BUG=b:191370340 TEST=Build & Boot with and without NO_EARLY_BOOTBLOCK_POSTCODES enabled. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I0badb1c529e96ee4f81134287db53ce32473de6e Reviewed-on: https://review.coreboot.org/c/coreboot/+/55732 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-23mb/google/guybrush: Add guybrush specific AMDFW config fileMartin Roth
This takes the "generic" AMD firmware config file from the cezanne directory and removes pieces unnecessary for guybrush. Removed: - PSPTRUSTLETS_FILE TypeId0x0C_FtpmDrv_CZN.csbin - PSP_MP2FW0_FILE TypeId0x25_Mp2Fw_CZN.sbin - PSP_KVM_ENGINE_DUMMY_FILE TypeId0x29_KvmEngineDummy.csbin - DRTMTA_FILE TypeId0x47_DrtmTA_CZN.sbin - PSP_MP2CFG_FILE MP2FWConfig.sbin BUG=b:187103438 TEST=Build & Boot Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I5a0ed1edd7616a890f906b7f3e4a7d364758ca47 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55743 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-06-23mb/google/dedede/var/magolor: Enable weida touchscreen for magisterDavid Wu
Add weida touchscreen support for magister. BUG=b:191633024 BRANCH=dedede TEST=Build and verify that touchscreen works on magister. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I3de6a84d2d58ef87f0ae13e8a117a980a0210ac4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55708 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Randy Lai <randy.lai@weida.corp-partner.google.com>
2021-06-23soc/amd/common/block/cpu/noncar/memmap: move BERT region back into CBMEMFelix Held
The original reason the BERT table was moved out of CBMEM was because the OS was not able to access the region. This happened because the CBMEM region was marked as type 16 in the e820 table. The OS isn't aware of this type, so it prevents any drivers from accessing it. Depthcharge now correctly labels the CBMEM region as reserved in the e820 table so we can move the BERT table into CBMEM. TEST=BERT ACPI table generation still works on AMD/Mandolin with SeaBIOS as payload and BERT region inside CBMEM is inside a BIOS-e820 reserved range. BERT generation also works on Zork with depthcharge. Link: https://crrev.com/c/2939677 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie640e91c19ae5f9b275cc333284b4be34211fbf6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55279 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-06-23mb/google/dedede/var/sasukette: Change ELAN touchpad driverZhi Li
Use drivers/i2c/hid can't update firmware by kernel update script, so change to drivers/i2c/generic. BUG=b:188602529 BRANCH=dedede TEST=can update ELAN touchpad firmware(277.0_1.0) by kernel script Change-Id: I3592403fe5d0f8d0f67059f8296277e3c028c117 Signed-off-by: Zhi Li <lizhi7@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55248 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-23mb/{fb/fbg1701,portwell/m107}: Don't select HAVE_FSP_BINArthur Heymans
This selected by default if 3rdparty/fsp is used. There is no need to override this behavior in the mainboard Kconfig. Change-Id: I01ee2e90e0eceaa3100d911b5460cf99f413b185 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55453 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2021-06-23mb/facebook/fbg1701/Kconfig: Correct dependencyFrans Hendriks
Config items depends on USE_VENDORCODE_ELTAN but are VBOOT specific. Correct dependency of these items on VENDORCODE_ELTAN_VBOOT. BUG = NA TEST = Boot facebook FBG-1701 with possible combinations of Eltan security. Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Change-Id: Icd1c3e5c70ca562190308752f45aac734826649a Reviewed-on: https://review.coreboot.org/c/coreboot/+/52132 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-23soc/intel/common: Fix X2APIC NMI entry in ACPI MADTKyösti Mälkki
For X2APIC mode, replicate the APIC NMI entry flags and intention to address all the logical processors. Change-Id: I9c0537a3efba942329f80d7cfdbd910b8958516f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55182 Reviewed-by: Lance Zhao Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-23mb/intel/sm: Skip FSP to program UART0Subrata Banik
Set "SerialIoUartMode" for UART0 as PchSerialIoSkipInit Change-Id: Idc7da7bf38634c04b0f4acd4c7c2ea9fa88545e5 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55207 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-23soc/intel/elkhartlake: Use is_devfn_enabled() for Device4Enable UPDSubrata Banik
1. Replace pcidev_path_on_root() and is_dev_enabled() functions combination with is_devfn_enabled() while enabling Thermal config. 2. Remove unused local variable of device structure type (struct device *). Change-Id: Icc2a44d6d3f1a78bf47354049dd9e2a0ed2282ba Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55728 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-23soc/intel/alderlake: Use devfn_disable() function for XDCISubrata Banik
Use devfn_disable() for disabling a PCI device rather than using `dev->enabled = 0`. Also, use is_devfn_enabled() to get the device current state prior updating the FSP-S UPD for XDCI. TEST=FSP-S disabled XDCI when `xdci_can_enable` returns 0 and XDCI is disabled at PCI enumeration `PCI: 00:14.1: enabled 0`. Change-Id: I5e10e5d0b80986e1e73573a86a957985840fe0b3 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55727 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-23soc/intel/cannonlake: Use devfn_disable() function for XDCISubrata Banik
Use devfn_disable() for disabling a PCI device rather than using `dev->enabled = 0`. Also, use is_devfn_enabled() to get the device current state prior updating the FSP-S UPD for XDCI. TEST=FSP-S disabled XDCI when `xdci_can_enable` returns 0 and XDCI is disabled at PCI enumeration `PCI: 00:14.1: enabled 0`. Change-Id: I64ab77bc49d93aca1da0126d849e69ff75b182a3 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55726 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-23soc/intel/elkhartlake: Use devfn_disable() function for XDCISubrata Banik
Use devfn_disable() for disabling a PCI device rather than using `dev->enabled = 0`. Also, use is_devfn_enabled() to get the device current state prior updating the FSP-S UPD for XDCI. TEST=FSP-S disabled XDCI when `xdci_can_enable` returns 0 and XDCI is disabled at PCI enumeration `PCI: 00:14.1: enabled 0`. Change-Id: I8ca0813e18da0f95eb9293b6d0bbdf933a1e7039 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55725 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-23soc/intel/icelake: Use devfn_disable() function for XDCISubrata Banik
Use devfn_disable() for disabling a PCI device rather than using `dev->enabled = 0`. Also, use is_devfn_enabled() to get the device current state prior updating the FSP-S UPD for XDCI. TEST=FSP-S disabled XDCI when `xdci_can_enable` returns 0 and XDCI is disabled at PCI enumeration `PCI: 00:14.1: enabled 0`. Change-Id: I568cd39792eba1bbace4901e96d708d80f73c60a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55724 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-23soc/intel/jasperlake: Use devfn_disable() function for XDCISubrata Banik
Use devfn_disable() for disabling a PCI device rather than using `dev->enabled = 0`. Also, use is_devfn_enabled() to get the device current state prior updating the FSP-S UPD for XDCI. TEST=FSP-S disabled XDCI when `xdci_can_enable` returns 0 and XDCI is disabled at PCI enumeration `PCI: 00:14.1: enabled 0`. Change-Id: I038e43deead70d598cf26f320dd9993f17591b88 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55723 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-23soc/intel/tigerlake: Use devfn_disable() function for XDCISubrata Banik
Use devfn_disable() for disabling a PCI device rather than using `dev->enabled = 0`. Also, use is_devfn_enabled() to get the device current state prior updating the FSP-S UPD for XDCI. TEST=FSP-S disabled XDCI when `xdci_can_enable` returns 0 and XDCI is disabled at PCI enumeration `PCI: 00:14.1: enabled 0`. Change-Id: I0e400ded7ba268a5f289b0ac568598e0dad1899a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55722 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-23soc/intel/icelake: Make use of is_devfn_enabled() functionSubrata Banik
1. Replace all pcidev_path_on_root() and is_dev_enabled() functions combination with is_devfn_enabled(). 2. Remove unused local variable of device structure type (struct device *). 3. Replace pcidev_path_on_root() and dev->enabled check with is_devfn_enabled() call. 4. Leave SATA, eMMC controller FSP UPDs at default state if controller is not enabled and FSP UPDs are set to disable. TEST=Able to build and boot without any regression seen on ICLRVP. Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: Id6861af3b5d1ce4f44b6d2109301bd4f5857f324 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55721 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-23soc/mediatek/common: Add DPM_FOUR_CHANNEL optionRyan Chuang
Add DPM_FOUR_CHANNEL option for 4 channel configuration for DPM. Publicize reset_dpm() as dpm_reset() for external reference. Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com> Change-Id: If6e0d5c4d16a7ddd69c4a427488f8899870db327 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55719 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-06-23soc/mediatek/mt8195: Add DPM firmware filesRyan Chuang
Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com> Change-Id: I51e8ebf5a75ac629bed51665e12bafa740b4b81d Reviewed-on: https://review.coreboot.org/c/coreboot/+/55711 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-06-23soc/mediatek/mt8195: Add mt6360 driver for PMIC accessAndrew SH Cheng
Signed-off-by: Andrew SH Cheng <andrew-sh.cheng@mediatek.com> Change-Id: Ieaf234f35f2b7d440bdf1e6ec4c455af7b311623 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55710 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-22soc/amd/common: Add GPIO config for native func w/ output driveMartin Roth
Our existing native function gpio configuration macro (PAD_NF) only sets the pull. For PCIe reset, we now need to be able to set it to its native function (PCIE_RST_L), and drive it low, then high. BUG=b:182805349 TEST=Configure GPIO, see correct behavior. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I636371517c99f94f76834abc4575795d51aa0368 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55652 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-22mb/google/guybrush: Only enable early port80s if using psp_verstageMartin Roth
PSP_Verstage will enable eSPI early in the boot sequence. If the platform isn't using psp_verstage, the system can hang on the first port 80h postcode that comes out because they aren't routed to an active device until eSPI is configured. BUG=b:191370340 TEST=Build without PSP_Verstage, verify system doesn't hang. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I37fbb251cd79609b856c4480ca29ce94b08897d7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55738 Reviewed-by: Rob Barnes <robbarnes@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-22soc/intel/common: Unbreak masterTim Wawrzynczak
Commit 54b03569c moved a call to cse_trigger_recovery () around, and commit 09635f418 renamed the function, but was tested before the first commit was submitted, thus breaking the tree. Fix it. Change-Id: If21ea0c1ebf9ce85c59ee25ec7f879abde2e3259 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55766 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-22soc/intel/common/block/cse: Move cse_trigger_recovery functionTim Wawrzynczak
This function could be applicable in situations other than just for the CSE Lite SKU, therefore move this from cse_lite.c to cse.c Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ibc541f2e30ef06856da10f1f1219930dff493afa Reviewed-on: https://review.coreboot.org/c/coreboot/+/55673 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-22mb/intel/adlrvp: Update Mainboard part number and VendorMeera Ravindranath
dmidecode output should match with the CrOS kernel updated string. TEST=dmidecode grep "Manufacturer" = Intel Corporation dmidecode grep "Product name" = Alder Lake Client Platform Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Change-Id: I7cce423de624e7056e88b52a1443c554fd9123bc Reviewed-on: https://review.coreboot.org/c/coreboot/+/51408 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-22mb/google/brya/variants/primus: set up gpioMalik_Hsu
Set the GPIO configuration of primus BUG=b:190643562 Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com> Change-Id: I405561ae8a44d95ffdc526241f9c52761f67ed35 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55404 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-22soc/intel/{apl,cnl}: Remove FSP CAR optionArthur Heymans
One of the reason FSP-T support had to be kept in place was for Intel Bootguard. This now works with native CAR code, so there is no reason to keep FSP-T as an option for these platforms. APL did not even build with FSP_CAR and finding FSP-T using walkcbfs was only recently fixed using FMAP, so there can be no doubt that this option was never used with coreboot master. Change-Id: I0d5844b5a6fd291a13e5f467f4fc682b17eafa63 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55518 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-22soc/intel/car: Add support for bootguard CARArthur Heymans
Bootguard sets up CAR/NEM on its own so the only thing needed is to find free MTRRs for our own CAR region and clear that area to fill in cache lines. TESTED on prodrive/hermes with bootguard enabled. Change-Id: Ifac5267f8f4b820a61519fb4a497e2ce7075cc40 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36682 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-06-22soc/intel/common/cache_as_ram.S: Add macro to clear CARArthur Heymans
Add a macro to clear CAR which is replicated 3 times in this code. TEST: with BUILD_TIMELESS=1 the resulting binary is identical. Change-Id: Iec28e3f393c4fe222bfb0d5358f815691ec199ae Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37191 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-06-22soc/intel/common/cache_as_ram.S: Add macro to find a free MTRRArthur Heymans
This adds a macro to find an available MTRR(s) to set up CAR. This added complexity is not required on bootpaths without bootguard but with bootguard MTRR's have already been set up by the ACM so we need to figure out at runtime which ones are available. Change-Id: I7d5442c75464cfb2b3611c63a472c8ee521c014d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37190 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-06-22mb/asus/p8h61-m_pro_cm6630: Add initial supportAlice Sell
This motherboard is somewhat similar to the p8h61-m_pro, but also different. It has two exposed RAM slots with a pinout for four, and it's an OEM variant used in PCs ASUS sold in stores. Signed-off-by: Hunter Sell <alicelyralain@gmail.com> Change-Id: Id08349feb0aeaf21406f814f6d19bbe0d9312a4d Reviewed-on: https://review.coreboot.org/c/coreboot/+/55661 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-22nb/intel/haswell/pcie.c: Avoid needless deathAngel Pons
Using `config_of(dev)` to access `dev->chip_info` will make coreboot die if the latter is NULL, which is the case for devices detected at runtime (i.e. not statically declared in the devicetree). Given that the code is designed to work when the PEG config is all-zeroes (devicetree default), dying because `dev->chip_info` is NULL is foolish and unwarranted. Introduce a helper function that returns a pointer to devicetree config when available, and otherwise returns a pointer to a zero-filled static struct. In addition, avoid an out-of-bounds access in the very unlikely case where the device's function is too large. Tested on Asrock B85M Pro4, can now boot when `device pci 01.0 on end` is commented out in its devicetree. Without this commit, it could not. Change-Id: Ia2d3a03da9eab601fb834b0c51a8a51c9ae14c33 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55690 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-06-22nb/intel/haswell/pcie.c: Introduce helper variableAngel Pons
Introduce a helper variable to avoid some redundancy and to reduce the diffstat noise in follow-up changes. Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical. Change-Id: I490675aaddd2b5a13d990664431f79a605999254 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55689 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-06-22nb/intel/haswell/pcie.c: Fix getting PCI functionAngel Pons
Use `dev->path.pci.devfn` to obtain the `devfn` that `PCI_FUNC` needs. Tested on Asrock B85M Pro4, `PCI_FUNC` now obtains the correct value. Change-Id: Ia3bbd56ce0adba9d24f62ffc016cd825bcf3cc6a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55688 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-06-22mb/lenovo/t440p: Disable second PEG deviceAngel Pons
PEG bifurcation is strapped to x8/x8 on this board, but only the first port is used. Disable the PEG device at 00:01.1 because it is unused. Should fix booting with commit ae999503f62ef8a3b9b2756a2810d29c383a009e (nb/intel/haswell/pcie.c: Add missing pre-ASPM init). The `config_of()` function call added in that commit makes coreboot die if any PEG device that is enabled by strapping is not present in the devicetree. While it is true that the PEG code should not use `config_of()`, this PEG device should still be disabled on this board as it is never used. Change-Id: I16809e081f9a56ba2f1fdfcb4b8289d75161056b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55687 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Máté Kukri <kukri.mate@gmail.com>
2021-06-22mb/lenovo/t440p/devicetree.cb: Visually align devicesAngel Pons
Visually align devices and corresponding comments in the devicetree. Tested with BUILD_TIMELESS=1, Lenovo T440p remains identical. Change-Id: Id6f521275ffd0b35c247152dc9293c4182c4a96d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55686 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-06-22mb/lenovo/t440p: Drop redundancy in devtree commentsAngel Pons
Remove some redundant parts of devicetree comments. This used to happen when using autoport, but has been fixed at some point. Tested with BUILD_TIMELESS=1, Lenovo T440p remains identical. Change-Id: Ie24b5430c7771c9ce4dda6c9a10d70ee9000df7c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55685 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-06-22drivers/i2c: sx9310: fix overridetree.cbGwendal Grignou
An error in script did not set the attribute properly: - Entry CS0 is not used as sensor, but as ground, - Entry CS1 is used as the startup sensor. This fixes a regression caused by commit 689c25b9d6 (drivers/i2c: sx9310: Replace register map with descriptive names) EQ=b:173341604 BRANCH=volteer Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Change-Id: I92c01209031e9a917d95b1cb2537b0ce7b93e66d Reviewed-on: https://review.coreboot.org/c/coreboot/+/51893 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-22docker/coreboot.org-status: Update URL schemes to git reposPatrick Georgi
We moved from gitweb to cgit to gitiles and some of the URL schemes were lost during the transitions. Update to the gitiles scheme so board-status links work again. Change-Id: Id2a840bf89fab172e0eab21e303ac0c4666b6751 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55594 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-06-21soc/intel/common: Check CSE Lite RW statusSridahr Siricilla
The patch moves CSE Lite RW status check out of CSE RW update logic as the RW sanity check has to be done irrespective of CSE RW update logic is enabled or not. If coreboot detects CSE Lite RW status is not good, the coreboot triggers recovery. TEST=Verified boot on Brya Signed-off-by: Sridahr Siricilla <sridhar.siricilla@intel.com> Change-Id: I582b6cf24f8894c80ab461ca21f7c6e8caa738bc Reviewed-on: https://review.coreboot.org/c/coreboot/+/55619 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-21soc/amd/cezanne/fsp_m_params: set HD Audio enable UPD from devicetreeFelix Held
Pass the info if the non-graphics HD audio controller device is enabled or disabled in the board's devicetree via a UPD to the FSP so that it knows if it should enable or disable the corresponding device. TEST=When adding "device ref hda on end" to the devicetree of amd/majolica the non-graphics HD Audio controller shows up in lspci and when that line isn't added the PCIe device doesn't show up. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I9f5e164d308906bfc788e5c2674c13c7b2ebf471 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55680 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-06-21vc/amd/fsp/cezanne/FspmUpd: add hda_enable UPDFelix Held
This UPD to enable/disable the non-graphics HD audio controller was added in FSP build version 1.0.3.1, so sync the header file in coreboot with this. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I15eee45dc5d12a420eb688eaa5879c92b6d1b2c5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55679 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-06-21soc/amd/cezanne/fsp_m_params: set SATA enable UPD from devicetree infoFelix Held
Currently the FSP only has one switch to disable both AHCI controllers. If at least one of the two AHCI controller devices is enabled in the board's devicetree, set the SATA enable UPD to 1 and otherwise set it to 0. Setting the UPD value to 0 when both AHCI controllers are disabled saves around 60ms in boot time. BUG=b:191385289 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I84e7c8bf2ab08c8254271ddfefd2e4e7d8c2e87b Reviewed-on: https://review.coreboot.org/c/coreboot/+/55669 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-21soc/intel/apollolake: Use devfn_disable() functionSubrata Banik
Use devfn_disable() for disabling a PCI device rather than using `dev->enabled = 0`. Also, use is_devfn_enabled() to get the device current state prior updating the FSP-S UPD for XDCI. TEST=FSP-S disabled XDCI when `xdci_can_enable` returns 0 and XDCI is disabled at PCI enumeration `PCI: 00:15.1: enabled 0`. Change-Id: I449beae59d2f578c027d8110c03fa79f516c3fe9 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55666 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-21soc/intel/common: Add InSMM.STS supportAngel Pons
Tested on HP 280 G2, SMMSTORE v1 and v2 still work. Other tests: - If one does not set BIOS_CONTROL bit WPD, SMMSTORE breaks. - If one does not write the magic MSR `or 1`, SMMSTORE breaks. Change-Id: Ia90c0e3f8ccf895bfb6d46ffe26750393dab95fb Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51796 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-06-21security/intel: Add option to enable SMM flash access onlyAngel Pons
On platforms where the boot media can be updated externally, e.g. using a BMC, add the possibility to enable writes in SMM only. This allows to protect the BIOS region even without the use of vboot, but keeps SMMSTORE working for use in payloads. Note that this breaks flashconsole, since the flash becomes read-only. Tested on Asrock B85M Pro4 and HP 280 G2, SMM BIOS write protection works as expected, and SMMSTORE can still be used. Change-Id: I157db885b5f1d0f74009ede6fb2342b20d9429fa Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40830 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-06-21ec/google/wilco: Fix comment about enclosure typeKyösti Mälkki
SYSTEM_TYPE_CONVERTIBLE is not valid SMBIOS enclosure type, but selecting it implies SMBIOS_ENCLOSURE_CONVERTIBLE. Change-Id: Ib658af7b80586428b22f08a738964637e1fbd17a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42141 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-21security/intel/cbnt: Add loggingArthur Heymans
This decodes and logs the CBnT status and error registers. Change-Id: I8b57132bedbd944b9861ab0e2e0d14723cb61635 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54093 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-21security/intel/txt: Split off microcode error types string printingArthur Heymans
The purpose is to reuse the types string in CBnT error printing. Change-Id: I435de402fef6d4702c9c7250c8bd31243a04a46e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54092 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-21security/intel/txt: Always build logging.cArthur Heymans
Always building makes sure this code gets buildtested. Calling this code already was guarded by "if CONFIG(INTEL_TXT_LOGGING)". Also build this in all stages as future code will use this in bootblock. Change-Id: I654adf16b47513e3279335c8a8ad48b9371d438e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54295 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-21mb/google/dedede/var/storo: Update DPTF parametersTao Xia
Update DPTF parameters from internal thermal team. BUG=b:180875582 BRANCH=dedede TEST=emerge-dedede coreboot Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com> Change-Id: Ica2f2856000c8dcbf4d23b7b4a3c479dc7d4862b Reviewed-on: https://review.coreboot.org/c/coreboot/+/55388 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2021-06-21vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2207_01Ronak Kanabar
The headers added are generated as per FSP v2207_01. Previous FSP version was v2162_00. Changes Include: - Add IbeccProtectedRangeEnable, IbeccProtectedRangeBase and IbeccProtectedRangeMask in FspmUpd.h - Add UsbTcPortEn in FspsUpd.h - Adjust Reserved UPD Offset in FspmUpd.h - Few UPDs description update in FspmUpd.h and FspsUpd.h BUG=b:189731004 BRANCH=None TEST=Build and boot brya Change-Id: Ice44dfbd41e8eca4f171b76e7a3dcdf133a516fd Cq-Depend: chrome-internal:3876956, chrome-internal:3909162, chrome-internal:3909163 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55094 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-21mb/google/guybrush: Add devfn macros for devices on GPP bridgeKarthikeyan Ramasubramanian
Add devfn macros for some peripheral devices that are attached to PCIE GPP Bridge. BUG=None TEST=Build and boot to OS in Guybrush. Change-Id: I7c5433dff2329f13c282908e2b848405819347ff Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55601 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-06-21soc/intel/alderlake: Add GFx Device ID 0x46b3Meera Ravindranath
List of changes: 1. Add new GFx ID 0x46B3 into device/pci_ids.h 2. Update new GFx ID into common graphics.c 3. Add new GFx ID description into report_platform.c TEST=Build and boot brya Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Change-Id: I4343c7343875eb40c2955f6f4dd98d6446852dc0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55662 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2021-06-21security/intel/cbnt/Makefile.inc: Fix building cbnt-provArthur Heymans
This makes it possible to build cbnt-prov with Jenkins. Change-Id: I658723a4e10bff45176d7c1ea7a410edbb182dc6 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55667 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-21soc/intel/elkhartlake: Expose In-Band ECC config to mainboardWerner Zeh
Elkhart Lake provides a feature called "In-Band ECC" which uses a piece of system DRAM to store the ECC information in. There are a few parameters in FSP-M to set this feature up as needed. This patch adds code to expose these parameters to the devicetree so that they can be configured on mainboard level as needed. Change-Id: I7a4953d7b35277de01daff04211450e3d1bd8103 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55668 Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-21drivers/intel/mipi_camera: Change type for gpio_num to uint16_tVarshit B Pandya
gpio_num is used to indicate the GPIO which is taken from gpio_soc_defs.h file. Support for dynamic generation of ASL file for Camera was added for JSL when there were less than 256 GPIOs. ADL now has more GPIOs and therefore uint8_t is not enough any more Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com> Change-Id: I0a5fdb612c8cf689d356af8591b9ad101360c25d Reviewed-on: https://review.coreboot.org/c/coreboot/+/55538 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-21mb/google/dedede/var/blipper: Configure Acoustic noise mitigation UPDsZanxi Chen
Enable Acoustic noise mitigation for blipper and set slew rate to 1/8 which is calibrated value for the board. BUG=b:187760191 BRANCH=dedede TEST=build firmware to UPD and Acoustic noise test Change-Id: I187702c23712416eaaaaf1e210dcfc6b2c560041 Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55610 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-06-21mb/purism/librem_mini/hda_verb.c: Fix subsystem, jack detectMatt DeVillier
- set subsystem/subvendor ID to Realtek default, as the one dumped from the vendor UEFI firmware provides no advantages - Add a codec reset before setting the subvendor ID using the Azalia macro for consistency with all other Realtek HDA codecs - disable jack detect for the external mic on the 3.5mm jack, since it's not currently working, so that the external microphone can be manually selected Change-Id: Ib0f99e5088973a721c0a295899012c9aea5009cf Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55660 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-21mb/purism/librem_14/hda_verb.c: Fix subsystem, verb count, jack detectMatt DeVillier
- set subsystem/subvendor ID to Realtek default, as the one dumped from the vendor UEFI firmware provides no advantages - fix the number of verb entries, which excluded the 4 following the pin configs - issue the reset *before* setting the subvendor, and use the Azalia macro - disable jack detect for the 3.5mm jack, both line out and mic, since it's not currently working, so that the outputs can be manually selected Change-Id: Icd961c3c5aec23cf61d6a9ad65c603c6dc04697a Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55659 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-21mb/purism/librem_mini: Enable acoustic noise mitigationMatt DeVillier
Enable FastPkgCRampDisable for all domains, set SlowSlewRate to fast/16 for all domains. This aligns the settings with the Librem 14. Test: boot Librem Mini v2, observe high frequency acoustic noise reduced. Change-Id: I10bc2a3e6b631b8c0b430e204f376aa9a81ac683 Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55658 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-21ec/purism/librem/ec.asl: Disable notification for touchpad enable/disableMatt DeVillier
Somehow, enabling the notification to the OS driver breaks the functionality it was meant to enable. Until this can be resolved, disable the driver notification, so that the key functions as intended. Test: build/boot librem_bdw and librem_skl boards, verify trackpad enable toggle via Fn+F1 works properly. Change-Id: Ic7bdb3154a87c4202b5ee1fd333281ef78db1104 Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55657 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-21mb/purism/librem_14: set SA slew rate to fast/16Matt DeVillier
Decrease SA slew rate to match other domains and reduce high-frequency noise slightly. Change-Id: I02cd93481f6bfba6249cb338a0e2f47d471a438e Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55656 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-21mb/guybrush: Probe FW_CONFIG for FP_PRESENTRob Barnes
Only enable fingerprint device when FP=FP_PRESENT in FW_CONFIG. BUG=b:186685292 TEST=Boot guybrush, no "EC failed to respond in time" error Change-Id: Ifaea9e23e6cdfdae024464ff36c1520b8ad05e50 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55677 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-06-21security/tpm/tspi/crtm.c: Fix early initArthur Heymans
If the early crtm is not initialised there is nothing to write to PCR in the early tpm init. Change-Id: I9fa05f04588321163afc817de29c03bd426fc1f0 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55470 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-06-21include/pci_def.h: Add some PCI Power Management CSR bitsTim Wawrzynczak
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I84c8470764a4e6e09220044966111ffe72078099 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55674 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-21soc/intel/common/block/cse: Move enum csme_failure_reasonTim Wawrzynczak
CSE error codes may be applicable to move than just CSE Lite SKU errors, therefore move this enum to the intelblocks/cse.h file so that it can be used in other CSE-related code. While copying, remove `LITE_SKU` from a few of the enum values that are not necessarily CSE Lite SKU-specific. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I0351587c67ce12f781c536998ca18a6a804d080a Reviewed-on: https://review.coreboot.org/c/coreboot/+/55672 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-21southbridge/amd: Create ACPI MCFG MMCONFIGAngel Pons
These southbridges are paired with MMCONF-enabled northbridges. Change-Id: I0416de6425bb57471856731ad12ce8194ac98be2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55572 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-06-20util/ifdtool: Use ICH Strap Length (ISL) to identify APL chipsetSubrata Banik
Use offset FLMAP1 bit 24:31, called ISL (ICH Strap Lenth) to uniquely identify the chipsets without any additional logic. +---------+-----------+ | Chipset | PSL Value | +---------+-----------+ | APL | 0x13 | +---------+-----------+ BUG=b:153888802 TEST=Able to dump FD contains correctly without specifying platform quirks on APL (IFDv1) Platform. > ifdtool -d coreboot.rom PCH Revision: Apollo Lake: N3xxx, J3xxx Change-Id: I02bcc6b1ca61c4ee59582f1b310ed0fba0ef1d9a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55617 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-20util/ifdtool: Use -p platform name to detect IFDv2 platform and chipsetSubrata Banik
ifdtool uses `chipset` information to determine how certain straps are decoded. This has been used for IFDv1 platforms as well as IFDv2 platforms (CHIPSET_500_600_SERIES_TIGER_ALDER_POINT). IFDv2 platforms are all expected to pass in `-p` argument to identify the platform. This platform information can be used to identify the appropriate chipset information. For IFDv1 since `-p` argument is not provided, ifdtool needs to use certain fields in the descriptor (e.g. strap length) for unique identification of IFDv1 chipset. This change updates `check_ifd_version()` function to: 1. Determine if IFD version is v1 or v2 based on `-p` argument. If `-p` is not provided, it assumes that the platform is using IFDv1. 2. Based on IFD version, it calls either `ifd2_platform_to_chipset()` or `ifd1_guess_chipset()` to determine chipset information. This fixes the issue reported with CB:44815, where ifdtool is unable to identify Alder Lake chipsets. BUG=b:153888802 TEST=Able to dump FD contains correctly with platform quirks on Brya Platform. > ifdtool -d coreboot.rom -p adl PCH Revision: 500 series Tiger Point/ 600 series Alder Point Change-Id: I25f69ce775454409974056d8326c02e29038ec8a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54305 Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-19mb/google/dedede: Configure CBI EEPROM WPAseda Aboagye
On dedede boards without Cr50, the CrOS Board Info (CBI) EEPROM write protect signal is decoupled from the hardware write protect signal. Instead, we'd like for it to mirror the software write protect status. This commit simply checks the software write protect status of the SPI flash and sets the CBI EEPROM write protect if it's enabled. To prevent changing the WP signal at run-time, the GPIO configuration is also locked down after the level has been set. If HW WP is deasserted, the CBI EEPROM WP will be deasserted as well. BUG=b:191189275,b:184592299 BRANCH=None TEST=Build and flash lalala, disable SW WP by running `flashrom -p host --wp-disable` from a root shell and verify that the GPIO is asserted after a reboot. Export the gpio via sysfs and verify that attempting to change the value of the GPIO is futile. Enable SW WP via `flashrom -p host --wp-enable` and reboot the DUT. Again, export the GPIO via sysfs and verify that attempts to change the GPIO value are futile. localhost ~ # iotools mem_read32 0xfd6e08d0 0x44000200 localhost ~ # cd /sys/class/gpio/ localhost /sys/class/gpio # echo 217 > export localhost /sys/class/gpio # cd gpio217/ localhost /sys/class/gpio/gpio217 # echo out > direction localhost /sys/class/gpio/gpio217 # cat value 0 localhost /sys/class/gpio/gpio217 # echo 1 > value localhost /sys/class/gpio/gpio217 # cat value 1 localhost /sys/class/gpio/gpio217 # iotools mem_read32 0xfd6e08d0 0x44000200 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Change-Id: Ic103037921ec7d2f96f86178675c11a3a1357d1b Reviewed-on: https://review.coreboot.org/c/coreboot/+/55558 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-06-19soc/intel/common/block/smm: Add `mainboard_smi_finalize`Aseda Aboagye
This commit adds a method called `mainboard_smi_finalize` which provides a mechanism for a mainboard to execute some code as part of the finalize method in the SMM stage before SoC does its finalization. BUG=b:191189275 BRANCH=None TEST=Implement `mainboard_smi_finalize` on lalala and verify that the code executes in SMM. Signed-off-by: Aseda Aboagye <aaboagye@google.com> Change-Id: If1ee63431e3c2a5831a4656c3a361229acff3f42 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55649 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-06-19soc/intel/jasperlake: Add offsets for pad lockingAseda Aboagye
This commit simply adds the offset for the PADCFGLOCK register for the Intel Jasper Lake platform. This enables pads to be locked. BUG=b:191189275 BRANCH=None TEST=Enable pad locking on lalala by calling `gpio_lock_pad` and verify that the pad configuration is locked and cannot be manipulated from the OS. Signed-off-by: Aseda Aboagye <aaboagye@google.com> Change-Id: Iccfe536b4a881f081f22bcc258a375caad3ffcb3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55648 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-19soc/intel/common/block/gpio: Add `gpio_lock_pad()`Aseda Aboagye
This commit adds a method for locking a GPIO pad configuration and its TX state. When the configuration is locked, the following registers become Read-Only and software writes to these registers have no effect. Pad Configuration registers GPI_NMI_EN GPI_SMI_EN GPI_GPE_EN Note that this is only effective if the pad is owned by the host (set in the PAD_OWN register). Intel platforms that wish to leverage this function need to define the PADCFGLOCK offset for their platform. BUG=b:191189275 BRANCH=None TEST=With some other code, call gpio_lock_pad() against a pad and verify that the pad configuration is locked and the state of the pad cannot be changed from the OS. Signed-off-by: Aseda Aboagye <aaboagye@google.com> Change-Id: Id3c0da2f6942099c0289ca1e33a33c176f49d380 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55557 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-06-18soc/intel/alderlake: Add TBT PCIe root ports enablementBernardo Perez Priego
Ports are enabled according to devicetree. BUG=none TEST=Boot device, TBT should be functional Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com> Change-Id: I57e8eb13484014c17d24ad564643f0d03d11bc58 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54643 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-18soc/intel/common: Fix bugs for GPIO_LOCK_UNLOCKAseda Aboagye
Per the Intel External Design Specification (doc #618876), the opcode for GPIO_LOCK_UNLOCK is 0x13. This commit fixes a bug where the opcode was defined as 13 decimal instead of hexadecimal. Additionally, it fixes another issue where the `pcr_execute_sideband_msg()` function doesn't actually write the data when this opcode is selected. BUG=b:191189275 BRANCH=None TEST=With additional code that uses this opcode, verify that the lock functionality works by locking a pad in firmware and attempting to modify the configuration of the pad from the OS. Signed-off-by: Aseda Aboagye <aaboagye@google.com> Change-Id: Ie14fff595474cdfd647c2b36f1eeb5e018f67375 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55556 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-18nvs: Add Chrome OS NVS (CNVS) information to coreboot tablesFurquan Shaikh
CB:51638 separated Chrome OS NVS from global NVS by allocating it separately in CBMEM. CNVS is used in depthcharge to fill firmware information at boot time. Thus, location of CNVS needs to be shared in coreboot tables for depthcharge to use. This change adds a new coreboot table tag `CB_TAG_ACPI_CNVS`/`CB_TAG_ACPI_CNVS`(0x41) which provides the location of CNVS in CBMEM to payload (depthcharge). Additionally, CB:51639 refactored device nvs(DNVS) and moved it to the end of GNVS instead of the fixed offset 0x1000. DNVS is used on older Intel platforms like baytrail, braswell and broadwell and depthcharge fills this at boot time as well. Since DNVS is no longer used on any new platforms, this information is not passed in coreboot tables. Instead depthcharge is being updated to use statically defined offsets for DNVS. BUG=b:191324611, b:191324611 TEST=Verified that `crossystem fwid` which reads fwid information from CNVS is reported correctly on brya. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I3815d5ecb5f0b534ead61836c2d275083e397ff0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55665 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-18arch/x86/include/arch/smp/mpspec: improve mp_bustype enum definitionFelix Held
Since the raw values of the enum elements are used, explicitly assign the value 0 to the first element to make it clearer that the absolute values matter here. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I69f58cca7130ce5f0ebe4743754e4e31f55db289 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55615 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-06-18soc/amd/picasso,stoneyridge/acpi: use defines for MADT parametersFelix Held
Using existing defines instead of magic values improves readability of the code. Also add comments to the MADT IRQ overrides to make it clearer what those actually do. TEST=Timeless build results in identical binary for amd/gardenia (Stoneyridge), amd/mandolin (Picasso) and amd/majolica (Cezanne) Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I224ffbe8eb65bcdd5fc70c0ff8b15d55b3f6be01 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55613 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-18soc/mediatek/mt8195: add mt6691 driverhenryc.chen
Add mt6691 buck control for DRAM to run fast calibration test. It is needed to get and set voltage during testing. Signed-off-by: Henry Chen <henryc.chen@mediatek.com> Change-Id: I4fb9f7245d44383a6a3a0cf8d00f7f503cbdeb06 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55575 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-18mb/google/cherry: enable display supportJitao Shi
To enable display, we have to: 1. Configure panel power and backlight 2. Configure eDP driver BUG=b:189985956 Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> Change-Id: Ida6c157a6a3bd904d3fa3dd2001385ced34f7711 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55574 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-18soc/mediatek/mt8195: add eDP supportJitao Shi
BUG=b:189985956 Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I37326ad053295aa4944c8291e4e7a7d69c8f3f63 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55573 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-18soc/intel/common/block: fix storage size of HEST log addressRocky Phagura
This patch fixes the storage size to reflect the proper bits instead of bytes. It was a bug in the initial HEST patch (https://review.coreboot.org/c/coreboot/+/52090), and commit ID d4db36e672644ac7f528d12c5ce3539725456085 . Also fixed the comments to properly reflect the range being used. Change-Id: I9e968bb09f1c9cd805ff1d0849551b9c2ce2e2b6 Signed-off-by: Rocky Phagura <rphagura@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55393 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-18mb/intel/ehlcrb: Change default romsize and remove chromeos.fmdLean Sheng Tan
Change the default rom size to 32MB and remove chromeos.fmd because Chrome OS is not supported on EHL for now. Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: I49d9404eb901087037b5423a4a503c5271e14138 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55554 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-18soc/intel/jasperlake: Make use of FSP_ARRAY_LOAD macroLean Sheng Tan
Add FSP_ARRAY_LOAD macro for checking and loading array type configs into array type UPDs to increase readability. Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: Ia20cabcaf9724882c68633eb9b510230e993768c Reviewed-on: https://review.coreboot.org/c/coreboot/+/55560 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2021-06-18soc/intel/elkhartlake: Make use of FSP_ARRAY_LOAD macroLean Sheng Tan
Use FSP_ARRAY_LOAD macro for checking and loading array type configs into array type UPDs to increase readability. Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: I2562977e55f8909038697f7e19b82ec6b5e47fae Reviewed-on: https://review.coreboot.org/c/coreboot/+/55553 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2021-06-18intel/fsp2_0: Add FSP_ARRAY_LOAD macroLean Sheng Tan
Add FSP_ARRAY_LOAD macro for checking and loading array type configs into array type UPDs to increase readability. Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: I307340a2bfc0a54f2ab7241af2f24dfbf8bb111d Reviewed-on: https://review.coreboot.org/c/coreboot/+/55559 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-18mb/google/bry: remove GSC option as it's not usedYH Lin
BUG=None BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a Signed-off-by: YH Lin <yueherngl@google.com> Change-Id: I932178dc395a4a96682a2e2076131feb3342aa52 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55597 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-18drivers/intel/gma/opregion.c: Re-add lost log messageAngel Pons
Commit 926949d64c1d8ef49dcc6774dd8535a2cb1fd423 (drivers/intel/gma: Restructure IGD opregion init code) accidentally dropped this print statement. As it can be useful for debugging purposes, add it back. Change-Id: Iebd9e02bccc77538c0eed1e549294408586322f2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55567 Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.corp-partner.google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-18soc/intel/car/cache_as_ram.S: Fix typo in commentArthur Heymans
Change-Id: Ia91dbda44f60388324cf58dbccdbd2172dbff21d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55561 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-18util/ifdtool: Add Elkhart Lake platform support under IFDv2Lean Sheng Tan
Add EHL under same family tree as TGL & JSL, also fix a spacing inconsistency line. Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: Ice09861c104c4e339fc83631c75089fa069b3931 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55357 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-18includes: Move *abs() declarations into `stdlib.h`Nico Huber
Change-Id: Id4df2d3210735bee737353d293450e59cf93bd9a Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55593 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-18includes: Remove dangling doxygen @}Nico Huber
Change-Id: I05e02f9689c1a6dafb3943657a3db975c2aeacbe Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55592 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-18includes: Define `CHAR_BIT` in `limits.h`Nico Huber
Change-Id: Ib1d80d0c7457f90596ef5cd9d5ad0c4a33c8d473 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55591 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-18includes: Provide `wchar.h` with `wchar_t` and `wint_t`Nico Huber
Change-Id: Iacb0e4eaf3f0b6bf843f3bfda5bdfde0f7a98808 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55590 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-18includes: Add include guards to `stddef.h`Nico Huber
Change-Id: Ifae4f07abd75da9784967c2020eed2c3fe64afa0 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55589 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-10 22:12:32 +0000