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2022-08-31soc/mediatek/mt8188: Add DEVAPC basic driverNina Wu
Add basic DEVAPC (device access permission control) driver. DEVAPC driver is used to set up bus fabric security and data protection among hardwares. DEVAPC driver groups the master hardwares into different domains and gives secure and non-secure property. The slave hardware can configure different access permissions for different domains via DEVAPC driver. 1. Initialize DEVAPC. 2. Set master domain and secure side band. 3. Set default permission. TEST=check logs of DEVAPC ok. BUG=b:236331724 Signed-off-by: Nina Wu <nina-cm.wu@mediatek.com> Change-Id: Iad3569bc6f8ba032d478934ba839dc4b5387bafc Reviewed-on: https://review.coreboot.org/c/coreboot/+/66970 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-08-31soc/mediatek: Move common DEVPAC enums and functions to commonBo-Chen Chen
Some enums and functions are the same in DEVAPC driver for MT8195, MT8186, and MT8188, so we move them to common folder. TEST=build pass. BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: Ia7d2145780780fd54b76952db96424b8ea477594 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67171 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-08-31device/dram/ddr4.c: note that dimm size calculation won't work for 3DSKrystian Hebel
Change-Id: I52548e544165b4732d9989da6455c8fd77bf99d3 Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67185 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-08-31device/dram/ddr4.c: fill missing ECC info from SPDKrystian Hebel
Change-Id: I80fccfa6d108b68d6f33a3d47766205b423a41ff Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67058 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-08-31soc/mediatek/mt8188: Initialize DPM in ramstageXi Chen
Add initialization of DPM drvier for DRAM low power mode. DPM is an essential component on MediaTek SoC, so we initialize DPM in soc_init(). This DPM flow adds 22ms to the boot time. coreboot logs: CBFS: Found 'dpm.dm' @0x156c0 size 0xfc in mcache @0xfffdd110 mtk_init_mcu: Loaded (and reset) dpm.dm in 6 msecs (422 bytes) CBFS: Found 'dpm.pm' @0x15800 size 0x3c59 in mcache @0xfffdd140 mtk_init_mcu: Loaded (and reset) dpm.pm in 16 msecs (18910 bytes) TEST=build pass BUG=b:236331724 Signed-off-by: Xi Chen <xixi.chen@mediatek.corp-partner.google.com> Change-Id: I46baa7b49e90d53dd4d1d95af9c46622faf30419 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66969 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-31soc/mediatek/mt8188: Support 4 channel DRAM in DPM init flowXi Chen
TEST=build pass BUG=b:236331724 Signed-off-by: Xi Chen <xixi.chen@mediatek.corp-partner.google.com> Change-Id: Ia68aca1d1e8729739246157904727123e5d001e8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66968 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-31soc/mediatek/mt8188: Add DPM firmware filesXi Chen
DPM is a hardware module for DRAM power management, which is used for DRAM low power mode. TEST=build pass BUG=b:236331724 Signed-off-by: Xi Chen <xixi.chen@mediatek.corp-partner.google.com> Change-Id: I872396fe2c5accd92ba5c14b124125bd58257771 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66967 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-31soc/mediatek: Move dpm_4ch.c to commonXi Chen
MT8195 and MT8188 share the same dpm_4ch.c, so we move it to common folder. TEST=build pass BUG=b:236331724 Signed-off-by: Xi Chen <xixi.chen@mediatek.corp-partner.google.com> Change-Id: I13406707d3b331ced57af62f4ba4f365e9ac4f84 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66966 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-08-31allocator_v4: Completely ignore resources with 0 limitNico Huber
It seems pass 1 and 2 were inconsistent. The first would account for resources with a limit of 0 even though the second can't assign anything for them. Change-Id: I86fb8edc8d4b3c9310517e07f29f73a6b859a7c4 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65402 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-08-31mb/google/rex: Correct EC-is-trusted logicKapil Porwal
Fix EC_IN_RW config for Rex. Dauntless on Rex does not have an EC_IN_RW GPIO pin. Port of commit 7f339c6050c5 ("mb/google/corsola: Correct EC-is-trusted logic") BUG=b:243950850 TEST=Built and booted to Google Rex. Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I97e5c752b4f36c9221137903f755837880f6b1c4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67208 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-08-31Revert "mb/google/rex: Disable LID_SHUTDOWN"Subrata Banik
This reverts commit 47fee08fc3a383e14dc974754d6e463fa320badf. The required EC changes are now in place to revert this W/A that disables the LID based shutdown. BUG=b:243920003 TEST=No shutdown request has triggered while booting AP at depthcharge. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I5ae56912f030f6f0e3cb49282bbffc920fb389c0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67206 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-08-31vendorcode/intel/fsp: Add Raptor Lake FSP headers for FSP v3301.03Selma Bensaid
The headers added are generated as per FSP v3301.03 In the future, when Alder Lake and Raptor Lake fsp align, Raptor Lake fsp headers can be deleted and Raptor Lake soc will also use headers from alderlake/ folder. BUG=b:243693364 BRANCH=firmware-brya-14505.B TEST=Boot to OS Signed-off-by: Selma Bensaid <selma.bensaid@intel.com> Change-Id: Idbd39ed53d4ba05248a0e83c104846960253931e Reviewed-on: https://review.coreboot.org/c/coreboot/+/67084 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-08-30mb/google/skyrim: Fix APCB_SBR_D5.gen build rulesKarthikeyan Ramasubramanian
CB:66978 introduced an incorrect condition to check for the presence of SPD binaries to be injected into APCB_SBR_D5.gen. This caused the SPDs to be not injected into the APCB and hence the system fails to boot. Fix it by updating the path of the SPD binaries correctly. BUG=b:244173966 TEST=Build and boot to OS in Skyrim. Change-Id: I5efa634fafdcc4769dfad5f533d5512e7c03644f Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67210 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-08-30.gitignore: Add .vscode/Tim Van Patten
Visual Studio Code uses the directory .vscode/ to store data, so add it to the .gitignore. Signed-off-by: Tim Van Patten <timvp@google.com> Change-Id: I8fe6439f01bd5ada8ceb814a22602db241aa11d6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66701 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com>
2022-08-30soc/intel/cmn/block/acpi: Add new GPIO ASL MethodTim Wawrzynczak
Ths new Method, GSCI, allows control over whether or not IRQs are routed as SCI#s for the given GPIO. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ic61caaf77d2c6e295e67a1501544e8b8fc6f3b6a Reviewed-on: https://review.coreboot.org/c/coreboot/+/66813 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-30mb/google/nipperkin: Set BT enable_delay_ms to 10msRob Barnes
Override bluetooth enable_delay_ms to 10ms, per advise from vendor. BUG=b:233369179 BRANCH=guybrush TEST=Boot nipperkin, connect to headset, suspend and reboot, headset still functions. Change-Id: Ic00de6704018f27339512929f85531aa72205b0e Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67177 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com>
2022-08-30mb/google/guybrush: Set BT enable_delay_ms to 200msRob Barnes
Set bluetooth enable_delay_ms to 200ms. 200ms is the lowest common denominator between the two BT chipsets. BUG=b:233369179,b:236289478 BRANCH=guybrush TEST=Connect to headset, suspend and reboot, headset still functions Change-Id: Id4c23de37351d28d02aaa797fa19ff49e9dfa76c Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65180 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com>
2022-08-30soc/intel/cmn/block/acpi: Modify GPIO Methods to use bitfieldsTim Wawrzynczak
IMHO, using bitfields directly in the Field declaration makes the ASL code more readable then directly manipulating the entire 32-bit dword. TEST=ACPI code using several of these Methods still works (google/agah dGPU ACPI code) Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I9909700022d8b55db3f5208010bdff11ddaf4e7d Reviewed-on: https://review.coreboot.org/c/coreboot/+/66812 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-30mb/google/brya/variants/nivviks: Define DPTF policies for NirwenVidya Gopalakrishnan
Added DPTF passive, critical, active policies for Nirwen. Added additional TSR for Nivviks and updated the PL2 time window Ref: EDS doc#645550 BUG=b:238713292 TEST= Boot to OS and verify dptf policies are set based on fw_config. Signed-off-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.com> Change-Id: Iae46736d8d7723a20983dcaad42a7007d76cfad8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66833 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2022-08-30mb/google/nissa: Configure the DPTF policies based on fw_configV Sowmya
This change adds support to configure the DPTF policies based on the fw_config THERMAL_SOLUTION. BUG=b:238713292 TEST=Boot to OS and verify that dptf policies are set based on fw_config. Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: I0ffb9d7cc6c963add001a31ba23a6d6c351dd621 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66589 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-08-30mb/google/brya/vell: Update amp SSIDShon Wang
The current subsystem ID used by the amps may end up getting used again for future products, therefore this CL updates the subsystem ID to 103C8C08, which was specifically generated for this amp. BUG=b:202484541 BRANCH=brya TEST='FW_NAME=vell emerge-brya coreboot' Change-Id: I399d8d99ead4fb6fdfa24c2a7a3e3d5e63603b8b Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67014 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-08-30mb/google/skyrim/var/winterhold: Update memory and RAMID tableEricKY Cheng
Update memory and RAMID table BRANCH=None BUG=b:243337816 TEST= emerge-coreboot Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com> Change-Id: Iec3c2098be86661249b1786a02f0768f9d8ad0ff Reviewed-on: https://review.coreboot.org/c/coreboot/+/67106 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Amanda Hwang <amanda_hwang@compal.corp-partner.google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
2022-08-30util/spd_tools: Add AMD Mendocino (MDN) platformEricKY Cheng
This patch adds support for MDN platform to the spd_tools. This change replaces SBR with MDN. BUG=b:243337816 TEST=Able to generate SPD for LP5 DRAM part. Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com> Change-Id: If099af36de8a64e96fbfde32eaf15990f4b330c8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67105 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Amanda Hwang <amanda_hwang@compal.corp-partner.google.com>
2022-08-30mb/google/skyrim/var/winterhold: Update Lp5x and Lp5 memory supportEricKY Cheng
Update K3KL8L80CM-MGCT, K3KL9L90CM-MGCT,H58G66AK6BX070 support BRANCH=None BUG=b:243337816 TEST= SPD add Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com> Change-Id: I2c370fbd007c22b1f94074d9f16e5bc7c4e04848 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67104 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Amanda Hwang <amanda_hwang@compal.corp-partner.google.com>
2022-08-30mb/google/rex: Change GPP_A17 programmingTarun Tuli
To match byra commit 7c2514fc072f95eed6483518811fb6c39f780f5b (mb/google/brya: Change GPP_F17 programming), update A17 pad configuration to the APIC only. TEST=Verified booting to OS on Google/Rex. Signed-off-by: Tarun Tuli <taruntuli@google.com> Change-Id: Ie9f071dc4a2755dd1f396e2afe730ead66bb1dd0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67183 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-30amd/soc/common: Update CPPC valueZheng Bao
The CPPC table value for UEFI BIOS has been changed. The code has been merged to AGESA. We can get the value by dumping ACPI table. Then we align the coreboot code with the new value. BUG=b:190420984 Change-Id: I091ab3bbc5f94961f8b366a3fa00f50f5c9fa182 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63632 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-08-30mb/google/nissa: Mark CNVi wifi device as untrustedReka Norman
BUG=b:238937091 TEST=Dump the SSDT on nivviks and check that the wifi device has the DmaProperty. Change-Id: I910b7da7050f9aebfe0eb58552c82b1b29de3772 Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67044 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-08-29amdfwtool: Fix indentationZheng Bao
Change-Id: I4c57c9bade318d54315f9692cd37edb694e33aa9 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58320 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-29mb/prodrive/atlas: Fix SMBUS/SPD addressesMaximilian Brune
Commit 0e7cf3d81d121181a94b6a594b944628c2e5a939 (soc/intel/alderlake: Fix DDR5 channel mapping) fixed a bug in SoC code that messed up DDR5 SPD address mapping. Atlas uses the 0x50/0x52 addresses. However, the SoC code bug required commit 044883615d4471b7a0b883eb8b8224d95faf52af (mb/prodrive/atlas: Update correct SPD address) so that at least some RAM would work. Now that the SoC code bug is fixed, the workaround is no longer needed, so use the correct SPD address mapping. TEST=Boot Atlas and verify that both memory channels work Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I352d8f36eec63cffd3f63ab6e7421db16ca30163 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67075 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-08-29util/futility: Ignore deprecated declarations in OpenSSL 3.0Martin Roth
Building futility with OpenSSL 3.0 (default in latest Debian sid) results in a number of warnings that various declarations have been deprecated. Since we (and futility) have warnings as errors enabled, this causes the building of futility to fail, killing the entire coreboot build. To work around this until futility is updated, turn off the warnings about deprecated declarations. Bug 243994708 has been filed to get futility updated. This workaround can be removed when futility builds cleanly with the latest libsssl-dev. BUG=b:243994708 TEST=Futility build doesn't fail with libssl-dev > 3.0 Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I54e27e09b0d50530709864672afe35c59c76f06e Reviewed-on: https://review.coreboot.org/c/coreboot/+/67124 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Tom Hiller <thrilleratplay@gmail.com>
2022-08-29Documentation/tutorial: Fix markdown heading in Part 3Nicholas Chin
Part of the content was on the same line as the heading. Change-Id: Ia19487d80e9f004d59f96ff09e1f3de4f37c2f77 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67000 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-29soc/intel/alderlake: Rename pcie5 aliasBora Guvendik
Rename pcie5 alias as pcie5_0 since raptorlake is adding a new pcie5 RC. BRANCH=firmware-brya-14505.B TEST=none Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: Iee669e68e3607b7ffec9f0800e9f0a916defd498 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67107 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-08-29soc/amd/mendocino/psp_verstage/svc: Fix reset_system typeKarthikeyan Ramasubramanian
The size of the input parameter to RESET_SYSTEM svc call is expected to be 4 bytes. Fix the reset_system type from enum to uint32_t. BUG=b:243476183 TEST=Build and boot to OS in Skyrim with PSP verstage. Trigger a system reset to ensure that the system is reset successfully. Change-Id: I6319a1dfc89602722c1c2b1c4ee744493ae8b33f Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67117 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-29pciexp: Move PCI path check one level up to pciexp_enable_ltr()Nico Huber
If we have a PCIe root port without `ops_pci` or without `get_ltr_max_latencies`, the parent device wouldn't be PCI. Hence, check for a PCI path early. Change-Id: I358cb6756750bb10d0a23ab7133b917bfa25988b Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66845 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-08-29drivers/i2c/tpm: Remove TI50_FIRMWARE_VERSION_NOT_SUPPORTEDReka Norman
This workaround was added since reading the firmware version on Ti50 versions < 0.0.15 will cause the Ti50 to become unresponsive. No one is using Ti50 this old anymore, so remove the workaround. BUG=b:224650720,b:236911319 TEST=Boot to OS on nivviks with Ti50 0.22.4. Check the log contains the firmware version: [INFO ] Firmware version: Ti50/D3C1 RO_B:0.0.26/- RW_B:0.22.4/ti50_common:v095c Change-Id: I3628b799e436a80d0512dabd356c4b2566ed600a Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67138 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-08-27util/docker/coreboot-sdk: Install GNAT 12Felix Singer
For some reason GNAT 11 is not able to build GNAT 12, since there are some Ada errors during the compilation. However, it works with GNAT 12. So use GNAT 12 for the host toolchain instead. Change-Id: If00a05a0c8564e624809268a12fae28261e380a2 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66924 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-08-27util/docker/coreboot-sdk: Replace package qemu with qemu-systemFelix Singer
The qemu package doesn't exist anymore or it was renamed. Instead of installing QEMU for all available architectures, install only the packages which ship architectures that are supported by coreboot. * qemu-system-arm * qemu-system-misc (for RISC-V) * qemu-system-ppc * qemu-system-x86 Change-Id: Ifc46a8c9fcb1ab3c38dc8cbbc906882e93a719d7 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66923 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tom Hiller <thrilleratplay@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-08-27soc/mediatek/mt8188: Enable USE_CBMEM_DRAM_INFOXi Chen
The feature "USE_CBMEM_DRAM_INFO" is supported in MT8188. Therefore, we select this configuration to enable it. TEST=build pass BUG=b:233720142 Signed-off-by: Xi Chen <xixi.chen@mediatek.com> Change-Id: I14f3d971fe861cbd09cc86c8a5a1fb531bfe78d7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66280 Reviewed-by: Yidi Lin <yidilin@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-27soc/mediatek: Move emi.c to common folderRex-BC Chen
The emi.c is the same for MT8186 and MT8188, so we could move it to the common folder and reuse it. TEST=build pass BUG=b:236331724 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I225f1d07c973129172f01bf7f4d7f5d5abe7c02b Reviewed-on: https://review.coreboot.org/c/coreboot/+/66328 Reviewed-by: Yidi Lin <yidilin@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-27drivers/mrc_cache: Don't compute checksum if TPM hash is usedReka Norman
When MRC_SAVE_HASH_IN_TPM is selected, mrc_data_valid() uses the TPM hash to verify the MRC cache data, not the checksum. However, we still calculate the checksum when updating the cache. Skip this calculation when MRC_SAVE_HASH_IN_TPM is selected to save boot time. On nissa, this reduces boot time by ~14 ms: Before: 3:after RAM initialization 854,298 (28,226) After: 3:after RAM initialization 849,626 (14,463) Note, the reason the calculation is so slow is that the new MRC data lives in CBMEM, which is not yet marked as cacheable in romstage. BUG=b:242667207 TEST=MRC caching still works as expected on nivviks. After clearing the MRC cache, memory training happens on the next boot, but doesn't on subsequent boots. Change-Id: Ifbb75ecfa17421c0565aec1f3eb48d950244f821 Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67042 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Shelley Chen <shchen@google.com>
2022-08-27mb/google/corsola: Add new board Magikarpvan_chen
Add a new board 'Magikarp', and enable SDCARD_INIT for it. BUG=b:242822419 BRANCH=None TEST=none Change-Id: Id7432e33b6fd5f1c25536cf068ff76612575e8ee Signed-off-by: van_chen <van_chen@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67043 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Chen-Tsung Hsieh <chentsung@chromium.org>
2022-08-27soc/mediatek/mt8188: Add DRAM fast calibration supportXi Chen
Define fields of sdram_params and enable MEDIATEK_BLOB_FAST_INIT to run fast calibration for MT8188 using blob. DRAM fast calibration logs: DRAM-K: Fast calibration passed in 19530 msecs dram size (romstage): 0x200000000 TEST=Fast calibration pass. BUG=b:233720142 Signed-off-by: Xi Chen <xixi.chen@mediatek.com> Change-Id: I2468d971fe861cbd09cc86c8a5a1fb531bfe78d7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66279 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-08-27mb/google/geralt: Fully calibrate DRAMXi Chen
Initialize and calibrate DRAM in romstage. DRAM full calibration logs: dram_init: dram init end (result: 0) DRAM-K: Full calibration passed in 50176 msecs TEST=Full calibration pass. BUG=b:233720142 Signed-off-by: Xi Chen <xixi.chen@mediatek.com> Change-Id: I31f5693ffe4a1e30defbc8a96dc128de03d6b7e7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66278 Reviewed-by: Yidi Lin <yidilin@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-27soc/mediatek/mt8188: Add DRAM full calibration supportXi Chen
- Use common SoC drivers for DRAM calibration support. - Remove emi.h because sdram_size() is already declared in common/include/soc/emi.h. - Add dramc_param.h and dramc_soc.h to prepare for implementation of DRAM full calibration. TEST=build pass BUG=b:233720142 Signed-off-by: Xi Chen <xixi.chen@mediatek.com> Change-Id: I2f88d971fe861cbd09cc86c8a5a1fb531bfe78d7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66277 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-08-27util/docker/coreboot-sdk: Remove doxygenTom Hiller
Doxygen was removed at the project level. Remove the doxygen Debian package and make target. Change-Id: Ib82ba7890e7f53357eeca318b5f844164747aecd Signed-off-by: Tom Hiller <thrilleratplay@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67039 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-27mb/google/rex: Disable LID_SHUTDOWNSubrata Banik
This patch disables LID based shutdown requests. Google/Rex platform receives a forced shutdown request while booting to depthcharge due to EC wrongly detecting the LID is being closed. For now disable the LID based shutdown behaviour in depthcharge unless the EC issue gets resolved. BUG=b:243920003 TEST=Depthcharge no longer sees the force shutdown request now. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I03e33ea4d04dc48331d1cf98c47786b2a184c258 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67103 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-08-26tests/memrange-test: Correct final end test in test_memrange_steal()Nico Huber
If an inserted region's base wasn't aligned, the resulting range should still cover the original end (original region's base + size) and not the aligned-down base + size. Change-Id: I8f1c9456d6dbab4fa868de5c93fa3656397e54c1 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66607 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-26soc/intel/meteorlake: Update MTL_USE_COREBOOT_MP_INIT descriptionSridhar Siricilla
The patch update MTL_USE_COREBOOT_MP_INIT Kconfig description. TEST=Build code for MTL Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I38609cb03714084dd9092f41dd6e5b418a7f120a Reviewed-on: https://review.coreboot.org/c/coreboot/+/67077 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-08-26ec/google/chromeec: Call PNOT() when Battery Status ChangesTim Van Patten
PNOT() should be called when the battery status changes, to give the SOC an opportunity to handle it. This is in preparation for the low/no battery boot changes. This CL also updates the PNOT() comments to better match the name of the function and why it's called. BRANCH=none BUG=b:217911928 TEST=Boot skyrim Change-Id: I8b74313d242fd4959315a67579eb6c5f49a31a76 Signed-off-by: Tim Van Patten <timvp@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66993 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2022-08-26x86: Zero SMBIOS region before writing tablesJonathon Hall
Clear the SMBIOS region before writing SMBIOS tables. On librem_mini and librem_mini_v2, CBMEM allocations are offset by 4K for reboots relative to the cold boot. This means the unused SMBIOS region could contain the first 4K of the ACPI tables from the last boot (including the signature), which prevents Linux from booting. The CBMEM 4K offset appears to be due to FSP allocating memory differently between cold boot and reboot, this appears to be normal and causes the CBMEM base address to change. It is not clear why Linux examines an ACPI signature found in this region, but boot logs over serial confirm that it sees the corrupt table. The table is supposed to be found just below 1M, and kernel source appears to look in this region, but it is definitely finding the corrupt table in CBMEM. Normal cold boot: [ 0.008615] ACPI: RSDP 0x00000000000F6190 000024 (v02 COREv4) [ 0.008619] ACPI: XSDT 0x0000000099B480E0 00005C (v01 COREv4 COREBOOT 00000000 CORE 20220331) [ 0.008624] ACPI: FACP 0x0000000099B4A2A0 000114 (v06 COREv4 COREBOOT 00000000 CORE 20220331) [ 0.008634] ACPI: DSDT 0x0000000099B48280 00201F (v02 COREv4 COREBOOT 20110725 INTL 20220331) ... Reboot with corrupt table: [ 0.008820] ACPI: RSDP 0x00000000000F6190 000024 (v02 COREv4) [ 0.008823] ACPI: XSDT 0x0000000099B480E0 00005C (v01 COREv4 COREBOOT 00000000 CORE 20220331) [ 0.008828] ACPI: ???G 0x0000000099B4A2A0 20002001 (v00 ?G?$ 47020100 ?, 47020100) [ 0.008831] ACPI: �y 0x0000000099B4A3C0 54523882 (v67 ?_HID? A�? 65520D4E al T 20656D69) ... There are no specific errors but it returns to the firmware soon after, presumably due to a fault. This appears to be so early in the boot that panic=0 on the kernel command line has no effect. Test: build/boot Librem Mini, Librem Mini v2 and reboot. Change-Id: Ia20d0b30160e89e8d96add34d7e0e881f070ec61 Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66377 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-08-26mb/google/nissa/var/pujjo: Add FW_CONFIG probe for new audio devicesLeo Chou
Add FW_CONFIG probe for new audio sku: ALC5682I + MAX98357 BUG=b:243474931 TEST=Boot to OS and verify audio devices are set based on fw_config. Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Change-Id: I16af6cf4644c473034e184e95ff2038ca31b20de Reviewed-on: https://review.coreboot.org/c/coreboot/+/67016 Reviewed-by: Reka Norman <rekanorman@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-26soc/intel/mtl: Activate TME on all CPUsTarun Tuli
This patch runs `set_tme_core_activate()` on all CPUs (BSP+APs) as per MTL processor EDS. TEST= Able to build and boot RVP. Confirmed TME supported mode detected via temporary debug prints and MSR 0x9ff indicates activated. Signed-off-by: Tarun Tuli <taruntuli@google.com> Change-Id: Id368925504d81025239e94698d2cb0e2266a5a96 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66949 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-26mb/google/nissa/var/craask: Enable Cnvi BT Audio Offload featureTyler Wang
This patch enables Cnvi BT Audio Offload feature and also configures the virtual GPIO for CNVi Bluetooth I2S pads. BUG=b:239670216 TEST=emerge-nissa coreboot Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: Ibc7116e8dc5367fd94d29aba36b91778d0c21e4f Reviewed-on: https://review.coreboot.org/c/coreboot/+/66448 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-08-26tests/memrange-test: Correct commentary on test_memrange_steal()Nico Huber
Currently, memranges_steal() steals at the lowest possible address. This is actually reflected by the test code that checks if the *base* of the READONLY_TAG range changes. Furthermore, the test ends with the memranges restored, so revise the comment on the final state. Change-Id: Idef71ce464280c6805145f229de9e8913ba850bc Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66606 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Jan Dabros <jsd@semihalf.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-26ec/starlabs/merlin/cml: Correct the offset for Max ChargeSean Rhodes
The offset for Max Charge is located at 0x1a, so correct this in the definitions and EC memory ACPI. Change-Id: I92cc452d1189e62db78aed787f2de65fd5096564 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66962 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-08-26mb/google/brask/variants/moli: Override tdp pl1 valueRaihow Shi
Follow the "619907 Alder Lake-S and Raptor Lake-S Platform" and "685472 Intel® Dynamic Tuning Technology (Intel® DTT)" to override tdp pl1 in 15w cpu MSR to 55w and in 28w cpu MSR to 64w. BUG=b:236294162 TEST=emerge-brask coreboot and check MSR_Package Power Limit-1 in 15w and 28w CPU is correct. Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: Icb3d7c72b672fbd3e2a9f7ad1f2d1cb2ffc798c6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66910 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-26soc/amd/picasso: Reserve space for BIOS SIG in BIOS imageRitul Guru
Change-Id: I68667d084001c753e74ba480fa7b6e09b1b88cb8 Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66369 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-26util/amdfwtool: Add changes to reserve BIOS SIGRitul Guru
changes to reserve space for AMD_BIOS_SIG when BIOS image is signed with RTMSignature. Change-Id: Ia832fe83a3e29279c029fefc934c3ef4d335e2ea Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66259 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-08-26nb/intel/sandybridge: Align TOUUD down to 1 MiB granularityArthur Heymans
This register has a 1MiB granularity. The lowest bit is a lock bit. Change-Id: I688cb7818fc849784026ca0bc6acb7ef1ae92133 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66256 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-26mb/google/rex: Add mapping for GPIO_PCH_WPTarun Tuli
The define GPIO_PCH_WP needs to be mapped to GPP_H10 based on the Rex schematics 24/6/2022. TEST=Built and booted on Google Rex. Signed-off-by: Tarun Tuli <taruntuli@google.com> Change-Id: I2489c244bd4cbd9e10ed3db981a6e56a954b5e20 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67083 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-26mb/google/rex: Add mapping for EC_SYNC_IRQTarun Tuli
The define EC_SYNC_IRQ needs to be mapped to A17 based on the Rex schematics 24/6/2022. BUG=b:243781237 TEST=Successfully build rex and tested to ensure EC is now functional. Signed-off-by: Tarun Tuli <taruntuli@google.com> Change-Id: Ib61ddc9f73dd7b817d3b990bef8f0169f7cafbcd Reviewed-on: https://review.coreboot.org/c/coreboot/+/67082 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-08-26soc/intel/meteorlake: Provide access to IOE through P2SB SBI for TCSSJohn Zhao
This change provides access to IOE through P2SB Sideband interface for Meteor Lake TCSS functions of pad configuration and Thunderbolt authentication. There is a policy of locking the P2SB access at the end of platform initialization. The tbt_authentication is read from IOM register through IOE P2SB at early silicon initialization phase and its usage is deferred to usb4 driver. BUG=b:213574324 TEST=Built coreboot and validated booting to OS successfully on MTLRVP board. No boot hung was observed. Signed-off-by: John Zhao <john.zhao@intel.com> Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I8dcee90080c6e70dadc011cc1dbef3659fdbc8f7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66951 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-26soc/intel/p2sb: Refactor `p2sb_execute_sideband_access` functionSubrata Banik
This patch refactors p2sb_execute_sideband_access() to be able to handle SBI operations in both SMM and non-SMM scenarios. Prior to FSP-S operation being done, the IOE P2SB device will be visible on the PCI bus hence, performing the SBI operation using IOE P2SB doesn't involve unhide/hide operation. Post FSP-S, the IOE P2SB device is hidden. Additionally, SBI operations can't be performed as is. The only possible way to send SBI is inside SMM mode and to do that, coreboot needs to unhide the P2SB device prior to sending the SBI and hide it post sending SBI. As a result, the p2sb_execute_sideband_access() function has been refactored to manage these cases seamlessly without users of the p2sb_execute_sideband_access() actually being bothered about the calling mode. BUG=b:239806774 TEST=Able to perform p2sb_execute_sideband_access() function call in both SMM and non-SMM mode without any hang/die. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Iafebd5190deb50fd95382f17bf0248fcbfb23cb8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66950 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-08-25soc/amd: rework SPI flash MMIO region handlingFelix Held
Only 16 MByte of the SPI flash can be mapped right below the 4 GB boundary. In case of a larger SPI flash size, still only the 16 MByte region starting at 0xff000000 can be configured as WRPROT and be reserved for the MMIO mapped SPI flash region. The next 16 MByte MMIO region starting at address 0xfe000000 contain for example the LAPIC MMIO region, the ACPIMMIO region and the UART/I2C controller MMIO regions which shouldn't be configured as WRPROT. Reserving this region for the MMIO mapped SPI flash would also result in an overlap with the MMIO resources mentioned above. In the case of a smaller SPI flash, reserving the full 16 MByte flash MMIO region makes sure that the resource allocator won't try to put anything else in the lower parts of the 16 MByte SPI mapping region. To avoid the issues described above, always reserve/cache the maximum amount of 16 MBytes of flash that can be mapped below 4 GB. TEST=On boards with 16 MByte SPI flash chips, the resulting image of a timeless build doesn't change with this patch. Verified this on Chausie (Mendocino), Majolica (Cezanne), Cereme (Picasso) and Google/Careena (Stoneyridge). On Mandolin (Picasso) with an 8 MByte flash, the resulting image of a timeless build is different, but neither the coreboot console output nor the Linux dmesg output shows any errors that might be related to this change. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie12bd48e48e267a84dc494f67e8e0c7a4a01a320 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66700 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-25mb/google/brya/variants/crota: fine tune WWAN power sequencingTerry Chen
Because the poweron state of some of the WWAN GPIOs is the asserted state, this patch fixes the poweron sequence so that the WWAN module is always correctly powered on, in both cold and warm reboot scenarios. BUG=b:233564770 TEST=USE="project_crota emerge-brya coreboot" and verify it builds without error. Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com> Change-Id: I4ec8312c30392b9ca0a3e0321cb4578e76ec5787 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64816 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-08-25MAINTAINERS: Update AMD maintenance listsMartin Roth
- Add legacy AMD reference boards - Add Google AMD mainboards - Add mailing list for code changes to all AMD sections - Update people in AMD groups Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Change-Id: Ibd8001f8e4cd667bf9223dc32bc33a5a1dc9e89f Reviewed-on: https://review.coreboot.org/c/coreboot/+/66603 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-08-25mb/google/rex: Update DQS for RexTarun Tuli
Update the DQS for Rex as per the latest Rex schematics (08/25). BUG=b:243734885 TEST=Built successfully. Confirmed on HW. Change-Id: I2a458a3da725f953cbba8a194ac6f314f5467419 Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67041 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maulik Vaghela <maulikvaghela@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-08-25soc/intel/mtl: Hook up Lp5CccConfig FSP UPDKapil Porwal
Hook up Lp5CccConfig FSP UPD for Intel MeteorLake. BUG=b:243734885 TEST=Built and booted on Google Rex. Verified the UPD value in MRC log. Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I3d7ff8e08546f06cf7807ee825cfef84c14a6c5d Reviewed-on: https://review.coreboot.org/c/coreboot/+/67052 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Maulik Vaghela <maulikvaghela@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-08-25soc/intel/mtl: Hook up ECT FSP UPDKapil Porwal
Hook up ECT FSP UPD for Intel MeteorLake. BUG=b:243734885 TEST=Built and booted on Google Rex. Verified the UPD value in MRC log. Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: Idc23717c3ce52e3635e2da41733058f912545e5f Reviewed-on: https://review.coreboot.org/c/coreboot/+/67051 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maulik Vaghela <maulikvaghela@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-08-25soc/intel/mtl: Program MCHBASE prior enabling extended bios rangeSubrata Banik
This patch resolves the SoC programming dependency order where enabling extended bios support requires MCHBASE to be enabled. BUG=b:243693375 TEST=Able to boot from RW-A slot which is mapped to extended BIOS range. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I8bd9c3d3fb5e82e34f2d6af8548452c744d4b3c5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67046 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-25mb/google/rex: Configure GSC INT GPIO early in the bootKapil Porwal
This patch configures GPP_E03 (GSC_SOC_INT_ODL) as GPI/APIC in early GPIO tables. BUG=b:243641061 TEST=Able to build rex image. Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I4aa180c7105be3f356a0bbd5b92b4ced628c34fd Reviewed-on: https://review.coreboot.org/c/coreboot/+/67017 Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-08-25soc/amd/common/fsp/dmi: Set dimm voltage based on memory typeMatt DeVillier
Voltage set based on standard configuration for each type. TEST=build/boot google/skyrim, verify output in cbmem console log, DMI type 17 table. Change-Id: I9b1e68a9417e43cbb9c55b4c471664f3f9090342 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66981 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2022-08-25soc/amd/common/fsp/dmi: Print MT/s speeds, not frequency in debug outputMatt DeVillier
Since the frequency field is deprecated, print the max/configured MT/s speeds instead. TEST=build/boot google/skyrim, verify output in cbmem console log Change-Id: Icee5af762ca37c3b2ec8c9a52a7f32fb848390b0 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66980 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2022-08-25soc/amd/common/fsp/dmi: Translate DRAM speeds for (LP)DDR5Matt DeVillier
Hook up newly-added method to convert from frequency to MT/s so that boards which use (LP)DDR5 report their capability properly. BUG=b:239000826 TEST=build/boot google/skyrim, verify SMBIOS Type 17 table reports DRAM speeds correctly. Change-Id: I694b6c227a8d8fb40c897053808bc79df330ed0c Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66954 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2022-08-25device/dram: Add function to convert freq to MT/s for (LP)DDR5Matt DeVillier
As the frequency field in the SMBIOS type 17 table is deprecated, we need to provide the maximum and configured speed in MT/s. Add a method to convert from frequency to MT/s using a lookup table. BUG=b:239000826 TEST=Build and verify with other patches in train Change-Id: I0402b33a667f7d72918365a6a79b13c5b1719c0d Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66953 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2022-08-25util/apcb/apcb_v3_edit: Add support for LP5X SDRAMRobert Zieba
This commit adds support for LP5X SDRAM. BUG=b:242765117 TEST=Ran with LP5X SPDs and manually patched APCB Signed-off-by: Robert Zieba <robertzieba@google.com> Change-Id: I2d3cb9c9a1523cb4c5149ede1c96a16c3991a5d0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66840 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-25util/spd_tools: Add support for LP5X SPDsRobert Zieba
This commit adds support for LP5X SPDs. The SPD format is identical to LP5 except that the memory type is set to 0x15 instead of 0x13. Since they are essentially the same, LP5/5X parts share the same parts JSON file and SPD directory. LP5X parts are distinguished by the optional `lp5x` attribute. This commit also updates two existing LP5X memory parts with the correct attribute. BUG=b:242765117 TEST=Generated SPDs, verified that SPDs generated from LP5X parts match their LP5 counterparts except for memory type byte. Signed-off-by: Robert Zieba <robertzieba@google.com> Change-Id: I67df22bc3fd8ea45fe4dad16b8579351eb4d0d8b Reviewed-on: https://review.coreboot.org/c/coreboot/+/66839 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2022-08-24payloads/edk2: Separate the tasks required to build edk2Sean Rhodes
Separate the tasks that are required to be completed prior to building edk2 into a prep recipe. This allows this to be used for building different targets. This also ensures that the COREBOOT toolchain is used. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ic4ae8ac4118a5747f38297d0fbf4cb53aa3b6d6d Reviewed-on: https://review.coreboot.org/c/coreboot/+/66359 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-08-24payloads/edk2: Separate the Release String variableSean Rhodes
Separate the Release String from the Build String. This allows the makefile to locate built files more precisely. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Id98674f0bbf485b2bfdbf5784d325c5ac89ad076 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66358 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-24mb/google/skyrim: Create morthal variantMoises
Create the morthal variant of the skyrim reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:240970782 BRANCH=None TEST=util/abuild/abuild -p none -t google/skyrim -x -a make sure the build includes GOOGLE_MORTHAL Signed-off-by: Moises <moisesgarcia@google.com> Change-Id: I25c25f067a040e6930f4fc60fadb8be85dc8eda6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66989 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Jon Murphy <jpmurphy@google.com>
2022-08-24mb/google/skyrim: Check if SPD existsIsaac Lee
Update the build script to check if SPD exists, and only if SPD exists the APCB_SBR_D5.gen could be executed. BUG=None TEST=Build Change-Id: Ib7b977a89d403242e8bb1f684269e70082125e88 Signed-off-by: Isaac Lee <isaaclee@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66978 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Jon Murphy <jpmurphy@google.com>
2022-08-24soc/intel/common/block: Drop empty smm.hAngel Pons
This file has nothing useful. Get rid of it. Change-Id: Id2a42005d3b4b5161079c9ff48867cfc6fb0413d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66612 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2022-08-24mb/google/brya/var/agah: Reenable ASPM L1 substatesTim Wawrzynczak
Now that the GPU CLKREQ# signal is working correctly, ASPM L1 substates can be enabled and appear functional. BUG=b:240390998 TEST=lspci reports them as functional, MODS does not hang Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I8297f6bbf7f5a1f7d4ac519bc5b7b3112a74a9a0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66811 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-24mb/google/brya/var/agah: Update GPU GPIOsTim Wawrzynczak
Converge as many of the GPU's GPIOs to use PLTRST# as the reset signal explicitly, as the hardware engineers requested this. BUG=none TEST=boot and reboot agah, dGPU still visible on PCIe bus Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I78e58eb17cadc95083571affbecb4e1ce0adf16a Reviewed-on: https://review.coreboot.org/c/coreboot/+/66809 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-24mb/google/brya/var/agah: Enable DPTF oem_variablesTony Huang
Support oem_variables and change based on EC notify event. BUG=b:238921409 TEST=emerge-draco coreboot 1. check ACPI object ODVX has oem_variable[0]=0 Name (ODVX, Package (0x06) { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } 2. check can get EC oem variable change notify in the kernel log Change-Id: Ibd856563a43d73a3b1be09b3fbebca1b36b5eab1 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66575 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-24ec/google/chromeec/acpi: Add support for DPTF oem variable event notifyTony Huang
The agah EC code will monitor adapter current to choose corresponding DPTF oem variable table. When it changes, this event will send to the ACPI FW through host event and then pass onto the DPTF kernel driver. This patch adds support for that feature. BUG=b:238921409 TEST=add Printf() calls to the ACPI, and check these Printf() will show up in the kernel log when EC send oem variable table change notify. Change-Id: I1dbbfd9b3d65b56d77050c9ba9957e54530c3a0e Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66574 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-24libpayload: Add const for dma_coherent argumentYu-Ping Wu
Add the const modifier for the ptr argument of dma_coherent to avoid unnecessary type casting in payloads. BUG=none TEST=emerge-corsola libpayload BRANCH=none Change-Id: Ic4bb1d8318c7e83fd3ab3054aa0333cb27afe588 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66961 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Hsin-Te Yuan <yuanhsinte@google.com>
2022-08-24payloads/edk2: Move building to directory called workspaceSean Rhodes
The current edk2 makefile will work in a directory that's name is derived from the repository, such as `mrchromebox` or `starlabsltd`. Move this under a directory, so that it can be ignored by git and so that the makefile can be adjusted to use file targets, rather than phony recipes with wildcards. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: If0c80dbc59130f229b78cab9578115e14172301d Reviewed-on: https://review.coreboot.org/c/coreboot/+/66356 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-24soc/intel/adl: Consider INTEL_TME config prior TME MSR programmingSubrata Banik
This patch brings INTEL_TME config check prior programming TME Set Activation Core MSR on all cores. TEST=Able to boot Google/Taeko to OS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I8af7e305da1050f443929ab33be556e713e53e9a Reviewed-on: https://review.coreboot.org/c/coreboot/+/66976 Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-24mb/starlabs/lite: Enable P2SBSean Rhodes
Enable the P2SB so that the SPI is discoverable by the OS. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I9c12161d4868deae5b8900cfa2f42517a9f0b7e8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66977 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-08-24drivers: Implement EFI_PEI_MP_SERVICES_PPI with FSP_UNSUPPORTED typeSubrata Banik
This patch implements EFI_PEI_MP_SERVICES_PPI structure definitions with APIs that return mp_api_unsupported(). The reason behind this change is to fix an FSP issue where FSP assumes ownership of the APs (Application Processors) upon passing a `NULL` pointer to the CpuMpPpi FSP-S UPD.Hence, this patch implements `MP_SERVICES_PPI_DEFAULT` config to fill EFI_PEI_MP_SERVICES_PPI with `mp_api_unsupported` APIs. Later this data structure can be passed to the CpuMpPpi UPD to avoid APs from getting hijacked by FSP while coreboot decides to set SkipMpInit UPD. TEST=Able to build and boot Google/Taeko with this patch. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I31fcaa2aa633071b6d6bfa05dbe891ef87978d2c Reviewed-on: https://review.coreboot.org/c/coreboot/+/66708 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-08-24soc/intel/alderlake/hsphy: Add support for HSPHY firmware loadingMichał Żygowski
BIOS must send the IP_LOAD HECI command to fetch the firmware for CPU PCIe Gen5 and upload it via CPU REG BAR prior FSP Silicon Init. Implementation based on public Slimbootloader's "Silicon/AlderlakePkg/Library/CpuPcieHsPhyInitLib". TEST=Boot MSI PRO Z690-A and see the HSPHY FW is loaded. PCIe x16 Gen3 GPU card started working in the PCIE 5.0 slot. [DEBUG] HECI: Sending Get IP firmware command [DEBUG] HECI: Get IP firmware success. Response: [DEBUG] Payload size = 0x6944 [DEBUG] Hash type used for signing payload = 0x3 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I6c6c11581e3d3d9bab0131fae6ef487cafe98080 Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64074 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2022-08-24soc/intel/meteorlake: Enable GPIO 4 bits pad mode configurationJamie Ryu
This enables SOC_INTEL_COMMON_BLOCK_GPIO_PMODE_4BITS to support 4 bits GPIO pad mode to configure native function 8 to 15. BUG=b:239690757 TEST=build and verify pad mode configuration with Meteor Lake mtlrvp Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Change-Id: Ibf4b13a3d19095d15bf857c7fe4ec0affb54a4e8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66391 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-08-24soc/intel/common/gpio: Support 4 bits GPIO pad mode configurationJamie Ryu
Intel GPIO pad supports 4 bits pad mode, PAD_CFG_DW0[13:10] for pins that native function 8 to 15 is assigned. This adds native function definitions from NF8 to NF15 and updates PAD_CFG0_MODE_MASK to support 4 bits pad mode configuration. Since PAD_CFG_DW0[16:13] is reserved for pins that NF8 or higher is not assigned, this change would not cause an issue but Kconfig option is added to minimize an impact and support 4 bits pad mode configuration. BUG=b:239690757 TEST=build and verify pad mode configuration with Meteor Lake mtlrvp Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Change-Id: Iefd2daa92a86402f2154de2a013ea30f95d98108 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66375 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-08-24mb/google/rex: add arbitrage gpio.c headerKevin Chowski
This comment header is necessary for supporting propagation of overrides to variants. Change-Id: Iee92fa4fbc4851c7032401cff99ea49f87717c7f Signed-off-by: Kevin Chowski <chowski@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66846 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-08-24src/arch/x86/smbios.c: remove unneeded bracesFabio Aiuto
fix the following checkpatch errors: WARNING:BRACES: braces {} are not necessary for any arm of this statement 354: FILE: src/arch/x86/smbios.c:354: + if (CONFIG_ROM_SIZE >= 1 * GiB) { [...] + } else { [...] WARNING:BRACES: braces {} are not necessary for single statement blocks 561: FILE: src/arch/x86/smbios.c:561: + if (leaf_b_threads == 0) { + leaf_b_threads = 1; + } Signed-off-by: Fabio Aiuto <fabioaiuto83@gmail.com> Change-Id: I14c29e4358cad4cd5ef169ebab7079db2129d8fa Reviewed-on: https://review.coreboot.org/c/coreboot/+/66925 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-08-24vc/amd/fsp/mendocino: Update DMI_T17_MEMORY_TYPEMatt DeVillier
Synchronize with AGESA/AgesaModulePkg/Include/MemDmi.h. Add/correct values for DDR5, LPDDR5, LPDDR5X. BUG=b:239000826 TEST=Build and verify with other patches in train Change-Id: I127f21bfe2dfcd7794eb543185ea3fb362ff3914 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66952 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-08-24drivers/spi/tpm: Add Ti50 entry to dev_mapYidi Lin
BUG=none TEST=See "[INFO ] Initialized TPM device TI50 revision 83" Signed-off-by: Yidi Lin <yidilin@chromium.org> Change-Id: I3af5f4653b6b8ecd086f85ec573530a4e5c57211 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66786 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-08-23mb/**/hda_verb.c: Drop empty filesAngel Pons
These files are no longer required by the build system. Change-Id: I327e7c9211f46d4694591abab11cb38c9180bddb Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66610 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2022-08-23{sb,soc}/intel: Do not require hda_verb.cAngel Pons
Just use the conditional inclusion through `device/Makefile.inc`. Change-Id: Id363a97460ae2cfe4b10d491d4ef06394eb530c2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66609 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-15 03:32:44 +0000