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2023-02-02ifdtool: Cleanup IFDv1 detectionPatrick Rudolph
Change https://review.coreboot.org/c/coreboot/+/54305 "util/ifdtool: Use -p platform name to detect IFDv2 platform and chipset" made the '-p' argument mandatory for IFDv2 platforms. Drop the IFDv2 platform CHIPSET_C620_SERIES_LEWISBURG from IFDv1 detection. Change-Id: If29f8718b7aa696cdc07deef4c98be9a68c66f10 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68680 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-02util/ifdtool: Add Wellsburg supportPatrick Rudolph
Wellsburg is IFDv2 compatible in most fields, but not in all. It only has 8 regions and the flash master bits match the defines for IFDv1 and thus has an "IFDv1.5" descriptor. Add a new enum for IFDv1.5 descriptor and use them to properly operate on this IFD. The 'SPI programming guide' is inconsistent and mentions 6 regions in one place, but 7 regions in another chapter. Tests showed that it actually supports 7 regions. Add support using the -p argument to specify Wellsburg platform. The previous patch made sure that only 8 regions are used and that no corruption can happen when operating in IFDv2/IFDv1.5 mode. Tested on Intel Grangeville. Documents used: Intel Document Id: 516552 Intel Document Id: 565117 Change-Id: I651730b05deb512478d059174cf8615547d2fde4 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Co-developed-by: Julian Elischer <jrelis@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-02-02soc/intel/meteorlake: Enable V1p05-PHY supply external FET controlSubrata Banik
This patch enables S0i2.2 by letting 1.5V Phy supply to control the externa FET. BUG=b:256805904 Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I8771c11ce3b305343c7e96510e1375538d5e7f04 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72709 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2023-02-02nb/intel/{sandybridge,haswell}: Generate IOAPIC DMAR entries from hwBill XIE
Use acpi_create_dmar_ds_ioapic_from_hw() to generate DMAR entries. This can restore s3 resume capability for Sandy Bridge platforms lost after commit d165357ec37c ("sb,soc/intel: Use register_new_ioapic_gsi0()"). Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Change-Id: I83e735707cd9ff30aa339443593239cd7e3e4656 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72513 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-02-02soc/mediatek/mt8188: Remove the GPIO setting of USB1_DRV_VBUSLiju-Clr Chen
USB1_DRV_VBUS is used to provide 5V power for USB on MT8188 EVB and it's not used on Geralt. Therefore, remove the GPIO setting of USB1_DRV_VBUS. TEST=read usb data successfully. BUG=b:236331724 Change-Id: Iffea7b288c83c81648d4c7ca30d2f0961f9853ff Signed-off-by: Liju-Clr Chen <liju-clr.chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72641 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-01soc/qualcomm/sc7280: Memlayout change to support new Crypto sha updateVenkat Thogaru
With New Crypto upgrade we need to have 1 block of 4Kb increase in romstage, by which we can see an improvement of Boot performance by 100 msec. BUG=b:218406702 TEST=Validated on qualcomm sc7280 development board Boot performance improved by 100 msec observed. Change-Id: I9f5c8a79993fc1c529fae5cea4c4182663643ddd Signed-off-by: Sudheer Kumar Amrabadi <quic_samrabad@quicinc.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72646 Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com>
2023-02-01soc/qualcomm/common/qup: Avoid double decompress of gsi_fw blobSudheer Kumar Amrabadi
During boot, gpi_firmware_load gets called twice because there are 2 serial engines. Thus gsi_fw blob is also decompressed twice and is written to base addresses of SEs. This is redundant. Perform the decompression once on first call and save the header in static variable which can be reused in next call. BUG=b:262426214 TEST=Validated on qualcomm sc7280 development board Saving of 80ms observed while testing with 130 boot cycles. Change-Id: If98a3974f0791dffdf675c02cc28375d0485c485 Signed-off-by: Vijaya Nivarthi <vnivarth@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71927 Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-01soc/amd/mendocino: Force resets to be coldMartin Roth
Like Cezanne, Mendocino does not support warm resets. Change all resets (including resets in the OS) to cold resets (like Cezanne). BUG=b:248221908 TEST=Run suspend_stress_test, then reboot Change-Id: I1fbb4cc6eb6e6de9616d00d0191ccf3c0ac55278 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72486 Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com>
2023-02-01soc/intel/jsk: Move ME FSR structures to pertinent headerDinesh Gehlot
This patch moves ME host firmware status register structures to ME header file. It also marks unused structure fields to reserved. The idea here is to decouple ME specification defined structures from the source file `.c` and keep those into header files so that in future those spec defined header can move into common code. The current and future SoC platform will be able to select the correct ME spec header based on the applicable config. It might be also beneficial if two different SoC platforms would like to use the same ME specification and not necessarily share the same SoC directory. BUG=b:260309647 Test=Able to build and boot. Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: I58faed286718f5eab714cd39001177e50feb4f8b Reviewed-on: https://review.coreboot.org/c/coreboot/+/72414 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-02-01soc/intel/skl: Move ME FSR structures to pertinent headerDinesh Gehlot
This patch moves ME host firmware status register structures to ME header file. It also marks unused structure fields to reserved. The idea here is to decouple ME specification defined structures from the source file `.c` and keep those into header files so that in future those spec defined header can move into common code. The current and future SoC platform will be able to select the correct ME spec header based on the applicable config. It might be also beneficial if two different SoC platforms would like to use the same ME specification and not necessarily share the same SoC directory. BUG=b:260309647 Test=Able to build and boot. Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: Ic42c67163fe42392952499293e91e35537cb9147 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72415 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-02-01soc/intel/cnl: Move ME FSR structures to pertinent headerDinesh Gehlot
This patch moves ME host firmware status register structures to ME header file. It also marks unused structure fields to reserved. The idea here is to decouple ME specification defined structures from the source file `.c` and keep those into header files so that in future those spec defined header can move into common code. The current and future SoC platform will be able to select the correct ME spec header based on the applicable config. It might be also beneficial if two different SoC platforms would like to use the same ME specification and not necessarily share the same SoC directory. BUG=b:260309647 Test=Able to build and boot. Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: I34d3c4a60653fe0c1766cd50c96b8d3fe63637d1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72412 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-02-01soc/intel/mtl: remove DPTF from D-states list used to enter LPMEran Mitrani
The D-state list lists the devices with the corresponding D-state that the devices should be in, in order to enter LPM. DPTF is not mentioned in Intel's document 595644 as one of the devices. This CL removes it to avoid a potential error seen in ADL devices as mentioned in commit 3fd5b0c4cdeb ("soc/intel/adl: remove DPTF from D-states list used to enter LPM") TEST=Built and tested on Rex, saw SSDT generated properly. BUG=b:231582182 Signed-off-by: Eran Mitrani <mitrani@google.com> Change-Id: I9192ed9a7fb59ebba14f6d5082b400534b16ca72 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72603 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-01ec/google/wilco/acpi: Add DPTF RCDP() methodMatt DeVillier
The Windows DPTF drivers expect this method, and if not present appear to hang. Adding this method fixes DPTF under Windows on drallion. Modeled after existing method used by chrome-ec. TEST=build/boot Win11 on google/drallion, verify DPTF functional. Change-Id: I6570345379da413273251ecf5209c4997aac9b11 Original-patch-by: Coolstar <coolstarorganization@gmail.com> Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72578 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2023-02-01mb/google/brya/var/omnigul: Add memory configAmanda Huang
Configure the rcomp, dqs and dq tables based on the schematic. BUG=b:264340545 BRANCH=firmware-brya-14505.B TEST=FW_NAME=omnigul emerge-brya coreboot Change-Id: I82ca8aa9c3535983d5c506c15dbc69e7be926fa0 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71930 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Marx Wang <marx.wang@intel.com>
2023-02-01mb/google/brya/var/omnigul: Select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFSJamie Chen
This patch selects USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS for Google/Omnigul variant which intends to achieve a unified AP firmware image across UFS and non-UFS skus. BUG=b:263846075 TEST=FW_NAME=omnigul emerge-brya coreboot Change-Id: I90ae116ccccde48792aeafaa683c7420a95c9886 Signed-off-by: Jamie Chen <jamie_chen@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72509 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-01mb/google/geralt: Add USB3 HUB reset funtion to bootblockBo-Chen Chen
After powering on the device, we need to pull USB3_HUB_RST_L up to enable USB3 Hub. TEST=boot kernel from USB ok BUG=b:264841530 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Signed-off-by: Liju-Clr Chen <liju-clr.chen@mediatek.com> Change-Id: I8df35efb78e90a5b3314840fe2eae81d6e501242 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72594 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-01Documentation: Fix broken tablesNicholas Chin
- The 4.19 release notes included a list of outstanding issues formatted as a markdown table, which is not supported by Recommonmark. Reformat as an embedded reStructuredText table. - The table of boards supported on the 4.18 branch did not include row separators causing all rows to be rendered in a single row of cells. - Technotes/console.md had a typo in the rST table formatting which generated warnings in the Sphinx build, causing the table to not be rendered in the resulting html. Change-Id: I86e2c5d6d20e6002b87efc4688fc11b24b341227 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72623 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-02-01amdfwtool: Remove the duplicated entry RIBZheng Bao
It should be PSP_RIB_FILE which is already there. Change-Id: Ie7471489bd34554e357510b04473102d002f9988 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72506 Reviewed-by: ritul guru <ritul.bits@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-02-01mb/prodrive/atlas/data.vbt: Fix VBT lane countMaximilian Brune
Currently there is a problem, where two Displayports are not working. To be precise: TCP0 and TCP1 (Type-C Port 0/1) are not working. Setting the lane count of the TCP0 and TCP1 to x1 works fine. Setting the lane count of the TCP0 and TCP1 to x2 does not work. Setting the lane count of the TCP0 and TCP1 to x4 does not work. The reason for that is currently unknown. This change sets the lane count of the TCP0 and TCP1 Port to x1 length in the VBT binary. Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I182b528275152bf5adcb01a56816afd65674aed3 Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72610 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-01crossgcc: Upgrade LLVM version 15.0.6 to 15.0.7Elyes Haouas
Change-Id: I3198b065316b98f2d26360c4e65055e7460ea707 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71884 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-02-01mb/intel/mtlrvp: Modify the print messageHarsha B R
This patch updates the print message to start with uppercase, 'board' to 'Board'. BUG=b:224325352 BRANCH=None TEST=Able to observe proper print message when invalid board id is configured. Signed-off-by: Harsha B R <harsha.b.r@intel.com> Change-Id: Ie82df940cbd1eba9c5d485b48648c2bc8f234aae Reviewed-on: https://review.coreboot.org/c/coreboot/+/72638 Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Usha P <usha.p@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-01crossgcc: Upgrade CMake from version 3.25.0 to 3.25.2Elyes Haouas
Change-Id: Iaf0988997c6644e0e4f02d60a1d6de0e498e19bc Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71889 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-01Documentation/gerrit_guidelines: Fix newlinesNicholas Chin
Markdown does not render newlines unless there is an empty line in between the lines of text. Several command examples and a list were missing these empty lines, causing their content to be rendered inline with the preceding text. Fix this by adding triple backticks around code blocks and bullet points to rows of text in a list. Change-Id: I9c1d2b81acdeb378346c68bced0cdbfeeb81bf26 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72625 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-01treewide: Remove duplicated include <device/pci.h>Elyes Haouas
<device/pci.h> chain-includes <device/pci_def.h> & <device/pci_type.h>. Change-Id: I4e5999443e81ee1c4b1fd69942050b47f21f42f8 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72626 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-31soc/amd/glinda/acpi: use acpigen_write_processor_deviceFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iec9cf7c195fa5cb5c8d992aeab400d05cbe801c2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72494 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-01-31soc/amd/phoenix/acpi: use acpigen_write_processor_deviceFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I103cdce8c23ff4adbf1057fa26bd67275f2ab0e5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72493 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-01-31soc/amd/mendocino/acpi: use acpigen_write_processor_deviceFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I036dcddf89e8d865d0dc3ef0bd9e48842d8bf6c3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72492 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-01-31soc/amd/cezanne/acpi: use acpigen_write_processor_deviceFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I77a91c0a6d937772bf25fa936cec8a710b9acf72 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72491 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-01-31soc/amd/picasso/acpi: use acpigen_write_processor_deviceFelix Held
In CB:71614 Kyösti pointed out that ACPI_GPE0_BLK is the wrong address to assign to proc_blk_addr; the correct one would be ACPI_CPU_CONTROL. When looking a bit closer into this, it turned out that acpigen_write_processor is generating deprecated AML opcodes, so replace the acpigen_write_processor call with a call to the newly added acpigen_write_processor_device function that also doesn't have the proc_blk_addr and proc_blk_len parameters. The information about the IO port for entering C-states is already written into an SSDT by acpigen_write_CST_package which is likely also the reason why the wrong proc_blk_addr value wasn't noticed for a very long time. TEST=Mandolin still boots Ubuntu 22.04 LTS and Windows 10 and no possibly related errors show up. Linux gets the expected C-state information from the _CST package inside the processor device scope. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie67416e19e431029dd12da66ad44ddfa8586df03 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72490 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-01-31acpi/acpigen: introduce acpigen_write_processor_deviceFelix Held
The ACPI PROCESSOR_OP has been deprecated in ACPI 6.0 and dropped in ACPI 6.4 and is now permanently reserved. As a replacement, DEVICE_OP with the special HID ACPI0007 should be used instead. This special HID was introduced in version 3 of the ACPI spec. To have a function to generate this, acpigen_write_processor_device is introduced. The CPU index is used as UID which can be assumed to be unique. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ifb0da903a972be134bb3b9071f81b441f60917d1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72469 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-01-31mb/google/skyrim/var/winterhold: Update DPTC settings for SMTEricKY Cheng
Follow thermal team's request on b/248086651 comment#27. Update the thermal table setting for each mode and the conditions of temperature switching. BUG=b:248086651 TEST=emerge-skyrim coreboot Change-Id: Ida10d9b10c33dea11440879afda07c04c1eccb9f Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72006 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Jon Murphy <jpmurphy@google.com>
2023-01-31vendorcode: Add VariableFormat.hPatrick Rudolph
Add the EDK2 variable format header in order to access the SPI flash variable store. https://github.com/tianocore/edk2/blob/edk2-stable202005/MdeModulePkg/Include/Guid/VariableFormat.h Commit Hash: 9d510e61fceee7b92955ef9a3c20343752d8ce3f Change-Id: Ibe44925555a7d1d2361dd48c0325b840bd68e0ca Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61959 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-31soc/amd/common/block/include/acpi: drop MMIO_ACPI_CPU_CONTROL defineFelix Held
This register isn't used in coreboot and isn't defined in the Picasso PPR #55570 Rev 3.18. To enter a lower C-state, a read request to a special IO port is done. The base address of this group of IO ports is configured in set_cstate_io_addr via the MSR_CSTATE_ADDRESS and that read won't leave the CPU. IIRC trying to put the MMIO mapping for entering the lower C-states into the _CST package didn't work as expected when it was tried on I think Cezanne. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib189993879feaa0a22f6810c4bd5c1a0bc8c5a27 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72497 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-01-31soc/intel/ehl: Move ME FSR structures to pertinent headerDinesh Gehlot
This patch moves ME host firmware status register structures to ME header file. It also marks unused structure fields to reserved. The idea here is to decouple ME specification defined structures from the source file `.c` and keep those into header files so that in future those spec defined header can move into common code. The current and future SoC platform will be able to select the correct ME spec header based on the applicable config. It might be also beneficial if two different SoC platforms would like to use the same ME specification and not necessarily share the same SoC directory. BUG=b:260309647 Test=Able to build and boot. Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: I7dfd331e70f6d03c88248ca5147dbe6785a8e69d Reviewed-on: https://review.coreboot.org/c/coreboot/+/72413 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-01-31soc/intel/alderlake: Pick an unused and safer graphics address spaceJeremy Compostella
It turns out that the [0xfa000000-0xfaffffff] range conflicts with some North TraceHub address space ranges ([0xfad00000-0xfadfffff] and [0xfacfc000-0xfacfffff]). Experiments have established that this conflicting range results in an unpected PIPE A underrun issue reported by i915 and some visible flickers on the display during boot. The [0xf0000000-0xffffffff] range is a crowded memory space with resources statically assigned to some devices but also some ranges used at various point in the boot flow by the FSP. To not run into any other potential conflicts, we want to pick a unused memory space. But at this early stage of the boot, we do not have full knowledge of what memory space is going to be used by the FSP. As a result, we decided to pick the [0xaf000000-0xafffffff] range as: 1. It does not conflicting with any coreboot memory space usage 2. It is the address the FSP uses by default for GFX MMIO BAR0 and as such should not conflict with any FSP memory space usage. BUG=b:264648959 BRANCH=firmware-brya-14505.B TEST=No flickers observed on boot Change-Id: I6a00350ff4007bb7692d2ff6598b946cc6123302 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72605 Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-01-31console: Print architecturePatrick Rudolph
Useful to see which architecture x86_32 or x86_64 coreboot was built for. Change-Id: I34eec64ac32254c270dcbb97e20a7e6be0f478fc Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59761 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
2023-01-31soc/intel/apl: Ensure CPU_CLUSTER linked_list bus existsArthur Heymans
This fixes a NULL pointer deref introduced by 69cd729 (mb/*: Remove lapic from devicetree). Change-Id: I816fddfe3efe3c3aefe1b2ee28426dc1e1f3c962 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72599 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-01-31util/sconfig: Remove lapic devices from devicetree parsersArthur Heymans
This is all handled at runtime now, so there is no need to have the ability to statically add lapics to the devicetree. Change-Id: I0746eb808a2956ac75f76c8189a9ecf190e33ce9 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69378 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-31src/sbom: Add code documentation + fix misspellingMaximilian Brune
Functionality wise nothing changed, except that the first misspellings caused SBOM_BIOS_ACM_PATH and SBOM_SINIT_ACM_PATH to not work before. - Fix misspelling of CONFIG_BIOS_ACM_PATH -> CONFIG_SBOM_BIOS_ACM_PATH - Fix misspelling of CONFIG_SINIT_ACM_PATH -> CONFIG_SBOM_SINIT_ACM_PATH - Put SBOM_COMPILER_ handling into Kconfig instead of Makefile - Reorder CONFIG_ paths (for readablity) - Add in code comments (for readablity) Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: If67bc3bd0d330b9b5f083edc4d1697e92ace1ea0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72379 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-01-31soc/intel/common/block: Add LPC BIOS decode lockTim Chu
The LPC BIOS decode lock bit is defined in EBG EDS documentation. Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Change-Id: I60df7e6da2b22b8eeb2094aeb5ee9667043bb30b Reviewed-on: https://review.coreboot.org/c/coreboot/+/71954 Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-01-31crossgcc: Upgrade mpfr from 4.1.1 to 4.2.0Elyes Haouas
Changes: https://www.mpfr.org/mpfr-current/#changes Change-Id: Ife757d7a8247c11338ca795109044cdccdf86733 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-01-31crossgcc: Upgrade mpc from 1.2.1 to 1.3.1Elyes Haouas
Change-Id: I2d98c3b4c7edaf3ff097f5739c7cc0cd13592e91 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70530 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-01-31crossgcc/buildgcc: Add missing "\" at build_NASMElyes Haouas
"\" is missing at the end of CC line for build_NASM. Change-Id: Ic29ee731def31f958f939efe19bdb55b503eb6ba Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72512 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-01-31drivers/intel/fsp2_0: Simplify check for CONFIG_SAVE_MRC_AFTER_FSPSDavid Hendricks
This uses a simpler form of #if to check if CONFIG_SAVE_MRC_AFTER_FSPS is enabled, referencing the Kconfig variable only once and defaulting to the original behavior if not. Change-Id: I4711c1474d9a3a5c685dd31561619c568fab075c Signed-off-by: David Hendricks <david.hendricks@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72587 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-31mb/amd: Include <gpio.h> instead of <soc/gpio.h>Elyes Haouas
<gpio.h> chain-include <soc/gpio.h>. Change-Id: I48191064fcee53ca843a537aa36bdbbd57736bf2 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72588 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-01-31configs/config.facebook_fbg1701.sbom: Fix var namesMaximilian Brune
The variables defined in this defconfig are incorrectly named, therefore fix them. Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I9299be96f8c44d6a87d380f4f942c4d26af7050d Reviewed-on: https://review.coreboot.org/c/coreboot/+/72477 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-01-30src/mainboard: Remove unnecessary space after castsElyes Haouas
Change-Id: Id8e1a52279e6a606441eefe30e24bcd44e006aad Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69815 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
2023-01-30mb/siemens/mc_ehl3/gpio.c: Disable PSE GBE0 GPIOJan Samek
Since the PSE GBE0 MAC has been disabled on this board in commit 343644006f89 ("mb/siemens/mc_ehl3/devicetree.cb: Remove TSN GbE 0"), therefore disable the corresponding GPIOs as well. BUG=none TEST=Test link detection and IP assignment on the remaining ports (PSE GBE1 and PCH GBE0) of mc_ehl3. Change-Id: Ifa055f58894688471d68b9b93fcb994fdcb2a568 Signed-off-by: Jan Samek <jan.samek@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72449 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-30util/crossgcc/buildgcc: Remove extra "/" at the end of IASL_BASE_URLElyes Haouas
Change-Id: I8df1d93a8b0a0d562c7ae5a9f1a70f2eb26499c9 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71976 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-30mb/*: Remove lapic from devicetreeArthur Heymans
The parallel mp code picks up lapics at runtime, so remove it from all devicetrees that use this codebase. Change-Id: I5258a769c0f0ee4bbc4facc19737eed187b68c73 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69303 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-01-30payloads/external/LinuxBoot: Update u-root releases in Kconfigeliassouza
Building LinuxBoot with u-root newers releases can providing a better experience, Change-Id: Ie98f434c5296b7ba7c3750a766b244c747421baa Signed-off-by: eliassouza <eliascontato@protonmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72465 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-30mb/intel/mtlrvp: Add romstage and configure LP5 memory partsAshish Kumar Mishra
This patch adds initial romstage code and spd data for LP5 memory parts for MTL-RVP. This also configures memory based on the board id. Memory - x32 LPDDR5 Vendor/Model - Micron/MT62F2G32D8DR-031 WT:B Board ID - 0b0000 - Empty spd hex file 0b0001 - DDR5 (Empty spd hex file) 0b0010 - LPDDR5 (MT62F2G32D8DR-031 WT:B) BUG=b:224325352 TEST=Able to boot intel/mtlrvp (LP5 SKU) to ChromeOS Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com> Change-Id: I15b352eb246aed23da273e56490c7094eae9d176 Signed-off-by: Harsha B R <harsha.b.r@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69741 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-30mb/google/brya: Select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFSSubrata Banik
This patch selects USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS for Google/Marasov variant which intends to achieve a unified AP firmware image across UFS and non-UFS skus. Note: Enabling this config would introduce an additional warm reset during the cold-reset scenarios due to the function disabling of the UFS controller as results we are expecting ~300ms higher boot time (which might not be user visible because `cbmem -t` can't include impacted boot time due to in-between resets). BUG=b:264838335 TEST=Able to enter S0ix on Marasov NVMe sku after disabling UFS during boot path. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ie8b8814cdb5e0d97a382cebfe82868ada5762341 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71990 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-01-30arch/x86/smbios.c: Add socket type for Intel SPR-SPChristian Walter
Intel SPR-SP processor has socket type as PROCESSOR_UPGRADE_SOCKET_LGA4677 which is different from the socket type of CPX-SP and SKX-SP. Change-Id: Id2279cc0c1fa3f007d7c081af6f78e5aa98d2f3d Signed-off-by: Christian Walter <christian.walter@9elements.com> Signed-off-by: David Hendricks <ddaveh@amazon.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71947 Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-29soc/intel/xeon_sp/Kconfig: add SOC_INTEL_SAPPHIRERAPIDS_SPTim Chu
Intel SPR-SP (Sapphire Rapids Scalable Processor) chipset belongs to Xeon-SP family. It was product launched on Jan. 10, 2023. Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Change-Id: Ifece05e2fbcc454cdee8e849cb4f146c89f54333 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71946 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-01-29arch/x86/smbios.c: Update Xeon-SP socket typesDavid Hendricks
Now that we support >1 Xeon-SP, XEON_SP_COMMON_BASE no longer reflects the socket type. This uses SOC_INTEL_* Kconfig variables and returns the correct socket type for Cooper Lake-SP. Signed-off-by: David Hendricks <ddaveh@amazon.com> Change-Id: I142de5f040f3b76e352f27c00fe9e50787df5712 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72498 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-01-29vendorcode/intel/fsp/fsp2_0: add SPR-SP FSP header filesJonathan Zhang
Intel Sapphire Rapids Scalable Processor was product launched on Jan. 10, 2023. Add the FSP/HOB header files corresponding to 2022 ww43 git tag EGLSTRM.0.RPB.0090.D.03. Change-Id: I818da37c10f40045d98a9f73e82034c3fe6459e2 Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71948 Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2023-01-29drivers/intel/fsp2_0: Add saving MRC data after FSP-S optionJohnny Lin
When Kconfig SAVE_MRC_AFTER_FSPS is selected, save MRC training data after FSP-S instead of FSP-M. For now only SPR-SP server FSP supports this. This issue surfaces with SPR-SP, because of the memory type (DDR5 support) and memory capacity (more memory controllers, bigger DRAM capacity). Therefore Intel decided to save MRC training data after FSP-S with SPR-SP FSP. Change-Id: I3bab0c5004e717e842b484c89187e8c0b9c2b3eb Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71950 Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-29soc/intel/xeon_sp/include/soc/pmc.h: move to lbg directoryJonathan Zhang
The PMC registers are quite different between LBG and EBG. Move pmc.h to lbg directory to differentiate. Change-Id: I6f14059942210c222631e11cced0b5c05d3c1dc6 Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Signed-off-by: David Hendricks <ddaveh@amazon.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72399 Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-28soc/intel/common/block/acpi/pep: use acpigen_write_processor_namestringFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I43590f0f792fca1c90ee8f8b32e6be47943c59df Reviewed-on: https://review.coreboot.org/c/coreboot/+/72453 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-28acpi/acpigen: factor out acpigen_write_processor_namestringFelix Held
This functionality is used in multiple places, so factor it out into a function. Compared to acpigen_write_processor_cnot, the buffer size is decreased from 40 to 16 bytes, but the format string specified by CONFIG_ACPI_CPU_STRING results in 9 chars and a NULL byte which will fit into the buffer without any issue. I've seen the CPU devices being put into another scope within \_SB, but even in that case that would be 14 chars and a NULL byte whist still fits into the 16 byte buffer. For acpigen_write_processor and acpigen_write_processor_package this doesn't change any edge case behavior. In the unrealistic case of the format string resulting in a longer CPU device string, this would have been a problem before this patch too. Also drop the curly braces of the for loop in acpigen_write_processor_package. This makes the code a bit harder to read and isn't a very good idea, but with the curly braces in place, the linter breaks the build :( Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5d8291a2aaae2011cb185d72c7f7864b6e2220ec Reviewed-on: https://review.coreboot.org/c/coreboot/+/72452 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-01-28acpi/Kconfig: improve description of ACPI_CPU_STRING config optionFelix Held
ACPI_CPU_STRING specifies the format string for the scope of the processor devices in the generated ACPI code. Also point out that the resulting string will be truncated to at most 15 chars to fit into the 16 byte buffer used in two functions in acpigen.c. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1fb1db8adeecd783c835a500d28a13b823cda155 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72451 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-01-28ec/google/chrome-ec: Demote Vivaldi printk from error to infoMatt DeVillier
Not all Chrome-EC devices have a keyboard or use Vivaldi for key remapping, so demote the printk output when the EC doesn't support it from ERROR to INFO. Adjust the printk text for clarity. Change-Id: I14059f4e3e56ff891f302601d5acc1bb842cffc1 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72474 Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-27payloads/U-boot: Fix U-Boot cloning erroreliassouza
Renaming origin/master to just master fix error during cloning repo. Error: Remote branch origin/master not found in upstream origin Change-Id: Ib5d4bb0277076842f8a8400eb61da9ad23465b66 Signed-off-by: eliassouza <eliascontato@protonmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72464 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-01-27amdfwtool: Update and extend PSP header format descriptionZheng Bao
The comment in the header amdfwtool.c was written long time ago and is needed to get updated. Change-Id: I6f64c9a240503f9d0bf240916c1066944fa39d27 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55602 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-01-27mb/starlabs/starbook/adl: Fix the disable wireless CMOS optionSean Rhodes
The current CMOS option causes Linux to not boot, as the GRUB EFI loader will report an incorrect parameter. Update the CMOS option so that the corresponding UPD is changed when the wireless is set to disable, so that the root port for the wireless is also disabled. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I607d700319d6a58618ec95b3440e695c82dff196 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71896 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-27mb/starlabs/starbook/adl: Make Type-C USB a standard portSean Rhodes
Change the Type-C USB 2.0 interface to a standard port, as the Type-C macro will not work in Linux (dmesg says the cable is faulty), This makes the port work reliably in Linux, tested with: * Manjaro 21 * Ubuntu 22.04 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I6dbf31b6e4603685297e9e5203b0db6ac1b9e24a Reviewed-on: https://review.coreboot.org/c/coreboot/+/72387 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-27intelblocks/cse: Add functions to check and change PTT stateMichał Żygowski
Add functions that allow checking and changing PTT state at runtime. Can be useful for platforms that want to use dTPM instead and have no means to stitch ME firmware binary with disabled PTT. The changing function also checks for the current feature states via HECI to ensure that the feature state will not be changed if not needed. TEST=Successfully switch to dTPM on Comet Lake i5-10210U SoC. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I8426c46eada2d503d6ee72324c5d0025da3f2028 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68919 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
2023-01-27elogtool: Fix potential buffer overrunKapil Porwal
BUG=b:239110778 TEST=Make sure that the output of elogtool is unaffected by this change. Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: Ia1a6341abd834dd9ad5f12c9f2eefb0489364a08 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72099 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-27drivers/i2c/ptn3460: Use cb_err in mb_adjust_cfgJan Samek
Return generic coreboot error codes from the mb_adjust_cfg callback used in mainboards instead of '-1' constant and a driver-specific success-indicating define. BUG=none TEST=Boards siemens/mc_apl{1,4,5,7} and siemens/mc_ehl3 build correctly. Change-Id: I5e0d4e67703db518ed239a845f43047f569b94ec Signed-off-by: Jan Samek <jan.samek@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72071 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2023-01-27soc/intel/adl: remove DPTF from D-states list used to enter LPMEran Mitrani
The D-state list lists the devices with the corresponding D-state that the devices should be in, in order to enter LPM DPTF is not mentioned in Intel's document 595644 as one of the devices. This CL removes it to avoid an error seen after it was added to that table: "ACPI Error: AE_NOT_FOUND, While resolving a named reference package element - \_SB_.PCI0.DPTF (20200925/dspkginit-438)" TEST=Built and tested on anahera and saw the error is gone BUG=b:231582182 Change-Id: I00eddd7e4cc71a0c25e77ff53025dee5bf942de1 Signed-off-by: Eran Mitrani <mitrani@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72199 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-01-27docs/contributing: Rename "easy projects" to "small projects"Felix Singer
Depending on the actual issue and the experience of the contributor, "Easy projects" might not be an appropriate description for Coverity issues and similar things. Thus rename this section to "Small projects" and also update references to it. Change-Id: I3bdefd9f37440ab3ae493095b7fb5c76394d2ba1 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72447 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-01-27docs/contributing: Fix dead link to linter issuesFelix Singer
Change-Id: I169fa5a89d65d3a71e9cc84638216c7baa3815f1 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72446 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-01-27src/acpi: add debug message with concatenated stringCliff Huang
add functions for concatenate OP add debug message containing concatenated string with string, value, or OPs Ex1: to print string with another string provided from C side: acpigen_write_debug_concatenate_string_string("Wait loop Timeout! var=", name, LOCAL6_OP); will generate: Concatenate ("Wait loop Timeout! var=", "L23E", Local6) Debug = Local6 Ex2: to print string with a value: acpigen_write_debug_concatenate_string_int("ModPHY enabling for RP:", pcie_rp, LOCAL0_OP); will generate: Concatenate ("ModPHY enabling for RP:", 0x05, Local0) Debug = Local0 Ex3: to print string with an ACPI OP: acpigen_write_debug_concatenate_string_op("while Loop count: ", LOCAL7_OP, LOCAL6_OP) will generate: Concatenate ("while Loop count: ", Local7, Local6) Debug = Local6 TEST=Add above functions in the acpigen code and check the generated SSDT table after OS boot Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: I370745efe3d6b513ec2c5376248362a3eb4b3d21 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72126 Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2023-01-27soc/intel/mtl: Add missing claimed memory regionsEran Mitrani
This CL adds claimed memory regions that were missing for the resource allocator. See commit ca741055e6b6 ("soc/intel/adl: Add missing claimed memory regions") for details. TEST=Booted rex and saw the previously missing ranges getting added from AP Log (with this CL): SA MMIO resource: MCHBAR -> base = 0xfedc0000, size = 0x00020000 SA MMIO resource: DMIBAR -> base = 0xfeda0000, size = 0x00001000 SA MMIO resource: EPBAR -> base = 0xfeda1000, size = 0x00001000 SA MMIO resource: REGBAR -> base = 0xd0000000, size = 0x10000000 SA MMIO resource: EDRAMBAR -> base = 0xfed80000, size = 0x00004000 SA MMIO resource: CRAB_ABORT -> base = 0xfeb00000, size = 0x00080000 SA MMIO resource: LT_SECURITY -> base = 0xfed20000, size = 0x00060000 SA MMIO resource: APIC -> base = 0xfec00000, size = 0x00100000 SA MMIO resource: PCH_RESERVED -> base = 0xfd800000, size = 0x01000000 SA MMIO resource: MMCONF -> base = 0xc0000000, size = 0x10000000 SA MMIO resource: DSM -> base = 0x7c000000, size = 0x04000000 SA MMIO resource: TSEG -> base = 0x7b000000, size = 0x00800000 SA MMIO resource: GSM -> base = 0x7b800000, size = 0x00800000 dmesg: BIOS-e820: [mem 0x0000000000000000-0x0000000000000fff] reserved BIOS-e820: [mem 0x0000000000001000-0x000000000009ffff] usable BIOS-e820: [mem 0x00000000000a0000-0x00000000000fffff] reserved BIOS-e820: [mem 0x0000000000100000-0x00000000759c9fff] usable BIOS-e820: [mem 0x00000000759ca000-0x000000007fffffff] reserved BIOS-e820: [mem 0x00000000c0000000-0x00000000e0ffffff] reserved BIOS-e820: [mem 0x00000000f8000000-0x00000000f9ffffff] reserved BIOS-e820: [mem 0x00000000fd800000-0x00000000fe7fffff] reserved BIOS-e820: [mem 0x00000000feb00000-0x00000000feb7ffff] reserved BIOS-e820: [mem 0x00000000fec00000-0x00000000fecfffff] reserved BIOS-e820: [mem 0x00000000fed20000-0x00000000fed83fff] reserved BIOS-e820: [mem 0x00000000feda0000-0x00000000feda1fff] reserved BIOS-e820: [mem 0x00000000fedc0000-0x00000000feddffff] reserved BIOS-e820: [mem 0x00000000ff000000-0x00000000ffffffff] reserved BIOS-e820: [mem 0x0000000100000000-0x000000027fffffff] usable BIOS-e820: [mem 0x000003fff0aa0000-0x000003fff0aa1fff] reserved Change-Id: I749e7b6e969f8d6314fcd2906acd7de69d4d9f9c Signed-off-by: Eran Mitrani <mitrani@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71114 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-01-27mb/siemens/mc_apl1/var/mc_apl5: Enable early POSTJan Samek
Enable early POST code display on this variant using the common mc_apl1 baseboard functionality. BUG=none TEST=Boot on mc_apl5 and observe that POST codes are displayed before DRAM training. Change-Id: I390e0ab09ca830637e7a991db77e994d6c358e75 Signed-off-by: Jan Samek <jan.samek@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72386 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-27Updated the 4.19 release notes post-releaseMartin Roth
Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I2628d7b25d3fb7467772cb859cb7c8c7865e323c Reviewed-on: https://review.coreboot.org/c/coreboot/+/72480 Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-01-27Docs: Update boards supported on branches documentMartin Roth
- Update the notes for the 4.19 release. - Add the intel/icelake_rvp board as being supported on the 4.19 branch. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I5c283f64efc465d8f70fc19d570c5b7547474e80 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72481 Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-01-26soc/intel/alderlake: Wait for panel power cycle to completeJeremy Compostella
The Alder Lake PEIM graphics driver executed as part of the FSP does not wait for the panel power cycle to complete before it initializes communication with the display. It can result in AUX channel communication time out and PEIM graphics driver failing to bring up graphics. If we have performed some graphics operation in romstage, it is possible that a panel power cycle is still in progress. To prevent any issue with the PEIM graphics driver it is preferable to ensure that panel power cycle is complete. This patch replaces commit ba2cef5b5493 ("soc/intel/common/block/early_graphics: Introduce a 200 ms delay") workaround patch. BUG=b:264526798 BRANCH=firmware-brya-14505.B TEST=Developer screen is visible in the recovery flow Change-Id: Iadd6c9552b184f7d6ec8df9d0d392634864ba50b Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72419 Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-01-26drivers/intel/gma: Use libgfxinit Update_Output to turn off graphicsJeremy Compostella
We were using the libgfxinit `Initialize' function with the `Clean_State' parameter because the more appropriate `Update_Output' function was not performing all the necessary clean up operations for the PEIM driver to be successful when libgfxinit was used in romstage. Thanks to a lot of experiments and some log analysis efforts, we were able to identify the missing operation and fix the `Update_Output' function (cf. https://review.coreboot.org/c/libgfxinit/+/72123). The `initialized' global variable is now unnecessary as we track the initialization in the Ada code instead. Since the `Update_Output' function does not return any value, this patch modifies the `gma_gfxstop' prototype accordingly. This does not have any impact as the return value was not used anyway. BUG=b:264526798 BRANCH=firmware-brya-14505.B TEST=Developer screen is visible Change-Id: I53d6fadf65dc09bd984de96edb4c1f15b64aeed0 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72125 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-01-26drivers/intel/gma: Dump output setting only if DEBUG_ADA_CODE is setJeremy Compostella
This patch restricts the dump of the vebose graphics output settings to configuration with the `DEBUG_ADA_CODE' flag set. BUG=b:264526798 BRANCH=firmware-brya-14505.B TEST=Configuration dump is seen only if DEBUG_ADA_CODE is set Change-Id: Iadd6c9552b184f7d6ec8df9d0d392634864ba50c Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72418 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-01-26Documentation/distributions.md: Update Dasharo descriptionKacper Stojek
Add info on where to contribute to Dasharo. Signed-off-by: Kacper Stojek <kacper.stojek@3mdeb.com> Change-Id: I1b7e7aa05a0cabc990bddfaf957873402ebe183f Reviewed-on: https://review.coreboot.org/c/coreboot/+/70852 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-01-26src/mb/prodrive/atlas: Add GPIOs for configurationMaximilian Brune
CLKREQ Pins are intentionally not configured, because there seems to be a current Issue with FSP, that causes pci devices to not work if CLKREQ Pins are configured by coreboot. The msi/ms7d25 mainboard seems to have a similar issue and the cause is also documented in it's gpio.c file. Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: Iba35076af194de0e85de60ebc93d62fda24e9c24 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72388 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-01-26nb/intel/gm45: Add remaining raminit code to support DDR2Nico Huber
Add the remaining DDR2 code to program the registers for memory timings, ODT, RCOMP, and refresh mode; and perform receive-enable calibration. TEST: DDR2 systems boot - Tested on a Dell Latitude E6400 - Tested on a Compal JHL90 TEST: Ensure DDR3 systems still boot - Tested on a Thinkpad X200 Change-Id: I6d9a1853fea9e29171d7c2f9ffe7086685c9efad Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34834 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-26nb/intel/gm45: Split DDR2 I/O init outNico Huber
Move DDR3 memory I/O init to its own function and add DDR2 memory I/O init. Read I/O init is common to both DDR2 and DDR3. TEST: DDR2 systems boot (with the rest of the patch train) - Tested on a Dell Latitude E6400 - Tested on a Compal JHL90 TEST: Ensure DDR3 systems still boot - Tested on a Thinkpad X200 Change-Id: Ic4d5130f527249d3a5b98bae778cdf21a1753b04 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34833 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-26nb/intel/gm45: Split DDR2 JEDEC init outNico Huber
Split JEDEC init into common and DDR3 specific parts and add the DDR2 specific init code. This also replaces raw `mchbar_clrsetbits32` calls with a dedicated `jedec_command` function. TEST: DDR2 systems boot (with the rest of the patch train) - Tested on a Dell Latitude E6400 - Tested on a Compal JHL90 TEST: Ensure DDR3 systems still boot - Tested on a Thinkpad X200 Change-Id: I7a57549887c0323e5babbf18f691183412a99ba9 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34827 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-26nb/intel/gm45: Wedge DDR2 SPD support inNico Huber
Add initial support for DDR2. This also changes GM45 raminit to internally work in units of 1/256 ns for both DDR2 and DDR3 instead of the 1/8 ns MTB assumed for DDR3, which simplifies the handling of time values. DDR3 time values are thus scaled by a factor of 32 accordingly. TODO: - DDR2 JEDEC init - Memory IO init - Register programming TEST: DDR2 systems boot (with the rest of the patch train) - Tested on a Dell Latitude E6400 - Tested on a Compal JHL90 TEST: Ensure DDR3 systems still boot - Tested on a Thinkpad X200 Change-Id: I265938d58c30264fd5d4f7b89da7b689058b8cf8 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34826 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-26mb/starlabs/starbook/Kconfig: Move MAINBOARD_HAS_TPM2 to STARBOOK_SERIESElyes Haouas
Change-Id: I5f91ae1b5904405edd797b57fbeb46609301295c Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72434 Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-25mainboard: Drop invalid `hyper_threading` optionAngel Pons
Drop the `hyper_threading` CMOS option from most boards, as it's most likely not working properly and causing problems. The main reasons to remove the option are: * The used enum is backwards (0 ---> Enable, 1 ---> Disable) * Platform/SoC code does not honor the `hyper_threading` option Also, remove the now-unused enum used by the `hyper_threading` option. Change-Id: Ia8980a951f4751bc2e1a5d0e88835f578259b256 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69523 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2023-01-25mb/starlabs/starbook/adl: Enable pin widget 0x18Sean Rhodes
Enable pin 0x18 which is used for the 3.5mm combo jack microphone detection. Also, disable 0x17 as it is not used. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I05856627c073acaff49ea1ddc048a49a74b6268f Reviewed-on: https://review.coreboot.org/c/coreboot/+/71718 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-25mb/starlabs/starbook/adl: Change HDA verb hex values to lower caseSean Rhodes
Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I6a5c54ac46840fc1e03eb15b9ae2ddc34172ec08 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72011 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-25soc/intel/mtl/acpi: add FSPI to DSDTEran Mitrani
Getting an error from the Kernel on Rex devices: > ACPI Error: AE_NOT_FOUND, While resolving a named reference > package element - \_SB_.PCI0.FSPI (20210730/dspkginit-438) FSPI is defined in src/soc/intel/meteorlake/chipset.cb: device pci 1f.5 alias fast_spi on end This CL adds the corresponding FSPI device to the DSDT to prevent the error mentioned above. See commit feed8e4bd9dc ("soc/intel/adl/acpi: add FSPI to DSDT") for the corresponding ADL CL. TEST=Built and tested on brya by verifying the error is gone. Signed-off-by: Eran Mitrani <mitrani@google.com> Change-Id: Id8d2a1b5e074f036345e028b117d420bf36a9042 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72411 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-01-25soc/intel/common/gpio: Add function to read GPIO TX valueCliff Huang
This function reads out the current value set to output for a GPIO pin. Ex: GPP_E0 is set to output int e0_val; e0_val = gpio_tx_get(GPP_E0); Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: Ib02b9ab50d378eb163d91aed1576428b49cec2cf Reviewed-on: https://review.coreboot.org/c/coreboot/+/72127 Reviewed-by: Anil Kumar K <anil.kumar.k@intel.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2023-01-25amdfwtool: Remove comment "fallthrough"Zheng Bao
Fix the comment as "checkpatch" says. Change-Id: Ifa5d7de037aa7024779f3aa4a5d2f5033eed264a Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71648 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-01-25soc/intel/alderlake: Increase premem cbmem buffer size to 16KBTarun Tuli
Current size of the cbmem premem buffer (8KB) is sometimes insufficient to contain the complete debug log causing the cbmem console buffer to indicate overflow. This patch increases the premem cbmem buffer size to 16KB so that the complete debug log can be stored in it. TEST=Make sure that logs from all the boot stages can be seen using 'cbmem -c'. Change-Id: I60c68322c52191eabf7e06b4be06e66f90ff8751 Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71290 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-25mb/prodrive/atlas: Enable audio outputLean Sheng Tan
Before, the Intel HDA PCIe device was showing up in the lspci tool, but Audio wasn't working. This patch enables the corresponding FSP-M settings to make it work. Tested on Prodrive Atlas with Themis carrier board on Windows 10 and Linux 6.1.0-rc3. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I144618c453c1e6a3e759afc7532a4ac4a71814c9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72385 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-01-25mb/prodrive/atlas: Disable SaGv by defaultLean Sheng Tan
Customer needs SaGv to be disabled by default. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I8454c267dcc12d2ef7de7bd23296a17294f058a0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72384 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
2023-01-25soc/intel/cmn/block/pcie: Make ASPM configurableMaximilian Brune
Currently ASPM cannot be disabled by individual mainboards, if the soc Kconfig includes SOC_INTEL_COMMON_PCH_CLIENT. Other options like PCIEXP_CLK_PM and PCIEXP_L1_SUB_STATE are already configurable by individual mainboards if needed. This change makes PCIEXP_ASPM one of these configurable options. Test: build prodrive/atlas and see that build/config.h lists the option CONFIG_PCIEXP_ASPM as disabled. Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: Ic9c049f1d225bc21d8da5bd208651ad847ae0c6e Reviewed-on: https://review.coreboot.org/c/coreboot/+/72117 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-01-25mb/google/skyrim/baseboard/devicetree: enable mp2 deviceFelix Held
The mp2 PCI device is still present when no mp2 firmware is loaded. When this device isn't explicitly enabled in the mainboard's devicetree, the chipset devicetree default of the device being disabled is used. This results in coreboot's resource allocator not allocating resources to the device and since the bridge doesn't have enough MMIO space reserved, the Linux kernel can't assign resources to it. To fix this problem, enable the mp2 device in the mainboard's devicetree so that it gets its resources assigned by coreboot. An equivalent change was verified on Chausie. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1076ccacc6f51bf195b8280a6df5ad1849771519 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72196 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-25mb/amd/chausie/devicetree: enable mp2 deviceFelix Held
The mp2 PCI device is still present when no mp2 firmware is loaded. When this device isn't explicitly enabled in the mainboard's devicetree, the chipset devicetree default of the device being disabled is used. This results in coreboot's resource allocator not allocating resources to the device and since the bridge doesn't have enough MMIO space reserved, the Linux kernel can't assign resources to it. To fix this problem, enable the mp2 device in the mainboard's devicetree so that it gets its resources assigned by coreboot. TEST=Fixes the resource allocation for the mp2 PCI device. dmesg output before the patch: [ 0.210616] pci 0000:04:00.7: [1022:164a] type 00 class 0x118000 [ 0.210631] pci 0000:04:00.7: reg 0x18: [mem 0x00000000-0x000fffff] [ 0.210641] pci 0000:04:00.7: reg 0x24: [mem 0x00000000-0x00001fff] [ 0.210649] pci 0000:04:00.7: enabling Extended Tags [ 0.240570] pci 0000:04:00.7: BAR 2: no space for [mem size 0x00100000] [ 0.240572] pci 0000:04:00.7: BAR 2: failed to assign [mem size 0x00100000] [ 0.240574] pci 0000:04:00.7: BAR 5: assigned [mem 0xd05c6000-0xd05c7fff] dmesg output after the patch: [ 0.210483] pci 0000:04:00.7: [1022:164a] type 00 class 0x118000 [ 0.210501] pci 0000:04:00.7: reg 0x18: [mem 0xd0500000-0xd05fffff] [ 0.210515] pci 0000:04:00.7: reg 0x24: [mem 0xd06c6000-0xd06c7fff] [ 0.210524] pci 0000:04:00.7: enabling Extended Tags Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I680ef9798f2f0e7e0646f0fd30bef58398b7bf19 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72197 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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